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path: root/drivers/pinctrl/sh-pfc
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2018-12-18pinctrl: sh-pfc: sh73a0: Add missing TO pin to tpu4_to3 groupGeert Uytterhoeven
The tpu4_to3_mux[] array contains the TPU4TO3 pin mark, but the tpu4_to3_pins[] array lacks the corresponding pin number. Add the missing pin number, for non-GPIO pin F26. Fixes: 5da4eb049de803c7 ("sh-pfc: sh73a0: Add TPU pin groups and functions") Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> Reviewed-by: Simon Horman <horms+renesas@verge.net.au>
2018-12-18pinctrl: sh-pfc: r8a7791: Remove bogus marks from vin1_b_data18 groupGeert Uytterhoeven
The vin1_b_data18_mux[] arrays contains pin marks for the 2 LSB bits of the color components. The vin1_b_data18_pins[] array rightfully does not include the corresponding pin numbers, as RGB18 is subset of RGB24, containing only the 6 MSB bits of each component. Fixes: 8e32c9671f84acd8 ("pinctrl: sh-pfc: r8a7791: Add VIN pins") Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> Reviewed-by: Simon Horman <horms+renesas@verge.net.au>
2018-12-18pinctrl: sh-pfc: r8a7791: Remove bogus ctrl marks from qspi_data4_b groupGeert Uytterhoeven
The qspi_data4_b_mux[] array contains pin marks for the clock and chip select pins. The qspi_data4_b_pins[] array rightfully does not contain the corresponding pin numbers, as the control pins are provided by a separate group (qspi_ctrl_b). Fixes: 2d0c386f135e4186 ("pinctrl: sh-pfc: r8a7791: Add QSPI pin groups") Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> Reviewed-by: Simon Horman <horms+renesas@verge.net.au>
2018-12-18pinctrl: sh-pfc: r8a7740: Add missing LCD0 marks to lcd0_data24_1 groupGeert Uytterhoeven
The lcd0_data24_1_pins[] array contains the LCD0 D1[2-5] pin numbers, but the lcd0_data24_1_mux[] array lacks the corresponding pin marks. Fixes: 06c7dd866da70f6c ("sh-pfc: r8a7740: Add LCDC0 and LCDC1 pin groups and functions") Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> Reviewed-by: Simon Horman <horms+renesas@verge.net.au>
2018-12-18pinctrl: sh-pfc: r8a7740: Add missing REF125CK pin to gether_gmii groupGeert Uytterhoeven
The gether_gmii_mux[] array contains the REF125CK pin mark, but the gether_gmii_pins[] array lacks the corresponding pin number. Fixes: bae11d30d0cafdc5 ("sh-pfc: r8a7740: Add GETHER pin groups and functions") Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> Reviewed-by: Simon Horman <horms+renesas@verge.net.au>
2018-12-18pinctrl: sh-pfc: r8a77990: Fix IOCTRL reg state after s2ram on R-Car E3Geert Uytterhoeven
Due to an interaction with commit 9f2b76a2db3c4387 ("pinctrl: sh-pfc: r8a77990: Add R8A774C0 PFC support"), the state of the I/O Control Registers is saved/restored during s2ram on RZ/G2E, but not on R-Car E3. Hence on R-Car E3, SDHI voltage state is lost after system resume. Fix this by registering the I/O Control Registers on R-Car E3, too. Fixes: 33847a71373cd6ae ("pinctrl: sh-pfc: r8a77990: Add voltage switch operations for SDHI") Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> Reviewed-by: Wolfram Sang <wsa+renesas@sang-engineering.com> Reviewed-by: Simon Horman <horms+renesas@verge.net.au>
2018-12-18pinctrl: sh-pfc: r8a77990: Add support for pull-up only pinsGeert Uytterhoeven
The R-Car Gen3 HardWare Manual Errata for Rev. 1.00 (Jul 2, 2018) states that the USB30_OVC pin supports pull-up only. It has a bit assigned in the pull-enable register (PUEN5), but not in the pull-up/down control register (PUD5). Add a check for this, to prevent configuring a prohibited setting. Reported-by: Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com> Fixes: 83f6941a42a5e773 ("pinctrl: sh-pfc: r8a77990: Add bias pinconf support") Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> Reviewed-by: Simon Horman <horms+renesas@verge.net.au>
2018-11-20pinctrl: sh-pfc: r8a77980: Add QSPI pins, groups, and functionsDmitry Shifrin
Add the QSPI{0|1} pins/groups/functions to the R8A77980 PFC driver. [Sergei: ported to the upstream driver, fixed up the swapped QSPI0 SPCLK/ SSL pins, fixed up the comments, moved the QSPI pins/groups/functions to be in the alphanumeric order, removed unneeded empty lines, renamed the patch.] Signed-off-by: Dmitry Shifrin <dmitry.shifrin@cogentembedded.com> Signed-off-by: Sergei Shtylyov <sergei.shtylyov@cogentembedded.com> Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2018-11-19pinctrl: sh-pfc: r8a77990: Add CAN FD pins, groups and functionsTakeshi Kihara
This patch adds CAN FD{0,1} pins, groups and functions to the R8A77990 SoC. Signed-off-by: Takeshi Kihara <takeshi.kihara.df@renesas.com> Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com> [geert: Move canfd from common to automotive] Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2018-11-19pinctrl: sh-pfc: r8a77990: Add CAN pins, groups and functionsTakeshi Kihara
This patch adds CAN{0,1} pins, groups and functions to the R8A77990 SoC. Signed-off-by: Takeshi Kihara <takeshi.kihara.df@renesas.com> Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com> Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2018-11-19pinctrl: sh-pfc: r8a77965: Add CAN FD pins, groups and functionsTakeshi Kihara
This patch adds CAN FD{0,1} pins, groups and functions to the R8A77965 SoC. Signed-off-by: Takeshi Kihara <takeshi.kihara.df@renesas.com> Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com> Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2018-11-19pinctrl: sh-pfc: r8a77965: Add CAN pins, groups and functionsTakeshi Kihara
This patch adds CAN{0,1} pins, groups and functions to the R8A77965 SoC. Signed-off-by: Takeshi Kihara <takeshi.kihara.df@renesas.com> Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com> Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2018-11-19pinctrl: sh-pfc: r8a7796: Add I2C{0,3,5} pins, groups and functionsTakeshi Kihara
This patch adds I2C{0,3,5} pins, groups and functions to the R8A7796 SoC. These pins are physically muxed with other pins. Therefore, setup of MOD_SEL is needed for exclusive control with other pins. Signed-off-by: Takeshi Kihara <takeshi.kihara.df@renesas.com> Signed-off-by: Ulrich Hecht <uli+renesas@fpond.eu> Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2018-11-19pinctrl: sh-pfc: r8a7795-es1: Add I2C{0,3,5} pins, groups and functionsTakeshi Kihara
This patch adds I2C{0,3,5} pins, groups and functions to the R8A7795 ES1.x SoC. These pins are physically muxed with other pins. Therefore, setup of MOD_SEL is needed for exclusive control with other pins. Signed-off-by: Takeshi Kihara <takeshi.kihara.df@renesas.com> Signed-off-by: Ulrich Hecht <uli+renesas@fpond.eu> Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2018-11-19pinctrl: sh-pfc: r8a7795: Add I2C{0,3,5} pins, groups and functionsTakeshi Kihara
This patch adds I2C{0,3,5} pins, groups and functions to the R8A7795 SoC. These pins are physically muxed with other pins. Therefore, setup of MOD_SEL is needed for exclusive control with other pins. Signed-off-by: Takeshi Kihara <takeshi.kihara.df@renesas.com> Signed-off-by: Ulrich Hecht <uli+renesas@fpond.eu> Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2018-11-19pinctrl: sh-pfc: Add physical pin multiplexing helper macrosUlrich Hecht
Used by I2C controllers 0, 3 and 5 in R8A7795 and R8A7796 SoCs. Signed-off-by: Ulrich Hecht <uli+renesas@fpond.eu> Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2018-11-19pinctrl: sh-pfc: r8a77995: Remove unused PINMUX_IPSR_{MSEL2,PHYS}()Geert Uytterhoeven
The PINMUX_IPSR_MSEL2() and PINMUX_IPSR_PHYS() macros are unused, and will conflict with generic macros that are to be added. Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> Reviewed-by: Simon Horman <horms+renesas@verge.net.au>
2018-11-19pinctrl: sh-pfc: r8a77990: Add HSCIF pins, groups, and functionsTakeshi Kihara
This patch adds HSCIF{0,1,2,3,4} pins, groups and functions to the R8A77990 SoC. Signed-off-by: Takeshi Kihara <takeshi.kihara.df@renesas.com> Signed-off-by: Yoshihiro Kaneko <ykaneko0929@gmail.com> Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2018-11-13pinctrl: sh-pfc: r8a77990: Add VIN[4|5] groups/functionsJacopo Mondi
Add pin, mux and functions definitions for VIN4 and VIN5 for R-Car E3. Signed-off-by: Jacopo Mondi <jacopo+renesas@jmondi.org> Reviewed-by: Simon Horman <horms+renesas@verge.net.au> Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2018-11-13pinctrl: sh-pfc: r8a77965: Add VIN[4|5] groups/functionsJacopo Mondi
The VIN4 and VIN5 interfaces support parallel video input. Add pin, mux and functions definitions for VIN4 and VIN5 for R-Car M3-N. Signed-off-by: Jacopo Mondi <jacopo+renesas@jmondi.org> Reviewed-by: Ulrich Hecht <uli+renesas@fpond.eu> Reviewed-by: Simon Horman <horms+renesas@verge.net.au> Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2018-11-13pinctrl: sh-pfc: r8a7796: Fix VIN versioned groupsJacopo Mondi
Versioned VIN groups can appear on different sets of pins. Using the VIN_DATA_PIN_GROUP macro now supports proper naming of said groups through an optional 'version' argument. Use the 'version' argument for said macro to fix naming of versioned groups for the R-Car M3-W R8A7796 SoC. Fixes: a5c2949ff7bd ("pinctrl: sh-pfc: r8a7796: Deduplicate VIN4 pin definitions") Signed-off-by: Jacopo Mondi <jacopo+renesas@jmondi.org> Reviewed-by: Simon Horman <horms+renesas@verge.net.au> Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2018-11-13pinctrl: sh-pfc: r8a7795: Fix VIN versioned groupsJacopo Mondi
Versioned VIN groups can appear on different sets of pins. Using the VIN_DATA_PIN_GROUP macro now supports proper naming of said groups through an optional 'version' argument. Use the 'version' argument for said macro to fix naming of versioned groups for the R-Car H3 R8A7795 SoC. Fixes: 9942a5b52990 ("pinctrl: sh-pfc: r8a7795: Deduplicate VIN4 pin definitions") Signed-off-by: Jacopo Mondi <jacopo+renesas@jmondi.org> Reviewed-by: Simon Horman <horms+renesas@verge.net.au> Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2018-11-13pinctrl: sh-pfc: r8a7792: Fix VIN versioned groupsJacopo Mondi
Versioned VIN groups can appear on different sets of pins. Using the VIN_DATA_PIN_GROUP macro now supports proper naming of said groups through an optional 'version' argument. Use the 'version' argument for said macro to fix naming of versioned groups for the R-Car V2H R8A7792 SoC. Fixes: 7dd74bb1f058 ("pinctrl: sh-pfc: r8a7792: Add VIN pin groups") Signed-off-by: Jacopo Mondi <jacopo+renesas@jmondi.org> Reviewed-by: Simon Horman <horms+renesas@verge.net.au> Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2018-11-13pinctrl: sh-pfc: Add optional arg to VIN_DATA_PIN_GROUPJacopo Mondi
VIN data groups may appear on different sets of pins, usually named "vinX_data_[a|b]". The existing VIN_DATA_PIN_GROUP() does not support appending the '_a' or '_b' suffix, leading to the definition of group names not consistent with the ones defined using the SH_PFC_PIN_GROUP() macro. Fix this by making the VIN_DATA_PIN_GROUP macro a variadic one, which accepts an optional 'version' argument. Fixes: 423caa52534f ("pinctrl: sh-pfc: r8a779[01]: Move 'union vin_data' to shared header file") Signed-off-by: Jacopo Mondi <jacopo+renesas@jmondi.org> Reviewed-by: Simon Horman <horms+renesas@verge.net.au> Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2018-11-13pinctrl: sh-pfc: r8a77970: Add QSPI pins, groups, and functionsDmitry Shifrin
Add the QSPI{0|1} pins/groups/functions to the R8A77970 PFC driver. [Sergei: ported to the upstream driver, fixed up the swapped QSPI0 SPCLK/ SSL pins, fixed up the comments, moved the QSPI pins/groups/functions to be in the alphanumeric order, removed unneeded empty lines, renamed the patch.] Signed-off-by: Dmitry Shifrin <dmitry.shifrin@cogentembedded.com> Signed-off-by: Sergei Shtylyov <sergei.shtylyov@cogentembedded.com> Reviewed-by: Simon Horman <horms+renesas@verge.net.au> Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2018-11-13pinctrl: sh-pfc: r8a77990: Add voltage switch operations for SDHITakeshi Kihara
This patch supports the {get,set}_io_voltage operations of SDHI. This operates the IOCTRL30 register on the R8A77990 SoC and makes 1.8V/3.3V signal voltage switch possible. Signed-off-by: Takeshi Kihara <takeshi.kihara.df@renesas.com> Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com> Reviewed-by: Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com> Acked-by: Wolfram Sang <wsa+renesas@sang-engineering.com> Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2018-11-13pinctrl: sh-pfc: r8a77990: Add SDHI pins, groups and functionsTakeshi Kihara
This patch adds SDHI{0,1,3} pins, groups and functions to the R8A77990 SoC. Signed-off-by: Takeshi Kihara <takeshi.kihara.df@renesas.com> Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com> Reviewed-by: Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com> Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2018-11-06pinctrl: sh-pfc: r8a77470: Add SDHI supportFabrizio Castro
Add SH_PFC_PIN_CFG_IO_VOLTAGE definition for the SDHI pins capable of switching voltage, also add pin groups and functions for SDHI0 and SDHI1. Please note that with the RZ/G1C only 1 bit of the POC Control Register is used to control each interface. Signed-off-by: Fabrizio Castro <fabrizio.castro@bp.renesas.com> Reviewed-by: Biju Das <biju.das@bp.renesas.com> Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be> Reviewed-by: Simon Horman <horms+renesas@verge.net.au> Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2018-11-06pinctrl: sh-pfc: Reduce kernel size for narrow VIN channelsGeert Uytterhoeven
Some VIN channels support less than 24 lanes. As union vin_data always consumes space for 24 lanes, this wastes memory. Hence introduce new smaller unions vin_data12 and vin_data16, to accommodate VIN channels with only 12 or 16 lanes. This reduces the static pin controller driver size by 320 bytes for R-Car V2H, and by 96 bytes for R-Car E2. Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> Reviewed-by: Simon Horman <horms+renesas@verge.net.au> Reviewed-by: Niklas Söderlund <niklas.soderlund+renesas@ragnatech.se>
2018-11-06pinctrl: sh-pfc: r8a77990: Add Audio SSI pins, groups and functionsTakeshi Kihara
This patch adds Audio SSI{0,1,2,3,4,5,6,7,8,9} pins, groups and functions to the R8A77990 SoC. Signed-off-by: Takeshi Kihara <takeshi.kihara.df@renesas.com> [simon: rebase] Signed-off-by: Simon Horman <horms+renesas@verge.net.au> Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2018-11-06pinctrl: sh-pfc: r8a77990: Add Audio clock pins, groups and functionsTakeshi Kihara
This patch adds AUDIO_CLK{A,B,C}, AUDIO_CLKOUT, AUDIO_CLKOUT{1,2,3} pins, groups and functions to the R8A77990 SoC. Signed-off-by: Takeshi Kihara <takeshi.kihara.df@renesas.com> [simon: rebase] Signed-off-by: Simon Horman <horms+renesas@verge.net.au> Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2018-11-05pinctrl: sh-pfc: r8a77470: Add QSPI1 pin groupsFabrizio Castro
Add QSPI1 pin groups and function to the RZ/G1C (a.k.a. R8A77470) pinctrl driver. Signed-off-by: Fabrizio Castro <fabrizio.castro@bp.renesas.com> Reviewed-by: Fabrizio Castro <fabrizio.castro@bp.renesas.com> Reviewed-by: Simon Horman <horms+renesas@verge.net.au> Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2018-11-05pinctrl: sh-pfc: r8a77470: Add VIN pin groupsFabrizio Castro
Add VIN[01] pin groups and functions to the RZ/G1C (a.k.a. R8A77470) pinctrl driver. Signed-off-by: Fabrizio Castro <fabrizio.castro@bp.renesas.com> Reviewed-by: Biju Das <biju.das@bp.renesas.com> Reviewed-by: Simon Horman <horms+renesas@verge.net.au> Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2018-11-05pinctrl: sh-pfc: r8a77470: Add DU1 pin groupsFabrizio Castro
Add DU1 pin groups and function to the RZ/G1C (a.k.a. R8A77470) pinctrl driver. Signed-off-by: Fabrizio Castro <fabrizio.castro@bp.renesas.com> Reviewed-by: Biju Das <biju.das@bp.renesas.com> Reviewed-by: Simon Horman <horms+renesas@verge.net.au> Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2018-11-05pinctrl: sh-pfc: r8a77470: Add remaining I2C pin groupsFabrizio Castro
This patch adds I2C[0123] groups and functions to the RZ/G1C (a.k.a. R8A77470) pinctrl driver. Signed-off-by: Fabrizio Castro <fabrizio.castro@bp.renesas.com> Reviewed-by: Biju Das <biju.das@bp.renesas.com> Reviewed-by: Simon Horman <horms+renesas@verge.net.au> Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2018-10-02pinctrl: sh-pfc: r8a77990: Add INTC-EX pins, groups and functionGeert Uytterhoeven
Add pins, groups, and function for the Interrupt Controller for External Devices (INTC-EX) on the R-Car E3 SoC. Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> Reviewed-by: Simon Horman <horms+renesas@verge.net.au>
2018-09-28pinctrl: sh-pfc: rcar: Rename automotive-only arrays to automotiveGeert Uytterhoeven
Renesas RZ/G SoCs are pin compatible with R-Car SoCs, but lack several automotive-specific peripherals. Currently pin groups and functions for automotive-specific peripherals are grouped in arrays named after the automative SoC part numbers. Rename them to "automotive" for clarity and consistency. Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> Reviewed-by: Simon Horman <horms+renesas@verge.net.au>
2018-09-20pinctrl: sh-pfc: r8a77470: Add USB pin groupsFabrizio Castro
Add USB[01] pin groups and functions to the R8A77470 SoC. Signed-off-by: Fabrizio Castro <fabrizio.castro@bp.renesas.com> Reviewed-by: Biju Das <biju.das@bp.renesas.com> Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2018-09-20pinctrl: sh-pfc: r8a77470: Add SDHI2 pin groupsFabrizio Castro
Add SDHI2 pin groups and functions to the R8A77470 SoC. Signed-off-by: Fabrizio Castro <fabrizio.castro@bp.renesas.com> Reviewed-by: Biju Das <biju.das@bp.renesas.com> Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2018-09-20pinctrl: sh-pfc: r8a77470: Add QSPI0 pin groupsFabrizio Castro
Add QSPI0 pin groups and function to the R8A77470 SoC. Signed-off-by: Fabrizio Castro <fabrizio.castro@bp.renesas.com> Reviewed-by: Biju Das <biju.das@bp.renesas.com> Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2018-09-20pinctrl: sh-pfc: r8a77470: Add DU0 pin groupsFabrizio Castro
Add DU0 pin groups and function to the R8A77470 SoC. Signed-off-by: Fabrizio Castro <fabrizio.castro@bp.renesas.com> Reviewed-by: Biju Das <biju.das@bp.renesas.com> Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2018-09-20pinctrl: sh-pfc: r8a77470: Add I2C4 pin groupsFabrizio Castro
Add I2C4 pin groups and function to the R8A77470 SoC. Signed-off-by: Fabrizio Castro <fabrizio.castro@bp.renesas.com> Reviewed-by: Biju Das <biju.das@bp.renesas.com> Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2018-09-19pinctrl: sh-pfc: r8a77990: Add R8A774C0 PFC supportFabrizio Castro
Renesas RZ/G2E (a.k.a. r8a774c0) is pin compatible with R-Car E3 (a.k.a. r8a77990), however it doesn't have several automotive specific peripherals. Add a r8a77990 specific pin groups/functions along with common pin groups/functions for supporting both r8a77990 and r8a774c0 SoCs. Signed-off-by: Fabrizio Castro <fabrizio.castro@bp.renesas.com> Reviewed-by: Biju Das <biju.das@bp.renesas.com> Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2018-09-19pinctrl: sh-pfc: r8a7791: Add r8a7744 supportBiju Das
Renesas RZ/G1N (R8A7744) is pin compatible with R-Car M2-W/N (R8A7791/3) and RZ/G1M. Signed-off-by: Biju Das <biju.das@bp.renesas.com> Reviewed-by: Fabrizio Castro <fabrizio.castro@bp.renesas.com> Reviewed-by: Simon Horman <horms+renesas@verge.net.au> Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2018-09-11pinctrl: sh-pfc: Convert to SPDX identifiersKuninori Morimoto
This patch updates license to use SPDX-License-Identifier instead of verbose license text. Signed-off-by: Kuninori Morimoto <kuninori.morimoto.gx@renesas.com> Reviewed-by: Simon Horman <horms+renesas@verge.net.au> Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2018-09-11pinctrl: sh-pfc: r8a77995: Add MSIOF pins, groups and functionsTakeshi Kihara
This patch adds MSIOF{0,1,2,3} pins, groups and functions to R8A77995 SoC. Signed-off-by: Takeshi Kihara <takeshi.kihara.df@renesas.com> [ykaneko0929@gmail.com: fix the order of definitions] Signed-off-by: Yoshihiro Kaneko <ykaneko0929@gmail.com> Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2018-09-11pinctrl: sh-pfc: r8a77990: Add MSIOF pins, groups and functionsTakeshi Kihara
This patch adds MSIOF{0,1,2,3} pins, groups and functions to the R8A77990 SoC. Signed-off-by: Takeshi Kihara <takeshi.kihara.df@renesas.com> Reviewed-by: Simon Horman <horms+renesas@verge.net.au> Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2018-08-30pinctrl: sh-pfc: r8a77990: Add DU pins, groups and functionLaurent Pinchart
This patch adds DU pins, groups and function for the R8A77990 (E3) SoC. Signed-off-by: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com> Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2018-08-28pinctrl: sh-pfc: r8a77965: Add Audio SSI pin supportHoan Nguyen An
Add Audio SSI pin support for r8a77965. Signed-off-by: Hoan Nguyen An <na-hoan@jinso.co.jp> Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2018-08-28pinctrl: sh-pfc: r8a77965: Add Audio clock pin supportHoan Nguyen An
Add Audio clock pin support for r8a77965. Signed-off-by: Hoan Nguyen An <na-hoan@jinso.co.jp> Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
generated by cgit (git 2.34.1) at 2025-09-21 23:23:06 +0000