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Use pin numbers stored in the pin descriptors instead of index value while
creating the pin groups. Pin Id's are not same as Index values for Xilinx
Versal platform, so use the pin values from descriptor which works for both
ZynqMP and Versal platforms.
Signed-off-by: Swati Agarwal <swati.agarwal@amd.com>
Signed-off-by: Michal Simek <michal.simek@amd.com>
Link: https://lore.kernel.org/r/2413a1f99278d70313960f13daecda9ef54172d8.1716807432.git.michal.simek@amd.com
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
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The current version of the pinctrl driver has some issues:
1. Duplicated "gpio" pmx function
The common code will add a "gpio" pmx functon to every pin group, so
it's not necessary to define a separate "gpio" pmx function in pin
groups.
2. Duplicated pmx function name
There are some same function name in different pin groups, which will
cause some problems. For example, when we want to use PAD_GPIO0 as
refclk output function, the common clk framework code will search the
entire pin function lists, then return the first one matched, in this
case the matched function list only include the PAD_CO_CLKO pin group
because there are three "refclk" pin function, which is added by
refclk_grp, spi_cs1_grp and gpio_grp.
To solve this problem, a simple way is just add a pingrp refix to
function name like mt7620 pinctrl driver does.
3. Useless "-" or "rsvd" functon
It's really unnecessary to add a reserved pin mux function to the
function lists, because we never use it.
Signed-off-by: Weihao Li <cn.liweihao@gmail.com>
Link: https://lore.kernel.org/r/20240527022036.31985-1-user@blabla
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
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tps6594_muxval_remap as static to fix sparse warning
pinctrl: tps6594: Fix sparse warning.
warning: symbol 'tps65224_muxval_remap' was not declared. Should it be static?
warning: symbol 'tps6594_muxval_remap' was not declared. Should it be static?
Signed-off-by: Nirmala Devi Mal Nadar <m.nirmaladevi@ltts.com>
Reported-by: kernel test robot <lkp@intel.com>
Closes: https://lore.kernel.org/oe-kbuild-all/202405111523.9yt759uX-lkp@intel.com/
Link: https://lore.kernel.org/r/0109018f85002ae1-6fb831b2-74c2-4559-98f1-a3ef25e72558-000000@ap-south-1.amazonses.com
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
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PMC8380 is a new chip, featuring 10 GPIOs. Describe it.
Signed-off-by: Konrad Dybcio <konrad.dybcio@linaro.org>
Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
Reviewed-by: Neil Armstrong <neil.armstrong@linaro.org>
Link: https://lore.kernel.org/r/20240525-topic-pmc8380_gpio-v2-2-2de50cb28ac1@linaro.org
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
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We were not resetting the pointer to the associated gpio_device once
we are done displaying a pin's information.
This meant that once we reached the end of a gpio-range, if there
were pins right after it that did not belong to any known range,
they would be associated with the previous range's gpio device.
This resulted in those pins appearing as <4294966783:old_gdev> instead
of the expected <0:?> (due to gpio_num being -1).
Signed-off-by: Léo DUBOIN <lduboin@freebox.fr>
Link: https://lore.kernel.org/r/c40d0634abefa19e689ffd450e0f48a8d63c4fc4.1714049455.git.lduboin@freebox.fr
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
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We previously only looked at the 'pin_base' of the pinctrl_gpio_ranges
struct for determining if a pin matched a GPIO number.
This value is present only if the 'pins' array is not NULL,
and is 0 otherwise. This means that GPIO ranges declared using
gpiochip_add_pingroup_range(), thus making use of pins, were always matched
by the pins in the range [0-npins] even if they contained pins in a
completely separate range.
Signed-off-by: Léo DUBOIN <lduboin@freebox.fr>
Link: https://lore.kernel.org/r/6df39bd47942156be5713f8f4e317d2ad3e0ddeb.1714049455.git.lduboin@freebox.fr
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
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Add common pinctrl and GPIO driver for Nuvoton MA35 series SoC, and
add support for ma35d1 pinctrl.
Signed-off-by: Jacky Huang <ychuang3@nuvoton.com>
Link: https://lore.kernel.org/r/20240521012447.42211-4-ychuang570808@gmail.com
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
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Use scope based of_node_put() cleanup to simplify code.
Signed-off-by: Peng Fan <peng.fan@nxp.com>
Reviewed-by: Patrice Chotard <patrice.chotard@foss.st.com>
Link: https://lore.kernel.org/r/20240504-pinctrl-cleanup-v2-8-26c5f2dc1181@nxp.com
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
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Use scope based of_node_put() cleanup to simplify code.
Signed-off-by: Peng Fan <peng.fan@nxp.com>
Reviewed-by: Patrice Chotard <patrice.chotard@foss.st.com>
Link: https://lore.kernel.org/r/20240504-pinctrl-cleanup-v2-3-26c5f2dc1181@nxp.com
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
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Add NXP i.MX91 pinctrl driver
Signed-off-by: Peng Fan <peng.fan@nxp.com>
Link: https://lore.kernel.org/r/20240513-imx91-pinctrl-v1-2-c99a23c6843a@nxp.com
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
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The SPMI GPIO driver assumes that the parent device is an SPMI device
and accesses random data when backcasting the parent struct device
pointer for non-SPMI devices.
Fortunately this does not seem to cause any issues currently when the
parent device is an I2C client like the PM8008, but this could change if
the structures are reorganised (e.g. using structure randomisation).
Notably the interrupt implementation is also broken for non-SPMI devices.
Also note that the two GPIO pins on PM8008 are used for interrupts and
reset so their practical use should be limited.
Drop the broken GPIO support for PM8008 for now.
Fixes: ea119e5a482a ("pinctrl: qcom-pmic-gpio: Add support for pm8008")
Cc: stable@vger.kernel.org # 5.13
Reviewed-by: Bryan O'Donoghue <bryan.odonoghue@linaro.org>
Reviewed-by: Stephen Boyd <swboyd@chromium.org>
Signed-off-by: Johan Hovold <johan+linaro@kernel.org>
Link: https://lore.kernel.org/r/20240529162958.18081-9-johan+linaro@kernel.org
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
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Add pinctrl driver support for RZ/V2H(P) SoC.
Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
Link: https://lore.kernel.org/r/20240530173857.164073-16-prabhakar.mahadev-lad.rj@bp.renesas.com
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
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To keep consistency with rzg2l_pinctrl_set_pfc_mode(), acquire the lock
in rzg2l_pinctrl_pm_setup_pfc() during PFC setup.
Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
Tested-by: Claudiu Beznea <claudiu.beznea.uj@bp.renesas.com> # on RZ/G3S
Link: https://lore.kernel.org/r/20240530173857.164073-15-prabhakar.mahadev-lad.rj@bp.renesas.com
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
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In preparation for passing custom params for RZ/V2H(P) SoC assign the
custom params that are being passed via struct rzg2l_pinctrl_data.
Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
Link: https://lore.kernel.org/r/20240530173857.164073-14-prabhakar.mahadev-lad.rj@bp.renesas.com
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
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pinconf_generic_parse_dt_config()
Pass the pincontrol device pointer to pinconf_generic_parse_dt_config()
in preparation for passing custom params.
Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
Tested-by: Claudiu Beznea <claudiu.beznea.uj@bp.renesas.com> # on RZ/G3S
Link: https://lore.kernel.org/r/20240530173857.164073-13-prabhakar.mahadev-lad.rj@bp.renesas.com
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
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Add support to configure bias-disable, bias-pull-up, and bias-pull-down
properties of the pin.
Two new function pointers, hw_to_bias_param() and bias_param_to_hw(),
are introduced in the struct rzg2l_pinctrl_data to configure bias
settings, as the values in the PUPD register differ when compared to the
RZ/G2L family and the RZ/V2H(P) SoC.
Value | RZ/G2L | RZ/V2H
---------------------------------
00b: | Bias Disabled | Pull up/down disabled
01b: | Pull-up | Pull up/down disabled
10b: | Pull-down | Pull-down
11b: | Prohibited | Pull-up
Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
Link: https://lore.kernel.org/r/20240530173857.164073-12-prabhakar.mahadev-lad.rj@bp.renesas.com
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
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Add support to configure slew-rate property of the pin.
Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
Link: https://lore.kernel.org/r/20240530173857.164073-11-prabhakar.mahadev-lad.rj@bp.renesas.com
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
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Introduce function pointers oen_read() and oen_write(), in the struct
rzg2l_pinctrl_data to facilitate reading and writing to the PFC_OEN
register. On the RZ/V2H(P) SoC, unlocking the PWPR.REGWE_B bit before
writing to the PFC_OEN register is necessary, and the PFC_OEN register
has more bits compared to the RZ/G2L family. To handle these
differences between RZ/G2L and RZ/V2H(P) and to reuse the existing code
for RZ/V2H(P), these function pointers are introduced.
Additionally, populate these function pointers with appropriate data for
existing SoCs.
Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
Tested-by: Claudiu Beznea <claudiu.beznea.uj@bp.renesas.com> # on RZ/G3S
Link: https://lore.kernel.org/r/20240530173857.164073-10-prabhakar.mahadev-lad.rj@bp.renesas.com
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
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Introduces pmc_writeb() function pointer, in the struct
rzg2l_pinctrl_data to facilitate writing to the PMC register. On the
RZ/V2H(P) SoC, unlocking the PWPR.REGWE_A bit before writing to PMC
registers is required, whereas this is not the case for the existing
RZ/G2L family. This addition enables the reuse of existing code for
RZ/V2H(P). Additionally, populate this function pointer with
appropriate data for existing SoCs.
Note that this functionality is only handled in rzg2l_gpio_request(), as
PMC unlock/lock during PFC setup will be taken care of in the
pwpr_pfc_lock_unlock() function pointer.
Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
Tested-by: Claudiu Beznea <claudiu.beznea.uj@bp.renesas.com> # on RZ/G3S
Link: https://lore.kernel.org/r/20240530173857.164073-9-prabhakar.mahadev-lad.rj@bp.renesas.com
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
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On the RZ/G2L SoC, the PFCWE bit controls writing to PFC registers.
However, on the RZ/V2H(P) SoC, the PFCWE (REGWE_A on RZ/V2H) bit controls
writing to both PFC and PMC registers. Additionally, BIT(7) B0WI is
undocumented for the PWPR register on RZ/V2H(P) SoC. To accommodate these
differences across SoC variants, introduce the pwpr_pfc_lock_unlock()
function pointer.
Note, in rzg2l_pinctrl_set_pfc_mode() the pwpr_pfc_lock_unlock(.., false)
is now called before PMC read/write and pwpr_pfc_lock_unlock(.., true) is
now called after PMC read/write this is to keep changes minimal for
RZ/V2H(P) SoC.
Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
Tested-by: Claudiu Beznea <claudiu.beznea.uj@bp.renesas.com> # on RZ/G3S
Link: https://lore.kernel.org/r/20240530173857.164073-8-prabhakar.mahadev-lad.rj@bp.renesas.com
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
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On RZ/V2H(P) SoC, the power registers for SD and ETH do not exist,
resulting in invalid register offsets. Ensure that the register offsets
are valid before any read/write operations are performed. If the power
registers are not available, both SD and ETH will be set to '0'.
Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
Tested-by: Claudiu Beznea <claudiu.beznea.uj@bp.renesas.com> # on RZ/G3S
Link: https://lore.kernel.org/r/20240530173857.164073-7-prabhakar.mahadev-lad.rj@bp.renesas.com
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
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Enable parsing of variable configuration for all architectures. This
prepares for adding support for the RZ/V2H SoC, which utilizes the ARM64
architecture and features port pins with variable configuration.
Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
Tested-by: Claudiu Beznea <claudiu.beznea.uj@bp.renesas.com> # on RZ/G3S
Link: https://lore.kernel.org/r/20240530173857.164073-6-prabhakar.mahadev-lad.rj@bp.renesas.com
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
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Drop the rzg2l_variable_pin_cfg struct and instead use the
RZG2L_VARIABLE_PIN_CFG_PACK() macro for the variable pin configuration.
Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
Tested-by: Claudiu Beznea <claudiu.beznea.uj@bp.renesas.com> # on RZ/G3S
Link: https://lore.kernel.org/r/20240530173857.164073-5-prabhakar.mahadev-lad.rj@bp.renesas.com
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
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The pin configuration bits have been growing for every new SoCs being
added for the pinctrl-rzg2l driver which would mean updating the macros
every time for each new configuration. To avoid this allocate additional
bits for pin configuration by relocating the known fixed bits to the very
end of the configuration.
Also update the size of 'cfg' to 'u64' to allow more configuration bits
in the 'struct rzg2l_variable_pin_cfg'.
Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
Tested-by: Claudiu Beznea <claudiu.beznea.uj@bp.renesas.com> # on RZ/G3S
Link: https://lore.kernel.org/r/20240530173857.164073-4-prabhakar.mahadev-lad.rj@bp.renesas.com
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
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Use the scoped variant of for_each_child_of_node() to simplify the code.
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Link: https://lore.kernel.org/r/c0a28f466c42d5d59c7fadfa1fd05fd512d43b6f.1717060708.git.geert+renesas@glider.be
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Use scope based of_node_put() cleanup to simplify code.
Signed-off-by: Peng Fan <peng.fan@nxp.com>
Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
Link: https://lore.kernel.org/r/20240504-pinctrl-cleanup-v2-7-26c5f2dc1181@nxp.com
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
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On PREEMPT_RT kernels the spinlock_t maps to an rtmutex. Using
raw_spin_lock_irqsave()/raw_spin_unlock_irqrestore() on
&pctrl->lock.rlock breaks the PREEMPT_RT builds. To fix this use
spin_lock_irqsave()/spin_unlock_irqrestore() on &pctrl->lock.
Fixes: 02cd2d3be1c3 ("pinctrl: renesas: rzg2l: Configure the interrupt type on resume")
Reported-by: Diederik de Haas <didi.debian@cknow.org>
Closes: https://lore.kernel.org/all/131999629.KQPSlr0Zke@bagend
Signed-off-by: Claudiu Beznea <claudiu.beznea.uj@bp.renesas.com>
Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
Link: https://lore.kernel.org/r/20240522055421.2842689-1-claudiu.beznea.uj@bp.renesas.com
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
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git://git.kernel.org/pub/scm/linux/kernel/git/lee/mfd
Pull MFD updates from Lee Jones:
"New Device Support:
- Add support for X-Powers AXP717 PMIC to AXP22X
- Add support for Rockchip RK816 PMIC to RK8XX
- Add support for TI TPS65224 PMIC to TPS6594
New Functionality:
- Add Power Off functionality to Rohm BD71828
- Allow I2C SMBus access in Renesas RSMU
Fix-ups:
- Device Tree binding adaptions/conversions/creation
- Shift Intel support over to MSI interrupts
- Generify adding platform data away from being ACPI specific
- Use device core supplied attribute to register sysfs entries
- Replace hand-rolled functionality with generic APIs
- Utilise centrally provided helpers and macros
- Clean-up error handling
- Remove superfluous/duplicated/unused sections
- Trivial; spelling, whitespace, coding-style adaptions
- More Maple Tree conversions"
* tag 'mfd-next-6.10' of git://git.kernel.org/pub/scm/linux/kernel/git/lee/mfd: (44 commits)
dt-bindings: mfd: Use full path to other schemas
mfd: rsmu: support I2C SMBus access
dt-bindings: mfd: Convert lp873x.txt to json-schema
dt-bindings: mfd: aspeed: Drop 'oneOf' for pinctrl node
dt-bindings: mfd: allwinner,sun6i-a31-prcm: Use hyphens in node names
mfd: ssbi: Remove unused field 'slave' from 'struct ssbi'
mfd: kempld: Remove custom DMI matching code
mfd: cs42l43: Update patching revision check
dt-bindings: mfd: qcom: pm8xxx: Add pm8901 compatible
mfd: timberdale: Remove redundant assignment to variable err
dt-bindings: mfd: qcom,spmi-pmic: Add pbs to SPMI device types
dt-bindings: mfd: syscon: Add ti,am62p-cpsw-mac-efuse compatible
dt-bindings: mfd: qcom,tcsr: Add compatible for SDX75
mfd: axp20x: Convert to use Maple Tree register cache
mfd: bd71828: Remove commented code lines
mfd: intel-m10-bmc: Change staging size to a variable
dt-bindings: mfd: Add ROHM BD71879
mfd: Tidy Kconfig dependency's parentheses
mfd: ocelot-spi: Use spi_sync_transfer()
dt-bindings: mfd: syscon: Add missing simple syscon compatibles
...
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git://git.kernel.org/pub/scm/linux/kernel/git/linusw/linux-pinctrl
Pull pin control updates from Linus Walleij:
"Core changes:
- Use DEFINE_SHOW_STORE_ATTRIBUTE() in debugfs entries
New drivers:
- Qualcomm PMIH0108, PMD8028, PMXR2230 and PM6450 pin control support
Improvements:
- Serious cleanup of the recently merged aw9523 driver
- Fix PIN_CONFIG_BIAS_DISABLE handling in pinctrl-single
- A slew of device tree binding cleanups
- Support a bus clock in the Samsung driver"
* tag 'pinctrl-v6.10-1' of git://git.kernel.org/pub/scm/linux/kernel/git/linusw/linux-pinctrl: (48 commits)
pinctrl: bcm2835: Make pin freeing behavior configurable
dt-bindings: pinctrl: qcom,pmic-gpio: Fix "comptaible" typo for PMIH0108
pinctrl: qcom: pinctrl-sm7150: Fix sdc1 and ufs special pins regs
dt-bindings: pinctrl: mediatek: mt7622: add "antsel" function
dt-bindings: pinctrl: mediatek: mt7622: fix array properties
pinctrl: samsung: drop redundant drvdata assignment
pinctrl: samsung: support a bus clock
dt-bindings: pinctrl: samsung: google,gs101-pinctrl needs a clock
pinctrl: renesas: rzg2l: Limit 2.5V power supply to Ethernet interfaces
pinctrl: renesas: r8a779h0: Add INTC-EX pins, groups, and function
pinctrl: renesas: r8a779h0: Fix IRQ suffixes
pinctrl: renesas: rzg2l: Remove extra space in function parameter
dt-bindings: pinctrl: qcom,pmic-mpp: add support for PM8901
pinctrl: pinconf-generic: print hex value
pinctrl: realtek: fix module autoloading
pinctrl: qcom: sm7150: fix module autoloading
pinctrl: loongson2: fix module autoloading
pinctrl: mediatek: fix module autoloading
pinctrl: freescale: imx8ulp: fix module autoloading
dt-bindings: pinctrl: qcom,pmic-gpio: Allow gpio-hog nodes
...
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git://git.kernel.org/pub/scm/linux/kernel/git/brgl/linux
Pull gpio updates from Bartosz Golaszewski
"This was a quiet release cycle for the GPIO tree and so this
pull-request is relatively small.
We have one new driver, some minor improvements to the GPIO core code
and across several drivers, some DT and documentation updates but in
general nothing stands out or is controversial. All changes have spent
time in next with no reported issues (or ones that were quickly
fixed).
GPIO core:
- remove more unused legacy interfaces (after converting the last
remaining users to better alternatives)
- update kerneldocs
- improve error handling and log messages in GPIO ACPI code
- remove dead code (always true checks) from GPIOLIB
New drivers:
- add a driver for Intel Granite Rapids-D vGPIO
Driver improvements:
- use -ENOTSUPP consistently in gpio-regmap and gpio-pcie-idio-24
- provide an ID table for gpio-cros-ec to avoid a driver name
fallback check
- add support for gpio-ranges for GPIO drivers supporting multiple
GPIO banks
- switch to using dynamic GPIO base in gpio-brcmstb
- fix irq handling in gpio-npcm-sgpio
- switch to memory mapped IO accessors in gpio-sch
DT bindings:
- add support for gpio-ranges to gpio-brcmstb
- add support for a new model and the gpio-line-names property to
gpio-mpfs
Documentation:
- replace leading tabs with spaces in code blocks
- fix typos"
* tag 'gpio-updates-for-v6.10-rc1' of git://git.kernel.org/pub/scm/linux/kernel/git/brgl/linux: (30 commits)
gpio: nuvoton: Fix sgpio irq handle error
gpiolib: Discourage to use formatting strings in line names
gpio: brcmstb: add support for gpio-ranges
gpio: of: support gpio-ranges for multiple gpiochip devices
dt-bindings: gpio: brcmstb: add gpio-ranges
gpio: Add Intel Granite Rapids-D vGPIO driver
gpio: brcmstb: Use dynamic GPIO base numbers
gpiolib: acpi: Set label for IRQ only lines
gpiolib: acpi: Add fwnode name to the GPIO interrupt label
gpiolib: Get rid of never false gpio_is_valid() calls
gpiolib: acpi: Pass con_id instead of property into acpi_dev_gpio_irq_get_by()
gpiolib: acpi: Move acpi_can_fallback_to_crs() out of __acpi_find_gpio()
gpiolib: acpi: Simplify error handling in __acpi_find_gpio()
gpiolib: acpi: Extract __acpi_find_gpio() helper
gpio: sch: Utilise temporary variable for struct device
gpio: sch: Switch to memory mapped IO accessors
gpio: regmap: Use -ENOTSUPP consistently
gpio: pcie-idio-24: Use -ENOTSUPP consistently
Documentation: gpio: Replace leading TABs by spaces in code blocks
gpiolib: acpi: Check for errors first in acpi_find_gpio()
...
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git://git.kernel.org/pub/scm/linux/kernel/git/soc/soc
Pull SoC driver updates from Arnd Bergmann:
"As usual, these are updates for drivers that are specific to certain
SoCs or firmware running on them.
Notable updates include
- The new STMicroelectronics STM32 "firewall" bus driver that is used
to provide a barrier between different parts of an SoC
- Lots of updates for the Qualcomm platform drivers, in particular
SCM, which gets a rewrite of its initialization code
- Firmware driver updates for Arm FF-A notification interrupts and
indirect messaging, SCMI firmware support for pin control and
vendor specific interfaces, and TEE firmware interface changes
across multiple TEE drivers
- A larger cleanup of the Mediatek CMDQ driver and some related bits
- Kconfig changes for riscv drivers to prepare for adding Kanaan k230
support
- Multiple minor updates for the TI sysc bus driver, memory
controllers, hisilicon hccs and more"
* tag 'soc-drivers-6.10' of git://git.kernel.org/pub/scm/linux/kernel/git/soc/soc: (103 commits)
firmware: qcom: uefisecapp: Allow on sc8180x Primus and Flex 5G
soc: qcom: pmic_glink: Make client-lock non-sleeping
dt-bindings: soc: qcom,wcnss: fix bluetooth address example
soc/tegra: pmc: Add EQOS wake event for Tegra194 and Tegra234
bus: stm32_firewall: fix off by one in stm32_firewall_get_firewall()
bus: etzpc: introduce ETZPC firewall controller driver
firmware: arm_ffa: Avoid queuing work when running on the worker queue
bus: ti-sysc: Drop legacy idle quirk handling
bus: ti-sysc: Drop legacy quirk handling for smartreflex
bus: ti-sysc: Drop legacy quirk handling for uarts
bus: ti-sysc: Add a description and copyrights
bus: ti-sysc: Move check for no-reset-on-init
soc: hisilicon: kunpeng_hccs: replace MAILBOX dependency with PCC
soc: hisilicon: kunpeng_hccs: Add the check for obtaining complete port attribute
firmware: arm_ffa: Fix memory corruption in ffa_msg_send2()
bus: rifsc: introduce RIFSC firewall controller driver
of: property: fw_devlink: Add support for "access-controller"
soc: mediatek: mtk-socinfo: Correct the marketing name for MT8188GV
soc: mediatek: mtk-socinfo: Add entry for MT8395AV/ZA Genio 1200
soc: mediatek: mtk-mutex: Add support for MT8188 VPPSYS
...
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'ib-mfd-pinctrl-regulator-6.10' and 'ib-mfd-regulator-6.10' into ibs-for-mfd-merged
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https://git.kernel.org/pub/scm/linux/kernel/git/conor/linux into soc/drivers
RISC-V SoC Kconfig Updates for v6.10
A few different bits of SoC-related Kconfig work. The first part of
this is shared with the DT updates - the modification of all SOC_CANAAN
users to SOC_CANAAN_K210 to split the existing m-mode nommu k210 away
from the k230 that is able to be used in a "common" kernel.
The other thing here is the removal of most of the SOC_VENDOR options,
with their ARCH_VENDOR equivalents that've been waiting in the wings for
1 year+ now made visible. Due a lapse on my part when originally adding
the ARCH_VENDOR stuff, the Microchip transition isn't complete - the
_POLARFIRE was a mistake to keep as there's gonna be non-PolarFire
RISC-V stuff from Microchip soonTM.
Signed-off-by: Conor Dooley <conor.dooley@microchip.com>
* tag 'riscv-config-for-v6.10' of https://git.kernel.org/pub/scm/linux/kernel/git/conor/linux:
riscv: config: enable ARCH_CANAAN in defconfig
RISC-V: drop SOC_VIRT for ARCH_VIRT
RISC-V: drop SOC_SIFIVE for ARCH_SIFIVE
RISC-V: drop SOC_MICROCHIP_POLARFIRE for ARCH_MICROCHIP
RISC-V: Drop unused SOC_CANAAN
reset: k210: Deprecate SOC_CANAAN and use SOC_CANAAN_K210
pinctrl: k210: Deprecate SOC_CANAAN and use SOC_CANAAN_K210
clk: k210: Deprecate SOC_CANAAN and use SOC_CANAAN_K210
soc: canaan: Deprecate SOC_CANAAN and use SOC_CANAAN_K210 for K210
riscv: Kconfig.socs: Split ARCH_CANAAN and SOC_CANAAN_K210
Link: https://lore.kernel.org/r/20240503-mardi-underling-3d81a9f97329@spud
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
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git://git.kernel.org/pub/scm/linux/kernel/git/andy/linux-gpio-intel into gpio/for-next
intel-gpio for v6.10-1
* New driver for vGPIO controller on Intel Granite Rapids-D
* Update ACPI GPIO library to unify the IRQ code path
* Better GPIO IRQ line labeling for ACPI
* Switched Intel SCH driver to use "mapped" I/O accessors
The following is an automated git shortlog grouped by driver:
Add Intel Granite Rapids-D vGPIO driver:
- Add Intel Granite Rapids-D vGPIO driver
crystalcove:
- Use -ENOTSUPP consistently
gpiolib:
- acpi: Set label for IRQ only lines
- acpi: Add fwnode name to the GPIO interrupt label
- acpi: Pass con_id instead of property into acpi_dev_gpio_irq_get_by()
- acpi: Move acpi_can_fallback_to_crs() out of __acpi_find_gpio()
- acpi: Simplify error handling in __acpi_find_gpio()
- acpi: Extract __acpi_find_gpio() helper
- acpi: Check for errors first in acpi_find_gpio()
- acpi: Remove never true check in acpi_get_gpiod_by_index()
sch:
- Utilise temporary variable for struct device
- Switch to memory mapped IO accessors
wcove:
- Use -ENOTSUPP consistently
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https://git.kernel.org/pub/scm/linux/kernel/git/pinctrl/samsung into devel
Samsung pinctrl drivers changes for v6.10
1. Add support for toggling bus clock (PCLK) for any pin controller
register accesses. This looks needed on newer Samsung chips, like
Google GS101 and probably Exynos850.
2. Drop old, deprecated in v6.1 bindings header with register constants.
The constants were moved to DTS headers.
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
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Until now after a bcm2835 pin was freed its pinmux was set to GPIO_IN.
So in case it was configured as GPIO_OUT before the configured output
level also get lost. As long as GPIO sysfs was used this wasn't
actually a problem because the pins and their possible output level
were kept by sysfs.
Since more and more Raspberry Pi users start using libgpiod they are
confused about this behavior. So make the pin freeing behavior of
GPIO_OUT configurable via module parameter. In case
pinctrl-bcm2835.persist_gpio_outputs is set to 1, the output level is
kept.
This patch based on the downstream work of Phil Elwell.
Link: https://github.com/raspberrypi/linux/pull/6117
Signed-off-by: Stefan Wahren <wahrenst@gmx.net>
Message-ID: <20240503062745.11298-1-wahrenst@gmx.net>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
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Add support for TPS65224 pinctrl and GPIOs to TPS6594 driver as they have
significant functional overlap.
TPS65224 PMIC has 6 GPIOS which can be configured as GPIO or other
dedicated device functions.
Signed-off-by: Nirmala Devi Mal Nadar <m.nirmaladevi@ltts.com>
Signed-off-by: Bhargav Raviprakash <bhargav.r@ltts.com>
Acked-by: Linus Walleij <linus.walleij@linaro.org>
Link: https://lore.kernel.org/r/0109018f2fdce15d-c13bd809-a11b-4202-9b7f-c9380d51b070-000000@ap-south-1.amazonses.com
Signed-off-by: Lee Jones <lee@kernel.org>
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This adds support for RK816 to the exising rk805 pinctrl driver
It has a single pin which can be configured as input from a thermistor (for
instance in an attached battery) or as a gpio.
Signed-off-by: Alex Bee <knaerzche@gmail.com>
Reviewed-by: Linus Walleij <linus.walleij@linaro.org>
Link: https://lore.kernel.org/r/20240416161237.2500037-4-knaerzche@gmail.com
Signed-off-by: Lee Jones <lee@kernel.org>
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SDC1 and UFS_RESET special pins are located in the west memory bank.
SDC1 have address 0x359a000:
0x3500000 (TLMM BASE) + 0x0 (WEST) + 0x9a000 (SDC1_OFFSET) = 0x359a000
UFS_RESET have address 0x359f000:
0x3500000 (TLMM BASE) + 0x0 (WEST) + 0x9f000 (UFS_OFFSET) = 0x359a000
Fixes: b915395c9e04 ("pinctrl: qcom: Add SM7150 pinctrl driver")
Signed-off-by: Danila Tikhonov <danila@jiaxyga.com>
Message-ID: <20240423203245.188480-1-danila@jiaxyga.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
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git://git.kernel.org/pub/scm/linux/kernel/git/linusw/linux-pinctrl
Pull pin control fixes from Linus Walleij:
- Fix a double-free in the pinctrl_enable() errorpath
- Fix a refcount leak in pinctrl_dt_to_map()
- Fix selecting the GPIO pin control state and the UART3 pin config
group in the Intel Baytrail driver
- Fix readback of schmitt trigger status in the Mediatek Paris driver,
along with some semantic pin config issues in this driver
- Fix a pin suffix typo in the Meson A1 driver
- Fix an erroneous register offset in he Aspeed G6 driver
- Fix an inconsistent lock state and the interrupt type on resume in
the Renesas RZG2L driver
- Fix some minor confusion in the Renesas DT bindings
* tag 'pinctrl-v6.9-2' of git://git.kernel.org/pub/scm/linux/kernel/git/linusw/linux-pinctrl:
pinctrl: renesas: rzg2l: Configure the interrupt type on resume
pinctrl: devicetree: fix refcount leak in pinctrl_dt_to_map()
pinctrl: baytrail: Add pinconf group for uart3
pinctrl: baytrail: Fix selecting gpio pinctrl state
pinctrl: mediatek: paris: Rework support for PIN_CONFIG_{INPUT,OUTPUT}_ENABLE
pinctrl: mediatek: paris: Fix PIN_CONFIG_INPUT_SCHMITT_ENABLE readback
pinctrl: core: delete incorrect free in pinctrl_enable()
pinctrl/meson: fix typo in PDM's pin name
pinctrl: pinctrl-aspeed-g6: Fix register offset for pinconf of GPIOR-T
pinctrl: renesas: rzg2l: Execute atomically the interrupt configuration
dt-bindings: pinctrl: renesas,rzg2l-pinctrl: Allow 'input' and 'output-enable' properties
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Fix W=1 warning:
drivers/pinctrl/samsung/pinctrl-samsung.c: In function ‘samsung_gpio_set_direction’:
drivers/pinctrl/samsung/pinctrl-samsung.c:633:42: warning: variable ‘drvdata’ set but not used [-Wunused-but-set-variable]
Fixes: f9c744747973 ("pinctrl: samsung: support a bus clock")
Reported-by: kernel test robot <lkp@intel.com>
Closes: https://lore.kernel.org/oe-kbuild-all/202404300825.6lxLwvUY-lkp@intel.com/
Reviewed-by: André Draszik <andre.draszik@linaro.org>
Link: https://lore.kernel.org/r/20240430060304.12332-1-krzysztof.kozlowski@linaro.org
Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
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git://git.kernel.org/pub/scm/linux/kernel/git/sudeep.holla/linux into soc/drivers
Arm SCMI updates for v6.10
1. Basic support for SCMI v3.2 pincontrol protocol
SCMI v3.2 introduces pincontrol protocol which is intended for
controlling pins and their configuration. The pin control protocol
provides commands to:
- List the pins, groups of pins, available functions, and their
association with each other.
- Set the parameter configuration and multiplexing of the pins or
groups of pins
- Optionally request exclusive access to a pin or group of pins.
- Optionally configure the permissions of an agent to access a pin
or group of pins.
These changes adds basic support for the same in the SCMI core layer
and an implementation of the generic scmi-pinctrl driver with associated
DT bindings.
2. Framework support for multiple vendors custom protocols
With the fixed space for vendor protocols, the possibility of having
multiple vendors implementing distinct SCMI vendor protocols with
the same overlapping protocol number is very high and with the need
to support them all in a single kernel image or a module is also high.
In order to implement the same we assume:
- vendor protocols has to be tagged at build time with a vendor_id
- vendor protocols could also optionally be tagged at build time with
sub_vendor_id and implementation version
At the initialisation all the built vendor protocols are registered
with the SCMI core using a key derived from the above tags
3. Logging and tracing improvements
This includes using dev_err_probe() to bail out from probe, adding
message dump traces for bad and unexpected replies and widening of
the tag buffer in trace_scmi_dump_msg to allow diverse tag names
4. Miscellaneous updates or improvements
This includes adding the accessor function get_max_msg_size() used
in pinctl protocol, updation of dt-bindings examples for protocol@13
to promote new bindings and simplification of scmi_devm_notifier_unregister
* tag 'scmi-updates-6.10' of git://git.kernel.org/pub/scm/linux/kernel/git/sudeep.holla/linux:
pinctrl: Implementation of the generic scmi-pinctrl driver
firmware: arm_scmi: Add basic support for SCMI v3.2 pincontrol protocol
dt-bindings: firmware: Support SCMI pinctrl protocol
firmware: arm_scmi: Introduce get_max_msg_size() helper/accessor
firmware: arm_scmi: Add support for multiple vendors custom protocols
dt-bindings: firmware: arm,scmi: Update examples for protocol@13
firmware: arm_scmi: Avoid non-constant printk format strings
firmware: arm_scmi: Use dev_err_probe to bail out
firmware: arm_scmi: Simplify scmi_devm_notifier_unregister
firmware: arm_scmi: Add message dump traces for bad and unexpected replies
firmware: arm_scmi: Add helper to trace bad messages
include: trace: Widen the tag buffer in trace_scmi_dump_msg
firmware: arm_scmi: Log the perf domain names in the error paths
Link: https://lore.kernel.org/r/20240426105031.1526987-1-sudeep.holla@arm.com
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
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On some Samsung-based SoCs there are separate bus clocks / gates each
for each pinctrl instance. To be able to access each pinctrl instance's
registers, this bus clock needs to be running, otherwise register
access will hang. Google Tensor gs101 is one example for such an
implementation.
Update the driver to handle this optional bus clock:
* handle an optional bus clock from DT
* prepare it during driver probe
* enclose all relevant register accesses with a clock enable & disable
Signed-off-by: André Draszik <andre.draszik@linaro.org>
Link: https://lore.kernel.org/r/20240426-samsung-pinctrl-busclock-v3-2-adb8664b8a7e@linaro.org
Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
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git://git.kernel.org/pub/scm/linux/kernel/git/geert/renesas-drivers into devel
pinctrl: renesas: Updates for v6.10
- Add external interrupt pin groups on R-Car V4M,
- Miscellaneous fixes and improvements.
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
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git://git.kernel.org/pub/scm/linux/kernel/git/pinctrl/intel into fixes
intel-pinctrl for v6.9-1
* Correct GPIO selection and add UART3 pins for Intel Bay Trail
The following is an automated git shortlog grouped by driver:
baytrail:
- Add pinconf group for uart3
- Fix selecting gpio pinctrl state
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
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git://git.kernel.org/pub/scm/linux/kernel/git/geert/renesas-drivers into fixes
pinctrl: renesas: Fixes for v6.9 (take two)
- Fix interrupt configuration on RZ/G2L after s2ram.
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
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The RZ/G3S SoC supports configurable supply voltages for several of its
I/O interfaces. All of these interfaces support both 1.8V and 3.3V
supplies, but only the Ethernet and XSPI interfaces support a 2.5V
supply.
Voltage selection for the XSPI interface is not yet supported, so this
leaves only the Ethernet interfaces currently supporting selection of a
2.5V supply. So we need to return an error if there is an attempt to
select a 2.5V supply for any non-Ethernet interface.
Fixes: 51996952b8b5 ("pinctrl: renesas: rzg2l: Add support to select power source for Ethernet pins")
Signed-off-by: Paul Barker <paul.barker.ct@bp.renesas.com>
Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
Link: https://lore.kernel.org/r/20240417114132.6605-1-paul.barker.ct@bp.renesas.com
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
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Add pins, groups, and function for the Interrupt Controller for External
Devices (INTC-EX) on the Renesas R-Car V4M (R8A779H0) SoC.
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Link: https://lore.kernel.org/r/258d03b27b77f60cc03fc3257bb4c6715b612a61.1713282028.git.geert+renesas@glider.be
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The suffixes of the IRQ identifiers, as used for pins related to the
Interrupt Controller for External Devices (INTC-EX), are inconsistent.
Correct them to match the Pin Multiplex attachment in Rev.0.51 of the
R-Car V4M Series Hardware User's Manual.
Fixes: 291f7856fc451cbe ("pinctrl: renesas: Initial R8A779H0 (R-Car V4M) PFC support")
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Link: https://lore.kernel.org/r/7d3c7498d9e8eda5583b15f9163eb25bb797ed24.1713282028.git.geert+renesas@glider.be
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Remove unnecessary space in rzg2l_pinctrl_pm_setup_pfc() function
parameter.
Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
Link: https://lore.kernel.org/r/20240226192530.141945-1-prabhakar.mahadev-lad.rj@bp.renesas.com
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
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