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2021-04-21mt76: introduce single-sku support for mt7663/mt7921Lorenzo Bianconi
Introduce support for rate-txpower compensation for mt7663/mt7921 chipsets. Rate-txpower limit is specified through dts Signed-off-by: Lorenzo Bianconi <lorenzo@kernel.org> Signed-off-by: Felix Fietkau <nbd@nbd.name>
2021-04-21mt76: mt7615: do not use mt7615 single-sku values for mt7663Lorenzo Bianconi
mt7663 mcu relies on different APIs to configure APIs per-rate power limit respect to mt7615 driver. Signed-off-by: Lorenzo Bianconi <lorenzo@kernel.org> Signed-off-by: Felix Fietkau <nbd@nbd.name>
2021-04-21mt76: mt7615: implement support for using DT rate power limitsFelix Fietkau
Limits are used to update the channel max_power settings and also passed to the firmware on channel changes Signed-off-by: Felix Fietkau <nbd@nbd.name> Signed-off-by: Lorenzo Bianconi <lorenzo@kernel.org> Signed-off-by: Felix Fietkau <nbd@nbd.name>
2021-04-21mt76: extend DT rate power limits to support 11ax devicesShayne Chen
Enable parsing per-rate txpower limits from DT for 11ax chipsets. Co-developed-by: Felix Fietkau <nbd@nbd.name> Signed-off-by: Felix Fietkau <nbd@nbd.name> Tested-by: Evelyn Tsai <evelyn.tsai@mediatek.com> Signed-off-by: Shayne Chen <shayne.chen@mediatek.com> Signed-off-by: Lorenzo Bianconi <lorenzo@kernel.org> Signed-off-by: Felix Fietkau <nbd@nbd.name>
2021-04-21mt76: add functions for parsing rate power limits from DTFelix Fietkau
This subnode can be used to set per-rate tx power limits either per country code / regdomain or globally. These limits are typically provided by the device manufacturers and are used to limit sideband emissions and stay within regulatory limits Signed-off-by: Felix Fietkau <nbd@nbd.name> Signed-off-by: Lorenzo Bianconi <lorenzo@kernel.org> Signed-off-by: Felix Fietkau <nbd@nbd.name>
2021-04-21mt76: flush tx status queue on DMA resetFelix Fietkau
After DMA reset, tx status information for queued frames will never arrive. Flush the queue to free skbs immediately instead of waiting for a timeout Signed-off-by: Felix Fietkau <nbd@nbd.name>
2021-04-21mt76: mt7921: add mt7921_dma_cleanup in mt7921_unregister_deviceLorenzo Bianconi
In order to avoid memory leaks, clean the dma engine unloading the module Signed-off-by: Lorenzo Bianconi <lorenzo@kernel.org> Signed-off-by: Felix Fietkau <nbd@nbd.name>
2021-04-21mt76: mt7615: use ieee80211_free_txskb() in mt7615_tx_token_put()Ryder Lee
We should use ieee80211_free_txskb() to report skb status avoid wrong aql accounting after reset. Cc: stable@vger.kernel.org Signed-off-by: Ryder Lee <ryder.lee@mediatek.com> Signed-off-by: Felix Fietkau <nbd@nbd.name>
2021-04-21mt76: mt7615: only free skbs after mt7615_dma_reset() when reset happensRyder Lee
In mt7615_mac_reset_work(), make sure freeing skbs after mt7615_dma_reset(). Signed-off-by: Ryder Lee <ryder.lee@mediatek.com> Signed-off-by: Felix Fietkau <nbd@nbd.name>
2021-04-21mt76: mt7915: only free skbs after mt7915_dma_reset() when reset happensRyder Lee
In mt7915_mac_reset_work(), make sure freeing skbs after mt7915_dma_reset(). Signed-off-by: Ryder Lee <ryder.lee@mediatek.com> Signed-off-by: Felix Fietkau <nbd@nbd.name>
2021-04-21mt76: mt7915: fix memleak when mt7915_unregister_device()Ryder Lee
mt7915_tx_token_put() should get call before mt76_free_pending_txwi(). Fixes: f285dfb98562 ("mt76: mt7915: reset token when mac_reset happens") Signed-off-by: Ryder Lee <ryder.lee@mediatek.com> Signed-off-by: Felix Fietkau <nbd@nbd.name>
2021-04-21mt76: mt7615: fix memleak when mt7615_unregister_device()Ryder Lee
mt7615_tx_token_put() should get call before mt76_free_pending_txwi(). Fixes: a6275e934605 ("mt76: mt7615: reset token when mac_reset happens") Signed-off-by: Ryder Lee <ryder.lee@mediatek.com> Signed-off-by: Felix Fietkau <nbd@nbd.name>
2021-04-21mt76: mt7915: fix rate setting of tx descriptor in testmodeShayne Chen
Fix ofdm rate index and ldpc setting in rate setting field of tx descriptor. Signed-off-by: Shayne Chen <shayne.chen@mediatek.com> Signed-off-by: Felix Fietkau <nbd@nbd.name>
2021-04-21mt76: mt7915: rework mt7915_tm_set_tx_len()Shayne Chen
Rework mt7915_tm_set_tx_len() with mt76_testmode_alloc_skb() to support larger packet based on a longer tx_time. Signed-off-by: Shayne Chen <shayne.chen@mediatek.com> Signed-off-by: Felix Fietkau <nbd@nbd.name>
2021-04-21mt76: testmode: add support to send larger packetShayne Chen
Add support to send larger packet in testmode to meet requirements of some test cases. The limit of max packet size is determined based on tx rate mode setting. Signed-off-by: Shayne Chen <shayne.chen@mediatek.com> Signed-off-by: Felix Fietkau <nbd@nbd.name>
2021-04-21rtlwifi: implement set_tim by update beacon contentPing-Ke Shih
Once beacon content is changed, we update the content to wifi card by send_beacon_frame(). Then, STA with PS can wake up properly to receive its packets. Since we update beacon content to PCI wifi devices every beacon interval, the only one usb device, 8192CU, needs to update beacon content when mac80211 calling set_tim. Reported-by: Maciej S. Szmigiero <mail@maciej.szmigiero.name> Signed-off-by: Ping-Ke Shih <pkshih@realtek.com> Tested-by: Maciej S. Szmigiero <mail@maciej.szmigiero.name> Signed-off-by: Kalle Valo <kvalo@codeaurora.org> Link: https://lore.kernel.org/r/20210419065956.6085-1-pkshih@realtek.com
2021-04-21libertas_tf: Remove duplicate struct declarationWan Jiabing
struct lbtf_private is declared twice. One has been declared at 157th line. Remove the duplicate. Signed-off-by: Wan Jiabing <wanjiabing@vivo.com> Signed-off-by: Kalle Valo <kvalo@codeaurora.org> Link: https://lore.kernel.org/r/20210331023557.2804128-4-wanjiabing@vivo.com
2021-04-21rtw88: refine napi deinit flowPo-Hao Huang
We used to stop napi before disabling irqs. And it turns out to cause some problem when we try to stop device while interrupt arrives. To safely stop pci, we do three steps: 1. disable interrupt 2. synchronize_irq 3. stop_napi Since step 2 and 3 may not finish as expected when interrupt is enabled, use rtwpci->running to decide whether interrupt should be re-enabled at the time. Fixes: 9e2fd29864c5 ("rtw88: add napi support") Signed-off-by: Po-Hao Huang <phhuang@realtek.com> Signed-off-by: Ping-Ke Shih <pkshih@realtek.com> Signed-off-by: Kalle Valo <kvalo@codeaurora.org> Link: https://lore.kernel.org/r/20210415084703.27255-4-pkshih@realtek.com
2021-04-21rtw88: Fix potential unrecoverable tx queue stopYu-Yen Ting
If there are lots of packets to be transmitted, the driver would check whether the available descriptors are sufficient according the read/write point of tx queue. Once the available descriptor is not enough, ieee80211_stop_queue is called. TX ISR, meanwhile, is releasing the tx resources after the packets are transmitted. This routine may call ieee80211_wake_queue by checking the available descriptor. The potential queue stop problem would occur when the tx queue is stopped due to the heavy traffic. Then thare is no chance to wake the queue up because the read point is not updated immediately, as a result, no more packets coulde be transmitted in this queue. This patch makes sure the ieee80211_wake_queue could be called properly and avoids the race condition when ring->r.rp, ring->queue_stopped are updated. Signed-off-by: Yu-Yen Ting <steventing@realtek.com> Signed-off-by: Ping-Ke Shih <pkshih@realtek.com> Signed-off-by: Kalle Valo <kvalo@codeaurora.org> Link: https://lore.kernel.org/r/20210415084703.27255-3-pkshih@realtek.com
2021-04-21rtw88: 8821c: Don't set RX_FLAG_DECRYPTED if packet has no encryptionGuo-Feng Fan
The value of GET_RX_DESC_SWDEC() indicates that if this RX packet requires software decryption or not. And software decryption is required when the packet was encrypted and the hardware failed to decrypt it. So, GET_RX_DESC_SWDEC() is negative does not mean that this packet is decrypted, it might just have no encryption at all. To actually see if the packet is decrypted, driver needs to further check if the hardware has successfully decrypted it, with a specific type of encryption algorithm. Signed-off-by: Guo-Feng Fan <vincent_fann@realtek.com> Signed-off-by: Ping-Ke Shih <pkshih@realtek.com> Signed-off-by: Kalle Valo <kvalo@codeaurora.org> Link: https://lore.kernel.org/r/20210415084703.27255-2-pkshih@realtek.com
2021-04-21rtw88: 8822c: debug: allow debugfs to enable/disable TXGAPKGuo-Feng Fan
Use "cat dm_cap" to show all features; where, prefix +/- means feature is enabled/disabled: $ cat dm_cap DM capability 0x00000002 ( 1) +TXGAPK To control dm_cap: use "echo +1 > dm_cap" to enable TXGAPK use "echo -1 > dm_cap" to disable TXGAPK Below is an example to disable TXGAPK. $ echo -1 > dm_cap $ cat dm_cap DM capability 0x00000000 ( 1) -TXGAPK Below is an example to show TXGAPK status $ echo 1 > dm_cap; cat dm_cap ( 1) +TXGAPK path 0: 0x56 = 0x88c89 [TXGAPK] offset 1 0 [TXGAPK] offset 1 1 [TXGAPK] offset 1 2 [TXGAPK] offset 1 3 [TXGAPK] offset 0 4 [TXGAPK] offset 0 5 [TXGAPK] offset 0 6 [TXGAPK] offset 0 7 [TXGAPK] offset 0 8 [TXGAPK] offset 0 9 path 1: 0x56 = 0x89c89 [TXGAPK] offset 1 0 [TXGAPK] offset 1 1 [TXGAPK] offset 1 2 [TXGAPK] offset 1 3 [TXGAPK] offset 0 4 [TXGAPK] offset 0 5 [TXGAPK] offset 0 6 [TXGAPK] offset 0 7 [TXGAPK] offset 0 8 [TXGAPK] offset 0 9 Signed-off-by: Guo-Feng Fan <vincent_fann@realtek.com> Signed-off-by: Ping-Ke Shih <pkshih@realtek.com> Signed-off-by: Kalle Valo <kvalo@codeaurora.org> Link: https://lore.kernel.org/r/20210419003748.3224-4-pkshih@realtek.com
2021-04-21rtw88: 8822c: Add gap-k calibration to improve long range performanceGuo-Feng Fan
gap-k is a calibration mechanism to eliminate power gaps between two nearly rate groups. This mechanism improves performance in long range test by applying proper power value to those rate groups which have nonlinear power gap. Signed-off-by: Guo-Feng Fan <vincent_fann@realtek.com> Signed-off-by: Ping-Ke Shih <pkshih@realtek.com> Signed-off-by: Kalle Valo <kvalo@codeaurora.org> Link: https://lore.kernel.org/r/20210419003748.3224-3-pkshih@realtek.com
2021-04-21rtw88: 8822c: reorder macro position according to the register numberGuo-Feng Fan
This patch doesn't change logic at all, just a refactor patch. 1. Move BIT MASK and BIT definition along with the register definition 2. Remove redundant definition 3. Align macros with Tab key Signed-off-by: Guo-Feng Fan <vincent_fann@realtek.com> Signed-off-by: Ping-Ke Shih <pkshih@realtek.com> Signed-off-by: Kalle Valo <kvalo@codeaurora.org> Link: https://lore.kernel.org/r/20210419003748.3224-2-pkshih@realtek.com
2021-04-21platform/chrome: cros_ec_lpc: Use DEFINE_MUTEX() for mutex lockYe Bin
mutex lock can be initialized automatically with DEFINE_MUTEX() rather than explicitly calling mutex_init(). Reported-by: Hulk Robot <hulkci@huawei.com> Signed-off-by: Ye Bin <yebin10@huawei.com> Signed-off-by: Enric Balletbo i Serra <enric.balletbo@collabora.com> Link: https://lore.kernel.org/r/20210409095138.2293869-1-yebin10@huawei.com
2021-04-21platform/chrome: cros_usbpd_notify: Listen to EC_HOST_EVENT_USB_MUX host eventPi-Hsun Shih
On system that use ACPI, cros_usbpd_notify gets notifications of USB MUX host event same as PD host events [1]. But currently on system that use DT, the driver only listen on EC_HOST_EVENT_PD_MCU. Add EC_HOST_EVENT_USB_MUX to the list of host events, so we have same behavior on all platforms. [1]: https://chromium.googlesource.com/chromiumos/third_party/coreboot/+/refs/heads/chromeos-2016.05/src/ec/google/chromeec/acpi/ec.asl#382 Signed-off-by: Pi-Hsun Shih <pihsun@chromium.org> Signed-off-by: Enric Balletbo i Serra <enric.balletbo@collabora.com> Link: https://lore.kernel.org/r/20210414064524.2450908-1-pihsun@chromium.org
2021-04-21platform/chrome: cros_ec_typec: Add DP mode checkPrashant Malani
There are certain transitional situations where the dp_mode field in the PD_CONTROL response might not be populated with the right DP pin assignment value yet. Add a check for that to avoid sending an invalid value to the Type C mode switch. Signed-off-by: Prashant Malani <pmalani@chromium.org> Signed-off-by: Enric Balletbo i Serra <enric.balletbo@collabora.com> Link: https://lore.kernel.org/r/20210421042108.2002-1-pmalani@chromium.org
2021-04-20drm/amdgpu/gmc9: remove dummy read workaround for newer chipsAlex Deucher
Aldebaran has a hw fix so no longer requires the workaround. Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2021-04-20drm/amdgpu: Add mem sync flag for IB allocated by SAJinzhou Su
The buffer of SA bo will be used by many cases. So it's better to invalidate the cache of indirect buffer allocated by SA before commit the IB. Signed-off-by: Jinzhou Su <Jinzhou.Su@amd.com> Reviewed-by: Christian König <christian.koenig@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2021-04-20drm/amdgpu: Fix SDMA RAS error reporting on AldebaranMukul Joshi
Fix the following issues with SDMA RAS error reporting: 1. Read the EDC_COUNTER2 register also to fetch error counts for all sub-blocks in SDMA. 2. SDMA RAS on Aldebaran suports single-bit uncorrectable errors only. So, report error count in UE count instead of CE count. Signed-off-by: Mukul Joshi <mukul.joshi@amd.com> Reviewed-By: John Clements <John.Clements@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2021-04-20drm/amdgpu: Reset RAS error count and status regsMukul Joshi
Reset the RAS error count and error status registers after reading to prevent over reporting error counts on Aldebaran. Signed-off-by: Mukul Joshi <mukul.joshi@amd.com> Reviewed-By: John Clements <John.Clements@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2021-04-20Revert "drm/amdgpu: workaround the TMR MC address issue (v2)"Oak Zeng
This reverts commit 2f055097daef498da57552f422f49de50a1573e6. 2f055097daef498da57552f422f49de50a1573e6 was a driver workaround when PSP firmware was not ready. Now the PSP fw is ready so we revert this driver workaround. Signed-off-by: Oak Zeng <Oak.Zeng@amd.com> Reviewed-by: Harish Kasiviswanathan <Harish.Kasiviswanathan@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2021-04-20drm/amd/display: 3.2.132Aric Cyr
Signed-off-by: Aric Cyr <aric.cyr@amd.com> Acked-by: Aurabindo Pillai <aurabindo.pillai@amd.com> Tested-by: Daniel Wheeler <daniel.wheeler@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2021-04-20drm/amd/display: [FW Promotion] Release 0.0.62Anthony Koo
Signed-off-by: Anthony Koo <Anthony.Koo@amd.com> Acked-by: Aurabindo Pillai <aurabindo.pillai@amd.com> Tested-by: Daniel Wheeler <daniel.wheeler@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2021-04-20drm/amd/display: add helper for enabling mst stream featuresBing Guo
[Why] Some MST devices uses different method to enable mst specific stream features. [How] Add dm_helpers_mst_enable_stream features. This can be modified later when we are ready to implement those features. Signed-off-by: Bing Guo <bing.guo@amd.com> Reviewed-by: Anthony Koo <Anthony.Koo@amd.com> Acked-by: Aurabindo Pillai <aurabindo.pillai@amd.com> Tested-by: Daniel Wheeler <daniel.wheeler@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2021-04-20drm/amd/display: Report Proper Quantization Range in AVI InfoframeDillon Varone
[Why?] When a monitor does not set both QS and QY bits, DC does not set Q0, Q1, QY0 and QY1 bits in AVI infoframe. Setting RGB bits should be separate from setting YCC bits. [How?] Separate logic for setting RGB and YCC quantization range bits in the AVI infoframe. Signed-off-by: Dillon Varone <dillon.varone@amd.com> Reviewed-by: Chris Park <Chris.Park@amd.com> Acked-by: Aurabindo Pillai <aurabindo.pillai@amd.com> Tested-by: Daniel Wheeler <daniel.wheeler@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2021-04-20drm/amd/display: Fix call to pass bpp in 16ths of a bitDillon Varone
[Why & How?] Call to dc_dsc_compute_bandwidth_range should have min and max bpp in 16ths of a bit. Multiply min and max bpp from policy. Signed-off-by: Dillon Varone <dillon.varone@amd.com> Reviewed-by: Eryk Brol <Eryk.Brol@amd.com> Acked-by: Aurabindo Pillai <aurabindo.pillai@amd.com> Tested-by: Daniel Wheeler <daniel.wheeler@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2021-04-20drm/amd/display: Fixed typo in function name.David Galiffi
[How & Why] Changed "prsent" to "present". Signed-off-by: David Galiffi <David.Galiffi@amd.com> Reviewed-by: Chris Park <Chris.Park@amd.com> Acked-by: Aurabindo Pillai <aurabindo.pillai@amd.com> Tested-by: Daniel Wheeler <daniel.wheeler@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2021-04-20drm/amd/display: Always poll for rxstatus in authenticateNicholas Kazlauskas
[Why] Requirement from the spec - we shouldn't be potentially exiting out early based on encryption status. [How] Drop the calls from HDCP1 and HDCP2 execution that exit out early based on link encryption status. Signed-off-by: Nicholas Kazlauskas <nicholas.kazlauskas@amd.com> Reviewed-by: Wenjing Liu <Wenjing.Liu@amd.com> Acked-by: Aurabindo Pillai <aurabindo.pillai@amd.com> Tested-by: Daniel Wheeler <daniel.wheeler@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2021-04-20drm/amd/display: Add link rate optimization logs for ILRMichael Strauss
[Why&How] Add logs to verify ILR optimization behaviour on boot Signed-off-by: Michael Strauss <michael.strauss@amd.com> Reviewed-by: Nicholas Kazlauskas <Nicholas.Kazlauskas@amd.com> Acked-by: Aurabindo Pillai <aurabindo.pillai@amd.com> Tested-by: Daniel Wheeler <daniel.wheeler@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2021-04-20drm/amd/display: Unconditionally clear training pattern set after ltWesley Chalmers
[WHY] While Link Training is being performed, and the LTTPRs are in Non-LTTPR or LTTPR Transparent mode, any DPCD registers besides those used for Link Training are not to be accessed. The spec defines the link training registers as DP_TRAINING_PATTERN_SET (102h) to DP_TRAINING_LANE3_SET (106h), and DP_LANE0_1_STATUS (202h) to DP_ADJUST_REQUEST_LANE2_3 (207h). [HOW] Move the current write to DPCD Address DP_LINK_TRAINING_PATTERN_SET out of its conditional block. Signed-off-by: Wesley Chalmers <Wesley.Chalmers@amd.com> Reviewed-by: Jun Lei <Jun.Lei@amd.com> Acked-by: Aurabindo Pillai <aurabindo.pillai@amd.com> Tested-by: Daniel Wheeler <daniel.wheeler@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2021-04-20drm/amd/display: Fix FreeSync when RGB MPO in useAric Cyr
[WHY] We should skip programming manual trigger on non-primary planes when MPO is enabled. [HOW] Implement an explicit mechanism for skipping manual trigger programming for planes that shouldn't cause the frame to end. Signed-off-by: Aric Cyr <aric.cyr@amd.com> Reviewed-by: Anthony Koo <Anthony.Koo@amd.com> Acked-by: Aurabindo Pillai <aurabindo.pillai@amd.com> Acked-by: Krunoslav Kovac <Krunoslav.Kovac@amd.com> Tested-by: Daniel Wheeler <daniel.wheeler@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2021-04-20drm/amd/display: treat memory as a single-channel for asymmetric memory v2Hugo Hu
Previous change had been reverted since it caused hang. Remake change to avoid defect. [Why] 1. Driver use umachannelnumber to calculate watermarks for stutter. In asymmetric memory config, the actual bandwidth is less than dual-channel. The bandwidth should be the same as single-channel. 2. We found single rank dimm need additional delay time for stutter. [How] Get information from each DIMM. Treat memory config as a single-channel for asymmetric memory in bandwidth calculating. Add additional delay time for single rank dimm. Fixes: b8720ed0b87d32 ("drm/amd/display: System black screen hangs on driver load") Signed-off-by: Hugo Hu <hugo.hu@amd.com> Reviewed-by: Sung Lee <Sung.Lee@amd.com> Acked-by: Aurabindo Pillai <aurabindo.pillai@amd.com> Tested-by: Daniel Wheeler <daniel.wheeler@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2021-04-20drm/amd/display: removed unused function dc_link_reallocate_mst_payload.Robin Singh
[Why] Found that dc_link_reallocate_mst_payload is not used anymore in any of the use case scenario. [How] removed dc_link_reallocate_mst_payload function definition and declaration. Signed-off-by: Robin Singh <robin.singh@amd.com> Reviewed-by: Harry Wentland <Harry.Wentland@amd.com> Acked-by: Aurabindo Pillai <aurabindo.pillai@amd.com> Tested-by: Daniel Wheeler <daniel.wheeler@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2021-04-20drm/amd/display: disable seamless boot for external DPAnthony Wang
[Why] Primary feature use case is with eDP panels. [How] Fail seamless boot validation if display is not an eDP panel. Signed-off-by: Anthony Wang <anthony1.wang@amd.com> Reviewed-by: Martin Leung <Martin.Leung@amd.com> Acked-by: Aurabindo Pillai <aurabindo.pillai@amd.com> Tested-by: Daniel Wheeler <daniel.wheeler@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2021-04-20drm/amd/display: add handling for hdcp2 rx id list validationDingchen (David) Zhang
[why] the current implementation of hdcp2 rx id list validation does not have handler/checker for invalid message status, e.g. HMAC, the V parameter calculated from PSP not matching the V prime from Rx. [how] return a generic FAILURE for any message status not SUCCESS or REVOKED. Signed-off-by: Dingchen (David) Zhang <dingchen.zhang@amd.com> Reviewed-by: Bhawanpreet Lakha <Bhawanpreet.Lakha@amd.com> Acked-by: Aurabindo Pillai <aurabindo.pillai@amd.com> Tested-by: Daniel Wheeler <daniel.wheeler@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2021-04-20drm/amd/display: update hdcp display using correct CP type.Dingchen (David) Zhang
[why] currently we enforce to update hdcp display using TYPE0, but there is case that connector CP type prop be TYPE1 instead of type0. [how] using the drm prop of CP type of the connector as input argument. Signed-off-by: Dingchen (David) Zhang <dingchen.zhang@amd.com> Reviewed-by: Bhawanpreet Lakha <Bhawanpreet.Lakha@amd.com> Acked-by: Aurabindo Pillai <aurabindo.pillai@amd.com> Tested-by: Daniel Wheeler <daniel.wheeler@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2021-04-20drm/amd/display: Add DSC check to seamless boot validationAnthony Wang
[Why & How] We want to immediately fail seamless boot validation if DSC is active, as VBIOS currently does not support DSC timings. Add a check for the relevant flag in dc_validate_seamless_boot_timing. Signed-off-by: Anthony Wang <anthony1.wang@amd.com> Reviewed-by: Martin Leung <Martin.Leung@amd.com> Acked-by: Aurabindo Pillai <aurabindo.pillai@amd.com> Tested-by: Daniel Wheeler <daniel.wheeler@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2021-04-20drm/amd/display: fixed divide by zero kernel crash during dsc enablementRobin Singh
[why] During dsc enable, a divide by zero condition triggered the kernel crash. [how] An IGT test, which enable the DSC, was crashing at the time of restore the default dsc status, becaue of h_totals value becoming 0. So add a check before divide condition. If h_total is zero, gracefully ignore and set the default value. kernel panic log: [ 128.758827] divide error: 0000 [#1] PREEMPT SMP NOPTI [ 128.762714] CPU: 5 PID: 4562 Comm: amd_dp_dsc Tainted: G W 5.4.19-android-x86_64 #1 [ 128.769728] Hardware name: ADVANCED MICRO DEVICES, INC. Mauna/Mauna, BIOS WMN0B13N Nov 11 2020 [ 128.777695] RIP: 0010:hubp2_vready_at_or_After_vsync+0x37/0x7a [amdgpu] [ 128.785707] Code: 80 02 00 00 48 89 f3 48 8b 7f 08 b ...... [ 128.805696] RSP: 0018:ffffad8f82d43628 EFLAGS: 00010246 ...... [ 128.857707] CR2: 00007106d8465000 CR3: 0000000426530000 CR4: 0000000000140ee0 [ 128.865695] Call Trace: [ 128.869712] hubp3_setup+0x1f/0x7f [amdgpu] [ 128.873705] dcn20_update_dchubp_dpp+0xc8/0x54a [amdgpu] [ 128.877706] dcn20_program_front_end_for_ctx+0x31d/0x463 [amdgpu] [ 128.885706] dc_commit_state+0x3d2/0x658 [amdgpu] [ 128.889707] amdgpu_dm_atomic_commit_tail+0x4b3/0x1e7c [amdgpu] [ 128.897699] ? dm_read_reg_func+0x41/0xb5 [amdgpu] [ 128.901707] ? dm_read_reg_func+0x41/0xb5 [amdgpu] [ 128.905706] ? __is_insn_slot_addr+0x43/0x48 [ 128.909706] ? fill_plane_buffer_attributes+0x29e/0x3dc [amdgpu] [ 128.917705] ? dm_plane_helper_prepare_fb+0x255/0x284 [amdgpu] [ 128.921700] ? usleep_range+0x7c/0x7c [ 128.925705] ? preempt_count_sub+0xf/0x18 [ 128.929706] ? _raw_spin_unlock_irq+0x13/0x24 [ 128.933732] ? __wait_for_common+0x11e/0x18f [ 128.937705] ? _raw_spin_unlock_irq+0x13/0x24 [ 128.941706] ? __wait_for_common+0x11e/0x18f [ 128.945705] commit_tail+0x8b/0xd2 [drm_kms_helper] [ 128.949707] drm_atomic_helper_commit+0xd8/0xf5 [drm_kms_helper] [ 128.957706] amdgpu_dm_atomic_commit+0x337/0x360 [amdgpu] [ 128.961705] ? drm_atomic_check_only+0x543/0x68d [drm] [ 128.969705] ? drm_atomic_set_property+0x760/0x7af [drm] [ 128.973704] ? drm_mode_atomic_ioctl+0x6f3/0x85a [drm] [ 128.977705] drm_mode_atomic_ioctl+0x6f3/0x85a [drm] [ 128.985705] ? drm_atomic_set_property+0x7af/0x7af [drm] [ 128.989706] drm_ioctl_kernel+0x82/0xda [drm] [ 128.993706] drm_ioctl+0x225/0x319 [drm] [ 128.997707] ? drm_atomic_set_property+0x7af/0x7af [drm] [ 129.001706] ? preempt_count_sub+0xf/0x18 [ 129.005713] amdgpu_drm_ioctl+0x4b/0x76 [amdgpu] [ 129.009705] vfs_ioctl+0x1d/0x2a [ 129.013705] do_vfs_ioctl+0x419/0x43d [ 129.017707] ksys_ioctl+0x52/0x71 [ 129.021707] __x64_sys_ioctl+0x16/0x19 [ 129.025706] do_syscall_64+0x78/0x85 [ 129.029705] entry_SYSCALL_64_after_hwframe+0x44/0xa9 Signed-off-by: Robin Singh <robin.singh@amd.com> Reviewed-by: Harry Wentland <Harry.Wentland@amd.com> Reviewed-by: Robin Singh <Robin.Singh@amd.com> Acked-by: Aurabindo Pillai <aurabindo.pillai@amd.com> Tested-by: Daniel Wheeler <daniel.wheeler@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2021-04-20drm/amdgpu: fix GCR_GENERAL_CNTL offset for dimgrey_cavefishJiansong Chen
dimgrey_cavefish has similar gc_10_3 ip with sienna_cichlid, so follow its registers offset setting. Signed-off-by: Jiansong Chen <Jiansong.Chen@amd.com> Reviewed-by: Tao Zhou <tao.zhou1@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2021-04-20drm/amdgpu: resolve erroneous gfx_v9_4_2 printsJohn Clements
resolve bug on aldebaran where gfx error counts will print on driver load when there are no errors present Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com> Signed-off-by: John Clements <john.clements@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
generated by cgit (git 2.34.1) at 2025-09-16 11:31:26 +0000