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2021-02-08clk: Drop unused efm32gg driverUwe Kleine-König
Support for this machine was just removed, so drop the now unused clk driver, too. Signed-off-by: Uwe Kleine-König <u.kleine-koenig@pengutronix.de> Link: https://lore.kernel.org/r/20210114151630.128830-3-u.kleine-koenig@pengutronix.de Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2021-02-08RDMA/rxe: Fix FIXME in rxe_udp_encap_recv()Bob Pearson
rxe_udp_encap_recv() drops the reference to rxe->ib_dev taken by rxe_get_dev_from_net() which should be held until each received skb is freed. This patch moves the calls to ib_device_put() to each place a received skb is freed. It also takes references to the ib_device for each cloned skb created to process received multicast packets. Fixes: 4c173f596b3f ("RDMA/rxe: Use ib_device_get_by_netdev() instead of open coding") Link: https://lore.kernel.org/r/20210128233318.2591-1-rpearson@hpe.com Signed-off-by: Bob Pearson <rpearson@hpe.com> Signed-off-by: Jason Gunthorpe <jgg@nvidia.com>
2021-02-08clk: qcom: mmcc-msm8998: Set bimc_smmu_gdsc always onAngeloGioacchino Del Regno
This GDSC enables (or cuts!) power to the Multimedia Subsystem IOMMU (mmss smmu), which has bootloader pre-set secure contexts. In the event of a complete power loss, the secure contexts will be reset and the hypervisor will crash the SoC. To prevent this, and get a working multimedia subsystem, set this GDSC as always on. Signed-off-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@somainline.org> Link: https://lore.kernel.org/r/20210114221059.483390-10-angelogioacchino.delregno@somainline.org Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2021-02-08clk: qcom: mmcc-msm8998: Add hardware clockgating registers to some clksAngeloGioacchino Del Regno
Hardware clock gating is supported on some of the clocks declared in there: ignoring that it does exist may lead to unstabilities on some firmwares. Add the HWCG registers where applicable to stop potential crashes. This was verified on a smartphone shipped with a recent MSM8998 firmware, which will experience random crashes without this change. Signed-off-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@somainline.org> Link: https://lore.kernel.org/r/20210114221059.483390-9-angelogioacchino.delregno@somainline.org Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2021-02-08clk: qcom: gcc-msm8998: Fix Alpha PLL type for all GPLLsAngeloGioacchino Del Regno
All of the GPLLs in the MSM8998 Global Clock Controller are Fabia PLLs and not generic alphas: this was producing bad effects over the entire clock tree of MSM8998, where any GPLL child clock was declaring a false clock rate, due to their parent also showing the same. The issue resides in the calculation of the clock rate for the specific Alpha PLL type, where Fabia has a different register layout; switching the MSM8998 GPLLs to the correct Alpha Fabia PLL type fixes the rate (calculation) reading. While at it, also make these PLLs fixed since their rate is supposed to *never* be changed while the system runs, as this would surely crash the entire SoC. Now all the children of all the PLLs are also complying with their specified clock table and system stability is improved. Fixes: b5f5f525c547 ("clk: qcom: Add MSM8998 Global Clock Control (GCC) driver") Signed-off-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@somainline.org> Link: https://lore.kernel.org/r/20210114221059.483390-7-angelogioacchino.delregno@somainline.org Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2021-02-08clk: qcom: gcc-msm8998: Mark gpu_cfg_ahb_clk as criticalAngeloGioacchino Del Regno
The GPU IOMMU depends on this clock and the hypervisor will crash the SoC if this clock gets disabled because the secure contexts that have been set on this IOMMU by the bootloader will become unaccessible (or they get reset). Mark this clock as critical to avoid this issue when the Adreno GPU is enabled. Signed-off-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@somainline.org> Link: https://lore.kernel.org/r/20210114221059.483390-6-angelogioacchino.delregno@somainline.org Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2021-02-08clk: qcom: gcc-msm8998: Add missing hmss_gpll0_clk_src clockAngeloGioacchino Del Regno
To achieve CPR-Hardened functionality this clock must be on: add it in order to be able to get it managed by the CPR3 driver. Signed-off-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@somainline.org> Link: https://lore.kernel.org/r/20210114221059.483390-5-angelogioacchino.delregno@somainline.org Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2021-02-08clk: qcom: gcc-msm8998: Wire up gcc_mmss_gpll0 clockAngeloGioacchino Del Regno
This clock enables the GPLL0 output to the multimedia subsystem clock controller. Signed-off-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@somainline.org> Link: https://lore.kernel.org/r/20210114221059.483390-3-angelogioacchino.delregno@somainline.org Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2021-02-08clk: qcom: videocc: Add gdsc mmcx-reg supply hookBryan O'Donoghue
This commit adds a regulator supply hook to mmcx-reg missing from - mvs0c_gdsc - mvs1c_gdsc - mvs0_gdsc - mvs1_gdsc Signed-off-by: Bryan O'Donoghue <bryan.odonoghue@linaro.org> Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Tested-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Link: https://lore.kernel.org/r/20210204150120.1521959-5-bryan.odonoghue@linaro.org Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2021-02-08clk: qcom: videocc: Add sm8250 VIDEO_CC_MVS0_CLKBryan O'Donoghue
This patch adds the missing video_cc_mvs0_clk entry to videocc-sm8250 replicating in upstream the explicit entry for this clock in downstream. Signed-off-by: Bryan O'Donoghue <bryan.odonoghue@linaro.org> Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Tested-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Link: https://lore.kernel.org/r/20210204150120.1521959-4-bryan.odonoghue@linaro.org Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2021-02-08clk: qcom: videocc: Add sm8250 VIDEO_CC_MVS0_DIV_CLK_SRCBryan O'Donoghue
This patch adds the missing video_cc_mvs0_div_clk_src entry to videocc-sm8250 replicating in upstream the explicit entry for this clock in downstream. Signed-off-by: Bryan O'Donoghue <bryan.odonoghue@linaro.org> Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Tested-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Link: https://lore.kernel.org/r/20210204150120.1521959-3-bryan.odonoghue@linaro.org Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2021-02-08clk: qcom: gcc: Add clock driver for SM8350Vivek Aknurwar
This adds Global Clock controller (GCC) driver for SM8350 SoC Signed-off-by: Vivek Aknurwar <viveka@codeaurora.org> Signed-off-by: Jeevan Shriram <jshriram@codeaurora.org> [vkoul: rebase and tidy up for upstream] Signed-off-by: Vinod Koul <vkoul@kernel.org> Reviewed-by: Bjorn Andersson <bjorn.andersson@linaro.org> Link: https://lore.kernel.org/r/20210127070811.152690-6-vkoul@kernel.org Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2021-02-08clk: qcom: clk-alpha-pll: Add support for Lucid 5LPE PLLVivek Aknurwar
Lucid 5LPE is a slightly different Lucid PLL with different offsets and porgramming sequence so add support for these Signed-off-by: Vivek Aknurwar <viveka@codeaurora.org> Signed-off-by: Jeevan Shriram <jshriram@codeaurora.org> [vkoul: rebase and tidy up for upstream] Signed-off-by: Vinod Koul <vkoul@kernel.org> Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@somainline.org> Reviewed-by: Bjorn Andersson <bjorn.andersson@linaro.org> Link: https://lore.kernel.org/r/20210127070811.152690-4-vkoul@kernel.org Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2021-02-08clk: qcom: clk-alpha-pll: modularize alpha_pll_trion_set_rate()Vinod Koul
Trion 5LPE set rate uses code similar to alpha_pll_trion_set_rate() but with different registers. Modularize these by moving out latch and latch ack bits so that we can reuse the function. Suggested-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@somainline.org> Reviewed-by: Bjorn Andersson <bjorn.andersson@linaro.org> Signed-off-by: Vinod Koul <vkoul@kernel.org> Link: https://lore.kernel.org/r/20210127070811.152690-3-vkoul@kernel.org Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2021-02-08clk: qcom: clk-alpha-pll: replace regval with valVinod Koul
Driver uses regval variable for holding register values, replace with a shorter one val Suggested-by: Stephen Boyd <sboyd@kernel.org> Reviewed-by: Bjorn Andersson <bjorn.andersson@linaro.org> Signed-off-by: Vinod Koul <vkoul@kernel.org> Link: https://lore.kernel.org/r/20210127070811.152690-2-vkoul@kernel.org Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2021-02-08clk: qcom: gcc: Add global clock controller driver for SC8180xBjorn Andersson
Add clocks, resets and some of the GDSC provided by the global clock controller found in the Qualcomm SC8180x platform. Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org> Link: https://lore.kernel.org/r/20210126043155.1847823-2-bjorn.andersson@linaro.org [sboyd@kernel.org: Drop F macro as it's already defined] Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2021-02-08clk: qcom: gcc-sc7180: Mark the MM XO clocks to be always ONTaniya Das
There are intermittent GDSC power-up failures observed for titan top gdsc, which requires the XO clock. Thus mark all the MM XO clocks always enabled from probe. Fixes: 8d4025943e13 ("clk: qcom: camcc-sc7180: Use runtime PM ops instead of clk ones") Signed-off-by: Taniya Das <tdas@codeaurora.org> Link: https://lore.kernel.org/r/1611128871-5898-1-git-send-email-tdas@codeaurora.org Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2021-02-08clk: qcom: rpmhcc: Add sc8180x rpmh clocksBjorn Andersson
Add clocks provides by RPMH in the Qualcomm SC8180x platform. Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org> Link: https://lore.kernel.org/r/20210120223741.1610344-2-bjorn.andersson@linaro.org Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2021-02-08clk: qcom: gfm-mux: fix clk maskSrinivas Kandagatla
For some reason global GFM_MASK ended up with bit 1 instead of bit 0. Remove the global GFM_MASK and reuse mux_mask field. Fixes: a2d8f507803e ("clk: qcom: Add support to LPASS AUDIO_CC Glitch Free Mux clocks") Signed-off-by: Srinivas Kandagatla <srinivas.kandagatla@linaro.org> Link: https://lore.kernel.org/r/20210119113851.18946-1-srinivas.kandagatla@linaro.org Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2021-02-08clk: qcom: Add SDX55 APCS clock controller supportManivannan Sadhasivam
Add a driver for the SDX55 APCS clock controller. It is part of the APCS hardware block, which among other things implements also a combined mux and half integer divider functionality. The APCS clock controller has 3 parent clocks: 1. Board XO 2. Fixed rate GPLL0 3. A7 PLL This is required for enabling CPU frequency scaling on SDX55-based platforms. Signed-off-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org> Link: https://lore.kernel.org/r/20210118041156.50016-6-manivannan.sadhasivam@linaro.org [sboyd@kernel.org: Fix unused ret in probe by hardcoding it] Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2021-02-08clk: qcom: Add A7 PLL supportManivannan Sadhasivam
Add support for PLL found in Qualcomm SDX55 platforms which is used to provide clock to the Cortex A7 CPU via a mux. This PLL can provide high frequency clock to the CPU above 1GHz as compared to the other sources like GPLL0. In this driver, the power domain is attached to the cpudev. This is required for CPUFreq functionality and there seems to be no better place to do other than this driver (no dedicated CPUFreq driver). Signed-off-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org> Link: https://lore.kernel.org/r/20210118041156.50016-5-manivannan.sadhasivam@linaro.org Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2021-02-08memory: tegra186-emc: Replace DEFINE_SIMPLE_ATTRIBUTE with ↵Jiapeng Chong
DEFINE_DEBUGFS_ATTRIBUTE Fix the following coccicheck warning: drivers/memory/tegra/tegra186-emc.c:158:0-23: WARNING: tegra186_emc_debug_max_rate_fops should be defined with DEFINE_DEBUGFS_ATTRIBUTE. Signed-off-by: Jiapeng Chong <jiapeng.chong@linux.alibaba.com> Link: https://lore.kernel.org/r/1612684970-125948-1-git-send-email-jiapeng.chong@linux.alibaba.com Signed-off-by: Krzysztof Kozlowski <krzk@kernel.org>
2021-02-08memory: samsung: exynos5422-dmc: Correct function names in kerneldocKrzysztof Kozlowski
Correct kerneldoc to fix W=1 warnings: drivers/memory/samsung/exynos5422-dmc.c:290: warning: expecting prototype for find_target_freq_id(). Prototype was for find_target_freq_idx() instead drivers/memory/samsung/exynos5422-dmc.c:1015: warning: expecting prototype for exynos5_dmc_align_initial_frequency(). Prototype was for exynos5_dmc_align_init_freq() instead Signed-off-by: Krzysztof Kozlowski <krzk@kernel.org> Reviewed-by: Lukasz Luba <lukasz.luba@arm.com> Link: https://lore.kernel.org/r/20210206111715.20774-1-krzk@kernel.org
2021-02-08memory: ti-emif-pm: Drop of_match_ptr from of_device_id tableKrzysztof Kozlowski
The driver can match only via the DT table so the table should be always used and the of_match_ptr does not have any sense (this also allows ACPI matching via PRP0001, even though it might be not relevant here). This fixes compile warning (!CONFIG_OF with clang): drivers/memory/ti-emif-pm.c:238:34: warning: unused variable 'ti_emif_of_match' [-Wunused-const-variable] Reported-by: kernel test robot <lkp@intel.com> Signed-off-by: Krzysztof Kozlowski <krzk@kernel.org> Reviewed-by: Nathan Chancellor <nathan@kernel.org> Link: https://lore.kernel.org/r/20210206111343.19273-1-krzk@kernel.org
2021-02-08Merge tag 'mt76-for-kvalo-2021-01-29' of https://github.com/nbd168/wirelessKalle Valo
mt76 patches for 5.12 * add new mt7921e driver * factor out common code shared between 7615/7663 and 7921 * performance optimizations * 7915 dbdc fixes * 802.11 encap offload support * support for multiple pcie gen1 host interfaces on 7915 * 7915 testmode support * bugfixes * testmode support enhancements * endian fixes * 7915 txbf support
2021-02-08Merge tag 'iwlwifi-next-for-kalle-2021-02-05' of ↵Kalle Valo
git://git.kernel.org/pub/scm/linux/kernel/git/iwlwifi/iwlwifi-next iwlwifi patches intended for v5.12 * Check FW notification sizes for robustness; * Improvements in the NAPI implementation; * Implement a workaround for CCA-EXT; * Add new FW API support; * Fix a CSA bug; * Implement PHY integration version parsing; * A bit of refactoring; * One more CSA bug fix, this time in the AP side; * Support for new So devices and a bit of reorg; * Per Platform Antenna Gain (PPAG) fixes and improvements; * Improvements in the debug framework; * Some other clean-ups and small fixes. # gpg: Signature made Fri 05 Feb 2021 12:04:21 PM EET using RSA key ID 1A3CC5FA # gpg: Good signature from "Luciano Roth Coelho (Luca) <luca@coelho.fi>" # gpg: aka "Luciano Roth Coelho (Intel) <luciano.coelho@intel.com>"
2021-02-08dm writecache: return the exact table values that were setMikulas Patocka
LVM doesn't like it when the target returns different values from what was set in the constructor. Fix dm-writecache so that the returned table values are exactly the same as requested values. Signed-off-by: Mikulas Patocka <mpatocka@redhat.com> Cc: stable@vger.kernel.org # v4.18+ Signed-off-by: Mike Snitzer <snitzer@redhat.com>
2021-02-08habanalabs/gaudi: don't enable clock gating on DMA5Oded Gabbay
Graph Compiler uses DMA5 in a non-standard way and it requires the driver to disable clock gating on that DMA. Signed-off-by: Oded Gabbay <ogabbay@kernel.org>
2021-02-08habanalabs: return block size + block IDOded Gabbay
When user gives us a block address to get its ID to mmap it, he also needs to get from us the block size to pass to the driver in the mmap function. Signed-off-by: Oded Gabbay <ogabbay@kernel.org>
2021-02-08habanalabs: update security map after init CPU QsOhad Sharabi
when reading CPU_BOOT_DEV_STS0 reg after FW reports SRAM AVAILABLE the value in the register might not yet be updated by FW. to overcome this issue another "up-to-date" read of this register is done at the end of CPU queues init. Signed-off-by: Ohad Sharabi <osharabi@habana.ai> Reviewed-by: Oded Gabbay <ogabbay@kernel.org> Signed-off-by: Oded Gabbay <ogabbay@kernel.org>
2021-02-08habanalabs: enable F/W events after init doneOded Gabbay
Only after the initialization of the device is done, the driver is ready to receive events from the F/W. The driver can't handle events before that because of races so it will ignore events. In case of a fatal event, the driver won't know about it and the device will be operational although it shouldn't be. Same logic should be applied after hard-reset. Signed-off-by: Oded Gabbay <ogabbay@kernel.org>
2021-02-08habanalabs/gaudi: use HBM_ECC_EN bit for ECC ERROhad Sharabi
driver should use ECC info from FW only if HBM ECC CAP is set. otherwise, try to fetch the data from MC regs only if security is disabled. Signed-off-by: Ohad Sharabi <osharabi@habana.ai> Reviewed-by: Oded Gabbay <ogabbay@kernel.org> Signed-off-by: Oded Gabbay <ogabbay@kernel.org>
2021-02-08habanalabs: support fetching first available user CQOfir Bitton
User must be aware of the available CQs when it needs to use them. Signed-off-by: Ofir Bitton <obitton@habana.ai> Reviewed-by: Oded Gabbay <ogabbay@kernel.org> Signed-off-by: Oded Gabbay <ogabbay@kernel.org>
2021-02-08habanalabs: improve communication protocol with cpucpOfir Bitton
Current messaging communictaion protocol with cpucp can get out of sync due to coherency issues. In order to improve the protocol reliability, we modify the protocol to expect a different acknowledgment for every packet sent to cpucp. Signed-off-by: Ofir Bitton <obitton@habana.ai> Reviewed-by: Oded Gabbay <ogabbay@kernel.org> Signed-off-by: Oded Gabbay <ogabbay@kernel.org>
2021-02-08habanalabs: fix integer handling issueOded Gabbay
Need to add ull suffix to constant when doing shift of constant into 64-bit variables Signed-off-by: Oded Gabbay <ogabbay@kernel.org>
2021-02-08Platform: OLPC: Constify static struct regulator_opsRikard Falkeborn
The only usage of it is to assign its address to the ops field in the regulator_desc struct, which is a pointer to const struct regulator_ops. Make it const to allow the compiler to put it in read-only memory. Signed-off-by: Rikard Falkeborn <rikard.falkeborn@gmail.com> Link: https://lore.kernel.org/r/20210206232152.58046-1-rikard.falkeborn@gmail.com Signed-off-by: Hans de Goede <hdegoede@redhat.com>
2021-02-08platform/surface: Add Surface Hot-Plug driverMaximilian Luz
Some Surface Book 2 and 3 models have a discrete GPU (dGPU) that is hot-pluggable. On those devices, the dGPU is contained in the base, which can be separated from the tablet part (containing CPU and touchscreen) while the device is running. It (in general) is presented as/behaves like a standard PCIe hot-plug capable device, however, this device can also be put into D3cold. In D3cold, the device itself is turned off and can thus not submit any standard PCIe hot-plug events. To properly detect hot-(un)plugging while the dGPU is in D3cold, out-of-band signaling is required. Without this, the device state will only get updated during the next bus-check, eg. via a manually issued lspci call. This commit adds a driver to handle out-of-band PCIe hot-(un)plug events on Microsoft Surface devices. On those devices, said events can be detected via GPIO interrupts, which are then forwarded to the corresponding ACPI DSM calls by this driver. The DSM then takes care of issuing the appropriate bus-/device-check, causing the PCI core to properly pick up the device change. Signed-off-by: Maximilian Luz <luzmaximilian@gmail.com> Link: https://lore.kernel.org/r/20210205012657.1951753-1-luzmaximilian@gmail.com Signed-off-by: Hans de Goede <hdegoede@redhat.com>
2021-02-08md/raid10: remove dead code in reshape_requestChristoph Hellwig
A bio allocated by bio_alloc_bioset comes pre-zeroed, no need to clear random fields. Signed-off-by: Christoph Hellwig <hch@lst.de> Acked-by: Song Liu <song@kernel.org> Signed-off-by: Jens Axboe <axboe@kernel.dk>
2021-02-08Merge tag 'ib-mfd-asoc-v5.12' of ↵Mark Brown
git://git.kernel.org/pub/scm/linux/kernel/git/lee/mfd into asoc-5.12 Immutable branch between MFD and [XXX] due for the v5.12 merge window
2021-02-08staging: rtl8192e: replace spaces with tab for a closing if bracePhillip Potter
Remove spaces preceding closing brace of one of the nested if statement blocks inside the rtl92e_leisure_ps_leave function, and replace with a tab, to align it properly with the start of the block. Fixes a checkpatch warning. Signed-off-by: Phillip Potter <phil@philpotter.co.uk> Link: https://lore.kernel.org/r/20210207194944.113613-1-phil@philpotter.co.uk Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
2021-02-08staging: rtl8192e: remove braces from single-line blockPhillip Potter
This removes the braces from the if statement that checks the wps_ie_len and ieee->wps_ie values in rtllib_association_req of rtllib_softmac.c as this block contains only one statement. Fixes a checkpatch warning. Signed-off-by: Phillip Potter <phil@philpotter.co.uk> Link: https://lore.kernel.org/r/20210207225703.114229-1-phil@philpotter.co.uk Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
2021-02-08staging: wfx: fix possible panic with re-queued framesJérôme Pouiller
When the firmware rejects a frame (because station become asleep or disconnected), the frame is re-queued in mac80211. However, the re-queued frame was 8 bytes longer than the original one (the size of the ICV for the encryption). So, when mac80211 try to send this frame again, it is a little bigger than expected. If the frame is re-queued secveral time it end with a skb_over_panic because the skb buffer is not large enough. Note it only happens when device acts as an AP and encryption is enabled. This patch more or less reverts the commit 049fde130419 ("staging: wfx: drop useless field from struct wfx_tx_priv"). Fixes: 049fde130419 ("staging: wfx: drop useless field from struct wfx_tx_priv") Signed-off-by: Jérôme Pouiller <jerome.pouiller@silabs.com> Link: https://lore.kernel.org/r/20210208135254.399964-1-Jerome.Pouiller@silabs.com Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
2021-02-08staging: gasket: fix indentation and lines ending with open parenthesisMahak Gupta
This patch fixes warnings of 'checkpatch.pl'. According to Linux coding guidelines, code should be aligned properly to match with open parenthesis and lines should not end with open parenthesis. Signed-off-by: Mahak Gupta <gmahak1@gmail.com> Link: https://lore.kernel.org/r/20210208025904.25928-1-gmahak1@gmail.com Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
2021-02-08staging: fieldbus: arcx-anybus: constify static structsRikard Falkeborn
Constify two static structs which are never modified, to allow the compiler to put them in read-only memory. The only usage of controller_attribute_group is to put its address in an array of pointers to const struct attribute_group, and the only usage of can_power_ops is to assign its address to the 'ops' field in the regulator_desc struct, which is a pointer to const struct regulator_ops. Reviewed-by: Sven Van Asbroeck <TheSven73@gmail.com> Signed-off-by: Rikard Falkeborn <rikard.falkeborn@gmail.com> Link: https://lore.kernel.org/r/20210207202501.9494-1-rikard.falkeborn@gmail.com Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
2021-02-08mfd: wm831x-auxadc: Prevent use after free in wm831x_auxadc_read_irq()Dan Carpenter
The "req" struct is always added to the "wm831x->auxadc_pending" list, but it's only removed from the list on the success path. If a failure occurs then the "req" struct is freed but it's still on the list, leading to a use after free. Fixes: 78bb3688ea18 ("mfd: Support multiple active WM831x AUXADC conversions") Signed-off-by: Dan Carpenter <dan.carpenter@oracle.com> Acked-by: Charles Keepax <ckeepax@opensource.cirrus.com> Signed-off-by: Lee Jones <lee.jones@linaro.org>
2021-02-08mfd: iqs62x: Do not change clock frequency during ATIJeff LaBundy
After a reset event, the device automatically triggers ATI at the default core clock frequency (16 MHz). Soon afterward, the driver loads firmware which may attempt to lower the frequency. If this initial ATI cycle is still in progress when the frequency is changed, however, the device incorrectly reports channels 0, 1 and 2 to be in a state of touch once ATI finally completes. To solve this problem, wait until ATI is complete before lowering the frequency. Because this particular ATI cycle occurs following a reset event, its duration is predictable and a simple delay can suffice. Signed-off-by: Jeff LaBundy <jeff@labundy.com> Signed-off-by: Lee Jones <lee.jones@linaro.org>
2021-02-08mfd: iqs62x: Do not poll during ATIJeff LaBundy
After loading firmware, the driver triggers ATI (calibration) with the newly loaded register configuration in place. Next, the driver polls a register field to ensure ATI completed in a timely fashion and that the device is ready to sense. However, communicating with the device over I2C while ATI is under- way may induce noise in the device and cause ATI to fail. As such, the vendor recommends not to poll the device during ATI. To solve this problem, let the device naturally signal to the host that ATI is complete by way of an interrupt. A completion prevents the sub-devices from being registered until this happens. The former logic that scaled ATI timeout and filter settling delay is not carried forward with the new implementation, as it produces overly conservative delays at lower clock rates. Instead, a single pair of delays that covers all cases is used. Signed-off-by: Jeff LaBundy <jeff@labundy.com> Signed-off-by: Lee Jones <lee.jones@linaro.org>
2021-02-08mfd: iqs62x: Increase interrupt handler return delayJeff LaBundy
The time the device takes to deassert its RDY output following an I2C stop condition scales with the core clock frequency. To prevent level-triggered interrupts from being reasserted after the interrupt handler returns, increase the time before returning to account for the worst-case delay (~90 us) plus margin. Signed-off-by: Jeff LaBundy <jeff@labundy.com> Signed-off-by: Lee Jones <lee.jones@linaro.org>
2021-02-08mfd: iqs62x: Rename regmap_config structJeff LaBundy
The regmap member of the driver's private data is called 'regmap', but the regmap_config struct is called 'iqs62x_map_config'. Rename the latter to 'iqs62x_regmap_config' for consistency. Signed-off-by: Jeff LaBundy <jeff@labundy.com> Signed-off-by: Lee Jones <lee.jones@linaro.org>
2021-02-08mfd: iqs62x: Remove unused bit maskJeff LaBundy
The register write that performed a mandatory soft reset during probe was removed during development of the driver, however the IQS62X_SYS_SETTINGS_SOFT_RESET bit mask was left behind. Remove it to keep stray macros out of the driver. Signed-off-by: Jeff LaBundy <jeff@labundy.com> Signed-off-by: Lee Jones <lee.jones@linaro.org>
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