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2018-07-30usb: dwc2: Turn on uframe_sched on "his" platformsDouglas Anderson
There's no reason to have the uframe scheduler off on dwc2. Running with uframe_sched = False is equivalent to saying "I don't want to run the correct code, I want to run the old and incorrect code". The uframe scheduler has been off on HiSilicon since commit 37dd9d65cc41 ("usb: dwc2: add support of hi6220"). Since then there have been many many improvements, notably the commit 9f9f09b048f5 ("usb: dwc2: host: Totally redo the microframe scheduler") Presumably if everyone is good w/ the uframe_sched turned back on we can kill all the old and crufty non-uframe sched code. Acked-by: Minas Harutyunyan <hminas@synopsys.com> Reviewed-by: Minas Harutyunyan <hminas@synopsys.com> Signed-off-by: Douglas Anderson <dianders@chromium.org> Tested-by: John Stultz <john.stultz@linaro.org> Signed-off-by: Felipe Balbi <felipe.balbi@linux.intel.com>
2018-07-30usb: dwc2: Turn on uframe_sched on "bcm" platformsDouglas Anderson
There's no reason to have the uframe scheduler off on dwc2. Running with uframe_sched = False is equivalent to saying "I don't want to run the correct code, I want to run the old and incorrect code". The uframe scheduler has been off on Broadcom since commit 58b179dcf28c ("staging: dwc2: disable uframe_sched on the bcm2835"). Since then there have been many many improvements, notably the commit 9f9f09b048f5 ("usb: dwc2: host: Totally redo the microframe scheduler") Presumably if everyone is good w/ the uframe_sched turned back on we can kill all the old and crufty non-uframe sched code. Reviewed-by: Minas Harutyunyan <hminas@synopsys.com> Signed-off-by: Douglas Anderson <dianders@chromium.org> Tested-by: Stefan Wahren <stefan.wahren@i2se.com> Signed-off-by: Felipe Balbi <felipe.balbi@linux.intel.com>
2018-07-30usb: dwc2: gadget: ISOC's starting flow improvementMinas Harutyunyan
To start ISOC transfers in handlers dwc2_gadget_handle_nak() and dwc2_gadget_handle_out_token_ep_disabled() driver reads current frame number, based on which, set target frame number to start first ISOC transfer. In case if system's high IRQ latency and multiple EP's asserted interrupt in same frame, there are high probability that when reading current frame number in EP's handlers, actual frame number can be increased. As result for bInterval > 1, starting target frame will be set wrongly and all ISOC packets will be dropped. In patch "usb: dwc2: Change reading of current frame number flow" reading of current frame number done ASAP in common interrupt handler. This frame number stored in frame_number variable which used as starting frame number for ISOC EP's in above mentioned handlers. Signed-off-by: Minas Harutyunyan <hminas@synopsys.com> Signed-off-by: Felipe Balbi <felipe.balbi@linux.intel.com>
2018-07-30usb: dwc2: Make dwc2_readl/writel functions endianness-agnostic.Gevorg Sahakyan
Declared dwc2_check_core_endianness() function for dynamicly check core endianness. Added needs_byte_swap flag to hsotg structure, and depending on flag swap value inside dwc2_readl/writel functions. Signed-off-by: Gevorg Sahakyan <sahakyan@synopsys.com> Signed-off-by: Felipe Balbi <felipe.balbi@linux.intel.com>
2018-07-30usb: dwc3: core: Enable AutoRetry feature in the controllerAnurag Kumar Vulisha
By default when core sees any transaction error (CRC or overflow) it replies with terminating retry ACK (Retry=1 and Nump == 0). Enabling this Auto Retry feature in controller will make the core send a non-terminanting ACK upon such transaction errors. That is, ACK TP with Retry=1 and Nump != 0. Doing so will give controller a chance to recover from transient error conditions. Signed-off-by: Anurag Kumar Vulisha <anurag.kumar.vulisha@xilinx.com> Signed-off-by: Felipe Balbi <felipe.balbi@linux.intel.com>
2018-07-30usb: dwc3: Set default mode for dwc_usb31Thinh Nguyen
dwc_usb31 does not support OTG mode. If the controller supports DRD but the dr_mode is not specified or set to OTG, then set the mode to peripheral. Signed-off-by: Thinh Nguyen <thinhn@synopsys.com> Signed-off-by: Felipe Balbi <felipe.balbi@linux.intel.com>
2018-07-30usb: gadget: udc: renesas_usb3: Add register of usb role switchYoshihiro Shimoda
This patch adds role switch support for R-Car SoCs into the USB 3.0 peripheral driver. Some R-Car SoCs (e.g. R-Car H3) have USB 3.0 dual-role device controller which has the USB 3.0 xHCI host and Renesas USB 3.0 peripheral. Unfortunately, the mode change register (DRD_CON) contains the USB 3.0 peripheral controller side only. So, this renesas_usb3 driver manages the DRD_CON now. However, in peripheral mode, the host should stop. Also the host hardware needs to reinitialize its own registers when the mode changes from peripheral to host mode. Otherwise, the host cannot work correctly (e.g. detect a device as high-speed). To achieve this reinitialization by a driver, this driver also registers a role switch driver to manage the DRD_CON and get a device pointer of usb 3.0 host from "companion" property of OF. Then, when the usb role is changed, renesas_usb3_role_switch_set() will attach/release the xhci-plat driver to reinitialize the host hardware. Signed-off-by: Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com> Reviewed-by: Heikki Krogerus <heikki.krogerus@linux.intel.com> Signed-off-by: Felipe Balbi <felipe.balbi@linux.intel.com>
2018-07-30usb: dwc2: replace ioread32/iowrite32_rep with dwc2_readl/writel_repGevorg Sahakyan
dwc2_readl_rep/dwc2_writel_rep functions using readl/writel in a loop. Signed-off-by: Gevorg Sahakyan <sahakyan@synopsys.com> Signed-off-by: Felipe Balbi <felipe.balbi@linux.intel.com>
2018-07-30usb: dwc2: Modify dwc2_readl/writel functions prototypeGevorg Sahakyan
Added hsotg argument to dwc2_readl/writel function prototype, and also instead of address pass offset of register. hsotg will contain flag field for endianness. Also customized dwc2_set_bit and dwc2_clear_bit function for dwc2_readl/writel functions. Signed-off-by: Gevorg Sahakyan <sahakyan@synopsys.com> Signed-off-by: Felipe Balbi <felipe.balbi@linux.intel.com>
2018-07-30usb: dwc3: pci: Intel Merrifield can be hostAndy Shevchenko
On Intel Edison board the OTG function is enabled, thus, USB can switch to the host mode. Allow that by changing dr_mode property to "otg" for Intel Merrifield. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Signed-off-by: Felipe Balbi <felipe.balbi@linux.intel.com>
2018-07-30usb: dwc3: pci: Supply device properties via driver dataAndy Shevchenko
For now all PCI enumerated dwc3 devices require some properties to be present. This allows us to unconditionally append them and supply via driver_data. No functional change intended. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Signed-off-by: Felipe Balbi <felipe.balbi@linux.intel.com>
2018-07-30usb: dwc3: Enable undefined length INCR burst typePengbo Mu
Enable the undefined length INCR burst type and set INCRx. Different platform may has the different burst size type. In order to get best performance, we need to tune the burst size to one special value, instead of the default value. Signed-off-by: Changming Huang <jerry.huang@nxp.com> Signed-off-by: Ran Wang <ran.wang_1@nxp.com> Signed-off-by: Pengbo Mu <pengbo.mu@nxp.com> Signed-off-by: Felipe Balbi <felipe.balbi@linux.intel.com>
2018-07-30usb: dwc3: add global soc bus configuration reg0Pengbo Mu
Add the macro definition for global soc bus configuration register 0 Signed-off-by: Changming Huang <jerry.huang@nxp.com> Signed-off-by: Ran Wang <ran.wang_1@nxp.com> Signed-off-by: Pengbo Mu <pengbo.mu@nxp.com> Signed-off-by: Felipe Balbi <felipe.balbi@linux.intel.com>
2018-07-30usb: dwc3: Describe 'wakeup_work' field of struct dwc3_pciAndy Shevchenko
Describe 'wakeup_work' field of struct dwc3_pci to avoid a warning: drivers/usb/dwc3/dwc3-pci.c:59: warning: Function parameter or member 'wakeup_work' not described in 'dwc3_pci' Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Signed-off-by: Felipe Balbi <felipe.balbi@linux.intel.com>
2018-07-30staging: erofs: use the wrapped PTR_ERR_OR_ZERO instead of open codeGao Xiang
Just clean up and logic doesn't change. Link: https://lists.01.org/pipermail/kbuild-all/2018-July/050766.html Fixes: d72d1ce60174 ("staging: erofs: add namei functions") Reported-by: kbuild test robot <lkp@intel.com> Signed-off-by: Gao Xiang <gaoxiang25@huawei.com> Reviewed-by: Chao Yu <yuchao0@huawei.com> Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
2018-07-30dmaengine: mic_x100_dma: use the new helper to simplify the codeHuang Shijie
Use dmaenginem_async_device_register() to simplify the code: remove the mic_dma_unregister_dma_device() Signed-off-by: Huang Shijie <sjhuang@iluvatar.ai> Signed-off-by: Vinod Koul <vkoul@kernel.org>
2018-07-30dmaengine: add a new helper dmaenginem_async_device_registerHuang Shijie
This patch adds the dmaenginem_async_device_register for DMA code. Use the Devres to call the release for the DMA engine driver. Signed-off-by: Huang Shijie <sjhuang@iluvatar.ai> Signed-off-by: Vinod Koul <vkoul@kernel.org>
2018-07-30dmaengine: imx-sdma: add memcpy interfaceRobin Gong
Add MEMCPY capability for imx-sdma driver. Signed-off-by: Robin Gong <yibin.gong@nxp.com> Signed-off-by: Vinod Koul <vkoul@kernel.org>
2018-07-30dmaengine: imx-sdma: add SDMA_BD_MAX_CNT to replace '0xffff'Robin Gong
Add macro SDMA_BD_MAX_CNT to replace '0xffff'. Signed-off-by: Robin Gong <yibin.gong@nxp.com> Signed-off-by: Vinod Koul <vkoul@kernel.org>
2018-07-30BackMerge v4.18-rc7 into drm-nextDave Airlie
rmk requested this for armada and I think we've had a few conflicts build up. Signed-off-by: Dave Airlie <airlied@redhat.com>
2018-07-30pinctrl: cannonlake: Fix community ordering for H variantAndy Shevchenko
The driver was written based on an assumption that BIOS provides unordered communities in ACPI DSDT. Nevertheless, it seems that BIOS getting fixed before being provisioned to OxM:s. So does driver. BugLink: https://bugzilla.kernel.org/show_bug.cgi?id=199911 Reported-by: Marc Landolt <2009@marclandolt.ch> Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Fixes: a663ccf0fea1 ("pinctrl: intel: Add Intel Cannon Lake PCH-H pin controller support") Acked-by: Mika Westerberg <mika.westerberg@linux.intel.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2018-07-29gpio: tegra: drop tegra specific GPIO lockdep classesStefan Agner
Since commit e45d1c80c0ee ("gpio: put GPIO IRQs into their own lock class") and commit a0a8bcf4670c ("gpiolib: irqchip: use different lockdep class for each gpio irqchip") GPIO lib takes care of lockdep classes. In fact, gpiochip_irq_map() overwrites the class anyway, so the lockdep class set by the driver is useless. Remove it. Signed-off-by: Stefan Agner <stefan@agner.ch> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2018-07-29pinctrl: tegra: define GPIO compatible node per SoCStefan Agner
Tegra 2 uses a different GPIO controller which uses "tegra20-gpio" as compatible string. Make the compatible string the GPIO node is using a SoC specific property. This prevents the kernel from registering the GPIO range twice in case the GPIO range is specified in the device tree. Fixes: 9462510ce31e ("pinctrl: tegra: Only set the gpio range if needed") Signed-off-by: Stefan Agner <stefan@agner.ch> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2018-07-29gpio: fix meaningless return expressionzhong jiang
Fix the following sparse error: drivers/gpio/gpio-ath79.c:54:16: error: return expression in void function Signed-off-by: zhong jiang <zhongjiang@huawei.com> Acked-by: Alban Bedel <albeu@free.fr> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2018-07-29pinctrl: intel: Do pin translation when lock IRQAndy Shevchenko
Default GPIOLIB callbacks for request and release IRQ do not do a GPIO to pin translation which is necessary for Intel hardware, such as Intel Cannonlake. Absence of the translation prevents some pins to be locked as IRQ due to direction check. Introduce own callbacks to make translation possible to avoid above issue. Fixes: a60eac3239f0 ("pinctrl: intel: Allow custom GPIO base for pad groups") Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Acked-by: Mika Westerberg <mika.westerberg@linux.intel.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2018-07-29pinctrl: imx: off by one in imx_pinconf_group_dbg_show()Dan Carpenter
The > should really be >= here. It's harmless because pinctrl_generic_get_group() will return a NULL if group is invalid. Fixes: ae75ff814538 ("pinctrl: pinctrl-imx: add imx pinctrl core driver") Reported-by: Dong Aisheng <aisheng.dong@nxp.com> Signed-off-by: Dan Carpenter <dan.carpenter@oracle.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2018-07-29gpio: mxs: Fit writel() into a single lineFabio Estevam
There is no need for splitting the writel() call in two lines. Make it fit into a single line instead. Signed-off-by: Fabio Estevam <fabio.estevam@nxp.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2018-07-29gpio: pxa: disable pinctrl calls for PXA3xxDaniel Mack
The pxa3xx driver uses the pinctrl-single driver since a while which does not implement a .gpio_set_direction() callback. The pinmux core will simply return 0 in this case, and the pxa3xx gpio driver hence believes the pinctrl driver did its job and returns as well. This effectively makes pxa_gpio_direction_{input,output} no-ops. To fix this, do not call into the pinctrl subsystem for the PXA3xx platform for now. We can revert this once the pinctrl-single driver learned to support setting pin directions. Signed-off-by: Daniel Mack <daniel@zonque.org> Acked-by: Robert Jarzmik <robert.jarzmik@free.fr> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2018-07-29pinctrl: mediatek: include chained_irq.h headerArnd Bergmann
Some randconfig builds fail in the mtk-eint driver: drivers/pinctrl/mediatek/mtk-eint.c: In function 'mtk_eint_irq_handler': drivers/pinctrl/mediatek/mtk-eint.c:324:2: error: implicit declaration of function 'chained_irq_enter'; did you mean 'rcu_irq_enter'? [-Werror=implicit-function-declaration] chained_irq_enter(chip, desc); ^~~~~~~~~~~~~~~~~ rcu_irq_enter drivers/pinctrl/mediatek/mtk-eint.c:367:2: error: implicit declaration of function 'chained_irq_exit'; did you mean 'rcu_irq_exit'? [-Werror=implicit-function-declaration] The functions are declared in linux/irqchip/chained_irq.h, and including that header makes it build in all configurations. Fixes: e46df235b4e6 ("pinctrl: mediatek: refactor EINT related code for all MediaTek pinctrl can fit") Signed-off-by: Arnd Bergmann <arnd@arndb.de> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2018-07-29gpio: ml-ioh: Fix buffer underwrite on probe error pathAnton Vasilyev
If ioh_gpio_probe() fails on devm_irq_alloc_descs() then chip may point to any element of chip_save array, so reverse iteration from pointer chip may become chip_save[-1] and gpiochip_remove() will operate with wrong memory. The patch fix the error path of ioh_gpio_probe() to correctly bypass chip_save array. Found by Linux Driver Verification project (linuxtesting.org). Signed-off-by: Anton Vasilyev <vasilyev@ispras.ru> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2018-07-29gpiolib: probe deferral error reportingMarcel Ziswiler
Actually report the error code from devm_regulator_get() which may as well just be a probe deferral. This is e.g. what one gets upon booting a Colibri T20: gpiochip_add_data_with_key: GPIOs 0..223 (tegra-gpio) failed to register Signed-off-by: Marcel Ziswiler <marcel.ziswiler@toradex.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2018-07-29pinctrl/amd: only handle irq if it is pending and unmaskedDaniel Kurtz
The AMD pinctrl driver demultiplexes GPIO interrupts and fires off their individual handlers. If one of these GPIO irqs is configured as a level interrupt, and its downstream handler is a threaded ONESHOT interrupt, the GPIO interrupt source is masked by handle_level_irq() until the eventual return of the threaded irq handler. During this time the level GPIO interrupt status will still report as high until the actual gpio source is cleared - both in the individual GPIO interrupt status bit (INTERRUPT_STS_OFF) and in its corresponding "WAKE_INT_STATUS_REG" bit. Thus, if another GPIO interrupt occurs during this time, amd_gpio_irq_handler() will see that the (masked-and-not-yet-cleared) level irq is still pending and incorrectly call its handler again. To fix this, have amd_gpio_irq_handler() check for both interrupts status and mask before calling generic_handle_irq(). Note: Is it possible that this bug was the source of the interrupt storm on Ryzen when using chained interrupts before commit ba714a9c1dea85 ("pinctrl/amd: Use regular interrupt instead of chained")? Signed-off-by: Daniel Kurtz <djkurtz@chromium.org> Acked-by: Thomas Gleixner <tglx@linutronix.de> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2018-07-29gpio: tegra: Fix tegra_gpio_irq_set_type()Dmitry Osipenko
Commit 36b312792b97 ("gpiolib: Respect error code of ->get_direction()") broke tegra_gpio_irq_set_type() because requesting of GPIO direction must be done after enabling GPIO function for a pin. This patch fixes drivers probe failure like this: gpio gpiochip0: (tegra-gpio): gpiochip_lock_as_irq: cannot get GPIO direction tegra-gpio 6000d000.gpio: unable to lock Tegra GPIO 144 as IRQ Fixes: 36b312792b97 ("gpiolib: Respect error code of ->get_direction()") Signed-off-by: Dmitry Osipenko <digetx@gmail.com> Acked-by: Jon Hunter <jonathanh@nvidia.com> Tested-by: Jon Hunter <jonathanh@nvidia.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2018-07-29gpio: mxc: add power management supportAnson Huang
GPIO registers could lose context on i.MX7D, when enter LPSR mode, the whole SoC will be powered off except LPSR domain, GPIO banks will lose context in this case, need to restore the context after resume from LPSR mode. This patch adds new compatible string for i.MX7D which supports GPIO power off feature in suspend, and adds the GPIO save/restore operations in noirq suspend/resume phase, since GPIO is fundamental module which could be used by other peripherals' resume phase. Signed-off-by: Anson Huang <Anson.Huang@nxp.com> Reviewed-by: Fabio Estevam <fabio.estevam@nxp.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2018-07-29pinctrl/amd: fix gpio irq level in debugfsDaniel Kurtz
According to the AMD BKDG, the GPIO ActiveLevel bits (10:9) map to: 00 Active High 01 Active Low 10 Active on both edges iff LevelTrig (bit 8) == 0 11 Reserved The current code has a bug where it interprets 00 => Active Low, and 01 => Active High. Fix the bug, restrict "Active on both" to just the edge trigger case, and refactor a bit to make the logic more readable. Signed-off-by: Daniel Kurtz <djkurtz@chromium.org> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2018-07-29qed: remove redundant functions qed_get_cm_pq_idx_rlYueHaibing
There are no in-tree callers of qed_get_cm_pq_idx_rl since it be there, so it can be removed. Signed-off-by: YueHaibing <yuehaibing@huawei.com> Signed-off-by: David S. Miller <davem@davemloft.net>
2018-07-29net-next: mediatek: cleanup unnecessary get chip id and its userSean Wang
Since driver is devicetree-based, all device type and charateristic can be determined by the compatible string and its data. It's unnecessary to create another dependent function to check chip ID and then decide whether the specific funciton is being supported on a certain device. It can be totally replaced by the existing flag, so a cleanup is made by removing the function and the only user, HWLRO. MT2701 also have a missing HWLRO support in old code, so add it the same patch. Signed-off-by: Sean Wang <sean.wang@mediatek.com> Signed-off-by: David S. Miller <davem@davemloft.net>
2018-07-29net-next: mediatek: improve more with using dma_zalloc_coherentSean Wang
Improve more in the existing code by reusing dma_zalloc_coherent instead of dma_alloc_coherent with __GFP_ZERO or superfluous zeroing buffer. Signed-off-by: Sean Wang <sean.wang@mediatek.com> Signed-off-by: David S. Miller <davem@davemloft.net>
2018-07-29pinctrl: stm32: add syscfg mask parameterLudovic Barre
This patch adds mask parameter to define IRQ mux field. This field could vary depend of IRQ mux selection register. To avoid backward compatibility, the drivers set the legacy value by default. Signed-off-by: Ludovic Barre <ludovic.barre@st.com> Acked-by: Alexandre TORGUE <alexandre.torgue@st.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2018-07-29Merge tag 'mlx5e-updates-2018-07-27' of ↵David S. Miller
git://git.kernel.org/pub/scm/linux/kernel/git/saeed/linux Saeed Mahameed says: ==================== mlx5e-updates-2018-07-27 (Vxlan updates) This series from Gal and Saeed provides updates to mlx5 vxlan implementation. Gal, started with three cleanups to reflect the actual hardware vxlan state - reflect 4789 UDP port default addition to software database - check maximum number of vxlan UDP ports - cleanup an unused member in vxlan work Then Gal provides performance optimization by replacing the vxlan radix tree with a hash table. Measuring mlx5e_vxlan_lookup_port execution time: Radix Tree Hash Table --------------- ------------ ------------ Single Stream 161 ns 79 ns (51% improvement) Multi Stream 259 ns 136 ns (47% improvement) Measuring UDP stream packet rate, single fully utilized TX core: Radix Tree: 498,300 PPS Hash Table: 555,468 PPS (11% improvement) Next, from Saeed, vxlan refactoring to allow sharing the vxlan table between different mlx5 netdevice instances like PF and VF representors, this is done by making mlx5 vxlan interface more generic and decoupling it from PF netdevice structures and logic, then moving it into mlx5 core as a low level interface so it can be used by VF representors, which is illustrated in the last patch of the serious. ==================== Signed-off-by: David S. Miller <davem@davemloft.net>
2018-07-29pinctrl: stm32: check node status before new gpio bank registeringAlexandre Torgue
Register a new GPIO bank only if GPIO bank node is enabled. This patch also adds checks on ranges which are defined only if a bank is registered. Signed-off-by: Alexandre Torgue <alexandre.torgue@st.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2018-07-29pinctrl: stm32: fix bank io port numberAlexandre Torgue
In case the exti line is not in line with the bank number (that is the case when there is an hole between two banks, for example GPIOK and then GPIOZ), use "st,bank-ioport" DT property to get the right exti line. Signed-off-by: Amelie Delaunay <amelie.delaunay@st.com> Signed-off-by: Alexandre Torgue <alexandre.torgue@st.com> Reviewed-by: Rob Herring <robh@kernel.org> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2018-07-29failover: change mtu has RTNLStephen Hemminger
When changing MTU, RTNL is held so use rtnl_dereference instead of rcu_dereference. Signed-off-by: Stephen Hemminger <stephen@networkplumber.org> Signed-off-by: David S. Miller <davem@davemloft.net>
2018-07-29gpio-pisosr: add support for get_multipleMorten Hein Tiljeset
Signed-off-by: Morten Hein Tiljeset <morten.tiljeset@prevas.dk> Reviewed-by: Sean Nyekjaer <sean.nyekjaer@prevas.dk> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2018-07-29net: ethernet: ti: cpsw: add missed RX_CTAG feature for second slaveIvan Khoronzhuk
Seems it was missed while adding for first net dev in dual-emac mode. Signed-off-by: Ivan Khoronzhuk <ivan.khoronzhuk@linaro.org> Reviewed-by: Grygorii Strashko <grygorii.strashko@ti.com> Signed-off-by: David S. Miller <davem@davemloft.net>
2018-07-29pinctrl: berlin: add the as370 SoC pinctrl driverJisheng Zhang
Add the pin-controller driver for Synaptics AS370 SoC, with definition of its groups and functions. This uses the core Berlin pinctrl driver. Signed-off-by: Jisheng Zhang <Jisheng.Zhang@synaptics.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2018-07-29NET: stmmac: align DMA stuff to largest cache line lengthEugeniy Paltsev
As for today STMMAC_ALIGN macro (which is used to align DMA stuff) relies on L1 line length (L1_CACHE_BYTES). This isn't correct in case of system with several cache levels which might have L1 cache line length smaller than L2 line. This can lead to sharing one cache line between DMA buffer and other data, so we can lose this data while invalidate DMA buffer before DMA transaction. Fix that by using SMP_CACHE_BYTES instead of L1_CACHE_BYTES for aligning. Signed-off-by: Eugeniy Paltsev <Eugeniy.Paltsev@synopsys.com> Signed-off-by: David S. Miller <davem@davemloft.net>
2018-07-29Merge tag 'linux-can-next-for-4.19-20180727' of ↵David S. Miller
ssh://gitolite.kernel.org/pub/scm/linux/kernel/git/mkl/linux-can-next Marc Kleine-Budde says: ==================== pull-request: can-next 2018-01-16 this is a pull request for net-next/master consisting of 38 patches. Dan Murphy's patch fixes the path to a file in the comment of the CAN Error Message Frame Mask structure. A patch by Colin Ian King fixes a typo in the cc770 driver. The next patch is by me an sorts the Kconfigand Makefile entries of the CAN-USB driver subdir alphabetically. The patch by Jakob Unterwurzacher adds support for the UCAN USB-CAN adapter. YueHaibing's patch replaces a open coded skb_put()+memset() by skb_put_zero() in the CAN-dev infrastructure. Zhu Yi provides a patch to enable multi-queue CAN devices. Three patches by Luc Van Oostenryck fix the return value of several driver's xmit function, I contribute a patch for the a fourth driver. Fabio Estevam's patch switches the flexcan driver to SPDX identifier. Two patches by Jia-Ju Bai replace the mdelay() by a usleep_range() in the sja1000 drivers. The next 6 patches are by Anssi Hannula and refactor the xilinx CAN driver and add support for the xilinx CAN FD core. A patch by Gustavo A. R. Silva adds fallthrough annotation to the peak_usb driver. 5 patches by Stephane Grosjean for the peak CANFD driver do some cleanups and provide more improvements for further firmware releases. The remaining 13 patches are by Jimmy Assarsson and the first clean up the kvaser_usb driver, so that the later patches add support for the Kvaser USB hydra family. ==================== Signed-off-by: David S. Miller <davem@davemloft.net>
2018-07-29qed: remove redundant functions qed_set_gft_event_id_cm_hdrYueHaibing
There are no in-tree callers of qed_set_gft_event_id_cm_hdr. Signed-off-by: YueHaibing <yuehaibing@huawei.com> Signed-off-by: David S. Miller <davem@davemloft.net>
2018-07-29liquidio: remove redundant function cn23xx_dump_vf_iq_regsYueHaibing
There are no in-tree callers. Signed-off-by: YueHaibing <yuehaibing@huawei.com> Signed-off-by: David S. Miller <davem@davemloft.net>
generated by cgit (git 2.34.1) at 2025-09-24 09:07:17 +0000