summaryrefslogtreecommitdiff
path: root/drivers
AgeCommit message (Collapse)Author
2022-10-01random: schedule jitter credit for next jiffy, not in two jiffiesJason A. Donenfeld
Counterintuitively, mod_timer(..., jiffies + 1) will cause the timer to fire not in the next jiffy, but in two jiffies. The way to cause the timer to fire in the next jiffy is with mod_timer(..., jiffies). Doing so then lets us bump the upper bound back up again. Fixes: 50ee7529ec45 ("random: try to actively add entropy rather than passively wait for it") Fixes: 829d680e82a9 ("random: cap jitter samples per bit to factor of HZ") Cc: Dominik Brodowski <linux@dominikbrodowski.net> Cc: Sebastian Andrzej Siewior <bigeasy@linutronix.de> Cc: Sultan Alsawaf <sultan@kerneltoast.com> Signed-off-by: Jason A. Donenfeld <Jason@zx2c4.com>
2022-09-30net: ethernet: mtk_eth_soc: fix state in __mtk_foe_entry_clearDaniel Golle
Setting ib1 state to MTK_FOE_STATE_UNBIND in __mtk_foe_entry_clear routine as done by commit 0e80707d94e4c8 ("net: ethernet: mtk_eth_soc: fix typo in __mtk_foe_entry_clear") breaks flow offloading, at least on older MTK_NETSYS_V1 SoCs, OpenWrt users have confirmed the bug on MT7622 and MT7621 systems. Felix Fietkau suggested to use MTK_FOE_STATE_INVALID instead which works well on both, MTK_NETSYS_V1 and MTK_NETSYS_V2. Tested on MT7622 (Linksys E8450) and MT7986 (BananaPi BPI-R3). Suggested-by: Felix Fietkau <nbd@nbd.name> Fixes: 0e80707d94e4c8 ("net: ethernet: mtk_eth_soc: fix typo in __mtk_foe_entry_clear") Fixes: 33fc42de33278b ("net: ethernet: mtk_eth_soc: support creating mac address based offload entries") Signed-off-by: Daniel Golle <daniel@makrotopia.org> Link: https://lore.kernel.org/r/YzY+1Yg0FBXcnrtc@makrotopia.org Signed-off-by: Jakub Kicinski <kuba@kernel.org>
2022-09-30nfp: add support restart of link auto-negotiationFei Qin
Add support restart of link auto-negotiation. This may be initiated using: # ethtool -r <intf> Signed-off-by: Fei Qin <fei.qin@corigine.com> Signed-off-by: Simon Horman <simon.horman@corigine.com> Signed-off-by: Jakub Kicinski <kuba@kernel.org>
2022-09-30nfp: add support for link auto negotiationYinjun Zhang
Report the auto negotiation capability if it's supported in management firmware, and advertise it if it's enabled. Changing port speed is not allowed when autoneg is enabled. The ethtool <intf> command displays the auto-neg capability: # ethtool enp1s0np0 Settings for enp1s0np0: Supported ports: [ FIBRE ] Supported link modes: Not reported Supported pause frame use: Symmetric Supports auto-negotiation: Yes Supported FEC modes: None RS BASER Advertised link modes: Not reported Advertised pause frame use: Symmetric Advertised auto-negotiation: Yes Advertised FEC modes: None RS BASER Speed: 25000Mb/s Duplex: Full Auto-negotiation: on Port: FIBRE PHYAD: 0 Transceiver: internal Link detected: yes Signed-off-by: Yinjun Zhang <yinjun.zhang@corigine.com> Signed-off-by: Simon Horman <simon.horman@corigine.com> Signed-off-by: Jakub Kicinski <kuba@kernel.org>
2022-09-30nfp: refine the ABI of getting `sp_indiff` infoYinjun Zhang
Considering that whether application firmware is indifferent to port speed is a firmware property instead of port property, now use a new rtsym to get the property instead of parsing per-port tlv caps. With this change, relevant code is moved to `nfp_main` layer. Signed-off-by: Yinjun Zhang <yinjun.zhang@corigine.com> Signed-off-by: Simon Horman <simon.horman@corigine.com> Signed-off-by: Jakub Kicinski <kuba@kernel.org>
2022-09-30nfp: avoid halt of driver init process when non-fatal error happensYinjun Zhang
It's not a fatal error when setting `hwinfo` into management firmware fails, no need to halt the whole driver initialization process. Signed-off-by: Yinjun Zhang <yinjun.zhang@corigine.com> Signed-off-by: Simon Horman <simon.horman@corigine.com> Signed-off-by: Jakub Kicinski <kuba@kernel.org>
2022-09-30nfp: add support for reporting active FEC modeYinjun Zhang
The latest management firmware can now report the active FEC mode. Adapt driver accordingly so that user can get the active FEC mode by running command: # ethtool --show-fec <intf> Also correct use of `fec` field. Signed-off-by: Yinjun Zhang <yinjun.zhang@corigine.com> Signed-off-by: Simon Horman <simon.horman@corigine.com> Signed-off-by: Jakub Kicinski <kuba@kernel.org>
2022-09-30r8169: add rtl_disable_rxdvgate()Chunhao Lin
rtl_disable_rxdvgate() is used for disable RXDV_GATE. It is opposite function of rtl_enable_rxdvgate(). Disable RXDV_GATE does not have to delay. So in this patch, also remove the delay after disale RXDV_GATE. Signed-off-by: Chunhao Lin <hau@realtek.com> Link: https://lore.kernel.org/r/20220928171356.3951-1-hau@realtek.com Signed-off-by: Jakub Kicinski <kuba@kernel.org>
2022-09-30Merge tag 'for-net-next-2022-09-30' of ↵Jakub Kicinski
git://git.kernel.org/pub/scm/linux/kernel/git/bluetooth/bluetooth-next Luiz Augusto von Dentz says: ==================== bluetooth-next pull request for net-next - Add RTL8761BUV device (Edimax BT-8500) - Add a new PID/VID 13d3/3583 for MT7921 - Add Realtek RTL8852C support ID 0x13D3:0x3592 - Add VID/PID 0489/e0e0 for MediaTek MT7921 - Add a new VID/PID 0e8d/0608 for MT7921 - Add a new PID/VID 13d3/3578 for MT7921 - Add BT device 0cb8:c549 from RTW8852AE - Add support for Intel Magnetor * tag 'for-net-next-2022-09-30' of git://git.kernel.org/pub/scm/linux/kernel/git/bluetooth/bluetooth-next: (49 commits) Bluetooth: hci_sync: Fix not indicating power state Bluetooth: L2CAP: Fix user-after-free Bluetooth: Call shutdown for HCI_USER_CHANNEL Bluetooth: Prevent double register of suspend Bluetooth: hci_core: Fix not handling link timeouts propertly Bluetooth: hci_event: Make sure ISO events don't affect non-ISO connections Bluetooth: hci_debugfs: Fix not checking conn->debugfs Bluetooth: hci_sysfs: Fix attempting to call device_add multiple times Bluetooth: MGMT: fix zalloc-simple.cocci warnings Bluetooth: hci_{ldisc,serdev}: check percpu_init_rwsem() failure Bluetooth: use hdev->workqueue when queuing hdev->{cmd,ncmd}_timer works Bluetooth: L2CAP: initialize delayed works at l2cap_chan_create() Bluetooth: RFCOMM: Fix possible deadlock on socket shutdown/release Bluetooth: hci_sync: allow advertise when scan without RPA Bluetooth: btusb: Add a new VID/PID 0e8d/0608 for MT7921 Bluetooth: btusb: Add a new PID/VID 13d3/3583 for MT7921 Bluetooth: avoid hci_dev_test_and_set_flag() in mgmt_init_hdev() Bluetooth: btintel: Mark Intel controller to support LE_STATES quirk Bluetooth: btintel: Add support for Magnetor Bluetooth: btusb: Add a new PID/VID 13d3/3578 for MT7921 ... ==================== Link: https://lore.kernel.org/r/20221001004602.297366-1-luiz.dentz@gmail.com Signed-off-by: Jakub Kicinski <kuba@kernel.org>
2022-09-30clk: mvebu: armada-37xx-tbg: Remove the unneeded result variableye xingchen
Return the value of_clk_add_hw_provider() directly instead of storing it in another redundant variable. Reported-by: Zeal Robot <zealci@zte.com.cn> Signed-off-by: ye xingchen <ye.xingchen@zte.com.cn> Link: https://lore.kernel.org/r/20220906072322.337253-1-ye.xingchen@zte.com.cn Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2022-09-30clk: ti: dra7-atl: Fix reference leak in of_dra7_atl_clk_probeMiaoqian Lin
pm_runtime_get_sync() will increment pm usage counter. Forgetting to putting operation will result in reference leak. Add missing pm_runtime_put_sync in some error paths. Fixes: 9ac33b0ce81f ("CLK: TI: Driver for DRA7 ATL (Audio Tracking Logic)") Signed-off-by: Miaoqian Lin <linmq006@gmail.com> Link: https://lore.kernel.org/r/20220602030838.52057-1-linmq006@gmail.com Reviewed-by: Tony Lindgren <tony@atomide.com> Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2022-09-30clk: Renesas versaclock7 ccf device driverAlex Helms
Renesas Versaclock7 is a family of configurable clock generator ICs with fractional and integer dividers. This driver has basic support for the RC21008A device, a clock synthesizer with a crystal input and 8 outputs. The supports changing the FOD and IOD rates, and each output can be gated. Signed-off-by: Alex Helms <alexander.helms.jy@renesas.com> Link: https://lore.kernel.org/r/20220912183613.22213-3-alexander.helms.jy@renesas.com Tested-by: Saeed Nowshadi <saeed.nowshadi@amd.com> Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2022-09-30clk: ti: Balance of_node_get() calls for of_find_node_by_name()Liang He
In ti_find_clock_provider(), of_find_node_by_name() will call of_node_put() for the 'from' argument, possibly putting the node one too many times. Let's maintain the of_node_get() from the previous search and only put when we're exiting the function early. This should avoid a misbalanced reference count on the node. Fixes: 51f661ef9a10 ("clk: ti: Add ti_find_clock_provider() to use clock-output-names") Signed-off-by: Liang He <windhl@126.com> Link: https://lore.kernel.org/r/20220915031121.4003589-1-windhl@126.com [sboyd@kernel.org: Rewrite commit text, maintain reference instead of get again] Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2022-09-30clk: imx: scu: fix memleak on platform_device_add() failsLin Yujun
No error handling is performed when platform_device_add() fails. Add error processing before return, and modified the return value. Fixes: 77d8f3068c63 ("clk: imx: scu: add two cells binding support") Signed-off-by: Lin Yujun <linyujun809@huawei.com> Link: https://lore.kernel.org/r/20220914033206.98046-1-linyujun809@huawei.com Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2022-09-30clk: vc5: Use regmap_{set,clear}_bits() where appropriateLars-Peter Clausen
regmap_set_bits() and regmap_clear_bits() are variations of regmap_update_bits() that can be used if all bits of the mask have to be set to either 1 or 0 respectively. Update the versaclk driver to use regmap_set_bits() and regmap_clear_bits() where appropriate. This results in slightly more compact code and also makes the intention of the code clearer which can help with review. Signed-off-by: Lars-Peter Clausen <lars@metafoo.de> Link: https://lore.kernel.org/r/20220719094637.844946-2-lars@metafoo.de Reviewed-by: Luca Ceresoli <luca@lucaceresoli.net> Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2022-09-30clk: vc5: Check IO access resultsLars-Peter Clausen
The devices of the versaclk clock generator family use an I2C control bus. IO access on an I2C bus can fail for various reasons. The driver currently ignores the return value of most IO operations. This results in silent failure. To avoid this check the return value and in case of an error abort the operation and propagate the error code to the caller. Signed-off-by: Lars-Peter Clausen <lars@metafoo.de> Link: https://lore.kernel.org/r/20220719094637.844946-1-lars@metafoo.de Reviewed-by: Luca Ceresoli <luca@lucaceresoli.net> Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2022-09-30Merge tag 'drm-fixes-2022-10-01' of git://anongit.freedesktop.org/drm/drmLinus Torvalds
Pull drm fixes from Daniel Vetter: "Some last minute amd fixes: - VCN 4.x and GC 11.x fixes, mostly around fw" * tag 'drm-fixes-2022-10-01' of git://anongit.freedesktop.org/drm/drm: drm/amdgpu/gfx11: switch to amdgpu_gfx_rlc_init_microcode drm/amdgpu: add helper to init rlc firmware drm/amdgpu: add helper to init rlc fw in header v2_4 drm/amdgpu: add helper to init rlc fw in header v2_3 drm/amdgpu: add helper to init rlc fw in header v2_2 drm/amdgpu: add helper to init rlc fw in header v2_1 drm/amdgpu: add helper to init rlc fw in header v2_0 drm/amdgpu: save rlcv/rlcp ucode version in amdgpu_gfx drm/amdgpu: Enable sram on vcn_4_0_2 drm/amdgpu: Enable VCN DPG for GC11_0_1
2022-09-30Merge tag 'clk-fixes-for-linus' of ↵Linus Torvalds
git://git.kernel.org/pub/scm/linux/kernel/git/clk/linux Pull clk driver fixes from Stephen Boyd: "Here's the last batch of clk driver fixes for this release. These patches fix serious problems, for example, i.MX has an issue where changing the NAND clk frequency hangs the system. On Allwinner H6 the GPU is being overclocked which could lead to long term hardware damage. And finally on some Broadcom SoCs the serial console stopped working because the clk tree hierarchy description got broken by an inadvertant DT node name change. That's fixed by using 'clock-output-names' to generate a stable and unique name for clks so the framework can properly link things up. There's also a couple build fixes in here. One to fix CONFIG_OF=n builds and one to avoid an array out of bounds bug that happens during clk registration on microchip. I hope that KASAN would have found that OOB problem, but probably KASAN wasn't attempted. Instead LLVM/clang compilation caused an oops, while GCC didn't" * tag 'clk-fixes-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/clk/linux: clk: imx93: drop of_match_ptr clk: iproc: Do not rely on node name for correct PLL setup clk: sunxi-ng: h6: Fix default PLL GPU rate clk: imx: imx6sx: remove the SET_RATE_PARENT flag for QSPI clocks clk: microchip: mpfs: make the rtc's ahb clock critical clk: microchip: mpfs: fix clk_cfg array bounds violation clk: ingenic-tcu: Properly enable registers before accessing timers
2022-09-30clk: mediatek: add driver for MT8365 SoCFabien Parent
Add clock drivers for MT8365 SoC. Signed-off-by: Fabien Parent <fparent@baylibre.com> Signed-off-by: Markus Schneider-Pargmann <msp@baylibre.com> Link: https://lore.kernel.org/r/20220822152652.3499972-5-msp@baylibre.com Reported-by: kernel test robot <lkp@intel.com> Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2022-09-30clk: mediatek: Export required common code symbolsMarkus Schneider-Pargmann
To make clk-mt8365 compilable as a module there are a few function symbols missing. This patch adds the required EXPORT_SYMBOL_GPL to the functions. Signed-off-by: Markus Schneider-Pargmann <msp@baylibre.com> Link: https://lore.kernel.org/r/20220822152652.3499972-4-msp@baylibre.com Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2022-09-30clk: mediatek: Provide mtk_devm_alloc_clk_dataMarkus Schneider-Pargmann
Provide a helper that replaces the kzalloc with devm_kzalloc so error handling gets easier. Signed-off-by: Markus Schneider-Pargmann <msp@baylibre.com> Link: https://lore.kernel.org/r/20220822152652.3499972-3-msp@baylibre.com Reported-by: kernel test robot <lkp@intel.com> Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2022-09-30clkdev: Simplify devm_clk_hw_register_clkdev() functionAndy Shevchenko
Use devm_add_action_or_reset() instead of devres_alloc() and devres_add(), which works the same. This will simplify the code. There is no functional changes. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Link: https://lore.kernel.org/r/20220623115719.52683-3-andriy.shevchenko@linux.intel.com Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2022-09-30clkdev: Remove never used devm_clk_release_clkdev()Andy Shevchenko
For the entire history of the devm_clk_release_clkdev() existence (since 2018) it was never used. Remove it for good. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Link: https://lore.kernel.org/r/20220623115719.52683-2-andriy.shevchenko@linux.intel.com Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2022-09-30clk: Remove never used devm_of_clk_del_provider()Andy Shevchenko
For the entire history of the devm_of_clk_del_provider) existence (since 2017) it was never used. Remove it for good. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Link: https://lore.kernel.org/r/20220623115719.52683-1-andriy.shevchenko@linux.intel.com Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2022-09-30clk: bcm: rpi: Add support for VEC clockDom Cobley
Platform driver clk-bcm2835 gets an inaccurate clock for VEC (107MHz). Export VEC clock trough clk-raspberrypi which uses the right PLL to get an accurate 108MHz. Signed-off-by: Dom Cobley <popcornmix@gmail.com> [iivanov: Adapted on top of v5.17-rc6] Signed-off-by: Ivan T. Ivanov <iivanov@suse.de> Link: https://lore.kernel.org/r/20220829152154.147250-4-iivanov@suse.de Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2022-09-30clk: bcm: rpi: Handle pixel clock in firmwareIvan T. Ivanov
The clk-bcm2835 handling of the pixel clock does not function correctly when the HDMI power domain is disabled. The firmware supports it correctly, so add it to the firmware clock driver. Acked-by: Maxime Ripard <maxime@cerno.tech> Acked-by: Dave Stevenson <dave.stevenson@raspberrypi.com> Signed-off-by: Ivan T. Ivanov <iivanov@suse.de> Link: https://lore.kernel.org/r/20220829152154.147250-3-iivanov@suse.de Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2022-09-30clk: bcm: rpi: Add support HEVC clockIvan T. Ivanov
Export clock required for RPiVid video decoder hardware. Cc: Dom Cobley <popcornmix@gmail.com> Acked-by: Maxime Ripard <maxime@cerno.tech> Signed-off-by: Ivan T. Ivanov <iivanov@suse.de> Link: https://lore.kernel.org/r/20220829152154.147250-2-iivanov@suse.de Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2022-09-30clk: bcm2835: fix bcm2835_clock_rate_from_divisor declarationStefan Wahren
The return value of bcm2835_clock_rate_from_divisor is always unsigned and also all caller expect this. So fix the declaration accordingly. Fixes: 41691b8862e2 ("clk: bcm2835: Add support for programming the audio domain clocks") Signed-off-by: Stefan Wahren <stefan.wahren@i2se.com> Link: https://lore.kernel.org/r/20220904141037.38816-1-stefan.wahren@i2se.com Reviewed-by: Ivan T. Ivanov <iivanov@suse.de> Reviewed-by: Florian Fainelli <f.fainelli@gmail.com> Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2022-09-30clk: bcm2835: Round UART input clock upIvan T. Ivanov
It was reported that RPi3[1] and RPi Zero 2W boards have issues with the Bluetooth. It turns out that when switching from initial to operation speed host and device no longer can talk each other because host uses incorrect UART baud rate. The UART driver used in this case is amba-pl011. Original fix, see below Github link[2], was inside pl011 module, but somehow it didn't look as the right place to fix. Beside that this original rounding function is not exactly perfect for all possible clock values. So I deiced to move the hack to the platform which actually need it. The UART clock is initialised to be as close to the requested frequency as possible without exceeding it. Now that there is a clock manager that returns the actual frequencies, an expected 48MHz clock is reported as 47999625. If the requested baud rate == requested clock/16, there is no headroom and the slight reduction in actual clock rate results in failure. If increasing a clock by less than 0.1% changes it from ..999.. to ..000.., round it up. [1] https://bugzilla.suse.com/show_bug.cgi?id=1188238 [2] https://github.com/raspberrypi/linux/commit/ab3f1b39537f6d3825b8873006fbe2fc5ff057b7 Cc: Phil Elwell <phil@raspberrypi.com> Signed-off-by: Ivan T. Ivanov <iivanov@suse.de> Reviewed-by: Stefan Wahren <stefan.wahren@i2se.com> Link: https://lore.kernel.org/r/20220912081306.24662-1-iivanov@suse.de Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2022-09-30clk: bcm2835: Make peripheral PLLC criticalMaxime Ripard
When testing for a series affecting the VEC, it was discovered that turning off and on the VEC clock is crashing the system. It turns out that, when disabling the VEC clock, it's the only child of the PLLC-per clock which will also get disabled. The source of the crash is PLLC-per being disabled. It's likely that some other device might not take a clock reference that it actually needs, but it's unclear which at this point. Let's make PLLC-per critical so that we don't have that crash. Reported-by: Noralf Trønnes <noralf@tronnes.org> Signed-off-by: Maxime Ripard <maxime@cerno.tech> Link: https://lore.kernel.org/r/20220926084509.12233-1-maxime@cerno.tech Reviewed-by: Stefan Wahren <stefan.wahren@i2se.com> Acked-by: Noralf Trønnes <noralf@tronnes.org> Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2022-09-30of: base: make of_device_compatible_match() accept const device nodeDmitry Torokhov
of_device_is_compatible() accepts const device node pointer, there is no reason why of_device_compatible_match() can't do the same. Signed-off-by: Dmitry Torokhov <dmitry.torokhov@gmail.com> Link: https://lore.kernel.org/r/YzY5MaU5N4A2st5R@google.com Signed-off-by: Rob Herring <robh@kernel.org>
2022-09-30clk: baikal-t1: Convert to platform device driverSerge Semin
In accordance with the way the MIPS platform is normally design there are only six clock sources which need to be available on the kernel start in order to one end up booting correctly: + CPU PLL: needed by the r4k and MIPS GIC timer drivers. The former one is initialized by the arch code, while the later one is implemented in the mips-gic-timer.c driver as the OF-declared timer. + PCIe PLL: required as a parental clock source for the APB/timer domains. + APB clock: needed in order to access all the SoC CSRs at least for the timer OF-declared drivers. + APB Timer{0-2} clocks: these are the DW APB timers which drivers dw_apb_timer_of.c are implemented as the OF-declared timers. So as long as the clocks above are available early the kernel will normally work. Let's convert the Baikal-T1 CCU drivers to the platform device drivers keeping that in mind. Generally speaking the conversion isn't that complicated since the driver infrastructure has been designed as flexible enough for that. First we need to add a new PLL/Divider clock features flag which indicates the corresponding clock source as a basic one and that clock sources will be available on the kernel early boot stages. Second the internal PLL/Divider descriptors need to be initialized with -EPROBE_DEFER value as the corresponding clock source is unavailable at the early stages. They will be allocated and initialized on the Baikal-T1 clock platform driver probe procedure. Finally the already available PLL/Divider init functions need to be split up into two ones: init procedure performed in the framework of the OF-declared clock initialization (of_clk_init()), and the probe procedure called by the platform devices bus driver. Note the later method will just continue the system clocks initialization started in the former one. Signed-off-by: Serge Semin <Sergey.Semin@baikalelectronics.ru> Link: https://lore.kernel.org/r/20220929225402.9696-9-Sergey.Semin@baikalelectronics.ru [sboyd@kernel.org: Remove module things because the Kconfig is still bool] Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2022-09-30clk: baikal-t1: Add DDR/PCIe directly controlled resets supportSerge Semin
Aside with a set of the trigger-like resets Baikal-T1 CCU provides two additional blocks with directly controlled reset signals. In particular it concerns DDR full and initial resets and various PCIe sub-domains resets. Let's add the direct reset assertion/de-assertion of the corresponding flags support into the Baikal-T1 CCU driver then. It will be required at least for the PCIe platform driver. Obviously the DDR controller isn't supposed to be fully reset in the kernel, so the corresponding controls are added just for the sake of the interface implementation completeness. Signed-off-by: Serge Semin <Sergey.Semin@baikalelectronics.ru> Reviewed-by: Philipp Zabel <p.zabel@pengutronix.de> Link: https://lore.kernel.org/r/20220929225402.9696-8-Sergey.Semin@baikalelectronics.ru Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2022-09-30clk: baikal-t1: Move reset-controls code into a dedicated moduleSerge Semin
Before adding the directly controlled resets support it's reasonable to move the existing resets control functionality into a dedicated object for the sake of the CCU dividers clock driver simplification. After the new functionality was added clk-ccu-div.c would have got to a mixture of the weakly dependent clocks and resets methods. Splitting the methods up into the two objects will make the code easier to read and maintain. It shall also improve the code scalability (though hopefully we won't need this part that much in the future). The reset control functionality is now implemented in the framework of a single unit since splitting it up doesn't make much sense due to relatively simple reset operations. The ccu-rst.c has been designed to be looking like ccu-div.c or ccu-pll.c with two globally available methods for the sake of the code unification and better code readability. This commit doesn't provide any change in the CCU reset implementation semantics. As before the driver will support the trigger-like CCU resets only, which are responsible for the AXI-bus, APB-bus and SATA-ref blocks reset. The assert/de-assert-capable reset controls support will be added in the next commit. Note the CCU Clock dividers and resets functionality split up was possible due to not having any side-effects (at least we didn't found ones) of the regmap-based concurrent access of the common CCU dividers/reset CSRs. Signed-off-by: Serge Semin <Sergey.Semin@baikalelectronics.ru> Reviewed-by: Philipp Zabel <p.zabel@pengutronix.de> Link: https://lore.kernel.org/r/20220929225402.9696-6-Sergey.Semin@baikalelectronics.ru Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2022-09-30clk: baikal-t1: Add SATA internal ref clock bufferSerge Semin
It turns out the internal SATA reference clock signal will stay unavailable for the SATA interface consumer until the buffer on it's way is ungated. So aside with having the actual clock divider enabled we need to ungate a buffer placed on the signal way to the SATA controller (most likely some rudiment from the initial SoC release). Seeing the switch flag is placed in the same register as the SATA-ref clock divider at a non-standard ffset, let's implement it as a separate clock controller with the set-rate propagation to the parental clock divider wrapper. As such we'll be able to disable/enable and still change the original clock source rate. Fixes: 353afa3a8d2e ("clk: Add Baikal-T1 CCU Dividers driver") Signed-off-by: Serge Semin <Sergey.Semin@baikalelectronics.ru> Link: https://lore.kernel.org/r/20220929225402.9696-5-Sergey.Semin@baikalelectronics.ru Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2022-09-30clk: baikal-t1: Add shared xGMAC ref/ptp clocks internal parentSerge Semin
Baikal-T1 CCU reference manual says that both xGMAC reference and xGMAC PTP clocks are generated by two different wrappers with the same constant divider thus each producing a 156.25 MHz signal. But for some reason both of these clock sources are gated by a single switch-flag in the CCU registers space - CCU_SYS_XGMAC_BASE.BIT(0). In order to make the clocks handled independently we need to define a shared parental gate so the base clock signal would be switched off only if both of the child-clocks are disabled. Note the ID is intentionally set to -2 since we are going to add a one more internal clock identifier in the next commit. Fixes: 353afa3a8d2e ("clk: Add Baikal-T1 CCU Dividers driver") Signed-off-by: Serge Semin <Sergey.Semin@baikalelectronics.ru> Link: https://lore.kernel.org/r/20220929225402.9696-4-Sergey.Semin@baikalelectronics.ru Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2022-09-30clk: baikal-t1: Fix invalid xGMAC PTP clock dividerSerge Semin
Most likely due to copy-paste mistake the divider has been set to 10 while according to the SoC reference manual it's supposed to be 8 thus having PTP clock frequency of 156.25 MHz. Fixes: 353afa3a8d2e ("clk: Add Baikal-T1 CCU Dividers driver") Signed-off-by: Serge Semin <Sergey.Semin@baikalelectronics.ru> Link: https://lore.kernel.org/r/20220929225402.9696-3-Sergey.Semin@baikalelectronics.ru Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2022-09-30clk: vc5: Fix 5P49V6901 outputs disabling when enabling FODSerge Semin
We have discovered random glitches during the system boot up procedure. The problem investigation led us to the weird outcomes: when none of the Renesas 5P49V6901 ports are explicitly enabled by the kernel driver, the glitches disappeared. It was a mystery since the SoC external clock domains were fed with different 5P49V6901 outputs. The driver code didn't seem like bogus either. We almost despaired to find out a root cause when the solution has been found for a more modern revision of the chip. It turned out the 5P49V6901 clock generator stopped its output for a short period of time during the VC5_OUT_DIV_CONTROL register writing. The same problem was found for the 5P49V6965 revision of the chip and was successfully fixed in commit fc336ae622df ("clk: vc5: fix output disabling when enabling a FOD") by enabling the "bypass_sync" flag hidden inside "Unused Factory Reserved Register". Even though the 5P49V6901 registers description and programming guide doesn't provide any intel regarding that flag, setting it up anyway in the officially unused register completely eliminated the denoted glitches. Thus let's activate the functionality submitted in commit fc336ae622df ("clk: vc5: fix output disabling when enabling a FOD") for the Renesas 5P49V6901 chip too in order to remove the ports implicit inter-dependency. Fixes: dbf6b16f5683 ("clk: vc5: Add support for IDT VersaClock 5P49V6901") Signed-off-by: Serge Semin <Sergey.Semin@baikalelectronics.ru> Reviewed-by: Luca Ceresoli <luca@lucaceresoli.net> Link: https://lore.kernel.org/r/20220929225402.9696-2-Sergey.Semin@baikalelectronics.ru Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2022-09-30Merge tag 'amd-drm-fixes-6.0-2022-09-30-1' of ↵Daniel Vetter
https://gitlab.freedesktop.org/agd5f/linux into drm-fixes amd-drm-fixes-6.0-2022-09-30-1: amdgpu: - VCN 4.x fixes - RLC fixes for GC 11.x Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch> From: Alex Deucher <alexander.deucher@amd.com> Link: https://patchwork.freedesktop.org/patch/msgid/20220930210454.542719-1-alexander.deucher@amd.com
2022-09-30drm/amdgpu/gfx11: switch to amdgpu_gfx_rlc_init_microcodeHawking Zhang
switch to common helper to initialize rlc firmware for gfx11 Signed-off-by: Hawking Zhang <Hawking.Zhang@amd.com> Acked-by: Christian König <christian.koenig@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2022-09-30drm/amdgpu: add helper to init rlc firmwareHawking Zhang
To initialzie rlc firmware according to rlc firmware header version v2: squash in backwards compat fix Signed-off-by: Hawking Zhang <Hawking.Zhang@amd.com> Acked-by: Christian König <christian.koenig@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2022-09-30drm/amdgpu: add helper to init rlc fw in header v2_4Hawking Zhang
To initialize rlc firmware in header v2_4 Signed-off-by: Hawking Zhang <Hawking.Zhang@amd.com> Acked-by: Christian König <christian.koenig@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2022-09-30drm/amdgpu: add helper to init rlc fw in header v2_3Hawking Zhang
To initialize rlc firmware in header v2_3 Signed-off-by: Hawking Zhang <Hawking.Zhang@amd.com> Acked-by: Christian König <christian.koenig@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2022-09-30drm/amdgpu: add helper to init rlc fw in header v2_2Hawking Zhang
To initialize rlc firmware in header v2_2 Signed-off-by: Hawking Zhang <Hawking.Zhang@amd.com> Acked-by: Christian König <christian.koenig@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2022-09-30drm/amdgpu: add helper to init rlc fw in header v2_1Hawking Zhang
To initialize rlc firmware in header v2_1 Signed-off-by: Hawking Zhang <Hawking.Zhang@amd.com> Acked-by: Christian König <christian.koenig@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2022-09-30drm/amdgpu: add helper to init rlc fw in header v2_0Hawking Zhang
To initialize rlc firmware in header v2_0 Signed-off-by: Hawking Zhang <Hawking.Zhang@amd.com> Acked-by: Christian König <christian.koenig@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2022-09-30drm/amdgpu: save rlcv/rlcp ucode version in amdgpu_gfxHawking Zhang
cache rlcv/rlcvp ucode version info in amdgpu_gfx structure Signed-off-by: Hawking Zhang <Hawking.Zhang@amd.com> Reviewed-by: Likun Gao <Likun.Gao@amd.com> Reviewed-by: Feifei Xu <Feifei.Xu@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2022-09-30clk: davinci: cfgchip: Use dev_err_probe() helperYang Yingliang
dev_err() can be replace with dev_err_probe() which will check if error code is -EPROBE_DEFER. Signed-off-by: Yang Yingliang <yangyingliang@huawei.com> Link: https://lore.kernel.org/r/20220913032228.985852-1-yangyingliang@huawei.com Reviewed-by: David Lechner <david@lechnology.com> Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2022-09-30clk: davinci: pll: fix spelling typo in commentJiangshan Yi
Fix spelling typo in comment. Reported-by: k2ci <kernel-bot@kylinos.cn> Signed-off-by: Jiangshan Yi <yijiangshan@kylinos.cn> Link: https://lore.kernel.org/r/20220905065833.1831473-1-13667453960@163.com Reviewed-by: David Lechner <david@lechnology.com> Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2022-09-30clk: mmp: pxa168: control shared SDH bits with separate clockDoug Brown
The PXA168 has a peculiar setup with the AXI clock enable control for the SDHC controllers. The bits in the SDH0 register control the AXI clock enable for both SDH0 and SDH1. Likewise, the bits in the SDH2 register control both SDH2 and SDH3. This is modeled with two new parentless clocks that control the shared bits. Previously, SDH0 had to be enabled in order for SDH1 to be used, and when SDH1 was enabled, unused bits in the SDH1 register were being controlled. This fixes those issues. A future commit will add support for these new shared clocks to be enabled by the PXA168 SDHC driver. Signed-off-by: Doug Brown <doug@schmorgal.com> Link: https://lore.kernel.org/r/20220612192937.162952-13-doug@schmorgal.com Signed-off-by: Stephen Boyd <sboyd@kernel.org>
generated by cgit (git 2.34.1) at 2025-09-13 21:11:43 +0000