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2019-09-03Merge tag 'soc-fsl-next-v5.4' of ↵Arnd Bergmann
git://git.kernel.org/pub/scm/linux/kernel/git/leo/linux into arm/drivers NXP/FSL SoC driver updates for v5.4 DPAA2 DPIO/MC driver - Remove explicit device_link_remove() and device_link_del() calls due to framework change DPAA QBman driver - Various changes to make it working with kexec - Remove dev_err() usage after platform_get_irq() GUTS driver - Add LS1028 SoC support * tag 'soc-fsl-next-v5.4' of git://git.kernel.org/pub/scm/linux/kernel/git/leo/linux: bus: fsl-mc: remove explicit device_link_del soc: fsl: dpio: remove explicit device_link_remove soc: fsl: guts: Add definition for LS1028A soc/fsl/qbman: Update device tree with reserved memory soc/fsl/qbman: Fixup qman_shutdown_fq() soc/fsl/qbman: Disable interrupts during portal recovery soc/fsl/qbman: Fix drain_mr_fqni() soc/fsl/qbman: Cleanup QMan queues if device was already initialized soc/fsl/qbman: Cleanup buffer pools if BMan was initialized prior to bootup soc/fsl/qbman: Rework QBMan private memory setup soc: fsl: qbman: Remove dev_err() usage after platform_get_irq() Link: https://lore.kernel.org/r/20190816195301.26660-1-leoyang.li@nxp.com Signed-off-by: Arnd Bergmann <arnd@arndb.de>
2019-09-03staging: exfat: cleanup braces for if/else statementsValentin Vidic
Fixes checkpatch.pl warnings: CHECK: Unbalanced braces around else statement CHECK: braces {} should be used on all arms of this statement Signed-off-by: Valentin Vidic <vvidic@valentin-vidic.from.hr> Link: https://lore.kernel.org/r/20190903164732.14194-1-vvidic@valentin-vidic.from.hr Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
2019-09-03coresight: tmc-etr: Add barrier packets when moving offset forwardMathieu Poirier
This patch adds barrier packets in the trace stream when the offset in the data buffer needs to be moved forward. Otherwise the decoder isn't aware of the break in the stream and can't synchronise itself with the trace data. Signed-off-by: Mathieu Poirier <mathieu.poirier@linaro.org> Tested-by: Yabin Cui <yabinc@google.com> Reviewed-by: Leo Yan <leo.yan@linaro.org> Link: https://lore.kernel.org/r/20190829202842.580-18-mathieu.poirier@linaro.org Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
2019-09-03coresight: tmc-etr: Decouple buffer sync and barrier packet insertionMathieu Poirier
If less space is available in the perf ring buffer than the ETR buffer, barrier packets inserted in the trace stream by tmc_sync_etr_buf() are skipped over when the head of the buffer is moved forward, resulting in traces that can't be decoded. This patch decouples the process of syncing ETR buffers and the addition of barrier packets in order to perform the latter once the offset in the trace buffer has been properly computed. Signed-off-by: Mathieu Poirier <mathieu.poirier@linaro.org> Reviewed-by: Leo Yan <leo.yan@linaro.org> Link: https://lore.kernel.org/r/20190829202842.580-17-mathieu.poirier@linaro.org Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
2019-09-03coresight: tmc: Make memory width mask computation into a functionMathieu Poirier
Make the computation of a memory mask representing the width of the memory bus into a function so that it can be re-used by the ETR driver. Signed-off-by: Mathieu Poirier <mathieu.poirier@linaro.org> Reviewed-by: Leo Yan <leo.yan@linaro.org> Link: https://lore.kernel.org/r/20190829202842.580-16-mathieu.poirier@linaro.org Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
2019-09-03coresight: tmc-etr: Fix perf_data checkYabin Cui
When tracing etm data of multiple threads on multiple cpus through perf interface, each cpu has a unique etr_perf_buffer while sharing the same etr device. There is no guarantee that the last cpu starts etm tracing also stops last. This makes perf_data check fail. Fix it by checking etr_buf instead of etr_perf_buffer. Also move the code setting and clearing perf_buf to more suitable places. Fixes: 3147da92a8a8 ("coresight: tmc-etr: Allocate and free ETR memory buffers for CPU-wide scenarios") Signed-off-by: Yabin Cui <yabinc@google.com> Signed-off-by: Mathieu Poirier <mathieu.poirier@linaro.org> Link: https://lore.kernel.org/r/20190829202842.580-15-mathieu.poirier@linaro.org Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
2019-09-03coresight: tmc-etr: Fix updating buffer in not-snapshot mode.Yabin Cui
TMC etr always copies all available data to perf aux buffer, which may exceed the available space in perf aux buffer. It isn't suitable for not-snapshot mode, because: 1) It may overwrite previously written data. 2) It may make the perf_event_mmap_page->aux_head report having more or less data than the reality. So change to only copy the latest data fitting the available space in perf aux buffer. Signed-off-by: Yabin Cui <yabinc@google.com> Signed-off-by: Mathieu Poirier <mathieu.poirier@linaro.org> Link: https://lore.kernel.org/r/20190829202842.580-14-mathieu.poirier@linaro.org Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
2019-09-03coresight: etm4x: improve clarity of etm4_os_unlock commentAndrew Murray
To improve clarity, let's update the comment for etm4_os_unlock to use the name of the register as per the ETM architecture specification. The existing comment is also misleading as it suggests any value written to TRCOSLAR unlocks the trace registers, however it must be '0' - let's also correct this. Signed-off-by: Andrew Murray <andrew.murray@arm.com> Reviewed-by: Suzuki K Poulose <suzuki.poulose@arm.com> Signed-off-by: Mathieu Poirier <mathieu.poirier@linaro.org> Link: https://lore.kernel.org/r/20190829202842.580-13-mathieu.poirier@linaro.org Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
2019-09-03coresight: etm4x: use module_param instead of module_param_namedAndrew Murray
Given that the user-exposed module parameter for 'boot_enable' matches the variable that it sets, let's use module_param instead of module_param_named. Let's also use octal permissions (checkpatch recommends this) and provide a module parameter description. Signed-off-by: Andrew Murray <andrew.murray@arm.com> Reviewed-by: Suzuki K Poulose <suzuki.poulose@arm.com> Signed-off-by: Mathieu Poirier <mathieu.poirier@linaro.org> Link: https://lore.kernel.org/r/20190829202842.580-12-mathieu.poirier@linaro.org Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
2019-09-03coresight: etm4x: Use explicit barriers on enable/disableAndrew Murray
Synchronization is recommended before disabling the trace registers to prevent any start or stop points being speculative at the point of disabling the unit (section 7.3.77 of ARM IHI 0064D). Synchronization is also recommended after programming the trace registers to ensure all updates are committed prior to normal code resuming (section 4.3.7 of ARM IHI 0064D). Let's ensure these syncronization points are present in the code and clearly commented. Note that we could rely on the barriers in CS_LOCK and coresight_disclaim_device_unlocked or the context switch to user space - however coresight may be of use in the kernel. On armv8 the mb macro is defined as dsb(sy) - Given that the etm4x is only used on armv8 let's directly use dsb(sy) instead of mb(). This removes some ambiguity and makes it easier to correlate the code with the TRM. Signed-off-by: Andrew Murray <andrew.murray@arm.com> Reviewed-by: Suzuki K Poulose <suzuki.poulose@arm.com> [Fixed capital letter for "use" in title] Signed-off-by: Mathieu Poirier <mathieu.poirier@linaro.org> Link: https://lore.kernel.org/r/20190829202842.580-11-mathieu.poirier@linaro.org Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
2019-09-03coresight: etm4x: Remove superfluous setting of os_unlockAndrew Murray
In addition to unlocking the OS lock, etm4_os_unlock will also set the os_unlock flag. Therefore let's avoid unnecessarily setting os_unlock flag outside of this function. Signed-off-by: Andrew Murray <andrew.murray@arm.com> Reviewed-by: Suzuki K Poulose <suzuki.poulose@arm.com> [Fixed capital letter for "remove" in the title] Signed-off-by: Mathieu Poirier <mathieu.poirier@linaro.org> Link: https://lore.kernel.org/r/20190829202842.580-10-mathieu.poirier@linaro.org Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
2019-09-03coresight: acpi: Static funnel supportSuzuki K Poulose
The ACPI bindings for CoreSight has been updated to add the device id for non-programmable CoreSight funnels (aka static funnels) as of v1.1 [0]. Add the ACPI id for static funnels in the driver. [0] https://static.docs.arm.com/den0067/a/DEN0067_CoreSight_ACPI_1.1.pdf Signed-off-by: Suzuki K Poulose <suzuki.poulose@arm.com> Signed-off-by: Mathieu Poirier <mathieu.poirier@linaro.org> Link: https://lore.kernel.org/r/20190829202842.580-9-mathieu.poirier@linaro.org Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
2019-09-03coresight: Convert pr_warn to dev_warn for obsolete bindingsSuzuki K Poulose
We warn the users of obsolete bindings in the DT for coresight replicator and funnel drivers. However we use pr_warn_once() which doesn't give a clue about which device it is bound to. Let us use dev_warn_once() to give the context. Cc: Mathieu Poirier <mathieu.poirier@linaro.org> Signed-off-by: Suzuki K Poulose <suzuki.poulose@arm.com> Signed-off-by: Mathieu Poirier <mathieu.poirier@linaro.org> Link: https://lore.kernel.org/r/20190829202842.580-8-mathieu.poirier@linaro.org Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
2019-09-03coresight: tmc-etr: Check if non-secure access is enabledSuzuki K Poulose
CoreSight TMC-ETR must have the non-secure invasive debug access enabled for use by self-hosted tracing. Without it, there is no point in enabling the ETR. So, let us check it in the TMC_AUTHSTATUS register and fail the probe if it is disabled. Cc: Mathieu Poirier <mathieu.poirier@linaro.org> Signed-off-by: Suzuki K Poulose <suzuki.poulose@arm.com> Signed-off-by: Mathieu Poirier <mathieu.poirier@linaro.org> Link: https://lore.kernel.org/r/20190829202842.580-7-mathieu.poirier@linaro.org Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
2019-09-03coresight: tmc-etr: Handle memory errorsSuzuki K Poulose
We have so far ignored the memory errors, assuming that we have perfect hardware and driver. Let us handle the memory errors reported by the TMC ETR in status and truncate the buffer. Cc: Mathieu Poirier <mathieu.poirier@linaro.org> Signed-off-by: Suzuki K Poulose <suzuki.poulose@arm.com> [Removed ASCII smiley face from changelog] Signed-off-by: Mathieu Poirier <mathieu.poirier@linaro.org> Link: https://lore.kernel.org/r/20190829202842.580-6-mathieu.poirier@linaro.org Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
2019-09-03coresight: etr_buf: Consolidate refcount initializationSuzuki K Poulose
We now use refcounts for the etr_buf users. Let us initialize it while we allocate it. Cc: Mathieu Poirier <mathieu.poirier@linaro.org> Signed-off-by: Suzuki K Poulose <suzuki.poulose@arm.com> Signed-off-by: Mathieu Poirier <mathieu.poirier@linaro.org> Link: https://lore.kernel.org/r/20190829202842.580-5-mathieu.poirier@linaro.org Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
2019-09-03coresight: cpu-debug: Add support for Qualcomm KryoSai Prakash Ranjan
Add support for coresight CPU debug module on Qualcomm Kryo CPUs. This patch adds the UCI entries for Kryo CPUs found on MSM8996 which shares the same PIDs as ETMs. Without this, below error is observed on MSM8996: [ 5.429867] OF: graph: no port node found in /soc/debug@3810000 [ 5.429938] coresight-etm4x: probe of 3810000.debug failed with error -22 [ 5.435415] coresight-cpu-debug 3810000.debug: Coresight debug-CPU0 initialized [ 5.446474] OF: graph: no port node found in /soc/debug@3910000 [ 5.448927] coresight-etm4x: probe of 3910000.debug failed with error -22 [ 5.454681] coresight-cpu-debug 3910000.debug: Coresight debug-CPU1 initialized [ 5.487765] OF: graph: no port node found in /soc/debug@3a10000 [ 5.488007] coresight-etm4x: probe of 3a10000.debug failed with error -22 [ 5.493024] coresight-cpu-debug 3a10000.debug: Coresight debug-CPU2 initialized [ 5.501802] OF: graph: no port node found in /soc/debug@3b10000 [ 5.512901] coresight-etm4x: probe of 3b10000.debug failed with error -22 [ 5.513192] coresight-cpu-debug 3b10000.debug: Coresight debug-CPU3 initialized Signed-off-by: Sai Prakash Ranjan <saiprakash.ranjan@codeaurora.org> Tested-by: Leo Yan <leo.yan@linaro.org> Signed-off-by: Mathieu Poirier <mathieu.poirier@linaro.org> Link: https://lore.kernel.org/r/20190829202842.580-4-mathieu.poirier@linaro.org Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
2019-09-03coresight: etm4x: Add ETM PIDs for SDM845 and MSM8996Sai Prakash Ranjan
Instead of overriding the peripheral id(PID) check in AMBA by hardcoding them in DT, add the PIDs to the ETM4x driver. Here we use Unique Component Identifier(UCI) for MSM8996 since the ETM and CPU debug module shares the same PIDs. SDM845 does not support CPU debug module. Signed-off-by: Sai Prakash Ranjan <saiprakash.ranjan@codeaurora.org> Reviewed-by: Suzuki K Poulose <suzuki.poulose@arm.com> Signed-off-by: Mathieu Poirier <mathieu.poirier@linaro.org> Link: https://lore.kernel.org/r/20190829202842.580-3-mathieu.poirier@linaro.org Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
2019-09-03coresight: etm4x: Two function calls lessMarkus Elfring
Avoid an extra function call in two function implementations by using a ternary operator instead of a conditional statement. This issue was detected by using the Coccinelle software. Signed-off-by: Markus Elfring <elfring@users.sourceforge.net> Signed-off-by: Mathieu Poirier <mathieu.poirier@linaro.org> Link: https://lore.kernel.org/r/20190829202842.580-2-mathieu.poirier@linaro.org Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
2019-09-03Merge tag 'fpga-cvp-for-5.4' of ↵Greg Kroah-Hartman
git://git.kernel.org/pub/scm/linux/kernel/git/mdf/linux-fpga into char-misc-next Moritz writes: FPGA Manager changes for 5.4-rc1 Here is the second set of changes for the 5.4 merge window. This patchset adds support for the v2 revision of Intel (Altera)'s CVP parts including the Stratix 10. All of this patches have been reviewed and been in the last few linux-next releases without issues. Signed-off-by: Moritz Fischer <mdf@kernel.org> * tag 'fpga-cvp-for-5.4' of git://git.kernel.org/pub/scm/linux/kernel/git/mdf/linux-fpga: fpga: altera-cvp: Add Stratix10 (V2) Support fpga: altera-cvp: Preparation for V2 parts. fpga: altera-cvp: Discover Vendor Specific offset
2019-09-03Merge tag 'thunderbolt-for-v5.4' of ↵Greg Kroah-Hartman
git://git.kernel.org/pub/scm/linux/kernel/git/westeri/thunderbolt into char-misc-next Mika writes: thunderbolt: Changes for v5.4 merge window The biggest change is the addition of Intel Ice Lake integrated Thunderbolt support. There are also a couple of smaller changes like converting the driver to use better device property interface and use correct format string in service key attribute. * tag 'thunderbolt-for-v5.4' of git://git.kernel.org/pub/scm/linux/kernel/git/westeri/thunderbolt: ACPI / property: Add two new Thunderbolt property GUIDs to the list thunderbolt: Add support for Intel Ice Lake thunderbolt: Expose active parts of NVM even if upgrade is not supported thunderbolt: Hide switch attributes that are not set thunderbolt: Do not fail adding switch if some port is not implemented thunderbolt: Use 32-bit writes when writing ring producer/consumer thunderbolt: Move NVM upgrade support flag to struct icm thunderbolt: Correct path indices for PCIe tunnel thunderbolt: Show key using %*pE not %*pEp thunderbolt: Switch to use device_property_count_uXX()
2019-09-03net/mlx5: Add devlink flow_steering_mode parameterMaor Gottlieb
Add new parameter (flow_steering_mode) to control the flow steering mode of the driver. Two modes are supported: 1. DMFS - Device managed flow steering 2. SMFS - Software/Driver managed flow steering. In the DMFS mode, the HW steering entities are created through the FW. In the SMFS mode this entities are created though the driver directly. The driver will use the devlink steering mode only if the steering domain supports it, for now SMFS will manages only the switchdev eswitch steering domain. User command examples: - Set SMFS flow steering mode:: $ devlink dev param set pci/0000:06:00.0 name flow_steering_mode value "smfs" cmode runtime - Read device flow steering mode:: $ devlink dev param show pci/0000:06:00.0 name flow_steering_mode pci/0000:06:00.0: name flow_steering_mode type driver-specific values: cmode runtime value smfs Signed-off-by: Maor Gottlieb <maorg@mellanox.com> Signed-off-by: Saeed Mahameed <saeedm@mellanox.com>
2019-09-03net/mlx5: Add support to use SMFS in switchdev modeMaor Gottlieb
In case that flow steering mode of the driver is SMFS (Software Managed Flow Steering), then use the DR (SW steering) API to create the steering objects. In addition, add a call to the set peer namespace when switchdev gets devcom pair event. It is required to support VF LAG in SMFS. Signed-off-by: Maor Gottlieb <maorg@mellanox.com> Reviewed-by: Mark Bloch <markb@mellanox.com> Signed-off-by: Saeed Mahameed <saeedm@mellanox.com>
2019-09-03net/mlx5: Add API to set the namespace steering modeMaor Gottlieb
Add API to set the flow steering root namesapce mode. Setting new mode should be called before any steering operation is executed on the namespace. This API is going to be used by steering users such switchdev. Signed-off-by: Maor Gottlieb <maorg@mellanox.com> Reviewed-by: Mark Bloch <markb@mellanox.com> Signed-off-by: Saeed Mahameed <saeedm@mellanox.com>
2019-09-03net/mlx5: Add direct rule fs_cmd implementationMaor Gottlieb
Add support to create flow steering objects via direct rule API (SW steering). New layer is added - fs_dr, this layer translates the command that fs_core sends to the FW into direct rule API. In case that direct rule is not supported in some feature then -EOPNOTSUPP is returned. Signed-off-by: Maor Gottlieb <maorg@mellanox.com> Reviewed-by: Mark Bloch <markb@mellanox.com> Signed-off-by: Saeed Mahameed <saeedm@mellanox.com>
2019-09-03net/mlx5: DR, Add CONFIG_MLX5_SW_STEERING for software steering supportAlex Vesker
Add new mlx5 Kconfig flag to allow selecting software steering support and compile all the steering files only if the flag is selected. Signed-off-by: Alex Vesker <valex@mellanox.com> Signed-off-by: Yevgeny Kliteynik <kliteyn@mellanox.com> Reviewed-by: Erez Shitrit <erezsh@mellanox.com> Reviewed-by: Mark Bloch <markb@mellanox.com> Signed-off-by: Saeed Mahameed <saeedm@mellanox.com>
2019-09-03net/mlx5: DR, Expose APIs for direct rule managingAlex Vesker
Expose APIs for direct rule managing to increase insertion rate by bypassing the firmware. Signed-off-by: Alex Vesker <valex@mellanox.com> Reviewed-by: Erez Shitrit <erezsh@mellanox.com> Reviewed-by: Mark Bloch <markb@mellanox.com> Signed-off-by: Saeed Mahameed <saeedm@mellanox.com>
2019-09-03net/mlx5: DR, Add required FW steering functionalityAlex Vesker
SW steering is capable of doing many steering functionalities but there are still some functionalities which are not exposed to upper layers and therefore performed by the FW. This is the support for recalculating checksum using a hairpin QP. The recalculation is required after a modify TTL action which skips the needed CS calculation in HW. Signed-off-by: Alex Vesker <valex@mellanox.com> Reviewed-by: Erez Shitrit <erezsh@mellanox.com> Reviewed-by: Mark Bloch <markb@mellanox.com> Signed-off-by: Saeed Mahameed <saeedm@mellanox.com>
2019-09-03net/mlx5: DR, Expose steering rule functionalityAlex Vesker
Rules are the actual objects that tie matchers, header values and actions. Each rule belongs to a matcher, which can hold multiple rules sharing the same mask. Each rule is a specific set of values and actions. When a packet reaches a matcher it is being matched against the matcher`s rules. In case of a match over a rule its actions will be executed. Each rule object contains a set of STEs, where each STE is a definition of match values and actions defined by the rule. This file handles the rule operations and processing. Signed-off-by: Alex Vesker <valex@mellanox.com> Signed-off-by: Erez Shitrit <erezsh@mellanox.com> Reviewed-by: Mark Bloch <markb@mellanox.com> Signed-off-by: Saeed Mahameed <saeedm@mellanox.com>
2019-09-03net/mlx5: DR, Expose steering action functionalityAlex Vesker
On rule creation a set of actions can be provided, the actions describe what to do with the packet in case of a match. It is possible to provide a set of actions which will be done by order. Signed-off-by: Alex Vesker <valex@mellanox.com> Reviewed-by: Erez Shitrit <erezsh@mellanox.com> Reviewed-by: Mark Bloch <markb@mellanox.com> Signed-off-by: Saeed Mahameed <saeedm@mellanox.com>
2019-09-03net/mlx5: DR, Expose steering matcher functionalityAlex Vesker
Matcher defines which packets fields are matched when a packet arrives. Matcher is a part of a table and can contain one or more rules. Where rule defines specific values of the matcher's mask definition. Signed-off-by: Alex Vesker <valex@mellanox.com> Reviewed-by: Erez Shitrit <erezsh@mellanox.com> Reviewed-by: Mark Bloch <markb@mellanox.com> Signed-off-by: Saeed Mahameed <saeedm@mellanox.com>
2019-09-03net/mlx5: DR, Expose steering table functionalityAlex Vesker
Tables are objects which are used for storing matchers, each table belongs to a domain and defined by the domain type. When a packet reaches the table it is being processed by each of its matchers until a successful match. Tables can hold multiple matchers ordered by matcher priority. Each table has a level. Signed-off-by: Alex Vesker <valex@mellanox.com> Reviewed-by: Erez Shitrit <erezsh@mellanox.com> Reviewed-by: Mark Bloch <markb@mellanox.com> Signed-off-by: Saeed Mahameed <saeedm@mellanox.com>
2019-09-03net/mlx5: DR, Expose steering domain functionalityAlex Vesker
Domain is the frame for all of the dr (direct rule) objects. There are different domain types which also affect the object under that domain. Each domain can hold multiple tables which can hold multiple matchers and so on, this means that all of the dr (direct rule) objects exist under a specific domain. The domain object also holds the resources needed for other objects such as memory management and communication with the device. Signed-off-by: Alex Vesker <valex@mellanox.com> Reviewed-by: Erez Shitrit <erezsh@mellanox.com> Reviewed-by: Mark Bloch <markb@mellanox.com> Signed-off-by: Saeed Mahameed <saeedm@mellanox.com>
2019-09-03net/mlx5: DR, Add Steering entry (STE) utilitiesAlex Vesker
Steering Entry (STE) object is the basic building block of the steering map. There are several types of STEs. Each rule can be constructed of multiple STEs. Each STE dictates which fields of the packet's header are being matched as well as the information about the next step in map (hit and miss pointers). The hardware gets a packet and tries to match it against the STEs, going to either the hit pointer or the miss pointer. This file handles the STE operations. Signed-off-by: Alex Vesker <valex@mellanox.com> Signed-off-by: Erez Shitrit <erezsh@mellanox.com> Reviewed-by: Mark Bloch <markb@mellanox.com> Signed-off-by: Saeed Mahameed <saeedm@mellanox.com>
2019-09-03net/mlx5: DR, Expose an internal API to issue RDMA operationsAlex Vesker
Inserting or deleting a rule is done by RDMA read/write operation to SW ICM device memory. This file provides the support for executing these operations. It includes allocating the needed resources and providing an API for writing steering entries to the memory. Signed-off-by: Alex Vesker <valex@mellanox.com> Signed-off-by: Mark Bloch <markb@mellanox.com> Reviewed-by: Erez Shitrit <erezsh@mellanox.com> Signed-off-by: Saeed Mahameed <saeedm@mellanox.com>
2019-09-03net/mlx5: DR, ICM pool memory allocatorAlex Vesker
ICM device memory is used for writing steering rules (STEs) to the NIC. An ICM memory pool allocator was implemented to manage the required memory. The pool consists of buckets, a bucket per chunk size. Once a bucket is empty we will cut a row of memory from the latest allocated MR, if the MR size is not sufficient we will allocate a new MR. HW design requires that chunks memory address should be aligned to the chunk size, this is the reason for managing the MR with row size that insures memory alignment. Current design is greedy in memory but provides quick allocation times in steady state. Signed-off-by: Alex Vesker <valex@mellanox.com> Reviewed-by: Erez Shitrit <erezsh@mellanox.com> Reviewed-by: Mark Bloch <markb@mellanox.com> Signed-off-by: Saeed Mahameed <saeedm@mellanox.com>
2019-09-03net/mlx5: DR, Add direct rule command utilitiesAlex Vesker
Add direct rule command utilities which consists of all the FW commands that are executed to provide the SW steering functionality. Signed-off-by: Alex Vesker <valex@mellanox.com> Reviewed-by: Erez Shitrit <erezsh@mellanox.com> Reviewed-by: Mark Bloch <markb@mellanox.com> Signed-off-by: Saeed Mahameed <saeedm@mellanox.com>
2019-09-03net/mlx5: DR, Add the internal direct rule types definitionsAlex Vesker
Add the internal header file that contains various types definition that will be used in coming patches as well as the internal functions decelerations. Signed-off-by: Alex Vesker <valex@mellanox.com> Signed-off-by: Yevgeny Kliteynik <kliteyn@mellanox.com> Reviewed-by: Erez Shitrit <erezsh@mellanox.com> Reviewed-by: Mark Bloch <markb@mellanox.com> Signed-off-by: Saeed Mahameed <saeedm@mellanox.com>
2019-09-03net/mlx5: Add flow steering actions to fs_cmd shim layerMaor Gottlieb
Add flow steering actions: modify header and packet reformat to the fs_cmd shim layer. This allows each namespace to define possibly different functionality for alloc/dealloc action commands. Signed-off-by: Maor Gottlieb <maorg@mellanox.com> Reviewed-by: Mark Bloch <markb@mellanox.com> Signed-off-by: Saeed Mahameed <saeedm@mellanox.com>
2019-09-03Merge tag 'phy-for-5.4' of ↵Greg Kroah-Hartman
git://git.kernel.org/pub/scm/linux/kernel/git/kishon/linux-phy into char-misc-next Kishon writes: phy: for 5.4 *) Add a new PHY driver for Lantiq VRX200/ARX300 PCIe PHY *) Add missing of_node_put() to a bunch of drivers using for_each_available_child_of_node() *) Add RXAUI/PCIe/SATA/USB3 support in Marvell's Armada CP110 COMPHY *) Other misc fixes and cleanup Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com> * tag 'phy-for-5.4' of git://git.kernel.org/pub/scm/linux/kernel/git/kishon/linux-phy: (30 commits) phy: marvell: phy-mvebu-cp110-comphy: rename instances of DLT phy: marvell: phy-mvebu-cp110-comphy: implement RXAUI support dt-bindings: pci: add PHY properties to Armada 7K/8K controller bindings dt-bindings: phy: Add Marvell COMPHY clocks phy: mvebu-cp110-comphy: Update comment about powering off all lanes at boot phy: mvebu-cp110-comphy: Add PCIe support phy: mvebu-cp110-comphy: Cosmetic change in a helper phy: mvebu-cp110-comphy: Add SATA support phy: mvebu-cp110-comphy: Add USB3 host/device support phy: mvebu-cp110-comphy: Allow non-Ethernet modes to be configured phy: mvebu-cp110-comphy: Rename the macro handling only Ethernet modes phy: mvebu-cp110-comphy: Add RXAUI support phy: mvebu-cp110-comphy: List already supported Ethernet modes phy: mvebu-cp110-comphy: Add SMC call support phy: mvebu-cp110-comphy: Explicitly initialize the lane submode phy: mvebu-cp110-comphy: Add clocks support phy-rockchip-inno-hdmi: Fix RK3328_TERM_RESISTOR_CALIB_SPEED_7_0's third value phy: qcom-qmp: Correct ready status, again phy: qualcomm: phy-qcom-qmp: Add of_node_put() before return phy: renesas: rcar-gen3-usb2: Disable clearing VBUS in over-current ...
2019-09-03Merge tag 'icc-5.4-rc1' of https://git.linaro.org/people/georgi.djakov/linux ↵Greg Kroah-Hartman
into char-misc-next Georgi writes: interconnect patches for 5.4 Here are the interconnect driver updates for the 5.4-rc1 merge window. - New feature is the path tagging support that helps with grouping and aggregating the bandwidth requests into separate buckets based on a tag. - The first user of the path tagging is the Qualcomm sdm845 driver that now implements support for wake/sleep sets. This allows consumer drivers to express their bandwidth needs for the different CPU power states. - New interconnect driver for the qcs404 platforms and a driver that communicates bandwidth requests with remote processor over shared memory. - Cleanups and fixes. Signed-off-by: Georgi Djakov <georgi.djakov@linaro.org> * tag 'icc-5.4-rc1' of https://git.linaro.org/people/georgi.djakov/linux: drivers: qcom: Add BCM vote macro to header interconnect: qcom: remove COMPILE_TEST from CONFIG_INTERCONNECT_QCOM_QCS404 interconnect: qcom: Add QCS404 interconnect provider driver interconnect: qcom: Add interconnect RPM over SMD driver dt-bindings: interconnect: Add Qualcomm QCS404 DT bindings interconnect: qcom: Add tagging and wake/sleep support for sdm845 interconnect: Add pre_aggregate() callback interconnect: Add support for path tags
2019-09-03hwmon: (w83793d) convert to use devm_i2c_new_dummy_deviceWolfram Sang
And simplify the error handling. Signed-off-by: Wolfram Sang <wsa+renesas@sang-engineering.com> Link: https://lore.kernel.org/r/20190903181256.13450-4-wsa+renesas@sang-engineering.com Signed-off-by: Guenter Roeck <linux@roeck-us.net>
2019-09-03hwmon: (w83792d) convert to use devm_i2c_new_dummy_deviceWolfram Sang
And simplify the error handling. Signed-off-by: Wolfram Sang <wsa+renesas@sang-engineering.com> Link: https://lore.kernel.org/r/20190903181256.13450-3-wsa+renesas@sang-engineering.com Signed-off-by: Guenter Roeck <linux@roeck-us.net>
2019-09-03hwmon: (w83791d) convert to use devm_i2c_new_dummy_deviceWolfram Sang
And simplify the error handling. Signed-off-by: Wolfram Sang <wsa+renesas@sang-engineering.com> Link: https://lore.kernel.org/r/20190903181256.13450-2-wsa+renesas@sang-engineering.com Signed-off-by: Guenter Roeck <linux@roeck-us.net>
2019-09-03hwmon: (as370-hwmon) fix devm_platform_ioremap_resource.cocci warningskbuild test robot
Use devm_platform_ioremap_resource helper which wraps platform_get_resource() and devm_ioremap_resource() together. Generated by: scripts/coccinelle/api/devm_platform_ioremap_resource.cocci Fixes: 658e687b4218 ("hwmon: Add Synaptics AS370 PVT sensor driver") CC: Jisheng Zhang <Jisheng.Zhang@synaptics.com> Signed-off-by: kbuild test robot <lkp@intel.com> Signed-off-by: Julia Lawall <julia.lawall@lip6.fr> Reviewed-by: Jisheng Zhang <Jisheng.Zhang@synaptics.com> Link: https://lore.kernel.org/r/alpine.DEB.2.21.1909030646180.3228@hadrien Signed-off-by: Guenter Roeck <linux@roeck-us.net>
2019-09-03hwmon: (lm75) Add support for writing sampling period on PCT2075Guenter Roeck
For PCT7027, the sampling period is configured using a dedicated register. Signed-off-by: Guenter Roeck <linux@roeck-us.net>
2019-09-03hwmon: (lm75) Add support for writing conversion time for TMP112Guenter Roeck
TMP112 uses an uncommon method to write the conversion time: its configuration register is 16 bit wide, and the conversion time is configured in its second byte. Signed-off-by: Guenter Roeck <linux@roeck-us.net>
2019-09-03hwmon: (lm75) Move updating the sample interval to its own functionGuenter Roeck
We'll need per-chip handling for updating the sample interval. To prepare for it, separate the code implementing it into its own function. Signed-off-by: Guenter Roeck <linux@roeck-us.net>
2019-09-03hwmon: (lm75) Support configuring the sample time for various chipsGuenter Roeck
The conversion (sample) time is configurable for several chips supported by the lm75 driver. With the necessary infrastructure in place, enable this support for all chips using the configuration register for this purpose. DS1775: Conversion time: 187.5, 375, 750, 1500 ms Sensor resolution: 9, 10, 11, 12 bit DS75, STDS75: Conversion time: 150, 300, 600, 1200 ms Sensor resolution: 9, 10, 11, 12 bit DS7505: Conversion time: 25, 50, 100, 200 ms Sensor resolution: 9, 10, 11, 12 bit MCP980[0123]: Conversion time: 75, 150, 300, 600 ms Sensor resolution: 9, 10, 11, 12 bit TMP100, TMP101: Conversion time: 75, 150, 300, 600 ms Sensor resolution: 9, 10, 11, 12 bit TMP75, TMP105, TMP175, TMP275: Conversion time: 38, 75, 150, 300 ms Sensor resolution: 9, 10, 11, 12 bit While doing this, it became obvious that the masks and values to set the converion (sample) time is similar for all those chips, and that other chips with configurable sample times will need separate code anyway. For that reason, replace the sample_set_masks and sample_clr_mask configuration parameters with a single array and with a constant. Signed-off-by: Guenter Roeck <linux@roeck-us.net>
2019-09-03hwmon: (nct7904) Fix incorrect temperature limitation register setting of LTD.amy.shih
According to kernel hwmon sysfs-interface documentation, temperature critical max value, typically greater than corresponding temp_max values. Thus, reads the LTD_HV_HL (LTD HIGH VALUE HIGH LIMITATION) and LTD_LV_HL (LTD LOW VALUE HIGH LIMITATION) for case hwmon_temp_crit and hwmon_temp_crit_hyst. Reads the LTD_HV_LL (HIGH VALUE LOW LIMITATION) and LTD_LV_LL (LOW VALUE LOW LIMITATION) for case hwmon_temp_max and hwmon_temp_max_hyst. Signed-off-by: amy.shih <amy.shih@advantech.com.tw> Link: https://lore.kernel.org/r/20850618155720.24857-1-Amy.Shih@advantech.com.tw Signed-off-by: Guenter Roeck <linux@roeck-us.net>
generated by cgit (git 2.34.1) at 2025-09-21 21:48:21 +0000