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2024-09-02drm/amdgpu/gfx12: per queue reset only on bare metalAlex Deucher
It's not supported under SR-IOV at the moment. Acked-by: Vitaly Prosyak <vitaly.prosyak@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2024-09-02drm/amdgpu/gfx11: per queue reset only on bare metalAlex Deucher
It's not supported under SR-IOV at the moment. Acked-by: Vitaly Prosyak <vitaly.prosyak@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2024-09-02drm/amdgpu/gfx10: per queue reset only on bare metalAlex Deucher
It's not supported under SR-IOV at the moment. Acked-by: Vitaly Prosyak <vitaly.prosyak@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2024-09-02drm/amdgpu/mes11: implement mmio queue reset for gfx11Jiadong Zhu
Implement queue reset for graphic and compute queue. v2: use amdgpu_gfx_rlc funcs to enter/exit safe mode. v3: use gfx_v11_0_request_gfx_index_mutex() v4: fix mutex handling Acked-by: Vitaly Prosyak <vitaly.prosyak@amd.com> Signed-off-by: Jiadong Zhu <Jiadong.Zhu@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2024-09-02drm/amdgpu/mes: implement amdgpu_mes_reset_hw_queue_mmioJiadong Zhu
The reset_queue api could be used from kfd or kgd. v2: add use_mmio parameter for mes_reset_legacy_queue. Acked-by: Vitaly Prosyak <vitaly.prosyak@amd.com> Signed-off-by: Jiadong Zhu <Jiadong.Zhu@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2024-09-02drm/amdgpu/mes: modify mes api for mmio queue resetJiadong Zhu
Add me/pipe/queue parameters for queue reset input. v2: fix build (Alex) Acked-by: Vitaly Prosyak <vitaly.prosyak@amd.com> Signed-off-by: Jiadong Zhu <Jiadong.Zhu@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2024-09-02drm/amdgpu/gfx12: fallback to driver reset compute queue directlyAlex Deucher
Since the MES FW resets kernel compute queue always failed, this may caused by the KIQ failed to process unmap KCQ. So, before MES FW work properly that will fallback to driver executes dequeue and resets SPI directly. Besides, rework the ring reset function and make the busy ring type reset in each function respectively. Acked-by: Vitaly Prosyak <vitaly.prosyak@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2024-09-02drm/amdgpu/gfx12: add ring reset callbacksAlex Deucher
Add ring reset callbacks for gfx and compute. Acked-by: Vitaly Prosyak <vitaly.prosyak@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2024-09-02drm/amdgpu/gfx10: rework reset sequenceAlex Deucher
To match other GFX IPs. Acked-by: Vitaly Prosyak <vitaly.prosyak@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2024-09-02drm/amdgpu/gfx10: wait for reset done before remapJiadong Zhu
There is a racing condition that cp firmware modifies MQD in reset sequence after driver updates it for remapping. We have to wait till CP_HQD_ACTIVE becoming false then remap the queue. v2: fix KIQ locking (Alex) v3: fix KIQ locking harder (Jessie) Acked-by: Vitaly Prosyak <vitaly.prosyak@amd.com> Signed-off-by: Jiadong Zhu <Jiadong.Zhu@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2024-09-02drm/amdgpu/gfx10: remap queue after reset successfullyJiadong Zhu
Kiq command unmap_queues only does the dequeueing action. We have to map the queue back with clean mqd. v2: fix up error handling (Alex) Acked-by: Vitaly Prosyak <vitaly.prosyak@amd.com> Signed-off-by: Jiadong Zhu <Jiadong.Zhu@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2024-09-02drm/amdgpu/gfx10: add ring reset callbacksAlex Deucher
Add ring reset callbacks for gfx and compute. v2: fix gfx handling v3: wait for KIQ to complete Acked-by: Vitaly Prosyak <vitaly.prosyak@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2024-09-02drm/amdgpu/gfx11: wait for reset done before remapJiadong Zhu
There is a racing condition that cp firmware modifies MQD in reset sequence after driver updates it for remapping. We have to wait till CP_HQD_ACTIVE becoming false then remap the queue. Acked-by: Vitaly Prosyak <vitaly.prosyak@amd.com> Signed-off-by: Jiadong Zhu <Jiadong.Zhu@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2024-09-02drm/amdgpu/gfx11: rename gfx_v11_0_gfx_init_queue()Alex Deucher
Rename to gfx_v11_0_kgq_init_queue() to better align with the other naming in the file. Acked-by: Vitaly Prosyak <vitaly.prosyak@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2024-09-02drm/amdgpu/gfx11: fallback to driver reset compute queue directly (v2)Prike Liang
Since the MES FW resets kernel compute queue always failed, this may caused by the KIQ failed to process unmap KCQ. So, before MES FW work properly that will fallback to driver executes dequeue and resets SPI directly. Besides, rework the ring reset function and make the busy ring type reset in each function respectively. Acked-by: Vitaly Prosyak <vitaly.prosyak@amd.com> Signed-off-by: Prike Liang <Prike.Liang@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2024-09-02drm/amd/display: 3.2.299Aric Cyr
This version brings along the following: - DCN35 fixes - DML2 fixes - IPS fixes - ODM fixes - Miscellaneous cleanups - MST fixes - SPL fixes Acked-by: Aurabindo Pillai <aurabindo.pillai@amd.com> Signed-off-by: Aric Cyr <aric.cyr@amd.com> Signed-off-by: Hamza Mahfooz <hamza.mahfooz@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2024-09-02drm/amd/display: Fix flickering caused by dccgHansen Dsouza
Always allow un-gating. Follow legacy workaround for repeated dppclk dto updates Reviewed-by: Muhammad Ahmed <ahmed.ahmed@amd.com> Signed-off-by: Hansen Dsouza <Hansen.Dsouza@amd.com> Signed-off-by: Hamza Mahfooz <hamza.mahfooz@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2024-09-02drm/amd/display: Block timing sync for different signals in PMODillon Varone
PMO assumes that like timings can be synchronized, but DC only allows this if the signal types match. Reviewed-by: Austin Zheng <austin.zheng@amd.com> Signed-off-by: Dillon Varone <dillon.varone@amd.com> Signed-off-by: Hamza Mahfooz <hamza.mahfooz@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2024-09-02drm/amd/display: fix graphics hang in multi-display mst caseGabe Teeger
[what] Graphics hang observed with 3 displays connected to DP2.0 mst dock. [why] There's a mismatch in dml and dc between the assignments of hpo link encoders. [how] Add a new array in dml that tracks the current mapping of HPO stream encoders to HPO link encoders in dc. Reviewed-by: Sung joon Kim <sungjoon.kim@amd.com> Reviewed-by: Nicholas Kazlauskas <nicholas.kazlauskas@amd.com> Signed-off-by: Gabe Teeger <Gabe.Teeger@amd.com> Signed-off-by: Hamza Mahfooz <hamza.mahfooz@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2024-09-02drm/amd/display: Add sharpness control interfaceRelja Vojvodic
- Add interface for controlling shapness level input into DCN. - Update SPL to support custom sharpness values. - Add support for different sharpness values depending on YUV/RGB content. Reviewed-by: Samson Tam <samson.tam@amd.com> Signed-off-by: Relja Vojvodic <Relja.Vojvodic@amd.com> Signed-off-by: Hamza Mahfooz <hamza.mahfooz@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2024-09-02Revert "drm/amd/display: Wait for all pending cleared before full update"Dillon Varone
This reverts commit f0b7dcf25834afd17df316367dfe5d4c890c713c. It is causing graphics hangs. Reviewed-by: Martin Leung <martin.leung@amd.com> Signed-off-by: Dillon Varone <Dillon.Varone@amd.com> Signed-off-by: Hamza Mahfooz <hamza.mahfooz@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2024-09-02drm/amd/display: disable sharpness if HDR Multiplier is too largeSamson Tam
[Why] Certain profiles have higher HDR multiplier than SDR boost max which is not currently supported [How] Disable sharpness for these profiles Fixes: 1b0ce903fe74 ("drm/amd/display: add improvements for text display and HDR DWM and MPO") Reviewed-by: Martin Leung <martin.leung@amd.com> Signed-off-by: Samson Tam <Samson.Tam@amd.com> Signed-off-by: Hamza Mahfooz <hamza.mahfooz@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2024-09-02drm/amd/display: Add dpia debug option to control power managementMeenakshikumar Somasundaram
[Why] To provide option to dpia control power management [How] By adding disable_usb4_pm_support bit field in dpia_debug option to control dpia power management Reviewed-by: Jun Lei <jun.lei@amd.com> Signed-off-by: Meenakshikumar Somasundaram <meenakshikumar.somasundaram@amd.com> Signed-off-by: Hamza Mahfooz <hamza.mahfooz@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2024-09-02drm/amdgpu/gfx11: add ring reset callbacksAlex Deucher
Add ring reset callbacks for gfx and compute. Acked-by: Vitaly Prosyak <vitaly.prosyak@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2024-09-02drm/amd/display: re-enable Dynamic ODM policySamson Tam
[Why] Previous disable ODM policy due to underflow issue with sharpener. Issue is resolved after updating sharpening policy to apply to both windowed and fullscreen video [How] Remove sharpness check disabling Dynamic ODM policy Reviewed-by: Martin Leung <martin.leung@amd.com> Signed-off-by: Samson Tam <Samson.Tam@amd.com> Signed-off-by: Hamza Mahfooz <hamza.mahfooz@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2024-09-02drm/amd/display: Lock DC and exit IPS when changing backlightLeo Li
Backlight updates require aux and/or register access. Therefore, driver needs to disallow IPS beforehand. So, acquire the dc lock before calling into dc to update backlight - we should be doing this regardless of IPS. Then, while the lock is held, disallow IPS before calling into dc, then allow IPS afterwards (if it was previously allowed). Reviewed-by: Aurabindo Pillai <aurabindo.pillai@amd.com> Reviewed-by: Roman Li <roman.li@amd.com> Signed-off-by: Leo Li <sunpeng.li@amd.com> Signed-off-by: Hamza Mahfooz <hamza.mahfooz@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2024-09-02drm/amd/display: only trigger BIOS related assert for older ASICsDaniel Sa
[Why] Some asserts are always hit on startup/Pnp when they should only be used to indicate when something has gone wrong. [How] Ignore result of getting function from bios cmd table for newer asics. Reviewed-by: Jun Lei <jun.lei@amd.com> Signed-off-by: Daniel Sa <Daniel.Sa@amd.com> Signed-off-by: Hamza Mahfooz <hamza.mahfooz@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2024-09-02drm/amd/display: Fix DCN35 set min dispclk logicNicholas Susanto
[Why] Setting min dispclk to 50Mhz outside clock lowering function causes unnecessary calls to SMU to lower dispclk and causes dentist hangs when there is no stream on the pipes. [How] Move the set minimum dispclk logic inside the lowering dispclk if statement. Fixes: 234441320552 ("DCN35 set min dispclk to 50Mhz") Reviewed-by: Nicholas Kazlauskas <nicholas.kazlauskas@amd.com> Signed-off-by: Nicholas Susanto <Nicholas.Susanto@amd.com> Signed-off-by: Hamza Mahfooz <hamza.mahfooz@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2024-09-02drm/amdgpu/gfx9.4.3: Implement compute pipe resetPrike Liang
Implement the compute pipe reset, and the driver will fallback to pipe reset when queue reset fails. The pipe reset only deactivates the queue which is scheduled in the pipe, and meanwhile the MEC pipe will be reset to the firmware _start pointer. So, it seems pipe reset will cost more cycles than the queue reset; therefore, the driver tries to recover by doing queue reset first. Reviewed-by: Lijo Lazar <lijo.lazar@amd.com> Signed-off-by: Prike Liang <Prike.Liang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2024-09-02dm: Make use of __assign_bit() APIHongbo Li
We have for some time the __assign_bit() API to replace open coded if (foo) __set_bit(n, bar); else __clear_bit(n, bar); Use this API to simplify the code. No functional change intended. Signed-off-by: Hongbo Li <lihongbo22@huawei.com> Signed-off-by: Mikulas Patocka <mpatocka@redhat.com>
2024-09-02hwmon: pmbus: pli12096bc: Add write delayPatrick Rudolph
Tests on PLI12096bc showed that sometimes a small delay is necessary after a write operation before a new operation can be processed. If not respected the device will probably NACK the data phase of the SMBus transaction. Tests showed that the probability to observe transaction errors can be raised by either reading sensor data or toggling the regulator enable. Further tests showed that 250 microseconds, as used previously for the CLEAR_FAULTS workaround, is sufficient. Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com> Message-ID: <20240902075319.585656-5-patrick.rudolph@9elements.com> Signed-off-by: Guenter Roeck <linux@roeck-us.net>
2024-09-02hwmon: pmbus: zl6100: Use generic codePatrick Rudolph
Use generic pmbus bus access delay. Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com> Message-ID: <20240902075319.585656-4-patrick.rudolph@9elements.com> Signed-off-by: Guenter Roeck <linux@roeck-us.net>
2024-09-02hwmon: pmbus: ucd9000: Use generic codePatrick Rudolph
Use generic pmbus bus write access delay. Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com> Message-ID: <20240902075319.585656-3-patrick.rudolph@9elements.com> Signed-off-by: Guenter Roeck <linux@roeck-us.net>
2024-09-02hwmon: pmbus: max15301: Use generic codePatrick Rudolph
Use the generic pmbus bus access delay. Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com> Message-ID: <20240902075319.585656-2-patrick.rudolph@9elements.com> Signed-off-by: Guenter Roeck <linux@roeck-us.net>
2024-09-02hwmon: pmbus: Implement generic bus access delayPatrick Rudolph
Some drivers, like the max15301 or zl6100, are intentionally delaying SMBus communications, to prevent transmission errors. As this is necessary on additional PMBus compatible devices, implement a generic delay mechanism in the pmbus core. Introduces two delay settings in the pmbus_driver_info struct, one applies to every SMBus transaction and the other is for write transaction only. Once set by the driver the SMBus traffic, using the generic pmbus access helpers, is automatically delayed when necessary. The two settings are: access_delay: - Unit in microseconds - Stores the accessed timestamp after every SMBus access - Delays when necessary before the next SMBus access write_delay: - Unit in microseconds - Stores the written timestamp after a write SMBus access - Delays when necessary before the next SMBus access This allows to drop the custom delay code from the drivers and easily introduce this feature in additional pmbus drivers. Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com> Message-ID: <20240902075319.585656-1-patrick.rudolph@9elements.com> Signed-off-by: Guenter Roeck <linux@roeck-us.net>
2024-09-02hwmon: (hp-wmi-sensors) Check if WMI event data existsArmin Wolf
The BIOS can choose to return no event data in response to a WMI event, so the ACPI object passed to the WMI notify handler can be NULL. Check for such a situation and ignore the event in such a case. Fixes: 23902f98f8d4 ("hwmon: add HP WMI Sensors driver") Signed-off-by: Armin Wolf <W_Armin@gmx.de> Reviewed-by: Ilpo Järvinen <ilpo.jarvinen@linux.intel.com> Message-ID: <20240901031055.3030-2-W_Armin@gmx.de> Signed-off-by: Guenter Roeck <linux@roeck-us.net>
2024-09-02gpio: modepin: Enable module autoloadingLiao Chen
Add MODULE_DEVICE_TABLE(), so modules could be properly autoloaded based on the alias from of_device_id table. Fixes: 7687a5b0ee93 ("gpio: modepin: Add driver support for modepin GPIO controller") Signed-off-by: Liao Chen <liaochen4@huawei.com> Reviewed-by: Michal Simek <michal.simek@amd.com> Link: https://lore.kernel.org/r/20240902115848.904227-1-liaochen4@huawei.com Signed-off-by: Bartosz Golaszewski <bartosz.golaszewski@linaro.org>
2024-09-02net: stmmac: drop the ethtool begin() callbackAndrew Halaney
This callback doesn't seem to serve much purpose, and prevents things like: - systemd.link files from disabling autonegotiation - carrier detection in NetworkManager - any ethtool setting prior to userspace bringing the link up. The only fear I can think of is accessing unclocked resources due to pm_runtime, but ethtool ioctls handle that as of commit f32a21376573 ("ethtool: runtime-resume netdev parent before ethtool ioctl ops") Reviewed-by: Dmitry Dolenko <d.dolenko@metrotek.ru> Tested-by: Dmitry Dolenko <d.dolenko@metrotek.ru> Signed-off-by: Andrew Halaney <ahalaney@redhat.com> Reviewed-by: Alexander Lobakin <aleksander.lobakin@intel.com> Signed-off-by: David S. Miller <davem@davemloft.net>
2024-09-02igc: Unlock on error in igc_io_resume()Dan Carpenter
Call rtnl_unlock() on this error path, before returning. Fixes: bc23aa949aeb ("igc: Add pcie error handler support") Signed-off-by: Dan Carpenter <dan.carpenter@linaro.org> Reviewed-by: Gerhard Engleder <gerhard@engleder-embedded.com> Signed-off-by: David S. Miller <davem@davemloft.net>
2024-09-02gpio: rockchip: fix OF node leak in probe()Krzysztof Kozlowski
Driver code is leaking OF node reference from of_get_parent() in probe(). Fixes: 936ee2675eee ("gpio/rockchip: add driver for rockchip gpio") Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Reviewed-by: Heiko Stuebner <heiko@sntech.de> Reviewed-by: Shawn Lin <shawn.lin@rock-chips.com> Link: https://lore.kernel.org/r/20240826150832.65657-1-krzysztof.kozlowski@linaro.org Signed-off-by: Bartosz Golaszewski <bartosz.golaszewski@linaro.org>
2024-09-02gpio: pch: kerneldoc fixes for excess membersKrzysztof Kozlowski
Drop kerneldoc description of 'lock' to fix W=1 warning: drivers/gpio/gpio-pch.c:101: warning: Excess struct member 'lock' description in 'pch_gpio' Reviewed-by: Andy Shevchenko <andy@kernel.org> Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Link: https://lore.kernel.org/r/20240902121258.64094-1-krzysztof.kozlowski@linaro.org Signed-off-by: Bartosz Golaszewski <bartosz.golaszewski@linaro.org>
2024-09-02Merge back cpufreq material for 6.12Rafael J. Wysocki
2024-09-02ACPI: CPPC: Fix MASK_VAL() usageClément Léger
MASK_VAL() was added as a way to handle bit_offset and bit_width for registers located in system memory address space. However, while suited for reading, it does not work for writing and result in corrupted registers when writing values with bit_offset > 0. Moreover, when a register is collocated with another one at the same address but with a different mask, the current code results in the other registers being overwritten with 0s. The write procedure for SYSTEM_MEMORY registers should actually read the value, mask it, update it and write it with the updated value. Moreover, since registers can be located in the same word, we must take care of locking the access before doing it. We should potentially use a global lock since we don't know in if register addresses aren't shared with another _CPC package but better not encourage vendors to do so. Assume that registers can use the same word inside a _CPC package and thus, use a per _CPC package lock. Fixes: 2f4a4d63a193 ("ACPI: CPPC: Use access_width over bit_width for system memory accesses") Signed-off-by: Clément Léger <cleger@rivosinc.com> Link: https://patch.msgid.link/20240826101648.95654-1-cleger@rivosinc.com [ rjw: Dropped redundant semicolon ] Signed-off-by: Rafael J. Wysocki <rafael.j.wysocki@intel.com>
2024-09-02irqchip/sifive-plic: Add ACPI supportSunil V L
Add ACPI support in PLIC driver. Use the mapping created early during boot to get details about the PLIC. Signed-off-by: Sunil V L <sunilvl@ventanamicro.com> Co-developed-by: Haibo Xu <haibo1.xu@intel.com> Signed-off-by: Haibo Xu <haibo1.xu@intel.com> Reviewed-by: Anup Patel <anup@brainfault.org> Tested-by: Björn Töpel <bjorn@rivosinc.com> Acked-by: Thomas Gleixner <tglx@linutronix.de> Link: https://patch.msgid.link/20240812005929.113499-18-sunilvl@ventanamicro.com [ rjw: Rebase on top of recent irqchip changes ] Signed-off-by: Rafael J. Wysocki <rafael.j.wysocki@intel.com>
2024-09-02drm/xe/display: remove unused compat kdev_to_i915() and pdev_to_i915()Jani Nikula
The display code no longer uses kdev_to_i915() or pdev_to_i915() helpers. Remove them. Reviewed-by: Gustavo Sousa <gustavo.sousa@intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/05b948f9012fc7c0b97d567c70b0bac8791d554a.1724942754.git.jani.nikula@intel.com Signed-off-by: Jani Nikula <jani.nikula@intel.com>
2024-09-02drm/i915/hdcp: migrate away from kdev_to_i915() in GSC messagingJani Nikula
Use to_intel_display() instead of kdev_to_i915() in the HDCP component API hooks. Avoid further drive-by changes at this point, and just convert the display pointer to i915, and leave the struct intel_display conversion for later. The NULL error checking in the hooks make this a bit cumbersome. I'm not actually sure they're really required, but don't go down that rabbit hole just now. Cc: Gustavo Sousa <gustavo.sousa@intel.com> Reviewed-by: Ankit Nautiyal <ankit.k.nautiyal@intel.com> Reviewed-by: Suraj Kandpal <suraj.kandpal@intel.com> Reviewed-by: Arun R Murthy <arun.r.murthy@intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/efd5c4c164c01b7ee50ad43f202b074b373fb810.1724942754.git.jani.nikula@intel.com Signed-off-by: Jani Nikula <jani.nikula@intel.com>
2024-09-02drm/xe: Fix merge fails related to display runtime PMMaarten Lankhorst
The most recent merge commits introduced some fails to drm/drm-next, I've noticed these when looking at the xe patches. Solve it! Fixes: 8bdb468dd7a5 ("Merge tag 'drm-xe-next-2024-08-28' of https://gitlab.freedesktop.org/drm/xe/kernel into drm-next") Signed-off-by: Maarten Lankhorst <maarten.lankhorst@linux.intel.com> [sima: add fixes line, and drop 3rd hunk because that's just a bugfix, not mismerge, which should go in seperately with proper fixes line and review/testing.] Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch> Link: https://patchwork.freedesktop.org/patch/msgid/20240902112002.489225-1-maarten.lankhorst@linux.intel.com
2024-09-02drm/i915/hdcp: migrate away from kdev_to_i915() in bind/unbindJani Nikula
Use to_intel_display() instead of kdev_to_i915() in the HDCP component API hooks. Avoid further drive-by changes at this point, and just convert the display pointer to i915, and leave the struct intel_display conversion for later. Reviewed-by: Gustavo Sousa <gustavo.sousa@intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/0beedaa438e912828b48d9980f017807e079d7ab.1724942754.git.jani.nikula@intel.com Signed-off-by: Jani Nikula <jani.nikula@intel.com>
2024-09-02drm/i915/audio: migrate away from kdev_to_i915()Jani Nikula
Use to_intel_display() instead of kdev_to_i915() in the audio component API hooks. Avoid further drive-by changes at this point, and just convert the display pointer to i915, and leave the struct intel_display conversion for later. Reviewed-by: Gustavo Sousa <gustavo.sousa@intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/35ef00470db0088eb82b0406e4f7730154f54baf.1724942754.git.jani.nikula@intel.com Signed-off-by: Jani Nikula <jani.nikula@intel.com>
2024-09-02drm/i915: support struct device and pci_dev in to_intel_display()Jani Nikula
Now that both xe and i915 store struct drm_device in drvdata, we can trivially support struct device and struct pci_dev in to_intel_display(). We do need to check for NULL drvdata before converting it into struct intel_device pointer, though. Do it in __drm_device_to_intel_display(). v2: Add NULL check in __drm_device_to_intel_display() (Gustavo) Reviewed-by: Gustavo Sousa <gustavo.sousa@intel.com> # v1 Link: https://patchwork.freedesktop.org/patch/msgid/f025a3fa4422725c78baac4501ad3ecc9e5b40d5.1724942754.git.jani.nikula@intel.com Signed-off-by: Jani Nikula <jani.nikula@intel.com>
generated by cgit (git 2.34.1) at 2025-09-28 22:08:46 +0000