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2016-05-11irqchip/bcm2836: Fix compiler warning on 64-bit buildEric Anholt
Signed-off-by: Eric Anholt <eric@anholt.net> Acked-by: Stephen Warren <swarren@wwwdotorg.org> Signed-off-by: Marc Zyngier <marc.zyngier@arm.com>
2016-05-11irqchip/bcm2836: Drop smp_set_ops on arm64 buildsEric Anholt
For arm64, the bootloader will instead be implementing the spin-table enable method. Signed-off-by: Eric Anholt <eric@anholt.net> Acked-by: Stephen Warren <swarren@wwwdotorg.org> Signed-off-by: Marc Zyngier <marc.zyngier@arm.com>
2016-05-11irqchip/gic: Add helper functions for GIC setup and teardownJon Hunter
Move the code that sets-up a GIC via device-tree into it's own function and add a generic function for GIC teardown that can be used for both device-tree and ACPI to unmap the GIC memory. Signed-off-by: Jon Hunter <jonathanh@nvidia.com> Signed-off-by: Marc Zyngier <marc.zyngier@arm.com>
2016-05-11irqchip/gic: Store GIC configuration parametersJon Hunter
Store the GIC configuration parameters in the GIC chip data structure. This will allow us to simplify the code by reducing the number of parameters passed between functions. Update the __gic_init_bases() function so that we only need to pass a pointer to the GIC chip data structure and no longer need to pass the GIC index in order to look-up the chip data. Signed-off-by: Jon Hunter <jonathanh@nvidia.com> Signed-off-by: Marc Zyngier <marc.zyngier@arm.com>
2016-05-11irqchip/gic: Pass GIC pointer to save/restore functionsJon Hunter
Instead of passing the GIC index to the save/restore functions pass a pointer to the GIC chip data. This will allow these save/restore functions to be re-used by a platform driver where the GIC chip data structure is allocated dynamically and so there is no applicable index for identifying the GIC. Signed-off-by: Jon Hunter <jonathanh@nvidia.com> Acked-by: Marc Zyngier <marc.zyngier@arm.com> Signed-off-by: Marc Zyngier <marc.zyngier@arm.com>
2016-05-11irqchip/gic: Return an error if GIC initialisation failsJon Hunter
If the GIC initialisation fails, then currently we do not return an error or clean-up afterwards. Although for root controllers, this failure may be fatal anyway, for secondary controllers, it may not be fatal and so return an error on failure and clean-up. Update the functions gic_cpu_init() and gic_pm_init() to return an error instead of calling BUG() and perform any necessary clean-up. For non-banked GIC controllers, make sure that we free any memory allocated if we fail to initialise the IRQ domain. Please note that free_percpu() only frees memory if the pointer passed to it is not NULL and so it is unnecessary to check if both pointers are valid or not. Signed-off-by: Jon Hunter <jonathanh@nvidia.com> Signed-off-by: Marc Zyngier <marc.zyngier@arm.com>
2016-05-11irqchip/gic: Remove static irq_chip definition for eoimode1Jon Hunter
There are only 3 differences (not including the name) in the definitions of the gic_chip and gic_eoimode1_chip structures. Instead of statically defining the gic_eoimode1_chip structure, remove it and populate the eoimode1 functions dynamically for the appropriate GIC irqchips. Signed-off-by: Jon Hunter <jonathanh@nvidia.com> Acked-by: Marc Zyngier <marc.zyngier@arm.com> Signed-off-by: Marc Zyngier <marc.zyngier@arm.com>
2016-05-11irqchip/gic: Don't initialise chip if mapping IO space failsJon Hunter
If we fail to map the address space for the GIC distributor or CPU interface, then don't attempt to initialise the chip, just WARN and return. Signed-off-by: Jon Hunter <jonathanh@nvidia.com> Acked-by: Marc Zyngier <marc.zyngier@arm.com> Signed-off-by: Marc Zyngier <marc.zyngier@arm.com>
2016-05-11irqchip/gic: WARN if setting the interrupt type for a PPI failsJon Hunter
Setting the interrupt type for private peripheral interrupts (PPIs) may not be supported by a given GIC because it is IMPLEMENTATION DEFINED whether this is allowed. There is no way to know if setting the type is supported for a given GIC and so the value written is read back to verify it matches the desired configuration. If it does not match then an error is return. There are cases where the interrupt configuration read from firmware (such as a device-tree blob), has been incorrect and hence gic_configure_irq() has returned an error. This error has gone undetected because the error code returned was ignored but the interrupt still worked fine because the configuration for the interrupt could not be overwritten. Given that this has done undetected and that failing to set the configuration for a PPI may not be a catastrophic, don't return an error but WARN if we fail to configure a PPI. This will allows us to fix up any places in the kernel where we should be checking the return status and maintain backward compatibility with firmware images that may have incorrect PPI configurations. Signed-off-by: Jon Hunter <jonathanh@nvidia.com> Acked-by: Marc Zyngier <marc.zyngier@arm.com> Signed-off-by: Marc Zyngier <marc.zyngier@arm.com>
2016-05-11irqchip/gic: Don't unnecessarily write the IRQ configurationJon Hunter
If the interrupt configuration matches the current configuration, then don't bother writing the configuration again. Signed-off-by: Jon Hunter <jonathanh@nvidia.com> Acked-by: Marc Zyngier <marc.zyngier@arm.com> Signed-off-by: Marc Zyngier <marc.zyngier@arm.com>
2016-05-11irqchip: Mask the non-type/sense bits when translating an IRQJon Hunter
The firmware parameter that contains the IRQ sense bits may also contain other data. When return the IRQ type, bits outside of these sense bits should be masked. If these bits are not masked and irq_create_fwspec_mapping() is called to map an IRQ, then the comparison of the type returned from irq_domain_translate() will never match that returned by irq_get_trigger_type() (because this function masks the none sense bits) and so we will always call irq_set_irq_type() to program the type even if it was not really necessary. Currently, the downside to this is unnecessarily re-programmming the type but nevertheless this should be avoided. The Tegra LIC and TI Crossbar irqchips all have client instances (from reviewing the device-tree sources) where bits outside the IRQ sense bits are set, but do not mask these bits. Therefore, ensure these bits are masked for these irqchips. Signed-off-by: Jon Hunter <jonathanh@nvidia.com> Acked-by: Marc Zyngier <marc.zyngier@arm.com> Signed-off-by: Marc Zyngier <marc.zyngier@arm.com>
2016-05-11irqchip/gic-v3: Configure all interrupts as non-secure Group-1Marc Zyngier
The GICv3 driver wrongly assumes that it runs on the non-secure side of a secure-enabled system, while it could be on a system with a single security state, or a GICv3 with GICD_CTLR.DS set. Either way, it is important to configure this properly, or interrupts will simply not be delivered on this HW. Cc: stable@vger.kernel.org Reported-by: Peter Maydell <peter.maydell@linaro.org> Tested-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Marc Zyngier <marc.zyngier@arm.com>
2016-05-11irqchip/gic-v2m: Add workaround for Broadcom NS2 GICv2m erratumRay Jui
Alex Barba <alex.barba@broadcom.com> discovered Broadcom NS2 GICv2m implementation has an erratum where the MSI data needs to be the SPI number subtracted by an offset of 32, for the correct MSI interrupt to be triggered. Here we are adding the workaround based on readings from the MSI_IIDR register, which contains a value unique to Broadcom NS2 GICv2m Reported-by: Alex Barba <alex.barba@broadcom.com> Acked-by: Marc Zyngier <marc.zyngier@arm.com> Signed-off-by: Ray Jui <ray.jui@broadcom.com> Signed-off-by: Marc Zyngier <marc.zyngier@arm.com>
2016-05-11irqchip/irq-alpine-msi: Don't use <asm-generic/msi.h>Christoph Hellwig
Acked-by: Marc Zyngier <marc.zyngier@arm.com> Signed-off-by: Christoph Hellwig <hch@lst.de> Signed-off-by: Marc Zyngier <marc.zyngier@arm.com>
2016-05-11irqchip/mbigen: Checking for IS_ERR() instead of NULLDan Carpenter
of_platform_device_create() returns NULL on error, it never returns error pointers. Fixes: ed2a1002d25c ('irqchip/mbigen: Handle multiple device nodes in a mbigen module') Acked-by: Marc Zyngier <marc.zyngier@arm.com> Signed-off-by: Dan Carpenter <dan.carpenter@oracle.com> Signed-off-by: Marc Zyngier <marc.zyngier@arm.com>
2016-05-11irqchip/gicv3-its: Don't allow devices whose ID is outside rangeShanker Donthineni
We are not checking whether the requested device identifier fits into the device table memory or not. The function its_create_device() assumes that enough memory has been allocated for whole DevID space (reported by ITS_TYPER.Devbits) during the ITS probe() and continues to initialize ITS hardware. This assumption is not perfect, sometimes we reduce memory size either because of its size crossing MAX_ORDER-1 or BASERn max size limit. The MAPD command fails if 'Device ID' is outside of device table range. Add a simple validation check to avoid MAPD failures since we are not handling ITS command errors. This change also helps to return an error -ENOMEM instead of success to caller. Signed-off-by: Shanker Donthineni <shankerd@codeaurora.org> Signed-off-by: Marc Zyngier <marc.zyngier@arm.com>
2016-05-11irqchip: Add LPC32xx interrupt controller driverVladimir Zapolskiy
The change adds improved support of NXP LPC32xx MIC, SIC1 and SIC2 interrupt controllers. This is a list of new features in comparison to the legacy driver: * irq types are taken from device tree settings, no more need to hardcode them, * old driver is based on irq_domain_add_legacy, which causes problems with handling MIC hardware interrupt 0 produced by SIC1, * there is one driver for MIC, SIC1 and SIC2, no more need to handle them separately, e.g. have two separate handlers for SIC1 and SIC2, * the driver does not have any dependencies on hardcoded register offsets, * the driver is much simpler for maintenance, * SPARSE_IRQS option is supported. Legacy LPC32xx interrupt controller driver was broken since commit 76ba59f8366f ("genirq: Add irq_domain-aware core IRQ handler"), which requires a private interrupt handler, otherwise any SIC1 generated interrupt (mapped to MIC hwirq 0) breaks the kernel with the message "unexpected IRQ trap at vector 00". The change disables compilation of a legacy driver found at arch/arm/mach-lpc32xx/irq.c, the file will be removed in a separate commit. Fixes: 76ba59f8366f ("genirq: Add irq_domain-aware core IRQ handler") Tested-by: Sylvain Lemieux <slemieux.tyco@gmail.com> Signed-off-by: Vladimir Zapolskiy <vz@mleia.com> Signed-off-by: Marc Zyngier <marc.zyngier@arm.com>
2016-05-11irqchip/gic: Ensure ordering between read of INTACK and shared dataWill Deacon
When an IPI is generated by a CPU, the pattern looks roughly like: <write shared data> smp_wmb(); <write to GIC to signal SGI> On the receiving CPU we rely on the fact that, once we've taken the interrupt, then the freshly written shared data must be visible to us. Put another way, the CPU isn't going to speculate taking an interrupt. Unfortunately, this assumption turns out to be broken. Consider that CPUx wants to send an IPI to CPUy, which will cause CPUy to read some shared_data. Before CPUx has done anything, a random peripheral raises an IRQ to the GIC and the IRQ line on CPUy is raised. CPUy then takes the IRQ and starts executing the entry code, heading towards gic_handle_irq. Furthermore, let's assume that a bunch of the previous interrupts handled by CPUy were SGIs, so the branch predictor kicks in and speculates that irqnr will be <16 and we're likely to head into handle_IPI. The prefetcher then grabs a speculative copy of shared_data which contains a stale value. Meanwhile, CPUx gets round to updating shared_data and asking the GIC to send an SGI to CPUy. Internally, the GIC decides that the SGI is more important than the peripheral interrupt (which hasn't yet been ACKed) but doesn't need to do anything to CPUy, because the IRQ line is already raised. CPUy then reads the ACK register on the GIC, sees the SGI value which confirms the branch prediction and we end up with a stale shared_data value. This patch fixes the problem by adding an smp_rmb() to the IPI entry code in gic_handle_irq. As it turns out, the combination of a control dependency and an ISB instruction from the EOI in the GICv3 driver is enough to provide the ordering we need, so we add a comment there justifying the absence of an explicit smp_rmb(). Cc: stable@vger.kernel.org Signed-off-by: Will Deacon <will.deacon@arm.com> Signed-off-by: Marc Zyngier <marc.zyngier@arm.com>
2016-05-11pinctrl: amlogic: Add support for Amlogic Meson GXBB SoCCarlo Caione
This patch adds the basic platform file to support the pin controller found on the Amlogic Meson GXBB SoCs. Signed-off-by: Carlo Caione <carlo@endlessm.com> Reviewed-by: Kevin Hilman <khilman@baylibre.com> Tested-by: Kevin Hilman <khilman@baylibre.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2016-05-11pinctrl: rockchip: fix pull setting error for rk3399David Wu
This patch fixes the pinctrl pull bias setting, since the pull up/down setting is the contrary for gpio0(just the gpio0a and gpio0b) and gpio2(just the gpio2c and gpio2d). From the TRM said, the gpio0a pull polarity setting: gpio0a_p GPIO0A PE/PS programmation section, every GPIO bit corresponding to 2bits[PS:PE] 2'b00: Z(Normal operation); 2'b11: weak 1(pull-up); 2'b01: weak 0(pull-down); 2'b10: Z(Normal operation); Then, the other gpios setting as the following: gpio1a_p (e.g.: gpio1, gpio2a, gpio2b, gpio3...) GPIO1A PU/PD programmation section, every GPIO bit corresponding to 2bits 2'b00: Z(Normal operation); 2'b01: weak 1(pull-up); 2'b10: weak 0(pull-down); 2'b11: Z(Normal operation); For example,(rk3399evb board) sdmmc_cd --->gpio0_a7 localhost / # io -r -4 0xff320040 ff320040: 00004d5f In general,the value should be 0x0000cd5f since the pin has been set in the dts. Signed-off-by: David Wu <david.wu@rock-chips.com> Signed-off-by: Caesar Wang <wxt@rock-chips.com> Cc: linux-gpio@vger.kernel.org Reviewed-by: Douglas Anderson <dianders@chromium.org> Reviewed-by: Heiko Stuebner <heiko@sntech.de> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2016-05-11drm/sti: include linux/seq_file.h where neededArnd Bergmann
The sti drm driver has a lot of debugfs interface that cause build errors in some configurations when seq_file.h is not included implicitly: drm/sti/sti_mixer.c: In function 'mixer_dbg_ctl': drm/sti/sti_mixer.c:88:2: error: implicit declaration of function 'seq_puts' [-Werror=implicit-function-declaration] drm/sti/sti_mixer.c:91:4: error: implicit declaration of function 'seq_printf' [-Werror=implicit-function-declaration] drm/sti/sti_gdp.c: In function 'gdp_dbg_ctl': drm/sti/sti_gdp.c:146:2: error: implicit declaration of function 'seq_puts' [-Werror=implicit-function-declaration] drm/sti/sti_gdp.c:149:4: error: implicit declaration of function 'seq_printf' [-Werror=implicit-function-declaration] drm/sti/sti_gdp.c: In function 'gdp_dbg_show': drm/sti/sti_gdp.c:208:32: error: dereferencing pointer to incomplete type 'struct seq_file' This adds an explicit #include statement in all of the affected files. Signed-off-by: Arnd Bergmann <arnd@arndb.de> Acked-by: Benjamin Gaignard <benjamin.gaignard@linaro.org> Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch> Link: http://patchwork.freedesktop.org/patch/msgid/1462830733-1710590-2-git-send-email-arnd@arndb.de
2016-05-11drm/tegra: Use lockless gem BO free callbackDaniel Vetter
No dev->struct_mutex anywhere to be seen. Cc: Thierry Reding <thierry.reding@gmail.com> Cc: Terje Bergström <tbergstrom@nvidia.com> Cc: linux-tegra@vger.kernel.org Signed-off-by: Daniel Vetter <daniel.vetter@intel.com> Acked-by: Thierry Reding <treding@nvidia.com> Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch> Link: http://patchwork.freedesktop.org/patch/msgid/1461691808-12414-28-git-send-email-daniel.vetter@ffwll.ch
2016-05-10eata_pio: missing break statementDan Carpenter
This missing break statement bug predates git. It's a very minor thing, it means that we print a '?' instead of a 'z' in dmesg. Signed-off-by: Dan Carpenter <dan.carpenter@oracle.com> Signed-off-by: Martin K. Petersen <martin.petersen@oracle.com>
2016-05-10hpsa: Fix type ZBC conditional checksPetros Koutoupis
The device ID obtained from the inquiry can only be of a single type. The original code places a check for TYPE_ZBC right after the check for TYPE_DISK. Logically, if the first if statement sees a device of a TYPE_DISK and moves on to the second statement checking if not TYPE_ZBC, it will always hit the continue. [mkp: Applied by hand] Signed-off-by: Petros Koutoupis <petros@petroskoutoupis.com> Acked-by: Don Brace <don.brace@microsemi.com> Signed-off-by: Martin K. Petersen <martin.petersen@oracle.com>
2016-05-10scsi_lib: Decode T10 vendor IDsHannes Reinecke
Some arrays / HBAs will only present T10 vendor IDs, so we should be decoding them, too. [mkp: Fixed T10 spelling] Suggested-by: Paul Mackerras <paulus@ozlabs.org> Signed-off-by: Hannes Reinecke <hare@suse.com> Tested-by: Paul Mackerras <paulus@ozlabs.org> Reviewed-by: Bart Van Assche <bart.vanassche@sandisk.com> Signed-off-by: Martin K. Petersen <martin.petersen@oracle.com>
2016-05-10scsi_dh_alua: do not fail for unknown VPD identificationHannes Reinecke
Not every device will return a useable VPD identification, but still might support ALUA. Rather than disable ALUA support we should be allowing the device identification to be empty and attach individual ALUA device handler to each devices. [mkp: Fixed typo reported by Bart] Reported-by: Paul Mackerras <paulus@ozlabs.org> Signed-off-by: Hannes Reinecke <hare@suse.com> Tested-by: Paul Mackerras <paulus@ozlabs.org> Reviewed-by: Bart Van Assche <bart.vanassche@sandisk.com> Signed-off-by: Martin K. Petersen <martin.petersen@oracle.com>
2016-05-10scsi_debug: use locally assigned naaDouglas Gilbert
For reported SAS addresses replace fake IEEE registered NAAs (5) with locally assigned NAAs (3). Signed-off-by: Douglas Gilbert <dgilbert@interlog.com> Reviewed-by: Hannes Reinecke <hare@suse.com> Reviewed-by: Bart Van Assche <bart.vanassche@sandisk.com> Signed-off-by: Martin K. Petersen <martin.petersen@oracle.com>
2016-05-10scsi_debug: uuid for lu nameDouglas Gilbert
Permit changing of a LU name from a (fake) IEEE registered NAA (5) to a locally assigned UUID. Using a UUID (RFC 4122) for a SCSI designation descriptor (e.g. a LU name) was added in spc5r08.pdf (a draft INCITS standard) on 25 January 2016. Add parameter uuid_ctl to use a separate UUID for each LU (storage device) name. Additional option for all LU names to have the same UUID (since their storage is shared). Previous action of using NAA identifier for LU name remains the default. Signed-off-by: Douglas Gilbert <dgilbert@interlog.com> Reviewed-by: Hannes Reinecke <hare@suse.com> Reviewed-by: Bart Van Assche <bart.vanassche@sandisk.com> Signed-off-by: Martin K. Petersen <martin.petersen@oracle.com>
2016-05-10scsi_debug: vpd and mode page workDouglas Gilbert
Cleanup some mode and vpd pages. Stop reporting SBC (disk) pages when peripheral type is something else (e.g. tape). Update version descriptors. Expand LBPRZ flag handling. Signed-off-by: Douglas Gilbert <dgilbert@interlog.com> Reviewed-by: Hannes Reinecke <hare@suse.com> Reviewed-by: Bart Van Assche <bart.vanassche@sandisk.com> Signed-off-by: Martin K. Petersen <martin.petersen@oracle.com>
2016-05-10scsi_debug: add multiple queue supportDouglas Gilbert
Add submit_queue parameter (minimum and default: 1; maximum: nr_cpu_ids) that controls how many queues are built, each with their own lock and in_use bit vector. Add statistics parameter which is default off. Signed-off-by: Douglas Gilbert <dgilbert@interlog.com> Reviewed-by: Bart Van Assche <bart.vanassche@sandisk.com> Signed-off-by: Martin K. Petersen <martin.petersen@oracle.com>
2016-05-11cpufreq: powernv: del_timer_sync when global and local pstate are equalAkshay Adiga
When global and local pstate are equal in a powernv_target_index() call, we don't queue a timer. But we may have timer already queued for future. This could cause the timer to fire one additional time for no use. Signed-off-by: Akshay Adiga <akshay.adiga@linux.vnet.ibm.com> Acked-by: Viresh Kumar <viresh.kumar@linaro.org> Signed-off-by: Rafael J. Wysocki <rafael.j.wysocki@intel.com>
2016-05-11cpufreq: powernv: Move smp_call_function_any() out of irq safe blockAkshay Adiga
Fix a WARN_ON caused by smp_call_function_any() when irq is disabled, because of changes made in the patch ('cpufreq: powernv: Ramp-down global pstate slower than local-pstate') https://patchwork.ozlabs.org/patch/612058/ WARNING: CPU: 0 PID: 4 at kernel/smp.c:291 smp_call_function_single+0x170/0x180 Call Trace: [c0000007f648f9f0] [c0000007f648fa90] 0xc0000007f648fa90 (unreliable) [c0000007f648fa30] [c0000000001430e0] smp_call_function_any+0x170/0x1c0 [c0000007f648fa90] [c0000000007b4b00] powernv_cpufreq_target_index+0xe0/0x250 [c0000007f648fb00] [c0000000007ac9dc] __cpufreq_driver_target+0x20c/0x3d0 [c0000007f648fbc0] [c0000000007b1b4c] od_dbs_timer+0xcc/0x260 [c0000007f648fc10] [c0000000007b3024] dbs_work_handler+0x54/0xa0 [c0000007f648fc50] [c0000000000c49a8] process_one_work+0x1d8/0x590 [c0000007f648fce0] [c0000000000c4e08] worker_thread+0xa8/0x660 [c0000007f648fd80] [c0000000000cca88] kthread+0x108/0x130 [c0000007f648fe30] [c0000000000095e8] ret_from_kernel_thread+0x5c/0x74 - Calling smp_call_function_any() with interrupt disabled (through spin_lock_irqsave) could cause a deadlock, as smp_call_function_any() relies on the IPI to complete. This is detected in the smp_call_function_any() call and hence the WARN_ON. - As the spinlock (gpstates->lock) is only used to synchronize access of global_pstate_info between timer irq handler and target_index calls. And the timer irq handler just try_locks() hence it would not cause a deadlock. Hence could do without making spinlocks irq safe. - As the smp_call_function_any() is a blocking call and does not access global_pstates_info, it could reduce the critcal section by moving smp_call_function_any() after giving up the lock. Reported-by: Abdul Haleem <abdhalee@linux.vnet.linux.com> Signed-off-by: Akshay Adiga <akshay.adiga@linux.vnet.ibm.com> Acked-by: Viresh Kumar <viresh.kumar@linaro.org> Signed-off-by: Rafael J. Wysocki <rafael.j.wysocki@intel.com>
2016-05-11Thermal / ACPI / video: add INT3406 thermal driverAaron Lu
INT3406 ACPI device object resembles an ACPI video output device, but its _BCM is said to be deprecated and should not be used. So we will make use of the raw interface to do the actual cooling. Signed-off-by: Aaron Lu <aaron.lu@intel.com> Acked-by: Zhang Rui <rui.zhang@intel.com> Signed-off-by: Rafael J. Wysocki <rafael.j.wysocki@intel.com>
2016-05-10mtd: spi-nor: support GigaDevice gd25lq64cBrian Norris
Also note the GigaDevice JEDEC ID. No write-protect support yet, since this flash uses a different status register layout. Cc: Ezequiel Garcia <ezequiel@vanguardiasur.com.ar> Signed-off-by: Brian Norris <computersforpeace@gmail.com> Acked-by: Marek Vasut <marex@denx.de>
2016-05-10net: phylib: fix interrupts re-enablement in phy_startShaohui Xie
If phy was suspended and is starting, current driver always enable phy's interrupts, if phy works in polling, phy can raise unexpected interrupt which will not be handled, the interrupt will block system enter suspend again. So interrupts should only be re-enabled if phy works in interrupt. Signed-off-by: Shaohui Xie <Shaohui.Xie@nxp.com> Reviewed-by: Florian Fainelli <f.fainelli@gmail.com> Signed-off-by: David S. Miller <davem@davemloft.net>
2016-05-10gtp: reload GTPv1 header after pskb_may_pull()Pablo Neira
The GTPv1 header flags indicate the presence of optional extensions after this header. Refresh the pointer to the GTPv1 header as skb->head might have be reallocated via pskb_may_pull(). Fixes: 459aa660eb1d ("gtp: add initial driver for datapath of GPRS Tunneling Protocol (GTP-U)") Reported-by: Eric Dumazet <eric.dumazet@gmail.com> Signed-off-by: Pablo Neira Ayuso <pablo@netfilter.org> Signed-off-by: David S. Miller <davem@davemloft.net>
2016-05-10block/drbd: align properly u64 in nl messagesNicolas Dichtel
The attribute 0 is never used in drbd, so let's use it as pad attribute in netlink messages. This minimizes the patch. Note that this patch is only compile-tested. Signed-off-by: Nicolas Dichtel <nicolas.dichtel@6wind.com> Signed-off-by: Lars Ellenberg <lars.ellenberg@linbit.com> Signed-off-by: David S. Miller <davem@davemloft.net>
2016-05-10iwlwifi: add default value to disable_11ac mod param descriptionEmmanuel Grumbach
Small change to make it clear that the default value is false. Signed-off-by: Emmanuel Grumbach <emmanuel.grumbach@intel.com> Signed-off-by: Luca Coelho <luciano.coelho@intel.com>
2016-05-10iwlwifi: pcie: grab NIC access only once on RX initSara Sharon
When initializing RX we grab NIC access for every read and write. This is redundant - we can just grab access once. Signed-off-by: Sara Sharon <sara.sharon@intel.com> Signed-off-by: Luca Coelho <luciano.coelho@intel.com>
2016-05-10iwlwifi: pcie: use shadow registers for updating write pointerSara Sharon
The RX queues have a shadow register for the write pointer that enables updates without grabbing NIC access. Use them instead of the periphery registers because accessing those is much more expensive. Signed-off-by: Sara Sharon <sara.sharon@intel.com> Signed-off-by: Luca Coelho <luciano.coelho@intel.com>
2016-05-10iwlwifi: mvm: support dqa-mode agg on non-shared queueLiad Kaufman
In non-shared queues, DQA requires re-configuring existing queues to become aggregated rather than allocating a new one. It also requires "un-aggregating" an existing queue when aggregations are turned off. Support this requirement for non-shared queues. Signed-off-by: Liad Kaufman <liad.kaufman@intel.com> Signed-off-by: Luca Coelho <luciano.coelho@intel.com>
2016-05-10iwlwifi: pcie: avoid msleep() with short timeoutJohannes Berg
Since msleep is based on jiffies, it can sleep for a long time. Use usleep_range() instead to shorten the maximum time. Signed-off-by: Johannes Berg <johannes.berg@intel.com> Signed-off-by: Luca Coelho <luciano.coelho@intel.com>
2016-05-10iwlwifi: pcie: extend device reset delayJohannes Berg
Newer hardware generations will take longer to be accessible again after reset, so we need to wait longer before continuing any flow that did a reset. Rather than make the wait time configurable, simply extend it for all. Since all of these code paths can sleep, use usleep_range() rather than mdelay(). Signed-off-by: Johannes Berg <johannes.berg@intel.com> Signed-off-by: Luca Coelho <luciano.coelho@intel.com>
2016-05-10iwlwifi: turn on SGI support for VHT 160MHzGregory Greenman
Devices supporting VHT 160MHz width are supporting also Short GI. Turn on this capability in vht cap. Signed-off-by: Gregory Greenman <gregory.greenman@intel.com> Signed-off-by: Luca Coelho <luciano.coelho@intel.com>
2016-05-10iwlwifi: make configuration structs smallerJohannes Berg
Since we have a lot of configuration structs (almost 70) saving some memory in each one of them leads to an overall saving of ~2.6KiB of memory. Signed-off-by: Johannes Berg <johannes.berg@intel.com> Signed-off-by: Luca Coelho <luciano.coelho@intel.com>
2016-05-10iwlwifi: don't access a nonexistent register upon assertEmmanuel Grumbach
The commit below added code to dump the content of FIFOs that are present only on dual CPU products (8000 and up). This broke 7265D whose firmware does advertise IWL_UCODE_TLV_CAPA_EXTEND_SHARED_MEM_CFG but doesn't have 2 CPUs. The current code does check the length of the FIFO before dumping them (and the nonexistent FIFO has a 0 length), but we still accessed a register to set the FIFO number and that made the DMA unhappy. The impact was a much longer recovery upon firmware assert. Fixes: 5b086414293f ("iwlwifi: mvm: support dumping UMAC internal txfifos") Signed-off-by: Emmanuel Grumbach <emmanuel.grumbach@intel.com> Signed-off-by: Luca Coelho <luciano.coelho@intel.com>
2016-05-10iwlwifi: remove IWLWIFI_DEBUG_EXPERIMENTAL_UCODEEmmanuel Grumbach
This Kconfig option allows to load a firmware for debugging with a different name. This mechanism has not been used for a few years now and replacing the firmware file works as well. Kill this Kconfig option and all the code that goes with it. Signed-off-by: Emmanuel Grumbach <emmanuel.grumbach@intel.com> Signed-off-by: Luca Coelho <luciano.coelho@intel.com>
2016-05-10iwlwifi: mvm: use helpers to get iwl_mvm_staSara Sharon
Getting the mvm station out of station id requires dereferencing the station id to get ieee80211_sta, then checking for pointer validity and only then extract mvm station out. Given that there are helpers to do it - use them instead of duplicating the code whenever we need only mvm station. Signed-off-by: Sara Sharon <sara.sharon@intel.com> Signed-off-by: Luca Coelho <luciano.coelho@intel.com>
2016-05-10iwlwifi: mvm: remove redundant alloc_ctx parameterSara Sharon
iwl_phy_db_set_section() is get called only from atomic context, the alloc_ctx parameter is not needed. Remove it. Signed-off-by: Sara Sharon <sara.sharon@intel.com> Signed-off-by: Luca Coelho <luciano.coelho@intel.com>
2016-05-10iwlwifi: mvm: make phy_db size dynamicSara Sharon
Driver is agnostic to the number of the phy_db entries and only serves the firmware as a pipe to move the data from init image to RT image. As the size of the arrays may change (as it does in 9000 device) allocate it dynamically. Firmware sends the largest index first so we can use this to know how much we should allocate. Signed-off-by: Sara Sharon <sara.sharon@intel.com> Signed-off-by: Luca Coelho <luciano.coelho@intel.com>
generated by cgit (git 2.34.1) at 2025-09-17 04:57:30 +0000