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2015-06-20drm/exynos: ipp: fix wrong index referencing a config elementHyungwon Hwang
Config depends on the opreation. So it must be referenced by an operation id, not a property id. Signed-off-by: Hyungwon Hwang <human.hwang@samsung.com> Signed-off-by: Inki Dae <inki.dae@samsung.com>
2015-06-20drm/exynos: dsi: check whether dsi is enabled before sending dataHyungwon Hwang
exynos_dsi_host_transfer() can be called through a panel driver while DSI is turning down. It is possible because the function checks only whether DSI is initialized or not, and there is a moment which DSI is set by uninitialized, but DSI is still turning down. To prevent it, DSI must be set by disabled before starting to be turned down, and exynos_dsi_host_transfer() must check whether DSI is enabled or not. Kernel dump: [ 4721.351448] Unhandled fault: synchronous external abort (0x96000210) at 0xffffff800015e018 [ 4721.351809] Internal error: : 96000210 [#1] PREEMPT SMP [ 4721.352031] Modules linked in: [ 4721.352173] CPU: 2 PID: 300 Comm: deviced Tainted: G W 4.0.4-01017-g7964a87 #1 [ 4721.353989] Hardware name: Samsung DRACO board (DT) [ 4721.358852] task: ffffffc0a0b70000 ti: ffffffc0a00ec000 task.ti: ffffffc0a00ec000 [ 4721.366327] PC is at exynos_dsi_enable_lane+0x14/0x5c [ 4721.371353] LR is at exynos_dsi_host_transfer+0x834/0x8d8 [ 4721.376731] pc : [<ffffffc000432bcc>] lr : [<ffffffc000434590>] pstate: 60000145 [ 4721.384107] sp : ffffffc0a00efbe0 [ 4721.387405] x29: ffffffc0a00efbe0 x28: ffffffc0a00ec000 [ 4721.392699] x27: ffffffc000968000 x26: 0000000000000040 [ 4721.397994] x25: ffffffc000f74dc0 x24: ffffffc0a00efec8 [ 4721.403290] x23: ffffffc0a4815400 x22: ffffffc0009f2729 [ 4721.408584] x21: ffffffc0a00efcc8 x20: ffffffc0a4a2a848 [ 4721.413879] x19: ffffffc0a4a2a818 x18: 0000000000000004 [ 4721.419173] x17: 0000007faa5cddf0 x16: ffffffc0001a40a8 [ 4721.424469] x15: 0000000000000009 x14: 000000000000000d [ 4721.429762] x13: 6e6e6f63206b726f x12: 0000000000000010 [ 4721.435058] x11: 0101010101010101 x10: 0000000000000000 [ 4721.440353] x9 : 000000000000000a x8 : 8386838282818381 [ 4721.445648] x7 : ffffffc0a201efe8 x6 : 0000000000000000 [ 4721.450943] x5 : 00000000fffffffa x4 : ffffffc0a201f170 [ 4721.456237] x3 : ffffff800015e000 x2 : ffffff800015e018 [ 4721.461531] x1 : 000000000000000f x0 : ffffffc0a4a2a818 [ 4721.466826] [ 4721.468305] Process deviced (pid: 300, stack limit = 0xffffffc0a00ec028) [ 4721.474989] Stack: (0xffffffc0a00efbe0 to 0xffffffc0a00f0000) [ 4721.480720] fbe0: a00efca0 ffffffc0 0042c944 ffffffc0 a0f2d680 ffffffc0 00000024 00000000 [ 4721.488895] fc00: a4b6d000 ffffffc0 009f2729 ffffffc0 a4815400 ffffffc0 a00efec8 ffffffc0 Signed-off-by: Hyungwon Hwang <human.hwang@samsung.com> Signed-off-by: Inki Dae <inki.dae@samsung.com>
2015-06-20drm/exynos: remove SoC checking codeAndrzej Hajda
SoC checking code is not necessary anymore, as exynos_drm_match_add and exynos_drm_platform_probe already properly handles situation when there are no Exynos DRM components. Signed-off-by: Andrzej Hajda <a.hajda@samsung.com> Tested-by: Gustavo Padovan <gustavo.padovan@collabora.co.uk> Signed-off-by: Inki Dae <inki.dae@samsung.com>
2015-06-20drm/exynos: fix broken component binding in case of multiple pipelinesAndrzej Hajda
In case there are multiple pipelines and deferred probe occurs, only components of the first pipeline were bound. As a result only one pipeline was available. The main cause of this issue was dynamic generation of component match table - every component driver during probe registered itself on helper list, if there was at least one pipeline present on this list component match table were created without deferred components. This patch removes this helper list, instead it creates match table from existing devices requiring exynos_drm KMS drivers. This way match table do not depend on probe/deferral order and contains all KMS components. As a side effect patch makes the code cleaner and significantly smaller. Signed-off-by: Andrzej Hajda <a.hajda@samsung.com> Signed-off-by: Inki Dae <inki.dae@samsung.com>
2015-06-20drm/exynos: consolidate driver/device initialization codeAndrzej Hajda
Code registering different drivers and simple platform devices was dispersed across multiple sub-modules. This patch moves it to one place. As a result initialization code is shorter and cleaner and should simplify further development. Signed-off-by: Andrzej Hajda <a.hajda@samsung.com> Signed-off-by: Inki Dae <inki.dae@samsung.com>
2015-06-20drm/exynos: add error messages if clks failed to get enabledGustavo Padovan
Check error and call DRM_ERROR if clk_prepare_enable() fails. Signed-off-by: Gustavo Padovan <gustavo.padovan@collabora.co.uk> Signed-off-by: Inki Dae <inki.dae@samsung.com>
2015-06-20drm/exynos: add a dependency on FB_S3C to DECON driverInki Dae
This patch makes one of Linux framebuffer and DRM CRTC drivers to be enabled. Display controllers, FIMD and DECON, can be controlled by Linux framebuffer or DRM CRTC drivers so only one of them should be enabled. Signed-off-by: Inki Dae <inki.dae@samsung.com> Reviewed-by: Gustavo Padovan <gustavo.padovan@collabora.co.uk>
2015-06-20drm/exynos: vidi: remove unused varablesInki Dae
This patch removes unnsed varables in vidi_disable function. Signed-off-by: Inki Dae <inki.dae@samsung.com> Reviewed-by: Gustavo Padovan <gustavo.padovan@collabora.co.uk>
2015-06-20drm/exynos: split exynos_crtc->dpms in enable() and disable()Gustavo Padovan
To follow more closely the new atomic API we split the dpms() helper into the enable() and disable() helper to get exactly the same semantics. Signed-off-by: Gustavo Padovan <gustavo.padovan@collabora.co.uk> Signed-off-by: Inki Dae <inki.dae@samsung.com>
2015-06-20drm/exynos: remove unnecessary calls to disable_plane()Gustavo Padovan
The planes are already disabled by the drm_atomic_helper_commit() code so we don't need to disable the in these two places. Signed-off-by: Gustavo Padovan <gustavo.padovan@collabora.co.uk> Reviewed-by: Joonyoung Shim <jy0922.shim@samsung.com> Tested-by: Tobias Jakobi <tjakobi@math.uni-bielefeld.de> Signed-off-by: Inki Dae <inki.dae@samsung.com>
2015-06-20drm/exynos: atomic dpms supportGustavo Padovan
Run dpms operations through the atomic intefaces. This basically removes the .dpms() callback from econders and crtcs and use .disable() and .enable() to turn the crtc on and off. v2: Address comments by Joonyoung: - make hdmi code call ->disable() instead of ->dpms() - do not use WARN_ON on crtc enable/disable v3: - Fix build failure after the hdmi change in v2 - Change dpms helper of ptn3460 bridge v4: - remove win_commit() call from .enable() v5: - move .atomic_check() to the atomic PageFlip patch, and transform it in .atomic_begin() Signed-off-by: Gustavo Padovan <gustavo.padovan@collabora.co.uk> Reviewed-by: Joonyoung Shim <jy0922.shim@samsung.com> Tested-by: Tobias Jakobi <tjakobi@math.uni-bielefeld.de> Signed-off-by: Inki Dae <inki.dae@samsung.com>
2015-06-20drm/exynos: add exynos specific .atomic_commit()Gustavo Padovan
exynos needs to update planes with the crtc enabled (mainly for the FIMD case) so this specific atomic commit changes the order of drm_atomic_helper_commit_modeset_enables() and drm_atomic_helper_commit_planes() to commit planes after we enable crtc and encoders. Signed-off-by: Gustavo Padovan <gustavo.padovan@collabora.co.uk> Signed-off-by: Inki Dae <inki.dae@samsung.com>
2015-06-20drm/exynos: move exynos_drm_crtc_disable()Gustavo Padovan
This is a preparation commit to move exynos_drm_crtc_disable() together with the future exynos_drm_crtc_enable() that will come from the split of exynos_drm_crtc_dpms() callback. Signed-off-by: Gustavo Padovan <gustavo.padovan@collabora.co.uk> Signed-off-by: Inki Dae <inki.dae@samsung.com>
2015-06-20drm/exynos: don't disable unused functions at initGustavo Padovan
Everything starts disabled so we don't really need to disable anything. Signed-off-by: Gustavo Padovan <gustavo.padovan@collabora.co.uk> Reviewed-by: Joonyoung Shim <jy0922.shim@samsung.com> Tested-by: Tobias Jakobi <tjakobi@math.uni-bielefeld.de> Signed-off-by: Inki Dae <inki.dae@samsung.com>
2015-06-20drm/exynos: remove exported functions from exynos_drm_planeGustavo Padovan
Now that no one is using the functions exported by exynos_drm_plane due to the atomic conversion we can make remove some of the them or make them static. v2: remove unused exynos_drm_crtc v3: fix checkpatch error (reported by Joonyoung) Signed-off-by: Gustavo Padovan <gustavo.padovan@collabora.co.uk> Reviewed-by: Joonyoung Shim <jy0922.shim@samsung.com> Tested-by: Tobias Jakobi <tjakobi@math.uni-bielefeld.de> Signed-off-by: Inki Dae <inki.dae@samsung.com>
2015-06-20drm/exynos: atomic phase 3: convert page flipsGustavo Padovan
PageFlips now use the atomic helper to work through the atomic modesetting API. Async page flips are not supported yet. v2: Add .atomic_begin() step to handle the vblank part we removed from exynos page_flip code. Signed-off-by: Gustavo Padovan <gustavo.padovan@collabora.co.uk> Reviewed-by: Joonyoung Shim <jy0922.shim@samsung.com> Tested-by: Tobias Jakobi <tjakobi@math.uni-bielefeld.de> Signed-off-by: Inki Dae <inki.dae@samsung.com>
2015-06-20drm/exynos: atomic phase 3: use atomic .set_config helperGustavo Padovan
Now that phase 1 and 2 are complete switch .set_config helper to use the atomic one. v2: also remove .prepare() callback v3: remove .mode_set() and .mode_set_base() and encoder's .prepare() callbacks Signed-off-by: Gustavo Padovan <gustavo.padovan@collabora.co.uk> Reviewed-by: Joonyoung Shim <jy0922.shim@samsung.com> Tested-by: Tobias Jakobi <tjakobi@math.uni-bielefeld.de> Signed-off-by: Inki Dae <inki.dae@samsung.com>
2015-06-20drm/exynos: atomic phase 3: atomic updates of planesGustavo Padovan
Now that phase 1 and 2 are complete we can switch the update/disable_plane callbacks to their atomic version. Signed-off-by: Gustavo Padovan <gustavo.padovan@collabora.co.uk> Reviewed-by: Joonyoung Shim <jy0922.shim@samsung.com> Tested-by: Tobias Jakobi <tjakobi@math.uni-bielefeld.de> Signed-off-by: Inki Dae <inki.dae@samsung.com>
2015-06-20drm/exynos: atomic phase 2: keep track of framebuffer pointerGustavo Padovan
Use drm_atomic_set_fb_for_plane() in the legacy page_flip path to keep track of the framebuffer pointer and reference. Signed-off-by: Gustavo Padovan <gustavo.padovan@collabora.co.uk> Reviewed-by: Joonyoung Shim <jy0922.shim@samsung.com> Tested-by: Tobias Jakobi <tjakobi@math.uni-bielefeld.de> Signed-off-by: Inki Dae <inki.dae@samsung.com>
2015-06-20drm/exynos: atomic phase 2: wire up state reset(), duplicate() and destroy()Gustavo Padovan
Set CRTC, planes and connectors to use the default implementations from the atomic helper library. The helpers will work to keep track of state for each DRM object. Signed-off-by: Gustavo Padovan <gustavo.padovan@collabora.co.uk> Reviewed-by: Joonyoung Shim <jy0922.shim@samsung.com> Tested-by: Tobias Jakobi <tjakobi@math.uni-bielefeld.de> Signed-off-by: Inki Dae <inki.dae@samsung.com>
2015-06-20drm/exynos: use adjusted_mode of crtc_state instead of modeJoonyoung Shim
Handle changes by removing copy from adjusted_mode to mode as using adjusted_mode of crtc_state. Signed-off-by: Joonyoung Shim <jy0922.shim@samsung.com> Signed-off-by: Inki Dae <inki.dae@samsung.com>
2015-06-20drm/exynos: atomic phase 1: add .mode_set_nofb() callbackGustavo Padovan
The new atomic infrastructure needs the .mode_set_nofb() callback to update CRTC timings before setting any plane. v2: remove WARN_ON(!crtc->state) from mode_set_nofb Signed-off-by: Gustavo Padovan <gustavo.padovan@collabora.co.uk> Reviewed-by: Joonyoung Shim <jy0922.shim@samsung.com> Tested-by: Tobias Jakobi <tjakobi@math.uni-bielefeld.de> Signed-off-by: Inki Dae <inki.dae@samsung.com>
2015-06-20drm/exynos: atomic phase 1: use drm_plane_helper_disable()Gustavo Padovan
The atomic helper to disable planes also uses the optional .atomic_disable() helper. The unique operation it does is calling .win_disable() Signed-off-by: Gustavo Padovan <gustavo.padovan@collabora.co.uk> Reviewed-by: Joonyoung Shim <jy0922.shim@samsung.com> Tested-by: Tobias Jakobi <tjakobi@math.uni-bielefeld.de> Signed-off-by: Inki Dae <inki.dae@samsung.com>
2015-06-20drm/exynos: atomic phase 1: use drm_plane_helper_update()Gustavo Padovan
Rip out the check from exynos_update_plane() and create exynos_check_plane() for the check phase enabling use to use the atomic helpers to call our check and update phases when updating planes. Update all users of exynos_update_plane() accordingly to call exynos_check_plane() before. Signed-off-by: Gustavo Padovan <gustavo.padovan@collabora.co.uk> Reviewed-by: Joonyoung Shim <jy0922.shim@samsung.com> Tested-by: Tobias Jakobi <tjakobi@math.uni-bielefeld.de>y Signed-off-by: Inki Dae <inki.dae@samsung.com>
2015-06-20drm/exynos: fix source data argument for planeJoonyoung Shim
The exynos_update_plane function needs 16.16 fixed point source data. Signed-off-by: Joonyoung Shim <jy0922.shim@samsung.com> Reviewed-by: Gustavo Padovan <gustavo.padovan@collabora.co.uk> Signed-off-by: Inki Dae <inki.dae@samsung.com>
2015-06-19regulator: qcom_spmi: Fix calculating number of voltagesAxel Lin
n /= range->step_uV + 1; is equivalent to n /= (range->step_uV + 1); which is wrong. Fix it. Signed-off-by: Axel Lin <axel.lin@ingics.com> Acked-by: Stephen Boyd <sboyd@codeaurora.org> Signed-off-by: Mark Brown <broonie@kernel.org>
2015-06-19drm: Avoid the double clflush on the last cache line in drm_clflush_virt_range()Chris Wilson
As the clflush operates on cache lines, and we can flush any byte address, in order to flush all bytes given in the range we issue an extra clflush on the last byte to ensure the last cacheline is flushed. We can can the iteration to be over the actual cache lines to avoid this double clflush on the last byte. Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk> Cc: Imre Deak <imre.deak@intel.com> Reviewed-by: Imre Deak <imre.deak@intel.com> Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
2015-06-19drm/atomic: Extract needs_modeset functionDaniel Vetter
We use the same check already in the atomic core, so might as well make this official. And it's also reused in e.g. i915. Motivated by Maarten's idea to extract a connector_changed state out of mode_changed. Cc: Maarten Lankhorst <maarten.lankhorst@linux.intel.com> Reviewed-By: Maarten Lankhorst <maarten.lankhorst@linux.intel.com> Signed-off-by: Daniel Vetter <daniel.vetter@intel.com>
2015-06-19Merge branches 'arm/rockchip', 'arm/exynos', 'arm/smmu', 'x86/vt-d', ↵Joerg Roedel
'x86/amd', 'default-domains' and 'core' into next
2015-06-19iommu/amd: Handle large pages correctly in free_pagetableJoerg Roedel
Make sure that we are skipping over large PTEs while walking the page-table tree. Cc: stable@kernel.org Fixes: 5c34c403b723 ("iommu/amd: Fix memory leak in free_pagetable") Signed-off-by: Joerg Roedel <jroedel@suse.de>
2015-06-19Merge branch 'ccf/atmel-fixes-for-4.1' of ↵Michael Turquette
https://github.com/bbrezillon/linux-at91 into clk-fixes
2015-06-19crypto: marvell/cesa - add support for Kirkwood and Dove SoCsArnaud Ebalard
Add the Kirkwood and Dove SoC descriptions, and control the allhwsupport module parameter to avoid probing the CESA IP when the old CESA driver is enabled (unless it is explicitly requested to do so). Signed-off-by: Arnaud Ebalard <arno@natisbad.org> Signed-off-by: Boris Brezillon <boris.brezillon@free-electrons.com> Signed-off-by: Herbert Xu <herbert@gondor.apana.org.au>
2015-06-19crypto: marvell/cesa - add support for Orion SoCsBoris BREZILLON
Add the Orion SoC description, and select this implementation by default to support non-DT probing: Orion is the only platform where non-DT boards are declaring the CESA block. Control the allhwsupport module parameter to avoid probing the CESA IP when the old CESA driver is enabled (unless it is explicitly requested to do so). Signed-off-by: Boris Brezillon <boris.brezillon@free-electrons.com> Signed-off-by: Herbert Xu <herbert@gondor.apana.org.au>
2015-06-19crypto: marvell/cesa - add allhwsupport module parameterBoris BREZILLON
The old and new marvell CESA drivers both support Orion and Kirkwood SoCs. Add a module parameter to choose whether these SoCs should be attached to the new or the old driver. The default policy is to keep attaching those IPs to the old driver if it is enabled, until we decide the new CESA driver is stable/secure enough. Signed-off-by: Boris Brezillon <boris.brezillon@free-electrons.com> Signed-off-by: Herbert Xu <herbert@gondor.apana.org.au>
2015-06-19crypto: marvell/cesa - add support for all armada SoCsBoris BREZILLON
Add CESA IP description for all the missing armada SoCs (XP, 375 and 38x). Signed-off-by: Boris Brezillon <boris.brezillon@free-electrons.com> Signed-off-by: Herbert Xu <herbert@gondor.apana.org.au>
2015-06-19crypto: marvell/cesa - add SHA256 supportArnaud Ebalard
Add support for SHA256 operations. Signed-off-by: Arnaud Ebalard <arno@natisbad.org> Signed-off-by: Boris Brezillon <boris.brezillon@free-electrons.com> Signed-off-by: Herbert Xu <herbert@gondor.apana.org.au>
2015-06-19crypto: marvell/cesa - add MD5 supportArnaud Ebalard
Add support for MD5 operations. Signed-off-by: Arnaud Ebalard <arno@natisbad.org> Signed-off-by: Boris Brezillon <boris.brezillon@free-electrons.com> Signed-off-by: Herbert Xu <herbert@gondor.apana.org.au>
2015-06-19crypto: marvell/cesa - add Triple-DES supportArnaud Ebalard
Add support for Triple-DES operations. Signed-off-by: Arnaud Ebalard <arno@natisbad.org> Signed-off-by: Boris Brezillon <boris.brezillon@free-electrons.com> Signed-off-by: Herbert Xu <herbert@gondor.apana.org.au>
2015-06-19crypto: marvell/cesa - add DES supportBoris BREZILLON
Add support for DES operations. Signed-off-by: Boris Brezillon <boris.brezillon@free-electrons.com> Signed-off-by: Arnaud Ebalard <arno@natisbad.org> Signed-off-by: Herbert Xu <herbert@gondor.apana.org.au>
2015-06-19crypto: marvell/cesa - add TDMA supportBoris BREZILLON
The CESA IP supports CPU offload through a dedicated DMA engine (TDMA) which can control the crypto block. When you use this mode, all the required data (operation metadata and payload data) are transferred using DMA, and the results are retrieved through DMA when possible (hash results are not retrieved through DMA yet), thus reducing the involvement of the CPU and providing better performances in most cases (for small requests, the cost of DMA preparation might exceed the performance gain). Note that some CESA IPs do not embed this dedicated DMA, hence the activation of this feature on a per platform basis. Signed-off-by: Boris Brezillon <boris.brezillon@free-electrons.com> Signed-off-by: Arnaud Ebalard <arno@natisbad.org> Signed-off-by: Herbert Xu <herbert@gondor.apana.org.au>
2015-06-19crypto: marvell/cesa - add a new driver for Marvell's CESABoris BREZILLON
The existing mv_cesa driver supports some features of the CESA IP but is quite limited, and reworking it to support new features (like involving the TDMA engine to offload the CPU) is almost impossible. This driver has been rewritten from scratch to take those new features into account. This commit introduce the base infrastructure allowing us to add support for DMA optimization. It also includes support for one hash (SHA1) and one cipher (AES) algorithm, and enable those features on the Armada 370 SoC. Other algorithms and platforms will be added later on. Signed-off-by: Boris Brezillon <boris.brezillon@free-electrons.com> Signed-off-by: Arnaud Ebalard <arno@natisbad.org> Signed-off-by: Herbert Xu <herbert@gondor.apana.org.au>
2015-06-19crypto: mv_cesa - explicitly define kirkwood and dove compatible stringsBoris BREZILLON
We are about to add a new driver to support new features like using the TDMA engine to offload the CPU. Orion, Dove and Kirkwood platforms are already using the mv_cesa driver, but Orion SoCs do not embed the TDMA engine, which means we will have to differentiate them if we want to get TDMA support on Dove and Kirkwood. In the other hand, the migration from the old driver to the new one is not something all people are willing to do without first auditing the new driver. Hence we have to support the new compatible in the mv_cesa driver so that new platforms with updated DTs can still attach their crypto engine device to this driver. Signed-off-by: Boris Brezillon <boris.brezillon@free-electrons.com> Signed-off-by: Herbert Xu <herbert@gondor.apana.org.au>
2015-06-19crypto: mv_cesa - use gen_pool to reserve the SRAM memory regionBoris BREZILLON
The mv_cesa driver currently expects the SRAM memory region to be passed as a platform device resource. This approach implies two drawbacks: - the DT representation is wrong - the only one that can access the SRAM is the crypto engine The last point is particularly annoying in some cases: for example on armada 370, a small region of the crypto SRAM is used to implement the cpuidle, which means you would not be able to enable both cpuidle and the CESA driver. To address that problem, we explicitly define the SRAM device in the DT and then reference the sram node from the crypto engine node. Also note that the old way of retrieving the SRAM memory region is still supported, or in other words, backward compatibility is preserved. Signed-off-by: Boris Brezillon <boris.brezillon@free-electrons.com> Signed-off-by: Herbert Xu <herbert@gondor.apana.org.au>
2015-06-19Merge branch 'mvebu/drivers' of ↵Herbert Xu
git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc Merge the mvebu/drivers branch of the arm-soc tree which contains just a single patch bfa1ce5f38938cc9e6c7f2d1011f88eba2b9e2b2 ("bus: mvebu-mbus: add mv_mbus_dram_info_nooverlap()") that happens to be a prerequisite of the new marvell/cesa crypto driver.
2015-06-19clk: at91: fix h32mx prototype inclusion in pmc headerNicolas Ferre
Trivial fix that prevents to compile this pmc clock driver if h32mx clock is present but smd clock isn't. Signed-off-by: Nicolas Ferre <nicolas.ferre@atmel.com> Signed-off-by: Boris Brezillon <boris.brezillon@free-electrons.com> Acked-by: Alexandre Belloni <alexandre.belloni@free-electrons.com> Fixes: bcc5fd49a0fd ("clk: at91: add a driver for the h32mx clock") Cc: <stable@vger.kernel.org> # 3.18+
2015-06-19clk: at91: fix PERIPHERAL_MAX_SHIFT definitionBoris Brezillon
Fix the PERIPHERAL_MAX_SHIFT definition (3 instead of 4) and adapt the round_rate and set_rate logic accordingly. Signed-off-by: Boris Brezillon <boris.brezillon@free-electrons.com> Reported-by: "Wu, Songjun" <Songjun.Wu@atmel.com>
2015-06-19clk: at91: pll: fix input range validity checkBoris Brezillon
The PLL impose a certain input range to work correctly, but it appears that this input range does not apply on the input clock (or parent clock) but on the input clock after it has passed the PLL divisor. Fix the implementation accordingly. Cc: <stable@vger.kernel.org> # v3.14+ Signed-off-by: Boris Brezillon <boris.brezillon@free-electrons.com> Reported-by: Jonas Andersson <jonas@microbit.se>
2015-06-19power_supply: Correct kerneldoc copy paste errorsBjorn Andersson
Signed-off-by: Bjorn Andersson <bjorn.andersson@sonymobile.com> Reviewed-by: Krzysztof Kozlowski <k.kozlowski@samsung.com> Signed-off-by: Sebastian Reichel <sre@kernel.org>
2015-06-19cxl: Fix typo in debug printMichael Neuling
Fix typo in debug print. p1_base() should be p2_base(). No change other than to the debug output. Signed-off-by: Michael Neuling <mikey@neuling.org> Acked-by: Ian Munsie <imunsie@au1.ibm.com> Signed-off-by: Michael Ellerman <mpe@ellerman.id.au>
2015-06-19cxl: Add CXL_KERNEL_API config optionMichael Neuling
Add CXL_KERNEL_API config option so drivers which depend on this new functionality won't be enabled until this is visible. This is useful for merging the cxlflash driver which comes in via the SCSI tree. The cxlflash driver can depend on CXL_KERNEL_API, hence it won't be enabled in the SCSI tree until this new config option is merged via the powerpc tree. Hence all trees will be bisectable at all times. Signed-off-by: Michael Neuling <mikey@neuling.org> Signed-off-by: Michael Ellerman <mpe@ellerman.id.au>
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