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2018-05-24i2c: mux: demux-pinctrl: use proper parent device for demux adapterWolfram Sang
Due to a typo, the wrong parent device was assigned to the newly created demuxing adapter device. It got connected to the demuxing platform device but not to the selected parent I2C adapter device. Fix it to get a proper parent-child relationship of the demuxed busses. Signed-off-by: Wolfram Sang <wsa+renesas@sang-engineering.com> Reviewed-by: Simon Horman <horms+renesas@verge.net.au> Signed-off-by: Peter Rosin <peda@axentia.se>
2018-05-24gpio: mxs: Switch to SPDX identifierFabio Estevam
Adopt the SPDX license identifier headers to ease license compliance management. Signed-off-by: Fabio Estevam <fabio.estevam@nxp.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2018-05-24i2c: mux: improve error message for failed symlinkWolfram Sang
Trivial, but still: the failed symlink is not *for* the channel but a link *to* the channel. Signed-off-by: Wolfram Sang <wsa+renesas@sang-engineering.com> Signed-off-by: Peter Rosin <peda@axentia.se>
2018-05-24pinctrl/stm32: Add irq_eoi for stm32gpio irqchipLudovic Barre
-Parent domain of stm32gpio evolves to hierarchy domain and could have a handle_fasteoi_irq. So an irq_eoi parent callback is needed for children. -Replace space by tabulation. Signed-off-by: Ludovic Barre <ludovic.barre@st.com> Signed-off-by: Marc Zyngier <marc.zyngier@arm.com>
2018-05-24irqchip/stm32: Add suspend/resume support for hierarchy domainLudovic Barre
This patch adds suspend/resume feature for exti hierarchy domain. -suspend function sets wake_active into imr of each banks -resume function restores the mask_cache interrupt into imr of each banks Signed-off-by: Ludovic Barre <ludovic.barre@st.com> Signed-off-by: Marc Zyngier <marc.zyngier@arm.com>
2018-05-24irqchip/stm32: Add stm32mp1 support with hierarchy domainLudovic Barre
Exti controller has been differently integrated on stm32mp1 SoC. A parent irq has only one external interrupt. A hierachy domain could be used. Handlers are call by parent, each parent interrupt could be masked and unmasked according to the needs. Signed-off-by: Ludovic Barre <ludovic.barre@st.com> Signed-off-by: Marc Zyngier <marc.zyngier@arm.com>
2018-05-24irqchip/stm32: Prepare common functionsLudovic Barre
This patch prepares functions which could be reused by next variant of stm32 exti controller. Signed-off-by: Ludovic Barre <ludovic.barre@st.com> Signed-off-by: Marc Zyngier <marc.zyngier@arm.com>
2018-05-24irqchip/stm32: Add host and driver data structuresLudovic Barre
This patch adds host and driver data structures to support different stm32 exti controllers with variants. Signed-off-by: Ludovic Barre <ludovic.barre@st.com> Signed-off-by: Marc Zyngier <marc.zyngier@arm.com>
2018-05-24irqchip/stm32: Add suspend supportLudovic Barre
This patch adds suspend feature. -Use default irq_set_wake function to store wakeup request. -Suspend function set wake_active into imr of each bank and save rising/falling trigger registers. -Resume function restore the mask_cache interrupt into imr of each bank and restore rising/falling trigger registers. Signed-off-by: Ludovic Barre <ludovic.barre@st.com> Signed-off-by: Marc Zyngier <marc.zyngier@arm.com>
2018-05-24irqchip/stm32: Add falling pending register supportLudovic Barre
This patch adds support of rising/falling pending registers. Falling pending register (fpr) is needed for next revision. Signed-off-by: Ludovic Barre <ludovic.barre@st.com> Signed-off-by: Marc Zyngier <marc.zyngier@arm.com>
2018-05-24irqchip/stm32: Checkpatch fixLudovic Barre
-WARNING: struct irq_domain_ops should normally be const -CHECK: Alignment should match open parenthesis Signed-off-by: Ludovic Barre <ludovic.barre@st.com> Signed-off-by: Marc Zyngier <marc.zyngier@arm.com>
2018-05-24irqchip/stm32: Optimizes and cleans up stm32-exti irq_domainRadoslaw Pietrzyk
- In stm32_exti_alloc function, discards irq_domain_set_info with handle_simple_irq. This overwrite the setting defined while init of generic chips. Exti controller manages edge irq type. - Removes acking in chained irq handler as this is done by irq_chip itself inside handle_edge_irq - removes unneeded irq_domain_ops.xlate callback Acked-by: Ludovic Barre <ludovic.barre@st.com> Tested-by: Ludovic Barre <ludovic.barre@st.com> Signed-off-by: Radoslaw Pietrzyk <radoslaw.pietrzyk@gmail.com> Signed-off-by: Ludovic Barre <ludovic.barre@st.com> Signed-off-by: Marc Zyngier <marc.zyngier@arm.com>
2018-05-24irqchip/meson-gpio: Add support for Meson-AXG SoCsYixun Lan
The Meson-AXG SoC uses the same GPIO interrupt controller IP block as the other Meson SoCs. A total of 100 pins can be spied on, which is the sum of: - 255:100 Undefined(no interrupt) - 99:84, 16 pins on bank GPIOY - 83:61, 23 pins on bank GPIOX - 60:40, 21 pins on bank GPIOA - 39:25, 15 pins on bank BOOT - 24:14, 11 pins on bank GPIOZ - 13:0 , 14 pins in the AO domain Signed-off-by: Yixun Lan <yixun.lan@amlogic.com> Signed-off-by: Marc Zyngier <marc.zyngier@arm.com>
2018-05-24i2c: mux: reg: failed memory allocation is logged elsewhereMarkus Elfring
Omit an extra message for a memory allocation failure in this function. This issue was detected by using the Coccinelle software. Signed-off-by: Markus Elfring <elfring@users.sourceforge.net> Reviewed-by: Alexander Sverdlin <alexander.sverdlin@nokia.com> Signed-off-by: Peter Rosin <peda@axentia.se>
2018-05-24drm/exynos: Fix default value for zpos plane propertyMarek Szyprowski
The default zpos property for all planes in Exynos DRM was fixed as zero. Fix this by providing proper value provided by hardware drivers, which typically matches hardware window number. Reported-by: Seung-Woo Kim <sw0312.kim@samsung.com> Fixes: e47726a11e11 ("drm/exynos: use generic code for managing zpos plane property") Signed-off-by: Marek Szyprowski <m.szyprowski@samsung.com> Signed-off-by: Inki Dae <inki.dae@samsung.com>
2018-05-24ACPI / watchdog: Prefer iTCO_wdt always when WDAT table uses RTC SRAMMika Westerberg
After we added quirk for Lenovo Z50-70 it turns out there are at least two more systems where WDAT table includes instructions accessing RTC SRAM. Instead of quirking each system separately, look for such instructions in the table and automatically prefer iTCO_wdt if found. Link: https://bugzilla.kernel.org/show_bug.cgi?id=199033 Reported-by: Arnold Guy <aurnoldg@gmail.com> Reported-by: Alois Nespor <nespor@fssp.cz> Reported-by: Yury Pakin <zxwarior@gmail.com> Reported-by: Ihor Chyhin <ihorchyhin@ukr.net> Signed-off-by: Mika Westerberg <mika.westerberg@linux.intel.com> Acked-by: Guenter Roeck <linux@roeck-us.net> Signed-off-by: Rafael J. Wysocki <rafael.j.wysocki@intel.com>
2018-05-24pinctrl: at91-pio4: add missing of_node_putJulia Lawall
The device node iterators perform an of_node_get on each iteration, so a jump out of the loop requires an of_node_put. The semantic patch that fixes this problem is as follows (http://coccinelle.lip6.fr): // <smpl> @@ expression root,e; local idexpression child; iterator name for_each_child_of_node; @@ for_each_child_of_node(root, child) { ... when != of_node_put(child) when != e = child + of_node_put(child); ? break; ... } ... when != child // </smpl> Signed-off-by: Julia Lawall <Julia.Lawall@lip6.fr> Acked-by: Ludovic Desroches <ludovic.desroches@microchip.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2018-05-24gpio: Remove VLA from stmpe driverLaura Abbott
The new challenge is to remove VLAs from the kernel (see https://lkml.org/lkml/2018/3/7/621) The number of GPIOs on the supported chips is fairly small so stack allocate to a known upper bound and spit out a warning if any new chips have more gpios. Signed-off-by: Laura Abbott <labbott@redhat.com> Reviewed-by: Phil Reid <preid@electromag.com.au> Reviewed-by: Kees Cook <keescook@chromium.org> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2018-05-24PM: wakeup: Use pr_debug() for the "aborting suspend" messageRafael J. Wysocki
The message printed by pm_wakeup_pending() on wakeup detection is not very useful if someone is not interested specifically in debugging wakeup, so turn it into a pm_debug() one. Signed-off-by: Rafael J. Wysocki <rafael.j.wysocki@intel.com>
2018-05-24pinctrl: armada-37xx: Fix spurious irq managementTerry Zhou
Until now, if we found spurious irq in irq_handler, we only updated the status in register but not the status in the code. Due to this the system will got stuck dues to the infinite loop [gregory.clement@bootlin.com: update comment and add fix and stable tags] Fixes: 30ac0d3b0702 ("pinctrl: armada-37xx: Add edge both type gpio irq support") Cc: <stable@vger.kernel.org> Signed-off-by: Terry Zhou <bjzhou@marvell.com> Reviewed-by: Gregory CLEMENT <gregory.clement@bootlin.com> Signed-off-by: Gregory CLEMENT <gregory.clement@bootlin.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2018-05-24PCI / PM: Clean up outdated comments in pci_target_state()Rafael J. Wysocki
Two comments in pci_target_state() are outdated, as the function doesn't set the target power state for the device any more, only finds one for it, so fix them accordingly. Reported-by: Bjorn Helgaas <bhelgaas@google.com> Signed-off-by: Rafael J. Wysocki <rafael.j.wysocki@intel.com> Acked-by: Bjorn Helgaas <bhelgaas@google.com>
2018-05-24PCI / PM: Do not clear state_saved for devices that remain suspendedRafael J. Wysocki
The state_saved flag should not be cleared in pci_pm_suspend() if the given device is going to remain suspended, or the device's config space will not be restored properly during the subsequent resume. Namely, if the device is going to stay in suspend, both the late and noirq callbacks return early for it, so if its state_saved flag is cleared in pci_pm_suspend(), it will remain unset throughout the remaining part of suspend and resume and pci_restore_state() called for the device going forward will return without doing anything. For this reason, change pci_pm_suspend() to only clear state_saved if the given device is not going to remain suspended. [This is analogous to what commit ae860a19f37c (PCI / PM: Do not clear state_saved in pci_pm_freeze() when smart suspend is set) did for hibernation.] Fixes: c4b65157aeef (PCI / PM: Take SMART_SUSPEND driver flag into account) Cc: 4.15+ <stable@vger.kernel.org> # 4.15+ Signed-off-by: Rafael J. Wysocki <rafael.j.wysocki@intel.com> Reviewed-by: Mika Westerberg <mika.westerberg@linux.intel.com> Acked-by: Bjorn Helgaas <bhelgaas@google.com>
2018-05-24gpio: mxc: Switch to SPDX identifierFabio Estevam
Adopt the SPDX license identifier headers to ease license compliance management. Signed-off-by: Fabio Estevam <fabio.estevam@nxp.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2018-05-24gpio: mxc: add clock operationAnson Huang
Some i.MX SoCs have GPIO clock gates in CCM CCGR, such as i.MX6SLL, need to enable clocks before accessing GPIO registers, add optional clock operation for GPIO driver. Signed-off-by: Anson Huang <Anson.Huang@nxp.com> Reviewed-by: Fabio Estevam <fabio.estevam@nxp.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2018-05-24gpiolib: discourage gpiochip_add_pin[group]_range for DT pinctrlsChristian Lamparter
This patch adds the stern warning to the kerneldoc text of both gpiochip_add_pin[group]_range() functions in hope of detering developers from ever using them in their DeviceTree-supported pinctrl drivers in the future. For anyone affected: Please refer to Section 2.1 of Documentation/devicetree/bindings/gpio/gpio.txt on how to bind pinctrl and gpio drivers via the "gpio-ranges" property. Signed-off-by: Christian Lamparter <chunkeey@gmail.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2018-05-24pinctrl: msm: fix gpio-hog related boot issuesChristian Lamparter
Sven Eckelmann reported an issue with the current IPQ4019 pinctrl. Setting up any gpio-hog in the device-tree for his device would "kill the bootup completely": | [ 0.477838] msm_serial 78af000.serial: could not find pctldev for node /soc/pinctrl@1000000/serial_pinmux, deferring probe | [ 0.499828] spi_qup 78b5000.spi: could not find pctldev for node /soc/pinctrl@1000000/spi_0_pinmux, deferring probe | [ 1.298883] requesting hog GPIO enable USB2 power (chip 1000000.pinctrl, offset 58) failed, -517 | [ 1.299609] gpiochip_add_data: GPIOs 0..99 (1000000.pinctrl) failed to register | [ 1.308589] ipq4019-pinctrl 1000000.pinctrl: Failed register gpiochip | [ 1.316586] msm_serial 78af000.serial: could not find pctldev for node /soc/pinctrl@1000000/serial_pinmux, deferring probe | [ 1.322415] spi_qup 78b5000.spi: could not find pctldev for node /soc/pinctrl@1000000/spi_0_pinmux, deferri This was also verified on a RT-AC58U (IPQ4018) which would no longer boot, if a gpio-hog was specified. (Tried forcing the USB LED PIN (GPIO0) to high.). The problem is that Pinctrl+GPIO registration is currently peformed in the following order in pinctrl-msm.c: 1. pinctrl_register() 2. gpiochip_add() 3. gpiochip_add_pin_range() The actual error code -517 == -EPROBE_DEFER is coming from pinctrl_get_device_gpio_range(), which is called through: gpiochip_add of_gpiochip_add of_gpiochip_scan_gpios gpiod_hog gpiochip_request_own_desc __gpiod_request chip->request gpiochip_generic_request pinctrl_gpio_request pinctrl_get_device_gpio_range pinctrl_get_device_gpio_range() is unable to find any valid pin ranges, since nothing has been added to the pinctrldev_list yet. so the range can't be found, and the operation fails with -EPROBE_DEFER. This patch fixes the issue by adding the "gpio-ranges" property to the pinctrl device node of all upstream Qcom SoC. The pin ranges are then added by the gpio core. In order to remain compatible with older, existing DTs (and ACPI) a check for the "gpio-ranges" property has been added to msm_gpio_init(). This prevents the driver of adding the same entry to the pinctrldev_list twice. Reported-by: Sven Eckelmann <sven.eckelmann@openmesh.com> Tested-by: Sven Eckelmann <sven.eckelmann@openmesh.com> [ipq4019] Reviewed-by: Bjorn Andersson <bjorn.andersson@linaro.org> Signed-off-by: Christian Lamparter <chunkeey@gmail.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2018-05-24drm/exynos: Fix error value in exynos_drm_crtc_get_by_type()Marek Szyprowski
EPERM is not the correct error value when the driver is not able to get its resources. Change it to ENODEV. Reported-by: Russell King - ARM Linux <linux@armlinux.org.uk> Signed-off-by: Marek Szyprowski <m.szyprowski@samsung.com> Signed-off-by: Inki Dae <inki.dae@samsung.com>
2018-05-24drm/exynos/dsi: mask frame-done interruptAndrzej Hajda
DSI driver is not really interested in this interrupt. It causes only unnecessary code execution of interrupt handler and could possibly cause FIFO overflow - as it triggers DSI interrupt handler to process next DSI transfer. With this patch we will get rid of about 30 IRQ handler calls per second. Fixes: e6f988a45857 ("drm/exynos: dsi: add support for Exynos5433") Signed-off-by: Andrzej Hajda <a.hajda@samsung.com> Signed-off-by: Inki Dae <inki.dae@samsung.com>
2018-05-24pinctrl: mediatek: remove unused fields in struct mtk_eint_hwSean Wang
The .name field has been not being used in existent code logic, so it's better that we remove them all. Signed-off-by: Sean Wang <sean.wang@mediatek.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2018-05-24pinctrl: mediatek: use generic EINT register maps for each SoCSean Wang
So far, EINT on each SoC all used exactly identical register map and thus it's better that we apply generic register map already supported in EINT library and stop copy-n-pasting the same data block and filling into its platform data. Signed-off-by: Sean Wang <sean.wang@mediatek.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2018-05-24pinctrl: mediatek: add EINT support to MT7622 SoCSean Wang
Add EINT support to MT7622 SoC and the support is made as just an option to MT7622 pinctrl. Signed-off-by: Sean Wang <sean.wang@mediatek.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2018-05-24pinctrl: mediatek: refactor EINT related code for all MediaTek pinctrl can fitSean Wang
This patch is in preparation for adding EINT support to MT7622 pinctrl, and the refactoring doesn't alter any existent logic. A reason we have to refactor EINT code pieces into a generic way is that currently, they're tightly coupled with a certain type of MediaTek pinctrl would cause a grown in a very bad way as there is different types of pinctrl devices getting to join. Therefore, it is an essential or urgent thing that EINT code pieces are refactored to eliminate any dependencies across GPIO and EINT as possible. Additional structure mtk_eint_[xt, hw, regs] are being introduced for indicating how maps being designed between GPIO and EINT hw number, how to set and get GPIO state for a certain EINT pin, what characteristic on a EINT device is present on various SoCs. Signed-off-by: Sean Wang <sean.wang@mediatek.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2018-05-24pinctrl: freescale: Switch to SPDX identifierFabio Estevam
Adopt the SPDX license identifier headers to ease license compliance management. Signed-off-by: Fabio Estevam <fabio.estevam@nxp.com> Reviewed-by: Stefan Agner <stefan@agner.ch> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2018-05-24Merge tag 'samsung-pinctrl-4.18-2' of ↵Linus Walleij
https://git.kernel.org/pub/scm/linux/kernel/git/pinctrl/samsung into devel Samsung pinctrl drivers changes for v4.18 1. Driver expects specific order of GPIO interrupt banks. For S5Pv220 and Exynos5410 this order was not preserved so fix and document it. 2. Remove support for Exynos5440 (tree-wide, support is dropped because there are no real users of this platform, it also did not get testing since long time). 3. Fix lost state of GPF1..5 pins on Exynos5433 during system suspend.
2018-05-24Merge tag 'sh-pfc-for-v4.18-tag2' of ↵Linus Walleij
git://git.kernel.org/pub/scm/linux/kernel/git/geert/renesas-drivers into devel pinctrl: sh-pfc: Updates for v4.18 (take two) - Add support for the new R-Car E3 SoC, - Add I2C pin groups on R-Car M3-N, - Small fixes and cleanups.
2018-05-24drm/amdgpu: Add SOC15_WAIT_ON_RREG macro defineRex Zhu
Add new macro to wait on a register field to be a specific value. Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Rex Zhu <Rex.Zhu@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2018-05-24drm/amdgpu: Add CG/PG flags for VCNRex Zhu
Define new clock and powergating flags for VCN block. Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Rex Zhu <Rex.Zhu@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2018-05-24drm/amd/pp: Add smu support for VCN powergating on RVRex Zhu
Add the powerplay callback for powergating VCN (same as UVD and VCE). Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Rex Zhu <Rex.Zhu@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2018-05-24drm/amdgpu: skip CG for VCN when late_init/finiRex Zhu
VCN clockgating is handled manually like VCE and UVD. Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Rex Zhu <Rex.Zhu@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2018-05-24drm/amd/pp: fix a couple locking issuesRex Zhu
We should return unlock on the error path Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Rex Zhu <Rex.Zhu@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2018-05-24drm/amd/pp: Fix static checker warningRex Zhu
error: uninitialized symbol 'xxxx' Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Rex Zhu <Rex.Zhu@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2018-05-23drm/amdgpu/gmc9: disable partial wr rmw if ECC is not enabledAlex Deucher
The vbios mistakenly sets this bit on some boards without ECC. This can lead to reduced performance in some workloads. Disable the bit if the board does not have ECC. Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com> Reviewed-by: Junwei Zhang <Jerry.Zhang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2018-05-23drm/amdgpu: add a df 1.7 implementation of enable_ecc_force_par_wr_rmwAlex Deucher
Needed for proper memory setup depending on whether ECC is enabled on a particular board. Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com> Reviewed-by: Junwei Zhang <Jerry.Zhang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2018-05-23drm/amdgpu: add new DF callback for ECC setupAlex Deucher
The ForceParWrRMW setting needs to be enabled for ECC, but disabled when ECC is not enabled. Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com> Reviewed-by: Junwei Zhang <Jerry.Zhang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2018-05-23drm/amdgpu: add new DF 1.7 register defsAlex Deucher
Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com> Reviewed-by: Junwei Zhang <Jerry.Zhang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2018-05-23Remove calls to suspend/resume atomic helpers from ↵Andrey Grodzovsky
amdgpu_device_gpu_recover. (v2) First of all it's already being called from the display code from amd_ip_funcs.suspend/resume hooks. Second of all, the place in amdgpu_device_gpu_recover it's being called is wrong for GPU stalls since it is called BEFORE we cancel and force completion of all in flight jobs which were not yet processed. So, as Bas pointed in the ticket we will try to wait for fence in amdgpu_pm_compute_clocks but the pipe is hanged so we end up in deadlock. v2: remove unused variable Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=106500 Signed-off-by: Andrey Grodzovsky <andrey.grodzovsky@amd.com> Reviewed-by: Harry Wentland <harry.wentland@amd.com> Reviewed-by: Christian König <christian.koenig@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2018-05-24drm/exynos: decon: Add support for hardware windows no 4 and 5Marek Szyprowski
Enable support for 2 more hardware windows. This require enabling a few more clocks and set proper plane type for all windows. In the new configuration primary plane uses hardware window no 3 and cursor uses window no 5. The remaining hardware windows are used for overlays. This gives us an overlay plane both below and above primary plane for both Decon and DeconTV (which uses hardware window nr 0 for background). Signed-off-by: Marek Szyprowski <m.szyprowski@samsung.com> Signed-off-by: Inki Dae <inki.dae@samsung.com>
2018-05-23Input: psmouse-smbus - allow to control psmouse_deactivateBenjamin Tissoires
This seems to be Synaptics specific, as some Elan touchpads are not correctly switching to SMBus if we call deactivate before switching to SMBus on cold boot and on resume. Tested with the T480s Signed-off-by: Benjamin Tissoires <benjamin.tissoires@redhat.com> Acked-by: KT Liao <kt.liao@emc.com.tw> Signed-off-by: Dmitry Torokhov <dmitry.torokhov@gmail.com>
2018-05-23Input: elantech - detect new ICs and setup Host Notify for themBenjamin Tissoires
New ICs are using a different scheme for the alternate bus parameter. Given that they are new and are only using either PS2 only or PS2 + SMBus Host Notify, we force those new ICs to use the SMBus solution for enhanced reporting. This allows the touchpad found on the Lenovo T480s to report 5 fingers every 8 ms, instead of having a limit of 2 every 8 ms. Signed-off-by: Benjamin Tissoires <benjamin.tissoires@redhat.com> Acked-by: KT Liao <kt.liao@emc.com.tw> Signed-off-by: Dmitry Torokhov <dmitry.torokhov@gmail.com>
2018-05-23Input: elantech - add support for SMBus devicesBenjamin Tissoires
Many of the Elantech devices are connected through PS/2 and a different bus (SMBus or plain I2C). To not break any existing device, we only enable SMBus based on a module parameter. If some laptops require the quirk to be set, we will have to rely on a list of PNPIds or MDI matching to individually expose those hardware over SMBus. the parameter mentioned above is elantech_smbus from the psmouse module. Signed-off-by: Benjamin Tissoires <benjamin.tissoires@redhat.com> Acked-by: KT Liao <kt.liao@emc.com.tw> Signed-off-by: Dmitry Torokhov <dmitry.torokhov@gmail.com>
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