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2022-07-29Merge tag 'thermal-v5.20-rc1' of ↵Rafael J. Wysocki
git://git.kernel.org/pub/scm/linux/kernel/git/thermal/linux Pull thermal control changes for 5.20-rc1 from Daniel Lezcano: "- Make per cpufreq / devfreq cooling device ops instead of using a global variable, fix comments and rework the trace information (Lukasz Luba) - Add the include/dt-bindings/thermal.h under the area covered by the thermal maintainer in the MAINTAINERS file (Lukas Bulwahn) - Improve the error output by giving the sensor identification when a thermal zone failed to initialize, the DT bindings by changing the positive logic and adding the r8a779f0 support on the rcar3 (Wolfram Sang) - Convert the QCom tsens DT binding to the dtsformat format (Krzysztof Kozlowski) - Remove the pointless get_trend() function in the QCom, Ux500 and tegra thermal drivers, along with the unused DROP_FULL and RAISE_FULL trends definitions. Simplify the code by using clamp() macros (Daniel Lezcano) - Fix ref_table memory leak at probe time on the k3_j72xx bandgap (Bryan Brattlof) - Fix array underflow in prep_lookup_table (Dan Carpenter) - Add static annotation to the k3_j72xx_bandgap_j7* data structure (Jin Xiaoyun) - Fix typos in comments detected on sun8i by Coccinelle (Julia Lawall) - Fix typos in comments on rzg2l (Biju Das) - Remove as unnecessary call to dev_err() as the error is already printed by the failing function on u8500 (Yang Li) - Register the thermal zones as hwmon sensors for the Qcom thermal sensors (Dmitry Baryshkov) - Fix 'tmon' tool compilation issue by adding phtread.h include (Markus Mayer) - Fix typo in the comments for the 'tmon' tool (Slark Xiao) - Consolidate the thermal core code by beginning to move the thermal trip structure from the thermal OF code as a generic structure to be used by the different sensors when registering a thermal zone (Daniel Lezcano)" * tag 'thermal-v5.20-rc1' of git://git.kernel.org/pub/scm/linux/kernel/git/thermal/linux: (36 commits) thermal/of: Initialize trip points separately thermal/of: Use thermal trips stored in the thermal zone thermal/core: Add thermal_trip in thermal_zone thermal/core: Rename 'trips' to 'num_trips' thermal/core: Move thermal_set_delay_jiffies to static thermal/core: Remove unneeded EXPORT_SYMBOLS thermal/of: Move thermal_trip structure to thermal.h thermal/of: Remove the device node pointer for thermal_trip thermal/of: Replace device node match with device node search thermal/core: Remove duplicate information when an error occurs thermal/core: Avoid calling ->get_trip_temp() unnecessarily thermal/tools/tmon: Fix typo 'the the' in comment thermal/tools/tmon: Include pthread and time headers in tmon.h thermal/ti-soc-thermal: Fix comment typo thermal/drivers/qcom/spmi-adc-tm5: Register thermal zones as hwmon sensors thermal/drivers/qcom/temp-alarm: Register thermal zones as hwmon sensors thermal/drivers/u8500: Remove unnecessary print function dev_err() thermal/drivers/rzg2l: Fix comments thermal/drivers/sun8i: Fix typo in comment thermal/drivers/k3_j72xx_bandgap: Make k3_j72xx_bandgap_j721e_data and k3_j72xx_bandgap_j7200_data static ...
2022-07-29PCI: Remove pci_mmap_page_range() wrapperArnd Bergmann
The ARCH_GENERIC_PCI_MMAP_RESOURCE symbol came up in a recent discussion, and I noticed that this was left behind by an unfinished cleanup from 2017. The only architecture that still relies on providing its own pci_mmap_page_range() helper instead of using the generic pci_mmap_resource_range() is sparc. Presumably the reasons for this have not changed, but at least this can be simplified by converting sparc to use the same interface as the others. The only difference between the two is the device-specific offset that gets added to or subtracted from vma->vm_pgoff. Change the only caller of pci_mmap_page_range() in common code to subtract this offset and call the modern interface, while adding it back in the sparc implementation to preserve the existing behavior. This removes the complexities of the dual interfaces from the common code, and keeps it all specific to the sparc architecture code. According to David Miller, the sparc code lets user space poke into the VGA I/O port registers by mmapping the I/O space of the parent bridge device, which is something that the generic pci_mmap_resource_range() code apparently does not. Link: https://lore.kernel.org/lkml/1519887203.622.3.camel@infradead.org/t/ Link: https://lore.kernel.org/lkml/20220714214657.2402250-3-shorne@gmail.com/ Link: https://lore.kernel.org/r/20220715153617.3393420-1-arnd@kernel.org Signed-off-by: Arnd Bergmann <arnd@arndb.de> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com> Cc: David Woodhouse <dwmw2@infradead.org> Cc: David S. Miller <davem@davemloft.net> Cc: Stafford Horne <shorne@gmail.com>
2022-07-29Merge branch 'thermal-core'Rafael J. Wysocki
Merge changes that make the thermal core use ida_alloc()/free() directly instead of ida_simple_get()/ida_simple_remove() that have been deprecated. * thermal-core: thermal: Directly use ida_alloc()/free()
2022-07-29Merge tag 'powerpc-5.19-6' of ↵Linus Torvalds
git://git.kernel.org/pub/scm/linux/kernel/git/powerpc/linux Pull powerpc fixes from Michael Ellerman: - Re-enable the new amdgpu display engine for powerpc, as long as the compiler is correctly configured. - Disable stack variable initialisation in prom_init to fix GCC 12 allmodconfig. Thanks to Dan Horák and Sudip Mukherjee. * tag 'powerpc-5.19-6' of git://git.kernel.org/pub/scm/linux/kernel/git/powerpc/linux: drm/amdgpu: Re-enable DCN for 64-bit powerpc powerpc/64s: Disable stack variable initialisation for prom_init
2022-07-29spi: spi-gxp: Add support for HPE GXP SoCsNick Hawkins
The GXP supports 3 separate SPI interfaces to accommodate the system flash, core flash, and other functions. The SPI engine supports variable clock frequency, selectable 3-byte or 4-byte addressing and a configurable x1, x2, and x4 command/address/data modes. The memory buffer for reading and writing ranges between 256 bytes and 8KB. This driver supports access to the core flash and bios part. Signed-off-by: Nick Hawkins <nick.hawkins@hpe.com> Link: https://lore.kernel.org/r/20220728161459.7738-2-nick.hawkins@hpe.com Signed-off-by: Mark Brown <broonie@kernel.org>
2022-07-29iavf: Fix 'tc qdisc show' listing too many queuesPrzemyslaw Patynowski
Fix tc qdisc show dev <ethX> root displaying too many fq_codel qdiscs. tc_modify_qdisc, which is caller of ndo_setup_tc, expects driver to call netif_set_real_num_tx_queues, which prepares qdiscs. Without this patch, fq_codel qdiscs would not be adjusted to number of queues on VF. e.g.: tc qdisc show dev <ethX> qdisc mq 0: root qdisc fq_codel 0: parent :4 limit 10240p flows 1024 quantum 1514 target 5ms interval 100ms memory_limit 32Mb ecn drop_batch 64 qdisc fq_codel 0: parent :3 limit 10240p flows 1024 quantum 1514 target 5ms interval 100ms memory_limit 32Mb ecn drop_batch 64 qdisc fq_codel 0: parent :2 limit 10240p flows 1024 quantum 1514 target 5ms interval 100ms memory_limit 32Mb ecn drop_batch 64 qdisc fq_codel 0: parent :1 limit 10240p flows 1024 quantum 1514 target 5ms interval 100ms memory_limit 32Mb ecn drop_batch 64 tc qdisc add dev <ethX> root mqprio num_tc 2 map 1 0 0 0 0 0 0 0 queues 1@0 1@1 hw 1 mode channel shaper bw_rlimit max_rate 5000Mbit 150Mbit tc qdisc show dev <ethX> qdisc mqprio 8003: root tc 2 map 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 queues:(0:0) (1:1) mode:channel shaper:bw_rlimit max_rate:5Gbit 150Mbit qdisc fq_codel 0: parent 8003:4 limit 10240p flows 1024 quantum 1514 target 5ms interval 100ms memory_limit 32Mb ecn drop_batch 64 qdisc fq_codel 0: parent 8003:3 limit 10240p flows 1024 quantum 1514 target 5ms interval 100ms memory_limit 32Mb ecn drop_batch 64 qdisc fq_codel 0: parent 8003:2 limit 10240p flows 1024 quantum 1514 target 5ms interval 100ms memory_limit 32Mb ecn drop_batch 64 qdisc fq_codel 0: parent 8003:1 limit 10240p flows 1024 quantum 1514 target 5ms interval 100ms memory_limit 32Mb ecn drop_batch 64 While after fix: tc qdisc add dev <ethX> root mqprio num_tc 2 map 1 0 0 0 0 0 0 0 queues 1@0 1@1 hw 1 mode channel shaper bw_rlimit max_rate 5000Mbit 150Mbit tc qdisc show dev <ethX> #should show 2, shows 4 qdisc mqprio 8004: root tc 2 map 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 queues:(0:0) (1:1) mode:channel shaper:bw_rlimit max_rate:5Gbit 150Mbit qdisc fq_codel 0: parent 8004:2 limit 10240p flows 1024 quantum 1514 target 5ms interval 100ms memory_limit 32Mb ecn drop_batch 64 qdisc fq_codel 0: parent 8004:1 limit 10240p flows 1024 quantum 1514 target 5ms interval 100ms memory_limit 32Mb ecn drop_batch 64 Fixes: d5b33d024496 ("i40evf: add ndo_setup_tc callback to i40evf") Signed-off-by: Przemyslaw Patynowski <przemyslawx.patynowski@intel.com> Co-developed-by: Grzegorz Szczurek <grzegorzx.szczurek@intel.com> Signed-off-by: Grzegorz Szczurek <grzegorzx.szczurek@intel.com> Co-developed-by: Kiran Patil <kiran.patil@intel.com> Signed-off-by: Kiran Patil <kiran.patil@intel.com> Signed-off-by: Jedrzej Jagielski <jedrzej.jagielski@intel.com> Tested-by: Bharathi Sreenivas <bharathi.sreenivas@intel.com> Signed-off-by: Tony Nguyen <anthony.l.nguyen@intel.com>
2022-07-29iavf: Fix max_rate limitingPrzemyslaw Patynowski
Fix max_rate option in TC, check for proper quanta boundaries. Check for minimum value provided and if it fits expected 50Mbps quanta. Without this patch, iavf could send settings for max_rate limiting that would be accepted from by PF even the max_rate option is less than expected 50Mbps quanta. It results in no rate limiting on traffic as rate limiting will be floored to 0. Example: tc qdisc add dev $vf root mqprio num_tc 3 map 0 2 1 queues \ 2@0 2@2 2@4 hw 1 mode channel shaper bw_rlimit \ max_rate 50Mbps 500Mbps 500Mbps Should limit TC0 to circa 50 Mbps tc qdisc add dev $vf root mqprio num_tc 3 map 0 2 1 queues \ 2@0 2@2 2@4 hw 1 mode channel shaper bw_rlimit \ max_rate 0Mbps 100Kbit 500Mbps Should return error Fixes: d5b33d024496 ("i40evf: add ndo_setup_tc callback to i40evf") Signed-off-by: Przemyslaw Patynowski <przemyslawx.patynowski@intel.com> Signed-off-by: Jun Zhang <xuejun.zhang@intel.com> Tested-by: Bharathi Sreenivas <bharathi.sreenivas@intel.com> Signed-off-by: Tony Nguyen <anthony.l.nguyen@intel.com>
2022-07-29Merge back cpuidle material for 5.20.Rafael J. Wysocki
2022-07-29Merge ath-next from git://git.kernel.org/pub/scm/linux/kernel/git/kvalo/ath.gitKalle Valo
ath.git patches for v5.20. Major changes: ath11k: * fix WCN9074 to work again * revert rfkill support as it was causing problems
2022-07-29wifi: rtw88: check the return value of alloc_workqueue()William Dean
The function alloc_workqueue() in rtw_core_init() can fail, but there is no check of its return value. To fix this bug, its return value should be checked with new error handling code. Fixes: fe101716c7c9d ("rtw88: replace tx tasklet with work queue") Reported-by: Hacash Robot <hacashRobot@santino.com> Signed-off-by: William Dean <williamsukatube@gmail.com> Reviewed-by: Ping-Ke Shih <pkshih@realtek.com> Signed-off-by: Kalle Valo <kvalo@kernel.org> Link: https://lore.kernel.org/r/20220723063756.2956189-1-williamsukatube@163.com
2022-07-29wifi: rtw89: 8852a: adjust IMR for SER L1Zong-Zhe Yang
SER (system error recovery) L1 (level 1) has a step-by-step handshake process with FW. These handshakes still rely on B_AX_HS0ISR_IND_INT_EN. So, even already during recovery, we enable this bit in IMR. Signed-off-by: Zong-Zhe Yang <kevin_yang@realtek.com> Signed-off-by: Ping-Ke Shih <pkshih@realtek.com> Signed-off-by: Kalle Valo <kvalo@kernel.org> Link: https://lore.kernel.org/r/20220721074952.19676-1-pkshih@realtek.com
2022-07-29wifi: rtw89: 8852a: update RF radio A/B R56Ping-Ke Shih
Update to internal tag HALRF_027_00_060. Signed-off-by: Ping-Ke Shih <pkshih@realtek.com> Signed-off-by: Kalle Valo <kvalo@kernel.org> Link: https://lore.kernel.org/r/20220622091937.11325-1-pkshih@realtek.com
2022-07-29wifi: wcn36xx: Add debugfs entry to read firmware feature stringsBryan O'Donoghue
Add in the ability to easily find the firmware feature bits reported in the get feature exchange without having to compile-in debug prints. root@linaro-alip:~# cat /sys/kernel/debug/ieee80211/phy0/wcn36xx/firmware_feat_caps MCC P2P DOT11AC SLM_SESSIONIZATION DOT11AC_OPMODE SAP32STA TDLS P2P_GO_NOA_DECOUPLE_INIT_SCAN WLANACTIVE_OFFLOAD BEACON_OFFLOAD SCAN_OFFLOAD BCN_MISS_OFFLOAD STA_POWERSAVE STA_ADVANCED_PWRSAVE BCN_FILTER RTT RATECTRL WOW WLAN_ROAM_SCAN_OFFLOAD SPECULATIVE_PS_POLL IBSS_HEARTBEAT_OFFLOAD WLAN_SCAN_OFFLOAD WLAN_PERIODIC_TX_PTRN ADVANCE_TDLS BATCH_SCAN FW_IN_TX_PATH EXTENDED_NSOFFLOAD_SLOT CH_SWITCH_V1 HT40_OBSS_SCAN UPDATE_CHANNEL_LIST WLAN_MCADDR_FLT WLAN_CH144 TDLS_SCAN_COEXISTENCE LINK_LAYER_STATS_MEAS MU_MIMO EXTENDED_SCAN DYNAMIC_WMM_PS MAC_SPOOFED_SCAN FW_STATS WPS_PRBRSP_TMPL BCN_IE_FLT_DELTA Signed-off-by: Bryan O'Donoghue <bryan.odonoghue@linaro.org> Signed-off-by: Kalle Valo <quic_kvalo@quicinc.com> Link: https://lore.kernel.org/r/20220727161655.2286867-5-bryan.odonoghue@linaro.org
2022-07-29wifi: wcn36xx: Move capability bitmap to string translation function to ↵Bryan O'Donoghue
firmware.c Move wcn36xx_get_cap_name() function in main.c into firmware.c as wcn36xx_firmware_get_cap_name(). Reviewed-by: Loic Poulain <loic.poulain@linaro.org> Signed-off-by: Bryan O'Donoghue <bryan.odonoghue@linaro.org> Signed-off-by: Kalle Valo <quic_kvalo@quicinc.com> Link: https://lore.kernel.org/r/20220727161655.2286867-4-bryan.odonoghue@linaro.org
2022-07-29wifi: wcn36xx: Move firmware feature bit storage to dedicated firmware.c fileBryan O'Donoghue
The naming of the get/set/clear firmware feature capability bits doesn't really follow the established namespace pattern of wcn36xx_logicalblock_do_something(); The feature bits are accessed by smd.c and main.c. It would be nice to display the found feature bits in debugfs. To do so though we should tidy up the namespace a bit. Move the firmware feature exchange API to its own file - firmware.c giving us the opportunity to functionally decompose other firmware related accessors as appropriate in future. Reviewed-by: Loic Poulain <loic.poulain@linaro.org> Signed-off-by: Bryan O'Donoghue <bryan.odonoghue@linaro.org> Signed-off-by: Kalle Valo <quic_kvalo@quicinc.com> Link: https://lore.kernel.org/r/20220727161655.2286867-3-bryan.odonoghue@linaro.org
2022-07-29wifi: wcn36xx: Rename clunky firmware feature bit enumBryan O'Donoghue
The enum name "place_holder_in_cap_bitmap" is self descriptively asking to be changed to something else. Rename place_holder_in_cap_bitmap to wcn36xx_firmware_feat_caps so that the contents and intent of the enum is obvious. Reviewed-by: Loic Poulain <loic.poulain@linaro.org> Signed-off-by: Bryan O'Donoghue <bryan.odonoghue@linaro.org> Signed-off-by: Kalle Valo <quic_kvalo@quicinc.com> Link: https://lore.kernel.org/r/20220727161655.2286867-2-bryan.odonoghue@linaro.org
2022-07-29pwm: lpc18xx: Fix period handlingUwe Kleine-König
The calculation: val = (u64)NSEC_PER_SEC * LPC18XX_PWM_TIMER_MAX; do_div(val, lpc18xx_pwm->clk_rate); lpc18xx_pwm->max_period_ns = val; is bogus because with NSEC_PER_SEC = 1000000000, LPC18XX_PWM_TIMER_MAX = 0xffffffff and clk_rate < NSEC_PER_SEC this overflows the (on lpc18xx (i.e. ARM32) 32 bit wide) unsigned int .max_period_ns. This results (dependant of the actual clk rate) in an arbitrary limitation of the maximal period. E.g. for clkrate = 333333333 (Hz) we get max_period_ns = 9 instead of 12884901897. So make .max_period_ns an u64 and pass period and duty as u64 to not discard relevant digits. And also make use of mul_u64_u64_div_u64() which prevents all overflows assuming clk_rate < NSEC_PER_SEC. Fixes: 841e6f90bb78 ("pwm: NXP LPC18xx PWM/SCT driver") Signed-off-by: Uwe Kleine-König <u.kleine-koenig@pengutronix.de> Signed-off-by: Thierry Reding <thierry.reding@gmail.com>
2022-07-29pwm: lpc18xx: Convert to use dev_err_probe()Uwe Kleine-König
This has various upsides: - It emits the symbolic name of the error code - It is silent in the EPROBE_DEFER case and properly sets the defer reason - It reduces the number of code lines slightly Signed-off-by: Uwe Kleine-König <u.kleine-koenig@pengutronix.de> Signed-off-by: Thierry Reding <thierry.reding@gmail.com>
2022-07-29pwm: twl-led: Document some limitations and link to the reference manualUwe Kleine-König
I found these just from reading the reference manual and the driver source. It's unclear to me if there are glitches when updating the ON and OFF registers. Signed-off-by: Uwe Kleine-König <u.kleine-koenig@pengutronix.de> Signed-off-by: Thierry Reding <thierry.reding@gmail.com>
2022-07-29pwm: Add clock based PWM output driverNikita Travkin
Some systems have clocks exposed to external devices. If the clock controller supports duty-cycle configuration, such clocks can be used as pwm outputs. In fact PWM and CLK subsystems are interfaced with in a similar way and an "opposite" driver already exists (clk-pwm). Add a driver that would enable pwm devices to be used via clk subsystem. Acked-by: Uwe Kleine-König <u.kleine-koenig@pengutronix.de> Signed-off-by: Nikita Travkin <nikita@trvn.ru> Signed-off-by: Thierry Reding <thierry.reding@gmail.com>
2022-07-29pwm: sifive: Shut down hardware only after pwmchip_remove() completedUwe Kleine-König
The PWMs are expected to be functional until pwmchip_remove() is called. So disable the clks only afterwards. Fixes: 9e37a53eb051 ("pwm: sifive: Add a driver for SiFive SoC PWM") Signed-off-by: Uwe Kleine-König <u.kleine-koenig@pengutronix.de> Tested-by: Emil Renner Berthing <emil.renner.berthing@canonical.com> Signed-off-by: Thierry Reding <thierry.reding@gmail.com>
2022-07-29pwm: sifive: Ensure the clk is enabled exactly once per running PWMUwe Kleine-König
.apply() assumes the clk to be for a given PWM iff the PWM is enabled. So make sure this is the case when .probe() completes. And in .remove() disable the according number of times. This fixes a clk enable/disable imbalance, if some PWMs are already running at probe time. Fixes: 9e37a53eb051 (pwm: sifive: Add a driver for SiFive SoC PWM) Signed-off-by: Uwe Kleine-König <u.kleine-koenig@pengutronix.de> Tested-by: Emil Renner Berthing <emil.renner.berthing@canonical.com> Signed-off-by: Thierry Reding <thierry.reding@gmail.com>
2022-07-29pwm: sifive: Simplify clk handlingUwe Kleine-König
The clk is necessary for both register access and (enabled) operation of the PWM. Instead of clk_enable() update_hw() if pwm_got_enabled(): clk_enable() elif pwm_got_disabled(): clk_disable() clk_disable() which is some cases only calls clk_enable() to immediately afterwards call clk_disable again, do: if (!prev_state.enabled) clk_enable() # clk enabled exactly once update_hw() if (!next_state.enabled) clk_disable() which is much easier. Signed-off-by: Uwe Kleine-König <u.kleine-koenig@pengutronix.de> Tested-by: Emil Renner Berthing <emil.renner.berthing@canonical.com> Signed-off-by: Thierry Reding <thierry.reding@gmail.com>
2022-07-29pwm: sifive: Enable clk only after period check in .apply()Uwe Kleine-König
For the period check and the initial calculations of register values there is no hardware access needed. So delay enabling the clk a bit to simplify the code flow a bit. Signed-off-by: Uwe Kleine-König <u.kleine-koenig@pengutronix.de> Tested-by: Emil Renner Berthing <emil.renner.berthing@canonical.com> Signed-off-by: Thierry Reding <thierry.reding@gmail.com>
2022-07-29pwm: sifive: Reduce time the controller lock is heldUwe Kleine-König
The lock is only to serialize access and update to user_count and approx_period between different PWMs served by the same pwm_chip. So the lock needs only to be taken during the check if the (chip global) period can and/or needs to be changed. Signed-off-by: Uwe Kleine-König <u.kleine-koenig@pengutronix.de> Tested-by: Emil Renner Berthing <emil.renner.berthing@canonical.com> Signed-off-by: Thierry Reding <thierry.reding@gmail.com>
2022-07-29pwm: sifive: Fold pwm_sifive_enable() into its only callerUwe Kleine-König
There is only a single caller of pwm_sifive_enable() which only enables or disables the clk. Put this implementation directly into pwm_sifive_apply() which allows further simplification in the next change. There is no change in behaviour. Signed-off-by: Uwe Kleine-König <u.kleine-koenig@pengutronix.de> Tested-by: Emil Renner Berthing <emil.renner.berthing@canonical.com> Signed-off-by: Thierry Reding <thierry.reding@gmail.com>
2022-07-29pwm: sifive: Simplify offset calculation for PWMCMP registersUwe Kleine-König
Instead of explicitly using PWM_SIFIVE_PWMCMP0 + pwm->hwpwm * PWM_SIFIVE_SIZE_PWMCMP for each access to one of the PWMCMP registers, introduce a macro that takes the hwpwm id as parameter. For the register definition using a plain 4 instead of the cpp constant PWM_SIFIVE_SIZE_PWMCMP is easier to read, so define the offset macro without the constant. The latter can then be dropped as there are no users left. Signed-off-by: Uwe Kleine-König <u.kleine-koenig@pengutronix.de> Tested-by: Emil Renner Berthing <emil.renner.berthing@canonical.com> Signed-off-by: Thierry Reding <thierry.reding@gmail.com>
2022-07-29netdevsim: fib: Add debugfs knob to simulate route deletion failureIdo Schimmel
The previous patch ("netdevsim: fib: Fix reference count leak on route deletion failure") fixed a reference count leak that happens on route deletion failure. Such failures can only be simulated by injecting slab allocation failures, which cannot be surgically injected. In order to be able to specifically test this scenario, add a debugfs knob that allows user space to fail route deletion requests when enabled. Signed-off-by: Ido Schimmel <idosch@nvidia.com> Reviewed-by: Amit Cohen <amcohen@nvidia.com> Reviewed-by: David Ahern <dsahern@kernel.org> Signed-off-by: David S. Miller <davem@davemloft.net>
2022-07-29netdevsim: fib: Fix reference count leak on route deletion failureIdo Schimmel
As part of FIB offload simulation, netdevsim stores IPv4 and IPv6 routes and holds a reference on FIB info structures that in turn hold a reference on the associated nexthop device(s). In the unlikely case where we are unable to allocate memory to process a route deletion request, netdevsim will not release the reference from the associated FIB info structure, thereby preventing the associated nexthop device(s) from ever being removed [1]. Fix this by scheduling a work item that will flush netdevsim's FIB table upon route deletion failure. This will cause netdevsim to release its reference from all the FIB info structures in its table. Reported by Lucas Leong of Trend Micro Zero Day Initiative. Fixes: 0ae3eb7b4611 ("netdevsim: fib: Perform the route programming in a non-atomic context") Signed-off-by: Ido Schimmel <idosch@nvidia.com> Reviewed-by: Amit Cohen <amcohen@nvidia.com> Reviewed-by: David Ahern <dsahern@kernel.org> Signed-off-by: David S. Miller <davem@davemloft.net>
2022-07-29net: ethernet: mtk_eth_soc: add xdp tx return bulking supportLorenzo Bianconi
Convert mtk_eth_soc driver to xdp_return_frame_bulk APIs. Signed-off-by: Lorenzo Bianconi <lorenzo@kernel.org> Signed-off-by: David S. Miller <davem@davemloft.net>
2022-07-29net: ethernet: mtk_eth_soc: introduce xdp multi-frag supportLorenzo Bianconi
Add the capability to map non-linear xdp frames in XDP_TX and ndo_xdp_xmit callback. Signed-off-by: Lorenzo Bianconi <lorenzo@kernel.org> Signed-off-by: David S. Miller <davem@davemloft.net>
2022-07-29net: ethernet: mtk_eth_soc: introduce mtk_xdp_frame_map utility routineLorenzo Bianconi
This is a preliminary patch to add xdp multi-frag support to mtk_eth_soc driver Signed-off-by: Lorenzo Bianconi <lorenzo@kernel.org> Signed-off-by: David S. Miller <davem@davemloft.net>
2022-07-29vmxnet3: do not reschedule napi for rx processingRonak Doshi
Commit '2c5a5748105a ("vmxnet3: add support for out of order rx completion")' added support for out of order rx completion. Within that patch, an enhancement was done to reschedule napi for processing rx completions. However, it can lead to missing an interrupt. So, this patch reverts that part of the code. Fixes: 2c5a5748105a ("vmxnet3: add support for out of order rx completion") Signed-off-by: Ronak Doshi <doshir@vmware.com> Acked-by: Guolin Yang <gyang@vmware.com> Signed-off-by: David S. Miller <davem@davemloft.net>
2022-07-29crypto: hisilicon/zip - Use the bitmap API to allocate bitmapsChristophe JAILLET
Use bitmap_zalloc()/bitmap_free() instead of hand-writing them. It is less verbose and it improves the semantic. While at it, add an explicit include <linux/bitmap.h>. Signed-off-by: Christophe JAILLET <christophe.jaillet@wanadoo.fr> Signed-off-by: Herbert Xu <herbert@gondor.apana.org.au>
2022-07-29crypto: hisilicon/sec - fix auth key size errorKai Ye
The authentication algorithm supports a maximum of 128-byte keys. The allocated key memory is insufficient. Fixes: 2f072d75d1ab ("crypto: hisilicon - Add aead support on SEC2") Signed-off-by: Kai Ye <yekai13@huawei.com> Signed-off-by: Herbert Xu <herbert@gondor.apana.org.au>
2022-07-29crypto: ccree - Remove a useless dma_supported() callChristophe JAILLET
There is no point in calling dma_supported() before calling dma_set_coherent_mask(). This function already calls dma_supported() and returns an error (-EIO) if it fails. So remove the superfluous dma_supported() call. Moreover, setting a larger DMA mask will never fail when setting a smaller one will succeed, so the whole "while" loop can be removed as well. (see [1]) While at it, fix the name of the function reported in a dev_err(). [1]: https://lore.kernel.org/all/YteQ6Vx2C03UtCkG@infradead.org/ Suggested-by: Christoph Hellwig <hch@infradead.org> Signed-off-by: Christophe JAILLET <christophe.jaillet@wanadoo.fr> Acked-by: Gilad Ben-Yossef <gilad@benyossef.com> Signed-off-by: Herbert Xu <herbert@gondor.apana.org.au>
2022-07-29crypto: ccp - Add support for new CCP/PSP device IDMario Limonciello
Add a new CCP/PSP PCI device ID. This uses same register offsets as the previously supported structure. Signed-off-by: Mario Limonciello <mario.limonciello@amd.com> Acked-by: Tom Lendacky <thomas.lendacky@amd.com> Acked-by: Rijo Thomas <Rijo-john.Thomas@amd.com> Signed-off-by: Herbert Xu <herbert@gondor.apana.org.au>
2022-07-29crypto: inside-secure - Add missing MODULE_DEVICE_TABLE for ofPali Rohár
Without MODULE_DEVICE_TABLE, crypto_safexcel.ko module is not automatically loaded on platforms where inside-secure crypto HW is specified in device tree (e.g. Armada 3720). So add missing MODULE_DEVICE_TABLE for of. Fixes: 1b44c5a60c13 ("crypto: inside-secure - add SafeXcel EIP197 crypto engine driver") Signed-off-by: Pali Rohár <pali@kernel.org> Acked-by: Marek Behún <kabel@kernel.org> Signed-off-by: Herbert Xu <herbert@gondor.apana.org.au>
2022-07-29crypto: hisilicon/hpre - don't use GFP_KERNEL to alloc mem during softirqZhengchao Shao
The hpre encryption driver may be used to encrypt and decrypt packets during the rx softirq, it is not allowed to use GFP_KERNEL. Fixes: c8b4b477079d ("crypto: hisilicon - add HiSilicon HPRE accelerator") Signed-off-by: Zhengchao Shao <shaozhengchao@huawei.com> Signed-off-by: Herbert Xu <herbert@gondor.apana.org.au>
2022-07-29mlxsw: spectrum: Support ethtool 'get_ts_info' callback in Spectrum-2Danielle Ratson
The 'get_ts_info' callback is used for obtaining information about time stamping and PTP hardware clock capabilities of a network device. The existing function of Spectrum-1 is used to advertise the PHC capabilities and the supported RX and TX filters. Implement a similar function for Spectrum-2, expose that the supported 'rx_filters' are all PTP event packets, as for these packets the driver fills the time stamp from the CQE in the SKB. In the future, mlxsw driver will be extended to support one-step PTP in Spectrum-2 and newer ASICs. Then additional 'tx_types' will be supported. Signed-off-by: Danielle Ratson <danieller@nvidia.com> Signed-off-by: Amit Cohen <amcohen@nvidia.com> Reviewed-by: Petr Machata <petrm@nvidia.com> Signed-off-by: Ido Schimmel <idosch@nvidia.com> Signed-off-by: David S. Miller <davem@davemloft.net>
2022-07-29mlxsw: spectrum_ptp: Support SIOCGHWTSTAMP, SIOCSHWTSTAMP ioctlsDanielle Ratson
The SIOCSHWTSTAMP ioctl configures HW timestamping on a given port. In Spectrum-2 and above, each packet gets time stamp by default, but in order to provide an accurate time stamp, software should configure to update the correction field. In addition, the PTP traps are not enabled by default, software should enable it per port or for all ports. The switch behaves like a transparent clock between CPU port and each front panel port. If ingress correction is set on a port for a given packet type, then when such a packet is received via the port, the current time stamp is subtracted from the correction field. If egress correction is set on a port for a given packet type, then when such a packet is transmitted via the port, the current time stamp is added to the correction field. The result is that as the packet ingresses through a port with ingress correction enabled, and egresses through a port with egress correction enabled, the PTP correction field is updated to reflect the time that the packet spent in the ASIC. This can be used to update the correction field of trapped packets by enabling ingress correction on a port where time stamping was enabled, and egress correction on the CPU port. Similarly, for packets transmitted from the host, ingress correction should be enabled on the CPU port, and egress correction on a front-panel port. However, since the correction fields will be updated for all PTP packets crossing the CPU port, in order not to mangle the correction field, the front panel port involved in the packet transfer must have the corresponding correction enabled as well. Therefore, when HW timestamping is enabled on at least one port, we have to configure hardware to update the correction field and trap PTP event packets on all ports. Add reference count as part of 'struct mlxsw_sp_ptp_state', to maintain how many ports use HW timestamping. Handle the correction field configuration only when the first port enables time stamping and when the last port disables time stamping. Store the configuration as part of 'struct mlxsw_sp_ptp_state', as it is global for all ports. The SIOCGHWTSTAMP ioctl is a getter for the current configuration, implement it and use the global configuration. Signed-off-by: Danielle Ratson <danieller@nvidia.com> Signed-off-by: Amit Cohen <amcohen@nvidia.com> Reviewed-by: Petr Machata <petrm@nvidia.com> Signed-off-by: Ido Schimmel <idosch@nvidia.com> Signed-off-by: David S. Miller <davem@davemloft.net>
2022-07-29mlxsw: spectrum: Support time stamping on Spectrum-2Danielle Ratson
As opposed to Spectrum-1, in which time stamps arrive through a pair of dedicated events into a queue and later are being matched to the corresponding packets, in Spectrum-2 we are reading the time stamps directly from the CQE. Software can get the time stamp in UTC format using CQEv2. Add a time stamp field to 'struct mlxsw_skb_cb'. In mlxsw_pci_cqe_{rdq,sdq}_handle() extract the time stamp from the CQE into the new time stamp field. Note that the time stamp in the CQE is represented by 38 bits, which is a short representation of UTC time. Software should create the full time stamp using the global UTC clock. Read UTC clock from hardware only for PTP packets which were trapped to CPU with PTP0 trap ID (event packets). Use the time stamp from the SKB when packet is received or transmitted. Signed-off-by: Danielle Ratson <danieller@nvidia.com> Signed-off-by: Amit Cohen <amcohen@nvidia.com> Reviewed-by: Petr Machata <petrm@nvidia.com> Signed-off-by: Ido Schimmel <idosch@nvidia.com> Signed-off-by: David S. Miller <davem@davemloft.net>
2022-07-29mlxsw: Send PTP packets as data packets to overcome a limitationDanielle Ratson
In Spectrum-2 and Spectrum-3, the correction field of PTP packets which are sent as control packets is not updated at egress port. To overcome this limitation, PTP packets which require time stamp, should be sent as data packets with the following details: 1. FID valid = 1 2. FID value above the maximum FID 3. rx_router_port = 1 >From Spectrum-4 and on, this limitation will be solved. Extend the function which handles TX header, in case that the packet is a PTP packet, add TX header with type=data and all the above mentioned requirements. Add operation as part of 'struct mlxsw_sp_ptp_ops', to be able to separate the handling of PTP packets between different ASICs. Use the data packet solution only for Spectrum-2 and Spectrum-3. Therefore, add a dedicated operation structure for Spectrum-4, as it will be same to Spectrum-2 in PTP implementation, just will not have the limitation of control packets. Signed-off-by: Danielle Ratson <danieller@nvidia.com> Signed-off-by: Amit Cohen <amcohen@nvidia.com> Reviewed-by: Petr Machata <petrm@nvidia.com> Signed-off-by: Ido Schimmel <idosch@nvidia.com> Signed-off-by: David S. Miller <davem@davemloft.net>
2022-07-29mlxsw: spectrum_ptp: Add implementation for physical hardware clock operationsDanielle Ratson
Implement physical hardware clock operations. The main difference between the existing operations of Spectrum-1 and the new operations of Spectrum-2 is the usage of UTC hardware clock instead of FRC. Add support for init() and fini() functions for PTP clock in Spectrum-2. Signed-off-by: Danielle Ratson <danieller@nvidia.com> Signed-off-by: Amit Cohen <amcohen@nvidia.com> Reviewed-by: Petr Machata <petrm@nvidia.com> Signed-off-by: Ido Schimmel <idosch@nvidia.com> Signed-off-by: David S. Miller <davem@davemloft.net>
2022-07-29mlxsw: Query UTC sec and nsec PCI offsets and valuesDanielle Ratson
Query UTC sec and nsec PCI offsets during the pci_init(), to be able to read UTC time later. Implement functions to read UTC seconds and nanoseconds from the offset which was read as part of initialization. Signed-off-by: Danielle Ratson <danieller@nvidia.com> Signed-off-by: Amit Cohen <amcohen@nvidia.com> Reviewed-by: Petr Machata <petrm@nvidia.com> Signed-off-by: Ido Schimmel <idosch@nvidia.com> Signed-off-by: David S. Miller <davem@davemloft.net>
2022-07-29mlxsw: spectrum_ptp: Add PTP initialization / finalization for Spectrum-2Danielle Ratson
Lay the groundwork for Spectrum-2 support. On Spectrum-2, the packets get the time stamps from the CQE, which means that the time stamp is attached to its packet. Configure MTPTPT to set which message types should arrive under which PTP trap. PTP0 will be used for event message types, which means that the packets require time stamp. PTP1 will be used for other packets. Note that in Spectrum-2, all packets contain time stamp by default. The two types of traps (PTP0, PTP1) will be used to separate between PTP_EVENT traps and PTP_GENERAL traps, so then the driver will fill the time stamp as part of the SKB only for event message types. Later the driver will enable the traps using 'MTPCPC.ptp_trap_en' bit. Then, PTP packets start arriving through the PTP traps. Currently, the structure 'mlxsw_sp2_ptp_state' contains only the common structure, the next patches will extend it. Signed-off-by: Danielle Ratson <danieller@nvidia.com> Signed-off-by: Amit Cohen <amcohen@nvidia.com> Reviewed-by: Petr Machata <petrm@nvidia.com> Signed-off-by: Ido Schimmel <idosch@nvidia.com> Signed-off-by: David S. Miller <davem@davemloft.net>
2022-07-29mlxsw: Support CQEv2 for SDQ in Spectrum-2 and newer ASICsDanielle Ratson
Currently, Tx completions are reported using Completion Queue Element version 1 (CQEv1). These elements do not contain the Tx time stamp, which is fine as Spectrum-1 reads Tx time stamps via a dedicated FIFO and Spectrum-2 does not currently support PTP. In preparation for Spectrum-2 PTP support, use CQEv2 for Spectrum-2 and newer ASICs, as this CQE format encodes the Tx time stamp. Signed-off-by: Danielle Ratson <danieller@nvidia.com> Signed-off-by: Amit Cohen <amcohen@nvidia.com> Reviewed-by: Petr Machata <petrm@nvidia.com> Signed-off-by: Ido Schimmel <idosch@nvidia.com> Signed-off-by: David S. Miller <davem@davemloft.net>
2022-07-29mlxsw: spectrum_ptp: Add helper functions to configure PTP trapsAmit Cohen
MTPTPT register is used to set which message types should arrive under which PTP trap. Currently, PTP0 is used for event message types, which means that the packets require time stamp. PTP1 is used for other packets. This configuration will be same for Spectrum-2 and newer ASICs. In preparation for Spectrum-2 PTP support, add helper functions to configure PTP traps and use them for Spectrum-1. These functions will be used later also for Spectrum-2. Signed-off-by: Amit Cohen <amcohen@nvidia.com> Reviewed-by: Petr Machata <petrm@nvidia.com> Signed-off-by: Ido Schimmel <idosch@nvidia.com> Signed-off-by: David S. Miller <davem@davemloft.net>
2022-07-29can: etas_es58x: remove useless calls to usb_fill_bulk_urb()Vincent Mailhol
Aside of urb->transfer_buffer_length and urb->context which might change in the TX path, all the other URB parameters remains constant during runtime. So, there is no reasons to call usb_fill_bulk_urb() each time before submitting an URB. Make sure to initialize all the fields of the URB at allocation time. For the TX branch, replace the call usb_fill_bulk_urb() by an assignment of urb->context. urb->urb->transfer_buffer_length is already set by the caller functions, no need to set it again. For the RX branch, because all parameters are unchanged, simply remove the call to usb_fill_bulk_urb(). Signed-off-by: Vincent Mailhol <mailhol.vincent@wanadoo.fr> Link: https://lore.kernel.org/all/20220729080902.25839-1-mailhol.vincent@wanadoo.fr Signed-off-by: Marc Kleine-Budde <mkl@pengutronix.de>
2022-07-29staging: r8188eu: remove initializer from ret in rtw_pwr_wakeupPhillip Potter
Remove the success initializer from the ret variable in rtw_pwr_wakeup, as we set it later anyway in the success path, and also set on failure. This makes the function appear cleaner and more consistent. Suggested-by: Dan Carpenter <dan.carpenter@oracle.com> Tested-by: Philipp Hortmann <philipp.g.hortmann@gmail.com> Signed-off-by: Phillip Potter <phil@philpotter.co.uk> Link: https://lore.kernel.org/r/20220728231150.972-2-phil@philpotter.co.uk Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
generated by cgit (git 2.34.1) at 2025-09-21 04:36:27 +0000