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2020-07-31drm/msm/dsi: Add DSI configuration for SDM660Konrad Dybcio
This also applies to sdm630/636 and their SDA counterparts. Signed-off-by: Konrad Dybcio <konradybcio@gmail.com> Signed-off-by: Rob Clark <robdclark@chromium.org>
2020-07-31drm/msm/mdp5: Add MDP5 configuration for SDM630Konrad Dybcio
This commit adds support for the MDP5 IP on Snapdragon 630. The configuration is different from SDM660's, as the latter one has two DSI outputs. Signed-off-by: Konrad Dybcio <konradybcio@gmail.com> Signed-off-by: Rob Clark <robdclark@chromium.org>
2020-07-31drm/msm/dsi: Add phy configuration for SDM630/636/660Konrad Dybcio
These SoCs make use of the 14nm phy, but at different addresses than other 14nm units. Signed-off-by: Konrad Dybcio <konradybcio@gmail.com> Signed-off-by: Rob Clark <robdclark@chromium.org>
2020-07-31drm/msm/a6xx: add A640/A650 hwcgJonathan Marek
Initialize hardware clock-gating registers on A640 and A650 GPUs. At least for A650, this solves some performance issues. Signed-off-by: Jonathan Marek <jonathan@marek.ca> Signed-off-by: Rob Clark <robdclark@chromium.org>
2020-07-31drm/msm/a6xx: hwcg tables in gpulistJonathan Marek
This will allow supporting different hwcg tables for a6xx. Signed-off-by: Jonathan Marek <jonathan@marek.ca> Signed-off-by: Rob Clark <robdclark@chromium.org>
2020-07-31drm/msm/dpu: add SM8250 to hw catalogJonathan Marek
This brings up basic video mode functionality for SM8250 DPU. Command mode and dual mixer/intf configurations are not working, future patches will address this. Scaler functionality and multiple planes is also untested. Signed-off-by: Jonathan Marek <jonathan@marek.ca> Signed-off-by: Rob Clark <robdclark@chromium.org>
2020-07-31drm/msm/dpu: add SM8150 to hw catalogJonathan Marek
This brings up basic video mode functionality for SM8150 DPU. Command mode and dual mixer/intf configurations are not working, future patches will address this. Scaler functionality and multiple planes is also untested. Signed-off-by: Jonathan Marek <jonathan@marek.ca> [fixup max_linewidth warning] Signed-off-by: Rob Clark <robdclark@chromium.org>
2020-07-31drm/msm/dpu: intf timing path for displayportJonathan Marek
Calculate the correct timings for displayport, from downstream driver. Signed-off-by: Jonathan Marek <jonathan@marek.ca> Signed-off-by: Rob Clark <robdclark@chromium.org>
2020-07-31drm/msm/dpu: set missing flush bits for INTF_2 and INTF_3Jonathan Marek
This fixes flushing of INTF_2 and INTF_3 on SM8150 and SM8250 hardware. Signed-off-by: Jonathan Marek <jonathan@marek.ca> Signed-off-by: Rob Clark <robdclark@chromium.org>
2020-07-31drm/msm/dpu: don't use INTF_INPUT_CTRL feature on sdm845Jonathan Marek
The INTF_INPUT_CTRL feature is not available on sdm845, so don't set it. This also adds separate feature bits for INTF (based on downstream) instead of using CTL feature bit for it, and removes the unnecessary NULL check in the added bind_pingpong_blk function. Fixes: 73bfb790ac786ca55fa2786a06f59 ("msm:disp:dpu1: setup display datapath for SC7180 target") Signed-off-by: Jonathan Marek <jonathan@marek.ca> Signed-off-by: Rob Clark <robdclark@chromium.org>
2020-07-31drm/msm/dpu: move some sspp caps to dpu_capsJonathan Marek
This isn't something that ever changes between planes, so move it to dpu_caps struct. Making this change will allow more re-use in the "SSPP sub blocks config" part of the catalog, in particular when adding support for SM8150 and SM8250 which have different max_linewidth. This also sets max_hdeci_exp/max_vdeci_exp to 0 for sc7180, as decimation is not supported on the newest DPU versions. (note that decimation is not implemented, so this changes nothing) Signed-off-by: Jonathan Marek <jonathan@marek.ca> Signed-off-by: Rob Clark <robdclark@chromium.org>
2020-07-31drm/msm/dpu: update UBWC config for sm8150 and sm8250Jonathan Marek
Update the UBWC registers to the right values for sm8150 and sm8250. This removes broken dpu_hw_reset_ubwc, which doesn't work because the "force blk offset to zero to access beginning of register region" hack is copied from downstream, where mapped region starts 0x1000 below what is used in the upstream driver. Also simplifies the overly complicated change that was introduced in e4f9bbe9f8beab9a1ce4 to work around dpu_hw_reset_ubwc being broken. Signed-off-by: Jonathan Marek <jonathan@marek.ca> Signed-off-by: Rob Clark <robdclark@chromium.org>
2020-07-31drm/msm/dpu: use right setup_blend_config for sm8150 and sm8250Jonathan Marek
All DPU versions starting from 4.0 use the sdm845 version, so check for that instead of checking each version individually. This chooses the right function for sm8150 and sm8250. Signed-off-by: Jonathan Marek <jonathan@marek.ca> Signed-off-by: Rob Clark <robdclark@chromium.org>
2020-07-31drm/msm/a6xx: set ubwc config for A640 and A650Jonathan Marek
This is required for A640 and A650 to be able to share UBWC-compressed images with other HW such as display, which expect this configuration. Signed-off-by: Jonathan Marek <jonathan@marek.ca> Reviewed-by: Jordan Crouse <jcrouse@codeaurora.org> Signed-off-by: Rob Clark <robdclark@chromium.org>
2020-07-31drm/msm/adreno: un-open-code some packetsRob Clark
Small cleanup, lets not open-code bits/bitfields that are properly defined in the rnndb xml (and therefore have builders in the generated headers) Signed-off-by: Rob Clark <robdclark@chromium.org> Reviewed-by: Jordan Crouse <jcrouse@codeaurora.org> Signed-off-by: Rob Clark <robdclark@chromium.org>
2020-07-31drm/msm: sync generated headersRob Clark
We haven't sync'd for a while.. pull in updates to get definitions for some fields in pkt7 payloads. Signed-off-by: Rob Clark <robdclark@chromium.org> Acked-by: Jordan Crouse <jcrouse@codeaurora.org> Signed-off-by: Rob Clark <robdclark@chromium.org>
2020-07-31drm/msm/a6xx: add build_bw_table for A640/A650Jonathan Marek
This sets up bw tables for A640/A650 similar to A618/A630, 0 DDR bandwidth vote, and the CNOC vote. A640 has the same CNOC addresses as A630 and was working, but this is required for A650 to work. Eventually the bw table should be filled by querying the interconnect driver for each BW in the dts, but use these dummy tables for now. Signed-off-by: Jonathan Marek <jonathan@marek.ca> Reviewed-by: Jordan Crouse <jcrouse@codeaurora.org> Signed-off-by: Rob Clark <robdclark@chromium.org>
2020-07-31drm/msm/a6xx: fix crashstate capture for A650Jonathan Marek
A650 has a separate RSCC region, so dump RSCC registers separately, reading them from the RSCC base. Without this change a GPU hang will cause a system reset if CONFIG_DEV_COREDUMP is enabled. Signed-off-by: Jonathan Marek <jonathan@marek.ca> Reviewed-by: Jordan Crouse <jcrouse@codeaurora.org> Signed-off-by: Rob Clark <robdclark@chromium.org>
2020-07-31drm/msm: Quiet error during failure in optional resource mappings.Eric Anholt
We don't expect to find vbif_nrt or regdma on sdm845, but were clogging up dmesg with errors about it. Signed-off-by: Eric Anholt <eric@anholt.net> Reported-by: kernel test robot <lkp@intel.com> Signed-off-by: Rob Clark <robdclark@chromium.org>
2020-07-31drm/msm: Garbage collect unused resource _len fields.Eric Anholt
Nothing was using the lengths of these ioremaps. Signed-off-by: Eric Anholt <eric@anholt.net> Signed-off-by: Rob Clark <robdclark@chromium.org>
2020-07-31drm/msm/dpu: fix/enable 6bpc dither with split-lmRob Clark
If split-lm is used (for ex, on sdm845), we can have multiple ping- pongs, but only a single phys encoder. We need to configure dithering on each of them. Signed-off-by: Rob Clark <robdclark@chromium.org> Tested-by: Steev Klimaszewski <steev@kali.org> Reviewed-by: Kalyan Thota <kalyan_t@codeaurora.org> Signed-off-by: Rob Clark <robdclark@chromium.org>
2020-07-31drm: msm: a6xx: fix gpu failure after system resumeAkhil P Oommen
On targets where GMU is available, GMU takes over the ownership of GX GDSC during its initialization. So, move the refcount-get on GX PD before we initialize the GMU. This ensures that nobody can collapse the GX GDSC once GMU owns the GX GDSC. This patch fixes some GMU OOB errors seen during GPU wake up during a system resume. Reported-by: Matthias Kaehlcke <mka@chromium.org> Signed-off-by: Akhil P Oommen <akhilpo@codeaurora.org> Tested-by: Matthias Kaehlcke <mka@chromium.org> Reviewed-by: Jordan Crouse <jcrouse@codeaurora.org> Signed-off-by: Rob Clark <robdclark@chromium.org>
2020-07-31drm/msm: dsi: Use OPP API to set clk/perf stateRajendra Nayak
On SDM845 and SC7180 DSI needs to express a performance state requirement on a power domain depending on the clock rates. Use OPP table from DT to register with OPP framework and use dev_pm_opp_set_rate() to set the clk/perf state. dev_pm_opp_set_rate() is designed to be equivalent to clk_set_rate() for devices without an OPP table, hence the change works fine on devices/platforms which only need to set a clock rate. Signed-off-by: Rajendra Nayak <rnayak@codeaurora.org> Reviewed-by: Matthias Kaehlcke <mka@chromium.org> Signed-off-by: Rob Clark <robdclark@chromium.org>
2020-07-31drm/msm/dpu: Use OPP API to set clk/perf stateRajendra Nayak
On some qualcomm platforms DPU needs to express a performance state requirement on a power domain depending on the clock rates. Use OPP table from DT to register with OPP framework and use dev_pm_opp_set_rate() to set the clk/perf state. Signed-off-by: Rajendra Nayak <rnayak@codeaurora.org> Reviewed-by: Rob Clark <robdclark@chromium.org> Reviewed-by: Matthias Kaehlcke <mka@chromium.org> Signed-off-by: Rob Clark <robdclark@chromium.org>
2020-07-31drm/msm: ratelimit crtc event overflow errorRob Clark
This can happen a lot when things go pear shaped. Lets not flood dmesg when this happens. Signed-off-by: Rob Clark <robdclark@chromium.org> Reviewed-by: Abhinav Kumar <abhinavk@codeaurora.org> Signed-off-by: Rob Clark <robdclark@chromium.org>
2020-07-31drm: msm: a6xx: send opp instead of a frequencySharat Masetty
This patch changes the plumbing to send the devfreq recommended opp rather than the frequency. Also consolidate and rearrange the code in a6xx to set the GPU frequency and the icc vote in preparation for the upcoming changes for GPU->DDR scaling votes. Signed-off-by: Sharat Masetty <smasetty@codeaurora.org> Signed-off-by: Akhil P Oommen <akhilpo@codeaurora.org> Signed-off-by: Rob Clark <robdclark@chromium.org>
2020-07-31drm/msm: Fix a null pointer access in msm_gem_shrinker_count()Akhil P Oommen
Adding an msm_gem_object object to the inactive_list before completing its initialization is a bad idea because shrinker may pick it up from the inactive_list. Fix this by making sure that the initialization is complete before moving the msm_obj object to the inactive list. This patch fixes the below error: [10027.553044] Unable to handle kernel NULL pointer dereference at virtual address 0000000000000068 [10027.573305] Mem abort info: [10027.590160] ESR = 0x96000006 [10027.597905] EC = 0x25: DABT (current EL), IL = 32 bits [10027.614430] SET = 0, FnV = 0 [10027.624427] EA = 0, S1PTW = 0 [10027.632722] Data abort info: [10027.638039] ISV = 0, ISS = 0x00000006 [10027.647459] CM = 0, WnR = 0 [10027.654345] user pgtable: 4k pages, 39-bit VAs, pgdp=00000001e3a6a000 [10027.672681] [0000000000000068] pgd=0000000198c31003, pud=0000000198c31003, pmd=0000000000000000 [10027.693900] Internal error: Oops: 96000006 [#1] PREEMPT SMP [10027.738261] CPU: 3 PID: 214 Comm: kswapd0 Tainted: G S 5.4.40 #1 [10027.745766] Hardware name: Qualcomm Technologies, Inc. SC7180 IDP (DT) [10027.752472] pstate: 80c00009 (Nzcv daif +PAN +UAO) [10027.757409] pc : mutex_is_locked+0x14/0x2c [10027.761626] lr : msm_gem_shrinker_count+0x70/0xec [10027.766454] sp : ffffffc011323ad0 [10027.769867] x29: ffffffc011323ad0 x28: ffffffe677e4b878 [10027.775324] x27: 0000000000000cc0 x26: 0000000000000000 [10027.780783] x25: ffffff817114a708 x24: 0000000000000008 [10027.786242] x23: ffffff8023ab7170 x22: 0000000000000001 [10027.791701] x21: ffffff817114a080 x20: 0000000000000119 [10027.797160] x19: 0000000000000068 x18: 00000000000003bc [10027.802621] x17: 0000000004a34210 x16: 00000000000000c0 [10027.808083] x15: 0000000000000000 x14: 0000000000000000 [10027.813542] x13: ffffffe677e0a3c0 x12: 0000000000000000 [10027.819000] x11: 0000000000000000 x10: ffffff8174b94340 [10027.824461] x9 : 0000000000000000 x8 : 0000000000000000 [10027.829919] x7 : 00000000000001fc x6 : ffffffc011323c88 [10027.835373] x5 : 0000000000000001 x4 : ffffffc011323d80 [10027.840832] x3 : ffffffff0477b348 x2 : 0000000000000000 [10027.846290] x1 : ffffffc011323b68 x0 : 0000000000000068 [10027.851748] Call trace: [10027.854264] mutex_is_locked+0x14/0x2c [10027.858121] msm_gem_shrinker_count+0x70/0xec [10027.862603] shrink_slab+0xc0/0x4b4 [10027.866187] shrink_node+0x4a8/0x818 [10027.869860] kswapd+0x624/0x890 [10027.873097] kthread+0x11c/0x12c [10027.876424] ret_from_fork+0x10/0x18 [10027.880102] Code: f9000bf3 910003fd aa0003f3 d503201f (f9400268) [10027.886362] ---[ end trace df5849a1a3543251 ]--- [10027.891518] Kernel panic - not syncing: Fatal exception Signed-off-by: Akhil P Oommen <akhilpo@codeaurora.org> Signed-off-by: Rob Clark <robdclark@chromium.org>
2020-07-31drm/msm/dpu: add support for dither block in displayKalyan Thota
This change enables dither block for primary interface in display. Enabled for 6bpc in the current version. Changes in v1: - Remove redundant error checks (Rob). Signed-off-by: Kalyan Thota <kalyan_t@codeaurora.org> Tested-by: Douglas Anderson <dianders@chromium.org> Tested-by: Kristian H. Kristensen <hoegsberg@google.com> Signed-off-by: Rob Clark <robdclark@chromium.org>
2020-07-31drm/msm/adreno: fix gpu probe if no interconnect-namesRob Clark
If there is no interconnect-names, but there is an interconnects property, then of_icc_get(dev, "gfx-mem"); would return an error rather than NULL. Also, if there is no interconnect-names property, there will never be a ocmem path. But of_icc_get(dev, "ocmem") would return -EINVAL instead of -ENODATA. Just don't bother trying in this case. v2: explicity check for interconnect-names property Fixes: 08af4769c7d2 ("drm/msm: handle for EPROBE_DEFER for of_icc_get") Fixes: 00bb9243d346 ("drm/msm/gpu: add support for ocmem interconnect path") Signed-off-by: Rob Clark <robdclark@chromium.org> Reviewed-by: Jordan Crouse <jcrouse@codeaurora.org> Signed-off-by: Rob Clark <robdclark@chromium.org>
2020-07-31staging: android: ashmem: Fix lockdep warning for write operationSuren Baghdasaryan
syzbot report [1] describes a deadlock when write operation against an ashmem fd executed at the time when ashmem is shrinking its cache results in the following lock sequence: Possible unsafe locking scenario: CPU0 CPU1 ---- ---- lock(fs_reclaim); lock(&sb->s_type->i_mutex_key#13); lock(fs_reclaim); lock(&sb->s_type->i_mutex_key#13); kswapd takes fs_reclaim and then inode_lock while generic_perform_write takes inode_lock and then fs_reclaim. However ashmem does not support writing into backing shmem with a write syscall. The only way to change its content is to mmap it and operate on mapped memory. Therefore the race that lockdep is warning about is not valid. Resolve this by introducing a separate lockdep class for the backing shmem inodes. [1]: https://lkml.kernel.org/lkml/0000000000000b5f9d059aa2037f@google.com/ Reported-by: syzbot+7a0d9d0b26efefe61780@syzkaller.appspotmail.com Signed-off-by: Suren Baghdasaryan <surenb@google.com> Cc: stable <stable@vger.kernel.org> Reviewed-by: Joel Fernandes (Google) <joel@joelfernandes.org> Link: https://lore.kernel.org/r/20200730192632.3088194-1-surenb@google.com Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
2020-07-31drivers: most: add USB adapter driverChristian Gromm
This patch adds the USB driver source file most_usb.c and modifies the Makefile and Kconfig accordingly. Signed-off-by: Christian Gromm <christian.gromm@microchip.com> Link: https://lore.kernel.org/r/1596198058-26541-1-git-send-email-christian.gromm@microchip.com Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
2020-07-31power: supply: wilco_ec: Add long life charging modeCrag Wang
This is a long life mode set in the factory for extended warranty battery, the power charging rate is customized so that battery at work last longer. Presently switching to a different battery charging mode is through EC PID 0x0710 to configure the battery firmware, this operation will be blocked by EC with failure code 0x01 when PLL mode is already in use. Signed-off-by: Crag Wang <crag.wang@dell.com> Reviewed-by: Mario Limonciello <mario.limonciello@dell.com> Signed-off-by: Sebastian Reichel <sebastian.reichel@collabora.com>
2020-07-31cpuidle: ACPI: fix 'return' with no value build warningNeal Liu
Add return value to fix return-type build warning introduced by commit efe9711214e6 ("cpuidle: change enter_s2idle() prototype"). Fixes: efe9711214e6 ("cpuidle: change enter_s2idle() prototype") Signed-off-by: Neal Liu <neal.liu@mediatek.com> [ rjw: Subject & changelog edits, make acpi_idle_enter_s2idle() return 0 in all cases ] Signed-off-by: Rafael J. Wysocki <rafael.j.wysocki@intel.com>
2020-07-31platform/chrome: cros_ec_proto: check for missing ↵Brian Norris
EC_CMD_HOST_EVENT_GET_WAKE_MASK As with cros_ec_cmd_xfer_status(), etc., it's not enough to simply check for the return status of send_command() -- that only covers transport or other similarly-fatal errors. One must also check the ->result field, to see whether the command really succeeded. If not, we can't use the data it returns. The caller of cros_ec_get_host_event_wake_mask() ignores this, and so for example, on EC's where the command is not implemented, we're using junk (or in practice, all zeros) for our wake-mask. We should be using a non-zero default (currently, it's supposed to be all-1's). Fix this by checking the ->result field and returning -EPROTO for errors. I might label this as fixing commit 29d99b966d60 ("cros_ec: Don't signal wake event for non-wake host events"), except that this fix alone actually may make things worse, as it now allows for a lot more spurious wakeups. The patch "platform/chrome: cros_ec_proto: ignore battery/AC wakeups on old ECs" helps to mitigate this. Signed-off-by: Brian Norris <briannorris@chromium.org> Signed-off-by: Enric Balletbo i Serra <enric.balletbo@collabora.com>
2020-07-31platform/chrome: cros_ec_proto: ignore unnecessary wakeups on old ECsBrian Norris
ECs that don't implement EC_CMD_HOST_EVENT_GET_WAKE_MASK should still have some reasonable default mask -- otherwise, they'll treat a variety of EC signals as spurious wakeups. Battery and AC events can be especially common, for devices that have been sitting at full charge plugged into AC for a long time, as they may cycle their charging off and on, or their battery may start reporting failures as it ages. Treating these as wakeups does not serve a useful purpose, and is instead often counterproductive. And indeed, later ECs (that implement the mask) don't include these events in their wake-mask. Note that this patch doesn't do anything without the subsequent patch ("platform/chrome: cros_ec_proto: check for missing EC_CMD_HOST_EVENT_GET_WAKE_MASK"), because cros_ec_get_host_event_wake_mask() currently does not return an error if EC_CMD_HOST_EVENT_GET_WAKE_MASK is not implemented. Some additional notes: While the EC typically knows not to wake the CPU for these unimportant events once the CPU reaches a sleep state, it doesn't really have a way to know that the CPU is "almost" asleep, unless it has support for EC_CMD_HOST_SLEEP_EVENT. Alas, these older ECs do not support that command either, so this solution is not 100% complete. Signed-off-by: Brian Norris <briannorris@chromium.org> Signed-off-by: Enric Balletbo i Serra <enric.balletbo@collabora.com>
2020-07-31platform/chrome: cros_ec_sensorhub: Simplify legacy timestamp spreadingGwendal Grignou
On some machines (nami), interrupt latency cause samples to appear to be from the future and are pegged to the current time. We would see samples with this pattern: [t, t + ~5ms, t + ~10ms, t + ~10ms + 100us, t + ~10ms + 200us], (current now) (current now) (t is the last timestamp time) Last 2 samples would be barely spread, causing applications to complain. We now spread the entire sequence. This is not great: in the example the sensor was supposed to send samples every 5ms, it now appears to send one every 2.5ms, but it is slightly closer to reality: sampling time in the example above At sensor level 1 2 3 4 5 +-----5ms-----+-----5ms-----+-----5ms-----+----5ms-----+---> t Before, at host level 1 2 3 4 5 --interrupt delay------+-----5ms-----+-----5ms-----+-+-+---> t Afer, at host level 1 2 3 4 5 --interrupt delay------+-2.5ms-+-2.5ms-+-2.5ms-+-2.5ms-+---> t Signed-off-by: Gwendal Grignou <gwendal@chromium.org> Signed-off-by: Enric Balletbo i Serra <enric.balletbo@collabora.com>
2020-07-31drm: re-add deleted doc for drm_gem_open_ioctlSteve Cohen
Add back the removed documentation for drm_gem_open_ioctl. This patch is submitted in response to [1]. [1] https://lore.kernel.org/linux-arm-msm/20200728085244.GY6419@phenom.ffwll.local/ Signed-off-by: Steve Cohen <cohens@codeaurora.org> Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch> Link: https://patchwork.freedesktop.org/patch/msgid/1596000952-27621-1-git-send-email-cohens@codeaurora.org
2020-07-31Merge tag 'qcom-drivers-for-5.9-2' of ↵Arnd Bergmann
git://git.kernel.org/pub/scm/linux/kernel/git/qcom/linux into arm/drivers Qualcomm driver additional updates for 5.9 This fixes a potential race condition with remoteprocs by not sending acknowledgements until after registered drivers has processed the event. It adds IPQ6018 support to the SMD RPM driver, fixes kerneldoc in the same and converts the related DT binding to YAML. Finally it fixes a compilation warning in the geni serial engine driver when compiled without CONFIG_SERIAL_EARLYCON. * tag 'qcom-drivers-for-5.9-2' of git://git.kernel.org/pub/scm/linux/kernel/git/qcom/linux: soc: qcom: geni: Fix unused label warning soc: qcom: smd-rpm: Fix kerneldoc soc: qcom: pdr: Reorder the PD state indication ack dt-bindings: soc: qcom: smd-rpm: Convert binding to YAML schema soc: qcom: smd-rpm: Add IPQ6018 compatible dt-bindings: soc: qcom: smd-rpm: Add IPQ6018 compatible Link: https://lore.kernel.org/r/20200730051852.649761-1-bjorn.andersson@linaro.org Signed-off-by: Arnd Bergmann <arnd@arndb.de>
2020-07-31Merge tag 'memory-controller-drv-5.9-2' of ↵Arnd Bergmann
git://git.kernel.org/pub/scm/linux/kernel/git/krzk/linux-mem-ctrl into arm/drivers Memory controller drivers for v5.9, part 2 1. Minor cleanups and fixes of multiple memory controller drivers, mostly around code quality and readability, 2. Add Git repository to drivers/memory entry in MAINTAINERS, 3. Allow MIPS jz4780 FUSE driver to probe by removing conflicting memory region with jz4780_nemc. * tag 'memory-controller-drv-5.9-2' of git://git.kernel.org/pub/scm/linux/kernel/git/krzk/linux-mem-ctrl: memory: jz4780_nemc: Only request IO memory the driver will use MAINTAINERS: Add Git repository for memory controller drivers memory: brcmstb_dpfe: Fix language typo memory: samsung: exynos5422-dmc: Correct white space issues memory: samsung: exynos-srom: Correct alignment memory: pl172: Enclose macro argument usage in parenthesis memory: of: Correct kerneldoc memory: omap-gpmc: Fix language typo memory: omap-gpmc: Correct white space issues memory: omap-gpmc: Use 'unsigned int' for consistency memory: omap-gpmc: Enclose macro argument usage in parenthesis memory: omap-gpmc: Correct kerneldoc memory: mvebu-devbus: Align with open parenthesis memory: mvebu-devbus: Add missing braces to all arms of if statement memory: bt1-l2-ctl: Add blank lines after declarations Link: https://lore.kernel.org/r/20200729163008.5820-1-krzk@kernel.org Signed-off-by: Arnd Bergmann <arnd@arndb.de>
2020-07-31crypto: sa2ul - Fix inconsistent IS_ERR and PTR_ERRGustavo A. R. Silva
Fix inconsistent IS_ERR and PTR_ERR in sa_dma_init(). The proper pointer to be passed as argument to PTR_ERR() is dd->dma_tx. This bug was detected with the help of Coccinelle. Fixes: 7694b6ca649f ("crypto: sa2ul - Add crypto driver") Signed-off-by: Gustavo A. R. Silva <gustavoars@kernel.org> Signed-off-by: Herbert Xu <herbert@gondor.apana.org.au>
2020-07-31hwrng: core - remove redundant initialization of variable retColin Ian King
The variable ret is being initialized with a value that is never read and it is being updated later with a new value. The initialization is redundant and can be removed. Addresses-Coverity: ("Unused value") Signed-off-by: Colin Ian King <colin.king@canonical.com> Signed-off-by: Herbert Xu <herbert@gondor.apana.org.au>
2020-07-31crypto: ingenic - Add hardware RNG for Ingenic JZ4780 and X1000周琰杰 (Zhou Yanjie)
Add JZ4780 SoC and X1000 SoC random number generator driver, based on PrasannaKumar Muralidharan's JZ4780 RNG driver. Tested-by: 周正 (Zhou Zheng) <sernia.zhou@foxmail.com> Tested-by: Mathieu Malaterre <malat@debian.org> Suggested-by: Jeffrey Walton <noloader@gmail.com> Signed-off-by: PrasannaKumar Muralidharan <prasannatsmkumar@gmail.com> Signed-off-by: 周琰杰 (Zhou Yanjie) <zhouyanjie@wanyeetech.com> Signed-off-by: Herbert Xu <herbert@gondor.apana.org.au>
2020-07-31crypto: caam/qi2 - add module aliasHoria Geantă
Add a module alias, to enable udev-based module autoloading: $ modinfo -F alias drivers/crypto/caam/dpaa2_caam.ko fsl-mc:v00001957ddpseci Signed-off-by: Horia Geantă <horia.geanta@nxp.com> Signed-off-by: Herbert Xu <herbert@gondor.apana.org.au>
2020-07-31crypto: caam - add more RNG hw error codesHoria Geantă
In some cases, e.g. when TRNG is not properly configured, the RNG module could issue a "Hardware error" at runtime. "Continuos check" error is emitted when some of the BISTs fail. Signed-off-by: Horia Geantă <horia.geanta@nxp.com> Signed-off-by: Herbert Xu <herbert@gondor.apana.org.au>
2020-07-31crypto: caam/jr - remove incorrect reference to caam_jr_register()Dan Douglass
caam_jr_register() function is no longer part of the driver since commit 6dad41158db6 ("crypto: caam - Remove unused functions from Job Ring") This patch removes a comment referencing the function. Signed-off-by: Dan Douglass <dan.douglass@nxp.com> Signed-off-by: Horia Geantă <horia.geanta@nxp.com> Signed-off-by: Herbert Xu <herbert@gondor.apana.org.au>
2020-07-31crypto: caam - silence .setkey in case of bad key lengthHoria Geantă
In case of bad key length, driver emits "key size mismatch" messages, but only for xts(aes) algorithms. Reduce verbosity by making them visible only when debugging. This way crypto fuzz testing log cleans up a bit. Signed-off-by: Horia Geantă <horia.geanta@nxp.com> Signed-off-by: Herbert Xu <herbert@gondor.apana.org.au>
2020-07-31crypto: caam/qi2 - create ahash shared descriptors only onceHoria Geantă
For keyed hash algorithms, shared descriptors are currently generated twice: -at tfm initialization time, in cra_init() callback -in setkey() callback Since it's mandatory to call setkey() for keyed algorithms, drop the generation in cra_init(). This is similar to the change in caamhash (caam/jr top-level library) commit 9a2537d0ebc9 ("crypto: caam - create ahash shared descriptors only once") Signed-off-by: Horia Geantă <horia.geanta@nxp.com> Signed-off-by: Herbert Xu <herbert@gondor.apana.org.au>
2020-07-31crypto: caam/qi2 - fix error reporting for caam_hash_allocHoria Geantă
Fix error reporting when preparation of an hmac algorithm for registration fails: print the hmac algorithm name, not the unkeyed hash algorithm name. Signed-off-by: Horia Geantă <horia.geanta@nxp.com> Signed-off-by: Herbert Xu <herbert@gondor.apana.org.au>
2020-07-31crypto: caam - remove deadcode on 32-bit platformsFranck LENORMAND
When building on a platform with a 32bit DMA address, taking the upper 32 bits makes no sense. Signed-off-by: Franck LENORMAND <franck.lenormand@nxp.com> Signed-off-by: Horia Geantă <horia.geanta@nxp.com> Signed-off-by: Herbert Xu <herbert@gondor.apana.org.au>
2020-07-31crypto: ccp - use generic power managementVaibhav Gupta
Drivers using legacy power management .suspen()/.resume() callbacks have to manage PCI states and device's PM states themselves. They also need to take care of standard configuration registers. Switch to generic power management framework using a single "struct dev_pm_ops" variable to take the unnecessary load from the driver. This also avoids the need for the driver to directly call most of the PCI helper functions and device power state control functions as through the generic framework, PCI Core takes care of the necessary operations, and drivers are required to do only device-specific jobs. Signed-off-by: Vaibhav Gupta <vaibhavgupta40@gmail.com> Acked-by: John Allen <john.allen@amd.com> Signed-off-by: Herbert Xu <herbert@gondor.apana.org.au>
generated by cgit (git 2.34.1) at 2025-09-13 23:20:34 +0000