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2012-03-13xHCI: count free TRBs on transfer ringAndiry Xu
In the past, the room_on_ring() check was implemented by walking all over the ring, which is wasteful and complicated. Count the number of free TRBs instead. The free TRBs number should be updated when enqueue/dequeue pointer is updated, or upon the completion of a set dequeue pointer command. Signed-off-by: Andiry Xu <andiry.xu@amd.com> Signed-off-by: Sarah Sharp <sarah.a.sharp@linux.intel.com> Tested-by: Paul Zimmerman <Paul.Zimmerman@synopsys.com>
2012-03-13xHCI: store ring's last segment and segment numbersAndiry Xu
Store the ring's last segment pointer and number of segments for ring expansion usage. Signed-off-by: Andiry Xu <andiry.xu@amd.com> Signed-off-by: Sarah Sharp <sarah.a.sharp@linux.intel.com> Tested-by: Paul Zimmerman <Paul.Zimmerman@synopsys.com>
2012-03-13OMAPDSS: APPLY: fix clearing shadow dirty flag with manual updateTomi Valkeinen
Currently the shadow-dirty flags for manual update displays is cleared in the apply_irq_handler when an update has finished. This is not correct, as the shadow registers are taken into use (i.e. after that they are not dirty) when the update is started. Move the mgr_clear_shadow_dirty() call from apply_irq_handler to dss_mgr_start_update() to fix this. Signed-off-by: Tomi Valkeinen <tomi.valkeinen@ti.com>
2012-03-13ath6kl: fix debug.c file modeKalle Valo
Commit 7504a3e1 ("ath6kl: add padding to firmware log records") accidentally changed debug.c mode from 100644 to 100755. Revert that back to original. Signed-off-by: Kalle Valo <kvalo@qca.qualcomm.com>
2012-03-13ath6kl: use max_t() in ath6kl_cfg80211_connect()Kalle Valo
ath6kl/cfg80211.c:589: WARNING: max() should probably be max_t(u16, vif->listen_intvl_t, ATH6KL_MAX_WOW_LISTEN_INTL) Signed-off-by: Kalle Valo <kvalo@qca.qualcomm.com>
2012-03-13ath6kl: fix open parenthesis alignment in ath6kl_sdio_suspend()Kalle Valo
ath6kl/sdio.c:875: CHECK: Alignment should match open parenthesis Signed-off-by: Kalle Valo <kvalo@qca.qualcomm.com>
2012-03-13ath6kl: replace strict_strtoul() with kstrtoul()Kalle Valo
Recommended by checkpatch. Signed-off-by: Kalle Valo <kvalo@qca.qualcomm.com>
2012-03-13ath6kl: fix regression in ath6kl_upload_board_file()Kalle Valo
My patch 24fc32b3 ("ath6kl: add ath6kl_bmi_write_hi32()") caused a regression in ath6kl_upload_board_file() and the board_address variable was not properly initialised in some cases: ath6kl/init.c:1068:6: warning: ‘board_address’ may be used uninitialized in this function Most likely this broke ar6004 support but I can't test that right now. Signed-off-by: Kalle Valo <kvalo@qca.qualcomm.com>
2012-03-13hwmon: (w83627ehf) Fix temp2 source for W83627UHGJean Delvare
Properly set the source of temp2 for the W83627UHG. Also fix a comment right before that, and document the W83627UHG as reporting up to 3 temperatures. Signed-off-by: Jean Delvare <khali@linux-fr.org> Cc: Guenter Roeck <guenter.roeck@ericsson.com> Cc: stable@vger.kernel.org Signed-off-by: Guenter Roeck <guenter.roeck@ericsson.com>
2012-03-13iommu/tegra-gart: fix spin_unlock in map failure pathLucas Stach
This must have been messed up while merging, the intention was clearly to unlock there. Signed-off-by: Lucas Stach <dev@lynxeye.de> Signed-off-by: Joerg Roedel <joerg.roedel@amd.com>
2012-03-13HID: tivo: add support for BT-version (0x1200)Jiri Kosina
Add support for BT-driven configuration of the TiVo remote. Reported-by: Joshua Dillon <jvdillon@gmail.com> Signed-off-by: Jiri Kosina <jkosina@suse.cz>
2012-03-13drm/nouveau: map first page of mmio early and determine chipset earlierBen Skeggs
Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2012-03-13drm/nvd0/disp: disconnect encoders before reprogramming themBen Skeggs
Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2012-03-13drm/nvd0/disp: move syncs/magic setup to or mode_setBen Skeggs
NVIDIA appear to do these around the same place they do the MODE_CTRL methods, and for DP at least we need to bash some extra bits in "syncs" to keep EVO happy. It's a bit of a guess as to the 6/8bpc, but i have no better idea yet. Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2012-03-13drm/nouveau/dp: account for channel coding overhead in link trainingBen Skeggs
Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2012-03-13drm/nvd0/disp: fix dcb sor link matching in supervisor handlerBen Skeggs
Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2012-03-13drm/nvd0/disp: initial implementation of displayportBen Skeggs
Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2012-03-13drm/nouveau/dp: make dp dpms function common, call from sor code insteadBen Skeggs
GF119 will use this too. Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2012-03-13drm/nv50/hwsq: some nv92 fixesMartin Peres
The shift from hwsq_data = 0x1400 to 0x080000 actually happened in nv94, not nv92 This fixes some reclocking issues on my newly acquired nv92 Signed-off-by: Martin Peres <martin.peres@labri.fr> Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2012-03-13drm/nouveau/dp: move all nv50/sor-specific code out of nouveau_dp.cBen Skeggs
Off-chip encoders (which we don't support yet anyway), and newer chipsets (such as NVD9...), will need their own code for this. Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2012-03-13drm/nouveau/dp: make functions for executing various bios tablesBen Skeggs
More code to do the same thing, but will make it easier to handle various changes that could possibly happen the the VBIOS tables. Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2012-03-13drm/nouveau/pm: fix oops if chipset has no pm support at allBen Skeggs
Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2012-03-13drm/nouveau/bios: rework vbios shadowingBen Skeggs
Refactored to allow shadowing of VBIOS images longer than 64KiB, which allows us to pass the VBIOS checksum test on certain boards. There's also a workaround for reading the PROM VBIOS on some chipsets. Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2012-03-13drm/nouveau/bios: attempt acpi rom fetch before pciromBen Skeggs
There's cards out there with completely messed up PCIROM images that have a perfectly valid signature.. Sigh! Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2012-03-13drm/nvd0/disp: attempt to handle more than 2 crtcs if possibleBen Skeggs
Theoretically handles CRTC2/CRTC3, should any GF119 out there actually have them enabled. The room is there for the regs etc, so why not :) Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2012-03-13drm/nvc0/vram: get part count from PUNITSBen Skeggs
Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2012-03-13drm/nv40/pm: fix fanspeed regressionBen Skeggs
Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2012-03-13drm/nouveau/pm: several fixes for nvc0 memory timingsRoy Spliet
This patch fixes two small issues in timing generation as spotted on several NVCx cards. In addition, the header of the file is updated to also contain (some of) the current developers of this code. Signed-off-by: Roy Spliet <r.spliet@student.tudelft.nl> Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2012-03-13drm/nvc0/pm: restrict pll mode to clocks that can actually use itBen Skeggs
Fixes reclocking failure on some chips where we attempted to set PDAEMON to PLL mode. Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2012-03-13drm/nouveau/dp: fix bad comparison in dp_link_train_commit()Xi Wang
The comparison (lpre == DP_TRAIN_PRE_EMPHASIS_9_5) is always false: lpre is initialized as (lane & 0x0c) >> 2, which is at most 3, while DP_TRAIN_PRE_EMPHASIS_9_5 is defined as (3 << 3). Signed-off-by: Xi Wang <xi.wang@gmail.com> Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2012-03-13drm/nouveau/mxm: call mxmi to determine revision before calling mxmsBen Skeggs
There's a HP laptop out there where the MXM version in the VBIOS doesn't match what the ACPI implementation is expecting. These tables will accept 0x00 to MXMS to return latest version, but *only* if MXMI has been called first.. Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2012-03-13drm/nouveau/pm: init only after display subsystem has been createdBen Skeggs
This patch fixes an oops cause by pm_trigger accessing the (uninitialised) crtc list. Reported-by: Roy Spliet <r.spliet@student.tudelft.nl> Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2012-03-13drm/nvc0/fb: detect presense of second rankBen Skeggs
Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2012-03-13drm/nv50/display: expose color vibrance controlChristoph Bumiller
Signed-off-by: Christoph Bumiller <e0425955@student.tuwien.ac.at> Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2012-03-13drm/nv50-nvc0/vm: support unsnooped system memoryBen Skeggs
v2 (Emil Velikov <emil.l.velikov@gmail.com>): - Fixed a regression on certain nv50 IGP due to not passing the correct target type to nv50_vm_addr() Signed-off-by: Ben Skeggs <bskeggs@redhat.com> Signed-off-by: Emil Velikov <emil.l.velikov@gmail.com> Tested-by: Johannes Obermayr <johannesobermayr@gmx.de>
2012-03-13drm/nouveau: recognise DCB connector type for DP+DVI+VGA DMS-59Ben Skeggs
Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2012-03-13drm/nouveau/mem: handle dll_off for ddr2/ddr3Ben Skeggs
Signed-off-by: Ben Skeggs <bskeggs@redhat.com> Signed-off-by: Martin Peres <martin.peres@labri.fr>
2012-03-13drm/nouveau/pm: extend profile interface for destroy/init/finiBen Skeggs
Signed-off-by: Ben Skeggs <bskeggs@redhat.com> Signed-off-by: Martin Peres <martin.peres@labri.fr>
2012-03-13drm/nouveau/pm: rework to allow selecting separate profiles for ac/batteryBen Skeggs
Signed-off-by: Ben Skeggs <bskeggs@redhat.com> Signed-off-by: Martin Peres <martin.peres@labri.fr>
2012-03-13drm/nouveau/pm: fix dll off -> dll on transitionsBen Skeggs
Signed-off-by: Ben Skeggs <bskeggs@redhat.com> Signed-off-by: Martin Peres <martin.peres@labri.fr>
2012-03-13drm/nouveau/pm: detect when we need dll disabled for gddr3Ben Skeggs
Fixes minor flickering on NVS295 when at perflvl 0. Signed-off-by: Ben Skeggs <bskeggs@redhat.com> Signed-off-by: Martin Peres <martin.peres@labri.fr>
2012-03-13drm/nv50: fix detection of second vram rankBen Skeggs
Goes a long way to correcting NVS295 memory reclocking issues. Signed-off-by: Ben Skeggs <bskeggs@redhat.com> Signed-off-by: Martin Peres <martin.peres@labri.fr>
2012-03-13drm/nouveau/pm: track mr2 for gddr3Ben Skeggs
There's some "extended" GDDR3 chipsets out there with EMRS2 settings that change the layout of MRS/EMRS1 bitmaps.. Sigh.. Still need to track down how exactly we're supposed to handle this. Signed-off-by: Ben Skeggs <bskeggs@redhat.com> Signed-off-by: Martin Peres <martin.peres@labri.fr>
2012-03-13drm/nv50/pm: wait for all fifo-connected engines to idle before reclockingMartin Peres
Signed-off-by: Martin Peres <martin.peres@labri.fr> Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2012-03-13drm/nv50/pm: use hwsq for engine reclocking tooBen Skeggs
Idea from Martin Peres, different implementation by me. v2: Martin Peres: - fix mast calculation Signed-off-by: Ben Skeggs <bskeggs@redhat.com> Signed-off-by: Martin Peres <martin.peres@labri.fr>
2012-03-13drm/nv50/disp: more accurate function to determine active crtcsBen Skeggs
Signed-off-by: Ben Skeggs <bskeggs@redhat.com> Signed-off-by: Martin Peres <martin.peres@labri.fr>
2012-03-13drm/nv50/pm: initial work towards proper memory reclocking, with timingsBen Skeggs
Signed-off-by: Ben Skeggs <bskeggs@redhat.com> Signed-off-by: Martin Peres <martin.peres@labri.fr>
2012-03-13drm/nouveau/pm: introduce ram reclocking helperBen Skeggs
This will probably result in more lines of code, however, we're going to have at least 3 slightly different implementations of this very soon and I'd rather keep the ram reclocking logic separate from the hw specifics. DDR2/DDR3/GDDR3 implemented thus far, others will be added as necessary. Signed-off-by: Ben Skeggs <bskeggs@redhat.com> Signed-off-by: Martin Peres <martin.peres@labri.fr>
2012-03-13drm/nouveau/pm: embed timings into perflvl structsBen Skeggs
Signed-off-by: Ben Skeggs <bskeggs@redhat.com> Signed-off-by: Martin Peres <martin.peres@labri.fr>
2012-03-13drm/nouveau/pm: calculate memory timings at perflvl creation timeBen Skeggs
Statically generating the PFB register and MR values for each timing set turns out to be insufficient. There's at least one (so far) known piece of information which effects MR values which is stored in the perflvl entry on some chipsets (and in another table on later ones), which is disconnected from the timing table entries. After this change we will generate a timing set based on an input clock frequency instead, and have this data stored in the performance level data. Signed-off-by: Ben Skeggs <bskeggs@redhat.com> Signed-off-by: Martin Peres <martin.peres@labri.fr>
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