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2018-10-16drm/i915: Remove crtc->config dereferences in intel_modeset_setup_hw_stateMaarten Lankhorst
The CRTC is idle at this point, so we can dereference crtc->state safely. Signed-off-by: Maarten Lankhorst <maarten.lankhorst@linux.intel.com> [mlankhorst: Keep dev_priv->drm in for_each_intel_crtc (Ville)] Reviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20181011100457.8776-8-maarten.lankhorst@linux.intel.com
2018-10-16drm/i915: Remove crtc->config dereferences in intel_sanitize_crtcMaarten Lankhorst
We know the crtc is idle because we're at the beginning of sanitization, so just dereference crtc->state instead. Signed-off-by: Maarten Lankhorst <maarten.lankhorst@linux.intel.com> Reviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20181011100457.8776-7-maarten.lankhorst@linux.intel.com
2018-10-16drm/i915: Pass crtc_state to update_scanline_offsetMaarten Lankhorst
No need to look at crtc->config when we have crtc_state in the caller. Signed-off-by: Maarten Lankhorst <maarten.lankhorst@linux.intel.com> Reviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20181011100457.8776-6-maarten.lankhorst@linux.intel.com
2018-10-16drm/edid: VSDB yCBCr420 Deep Color mode bit definitionsClint Taylor
HDMI Forum VSDB YCBCR420 deep color capability bits are 2:0. Correct definitions in the header for the mask to work correctly. Fixes: e6a9a2c3dc43 ("drm/edid: parse ycbcr 420 deep color information") Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=107893 Cc: <stable@vger.kernel.org> # v4.14+ Signed-off-by: Clint Taylor <clinton.a.taylor@intel.com> Reviewed-by: Jani Nikula <jani.nikula@intel.com> Reviewed-by: Shashank Sharma <shashank.sharma@intel.com> Signed-off-by: Jani Nikula <jani.nikula@intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/1538776335-12569-1-git-send-email-clinton.a.taylor@intel.com
2018-10-16drm/i915: Always read out M2_N2 in intel_cpu_transcoder_get_m_n, v2.Maarten Lankhorst
has_drrs is a flag we can't read out. We set it when seamless DRRS is enabled in pipe_config, so intel_dump_pipe_config() and intel_pipe_config_compare() will continue to do the right thing when has_drrs is set on the real state. This removes one more dereference of crtc->config. While at it, fixup the comment and also read out M2_N2 for CHV, since we program it in the set_m_n function. Changes since v1: - Only read out M2/N2 on platforms that support DRRS. Signed-off-by: Maarten Lankhorst <maarten.lankhorst@linux.intel.com> Reviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20181015094023.6211-1-maarten.lankhorst@linux.intel.com
2018-10-16drm/i915: Remove crtc->config references in vlv_prepare_pllMaarten Lankhorst
We already have a perfectly nice pipe_config, use that instead. Signed-off-by: Maarten Lankhorst <maarten.lankhorst@linux.intel.com> Reviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20181011100457.8776-4-maarten.lankhorst@linux.intel.com
2018-10-16drm/i915: Make intel_dp_set_m_n take crtc_stateMaarten Lankhorst
Another user of crtc->config gone. The functions it calls also needed crtc->config, so convert those as well. Signed-off-by: Maarten Lankhorst <maarten.lankhorst@linux.intel.com> [mlankhorst: Still pass m_n struct to intel_pch_transcoder_set_m_n (Ville)] Reviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20181011100457.8776-3-maarten.lankhorst@linux.intel.com
2018-10-16drm/rockchip: psr: do not dereference encoder before it is null checked.Enric Balletbo i Serra
'encoder' is dereferenced before it is null sanity checked, hence we potentially have a null pointer dereference bug. Instead, initialise drm_drv from encoder->dev->dev_private after we are sure 'encoder' is not null. Fixes: 5182c1a556d7f ("drm/rockchip: add an common abstracted PSR driver") Cc: stable@vger.kernel.org Signed-off-by: Enric Balletbo i Serra <enric.balletbo@collabora.com> Signed-off-by: Heiko Stuebner <heiko@sntech.de> Link: https://patchwork.freedesktop.org/patch/msgid/20181013105654.11827-1-enric.balletbo@collabora.com
2018-10-16drm: add flags to drm_syncobj_find_fenceChunming Zhou
flags can be used by driver to decide whether need to block wait submission. Signed-off-by: Chunming Zhou <david1.zhou@amd.com> SIgned-off-by: Christian König <christian.koenig@amd.com> Reviewed-by: Christian König <christian.koenig@amd.com> Link: https://patchwork.kernel.org/patch/10641339/
2018-10-16drm: Shift * to be adjacent to pointer nameMamta Shukla
Shift * to be adjacent to pointer name to follow Linux coding style. Issue found with checkpatch.pl ERROR: "foo * bar" should be "foo *bar" Signed-off-by: Mamta Shukla <mamtashukla555@gmail.com> Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch> Link: https://patchwork.freedesktop.org/patch/msgid/20181015212644.GA28579@armorer
2018-10-16pwm: lpss: Only set update bit if we are actually changing the settingsHans de Goede
According to the datasheet the update bit must be set if the on-time-div or the base-unit changes. Now that we properly order device resume on Cherry Trail so that the GFX0 _PS0 method no longer exits with an error, we end up with a sequence of events where we are writing the same values twice in a row. First the _PS0 method restores the duty cycle of 0% the GPU driver set on suspend and then the GPU driver first updates just the enabled bit in the pwm_state from 0 to 1, causing us to write the same values again, before restoring the pre-suspend duty-cycle in a separate pwm_apply call. When writing the update bit the second time, without changing any of the values the update bit clears immediately / instantly, instead of staying 1 for a while as usual. After this the next setting of the update bit seems to be ignored, causing the restoring of the pre-suspend duty-cycle to not get applied. This makes the backlight come up with a 0% dutycycle after suspend/resume. Any further brightness changes after this do work. This commit moves the setting of the update bit into pwm_lpss_prepare() and only sets the bit if we have actually changed any of the values. This avoids the setting of the update bit the second time we configure the PWM to 0% dutycycle, this fixes the backlight coming up with 0% duty-cycle after a suspend/resume. Signed-off-by: Hans de Goede <hdegoede@redhat.com> Signed-off-by: Thierry Reding <thierry.reding@gmail.com>
2018-10-16pwm: lpss: Force runtime-resume on suspend on Cherry TrailHans de Goede
On Cherry Trail devices under Windows the PWM controller used for the backlight is considered part of the GPU even though it is part of the LPSS block and thus is an entirely different independent hardware unit. Because of this on Cherry Trail the GPU's (GFX0 ACPI node) _PS3 and _PS0 methods save and restore the PWM controller registers. If userspace blanks the screen before suspending, such as e.g. GNOME does, then the PWM controller will be runtime-suspended when the suspend starts. This causes the GFX0 _PS? methods to save a value of 0xffffffff for the PWM control register and to restore this value on resume. 0xffffffff is not a valid value for the register and writing this causes problems such as e.g. a flickering backlight. This commit adds a prepare method to the dev_pm_ops and makes it return 0 on Cherry Trail devices forcing a runtime-resume before other device's suspend methods run. This fixes the reading and writing back of 0xffffffff. Since we now always runtime-resume the device on suspend, it will be resumed on resume too and we no longer need to check for the GFX0 _PS0 method having resumed it underneath us, so this commit removes the now no longer necessary complete dev_pm_op. Signed-off-by: Hans de Goede <hdegoede@redhat.com> Signed-off-by: Thierry Reding <thierry.reding@gmail.com>
2018-10-16pwm: Enable TI ECAP driver for ARCH_K3Vignesh R
K3 devices have the same ECAP IP as OMAP SoCs. Enable driver to be built for K3 devices. Also, drop reference to AM33xx in help text, as IP is found on multiple TI SoCs. Signed-off-by: Vignesh R <vigneshr@ti.com> Signed-off-by: Thierry Reding <thierry.reding@gmail.com>
2018-10-16USB: fix the usbfs flag sanitization for control transfersAlan Stern
Commit 7a68d9fb8510 ("USB: usbdevfs: sanitize flags more") checks the transfer flags for URBs submitted from userspace via usbfs. However, the check for whether the USBDEVFS_URB_SHORT_NOT_OK flag should be allowed for a control transfer was added in the wrong place, before the code has properly determined the direction of the control transfer. (Control transfers are special because for them, the direction is set by the bRequestType byte of the Setup packet rather than direction bit of the endpoint address.) This patch moves code which sets up the allow_short flag for control transfers down after is_in has been set to the correct value. Signed-off-by: Alan Stern <stern@rowland.harvard.edu> Reported-and-tested-by: syzbot+24a30223a4b609bb802e@syzkaller.appspotmail.com Fixes: 7a68d9fb8510 ("USB: usbdevfs: sanitize flags more") CC: Oliver Neukum <oneukum@suse.com> CC: <stable@vger.kernel.org> Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
2018-10-16rtc: m41t80: mark expected switch fall-throughGustavo A. R. Silva
In preparation to enabling -Wimplicit-fallthrough, mark switch cases where we are expecting to fall through. Notice that in this particular case, I replaced "Fall" with a proper "Fall through" comment. Addresses-Coverity-ID: 1373875 ("Missing break in switch") Signed-off-by: Gustavo A. R. Silva <gustavo@embeddedor.com> Signed-off-by: Alexandre Belloni <alexandre.belloni@bootlin.com>
2018-10-16rtc: tegra: Propagate errors from platform_get_irq()Thierry Reding
Instead of confusingly returning -EBUSY on failure to obtain an interrupt, propagate the real error code. While at it, let the user know why the interrupt could not be acquired. Signed-off-by: Thierry Reding <treding@nvidia.com> Signed-off-by: Alexandre Belloni <alexandre.belloni@bootlin.com>
2018-10-16devres: provide devm_kstrdup_const()Bartosz Golaszewski
Provide a resource managed version of kstrdup_const(). This variant internally calls devm_kstrdup() on pointers that are outside of .rodata section and returns the string as is otherwise. Make devm_kfree() check if the passed pointer doesn't point to .rodata and if so - don't actually destroy the resource. Signed-off-by: Bartosz Golaszewski <brgl@bgdev.pl> Reviewed-by: Bjorn Andersson <bjorn.andersson@linaro.org> Acked-by: Mike Rapoport <rppt@linux.vnet.ibm.com> Acked-by: Rasmus Villemoes <linux@rasmusvillemoes.dk> Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be> Reviewed-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
2018-10-16devres: constify p in devm_kfree()Bartosz Golaszewski
Make devm_kfree() signature uniform with that of kfree(). To avoid compiler warnings: cast p to (void *) when calling devres_destroy(). Signed-off-by: Bartosz Golaszewski <brgl@bgdev.pl> Reviewed-by: Bjorn Andersson <bjorn.andersson@linaro.org> Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be> Acked-by: Rasmus Villemoes <linux@rasmusvillemoes.dk> Reviewed-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
2018-10-16cpufreq: conservative: Take limits changes into account properlyRafael J. Wysocki
If the policy limits change between invocations of cs_dbs_update(), the requested frequency value stored in dbs_info may not be updated and the function may use a stale value of it next time. Moreover, if idle periods are takem into account by cs_dbs_update(), the requested frequency value stored in dbs_info may be below the min policy limit, which is incorrect. To fix these problems, always update the requested frequency value in dbs_info along with the local copy of it when the previous requested frequency is beyond the policy limits and avoid decreasing the requested frequency below the min policy limit when taking idle periods into account. Fixes: abb6627910a1 (cpufreq: conservative: Fix next frequency selection) Fixes: 00bfe05889e9 (cpufreq: conservative: Decrease frequency faster for deferred updates) Reported-by: Waldemar Rymarkiewicz <waldemarx.rymarkiewicz@intel.com> Cc: All applicable <stable@vger.kernel.org> Signed-off-by: Rafael J. Wysocki <rafael.j.wysocki@intel.com> Acked-by: Waldemar Rymarkiewicz <waldemarx.rymarkiewicz@intel.com> Acked-by: Viresh Kumar <viresh.kumar@linaro.org>
2018-10-16drm/i915/icl: Disable master intr before readingMika Kuoppala
Disable master interrupt before reading level indications. This will close a race where we get a level indication between reading and disabling, generating an extra interrupt where we could have avoided one. Further, as the reading acts also as a post, replace the write/post on the irq reset with the helper. On enabling side, posting doesn't serve any purpose so it can also be replaced with helper. Cc: Chris Wilson <chris@chris-wilson.co.uk> Cc: Ville Syrjälä <ville.syrjala@linux.intel.com> Cc: Daniele Ceraolo Spurio <daniele.ceraolospurio@intel.com> Signed-off-by: Mika Kuoppala <mika.kuoppala@linux.intel.com> Acked-by: Chris Wilson <chris@chris-wilson.co.uk> Reviewed-by: Daniele Ceraolo Spurio <daniele.ceraolospurio@intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20181015141440.21845-3-mika.kuoppala@linux.intel.com
2018-10-16drm/i915/icl: No need to ack intr through master controlMika Kuoppala
All other master control register bits, except the enable, are read only and they are level indications of the second level interrupt status. Only touch enable bit and rectify the comment. Cc: Chris Wilson <chris@chris-wilson.co.uk> Cc: Dhinakaran Pandiyan <dhinakaran.pandiyan@intel.com> Signed-off-by: Mika Kuoppala <mika.kuoppala@linux.intel.com> Reviewed-by: Matthew Auld <matthew.auld@intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20181015141440.21845-2-mika.kuoppala@linux.intel.com
2018-10-16drm/i915/gen8: Disable master intr before readingMika Kuoppala
Disable master interrupt before reading level indications. This will close a race where we get a level indication between reading and disabling, generating an extra interrupt where we could have avoided one. Further, as the reading acts also as a post, replace the write/post on the irq reset with the helper. On enabling side, posting doesn't serve any purpose so it can also be replaced with helper. Cc: Chris Wilson <chris@chris-wilson.co.uk> Cc: Ville Syrjälä <ville.syrjala@linux.intel.com> Signed-off-by: Mika Kuoppala <mika.kuoppala@linux.intel.com> Reviewed-by: Chris Wilson <chris@chris-wilson.co.uk> Link: https://patchwork.freedesktop.org/patch/msgid/20181015141440.21845-1-mika.kuoppala@linux.intel.com
2018-10-16fpga: add devm_fpga_region_createAlan Tull
Add devm_fpga_region_create() which is the managed version of fpga_region_create(). Change current region drivers to use devm_fpga_region_create(). Signed-off-by: Alan Tull <atull@kernel.org> Suggested-by: Federico Vaga <federico.vaga@cern.ch> Acked-by: Moritz Fischer <mdf@kernel.org> Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
2018-10-16fpga: bridge: add devm_fpga_bridge_createAlan Tull
Add devm_fpga_bridge_create() which is the managed version of fpga_bridge_create(). Change current bridge drivers to use devm_fpga_bridge_create(). Signed-off-by: Alan Tull <atull@kernel.org> Suggested-by: Federico Vaga <federico.vaga@cern.ch> Acked-by: Moritz Fischer <mdf@kernel.org> Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
2018-10-16fpga: mgr: add devm_fpga_mgr_createAlan Tull
Add devm_fpga_mgr_create() which is the managed version of fpga_mgr_create(). Change current FPGA manager drivers to use devm_fpga_mgr_create() Signed-off-by: Alan Tull <atull@kernel.org> Suggested-by: Federico Vaga <federico.vaga@cern.ch> Acked-by: Moritz Fischer <mdf@kernel.org> Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
2018-10-16cpufreq: intel_pstate: Add base_frequency attributeSrinivas Pandruvada
Expose base_frequency to user space via cpufreq sysfs when HWP is in use. This HWP base frequency is read from the ACPI _CPC object if present, or from the HWP Capabilities MSR otherwise. On the majority of the HWP platforms the _CPC object will point to the HWP Capabilities MSR using the "Functional Fixed Hardware" address space type. The address space type also can simply be ACPI_TYPE_INTEGER, however, in which case the platform firmware can set its value at the initialization time based on the system constraints. Signed-off-by: Srinivas Pandruvada <srinivas.pandruvada@linux.intel.com> [ rjw: Changelog ] Signed-off-by: Rafael J. Wysocki <rafael.j.wysocki@intel.com>
2018-10-16ACPI / CPPC: Add support for guaranteed performanceSrinivas Pandruvada
The Continuous Performance Control package may contain an optional guaranteed performance field. Add support to read guaranteed performance from _CPC. Signed-off-by: Srinivas Pandruvada <srinivas.pandruvada@linux.intel.com> Signed-off-by: Rafael J. Wysocki <rafael.j.wysocki@intel.com>
2018-10-16pinctrl: sunxi: Fix a memory leak in 'sunxi_pinctrl_build_state()'Christophe JAILLET
If 'krealloc()' fails, 'pctl->functions' is set to NULL. We should instead use a temp variable in order to be able to free the previously allocated memeory, in case of OOM. Signed-off-by: Christophe JAILLET <christophe.jaillet@wanadoo.fr> Acked-by: Maxime Ripard <maxime.ripard@bootlin.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2018-10-16ACPI/ADXL: Add address translation interface using an ACPI DSMTony Luck
Some new Intel servers provide an interface so that the OS can ask the BIOS to translate a system physical address to a memory address (socket, memory controller, channel, rank, dimm, etc.). This is useful for EDAC drivers that want to take the address of an error reported in a machine check bank and let the user know which DIMM may need to be replaced. Specification for this interface is available at: https://cdrdv2.intel.com/v1/dl/getContent/603354 [ Based on earlier code by Qiuxu Zhuo <qiuxu.zhuo@intel.com>. ] [ bp: Make the first pr_info() in adxl_init() pr_debug() so that it doesn't pollute every dmesg. ] Signed-off-by: Tony Luck <tony.luck@intel.com> Signed-off-by: Borislav Petkov <bp@suse.de> Acked-by: Rafael J. Wysocki <rafael.j.wysocki@intel.com> Tested-by: Qiuxu Zhuo <qiuxu.zhuo@intel.com> CC: Len Brown <lenb@kernel.org> CC: linux-acpi@vger.kernel.org CC: linux-edac@vger.kernel.org Link: http://lkml.kernel.org/r/20181015202620.23610-1-tony.luck@intel.com
2018-10-16gpio: uniphier: include <linux/bits.h> instead of <linux/bitops.h>Masahiro Yamada
The reason of including <linux/bitops.h> here is just for BIT() and GENMASK macros. Since commit 8bd9cb51daac8 ("locking/atomics, asm-generic: Move some macros from <linux/bitops.h> to a new <linux/bits.h> file"), <linux/bits.h> is enough for such compile-time macros. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2018-10-16pinctrl: uniphier: include <linux/bits.h> instead of <linux/bitops.h>Masahiro Yamada
The reason of including <linux/bitops.h> here is just for BIT() macro. Since commit 8bd9cb51daac8 ("locking/atomics, asm-generic: Move some macros from <linux/bitops.h> to a new <linux/bits.h> file"), <linux/bits.h> is enough for such compile-time macros. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2018-10-16gpio: Clarify kerneldoc on gpiochip_set_chained_irqchip()Stephen Boyd
This doesn't support nested anymore, so drivers shouldn't call it with the handler set to NULL. Cc: Evan Green <evgreen@chromium.org> Cc: Thierry Reding <treding@nvidia.com> Cc: Grygorii Strashko <grygorii.strashko@ti.com> Signed-off-by: Stephen Boyd <swboyd@chromium.org> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2018-10-16gpio: Remove unused 'irqchip' argument to gpiochip_set_cascaded_irqchip()Stephen Boyd
This argument hasn't ever been used since it was introduced in commit 1425052097b5 ("gpio: add IRQ chip helpers in gpiolib"). Let's drop it to reduce reading confusion. Cc: Evan Green <evgreen@chromium.org> Cc: Thierry Reding <treding@nvidia.com> Cc: Grygorii Strashko <grygorii.strashko@ti.com> Signed-off-by: Stephen Boyd <swboyd@chromium.org> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2018-10-16gpio: Drop parent irq assignment during cascade setupStephen Boyd
We want to set the irq parent for interrupts that we're setting up to be cascaded from another interrupt controller, but we may or may not have already mapped the gpiochip irqs into the kernel's virtual irq number space at this point. If we have mapped irqs before calling here, then we've gone through gpiochip_irq_map() and called irq_set_parent() already. If we haven't mapped irqs, then the gpiochip is dynamically mapping irqs and we can rely on gpiochip_irq_map() or the gpio driver's irqdomain ops to setup the irq parent properly. Either way, setting the parent here when cascading the gpiochip doesn't make much sense because it should be done at irq mapping time. In the dynamic mapping case, this code is mapping virq 0 to some parent virq in a loop. While that's benign, let's drop this code to simplify. Cc: Evan Green <evgreen@chromium.org> Cc: Thierry Reding <treding@nvidia.com> Cc: Grygorii Strashko <grygorii.strashko@ti.com> Signed-off-by: Stephen Boyd <swboyd@chromium.org> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2018-10-16pinctrl: geminilake: Sort register offsets by valueAndy Shevchenko
No functional change. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Acked-by: Mika Westerberg <mika.westerberg@linux.intel.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2018-10-16pinctrl: geminilake: Get rid of unneeded ->probe() stubAndy Shevchenko
The local ->probe() stub does nothing except calling a generic Intel pin control probe function. Thus, it's not needed and generic function may be called directly. This patch converts the driver accordingly. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Acked-by: Mika Westerberg <mika.westerberg@linux.intel.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2018-10-16pinctrl: geminilake: Update pin list for B0 steppingAndy Shevchenko
According to an updated pin list few names of the pins can be spelled better, taking into account their primary functions. Thus, update a pin list to cover B0 stepping. Note, SPI numbering had been fixed even in A0 public documentation. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Acked-by: Mika Westerberg <mika.westerberg@linux.intel.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2018-10-16RDMA/mlx5: Add support for flow tag to raw create flowMark Bloch
A user can provide a hint which will be attached to the packet and written to the CQE on receive. This can be used as a way to offload operations into the HW, for example parsing a packet which is a tunneled packet, and if so, pass 0x1 as the hint. The software can use that hint to decapsulate the packet and parse only the inner headers thus saving CPU cycles. Signed-off-by: Mark Bloch <markb@mellanox.com> Reviewed-by: Yishai Hadas <yishaih@mellanox.com> Signed-off-by: Leon Romanovsky <leonro@mellanox.com> Signed-off-by: Jason Gunthorpe <jgg@mellanox.com>
2018-10-16RDMA/mlx5: Remove extraneous error checkGal Pressman
Remove double error check from create user RQ error flow. Fixes: 79b20a6c3014 ("IB/mlx5: Add receive Work Queue verbs") Signed-off-by: Gal Pressman <pressmangal@gmail.com> Reviewed-by: Majd Dibbiny <majd@mellanox.com> Signed-off-by: Jason Gunthorpe <jgg@mellanox.com>
2018-10-16IB/mlx5: Verify DEVX object typeYishai Hadas
Verify that the input DEVX object type matches the created object. As the obj_id in the firmware is not globally unique the object type must be considered upon checking for a valid object id. Once both the type and the id match we know that the lock was taken on the correct object by the uverbs layer. Fixes: e662e14d801b ("IB/mlx5: Add DEVX support for modify and query commands") Signed-off-by: Yishai Hadas <yishaih@mellanox.com> Reviewed-by: Artemy Kovalyov <artemyko@mellanox.com> Signed-off-by: Leon Romanovsky <leonro@mellanox.com> Signed-off-by: Jason Gunthorpe <jgg@mellanox.com>
2018-10-15nfp: flower: use offsets provided by pedit instead of index for ipv6Pieter Jansen van Vuuren
Previously when populating the set ipv6 address action, we incorrectly made use of pedit's key index to determine which 32bit word should be set. We now calculate which word has been selected based on the offset provided by the pedit action. Fixes: 354b82bb320e ("nfp: add set ipv6 source and destination address") Signed-off-by: Pieter Jansen van Vuuren <pieter.jansenvanvuuren@netronome.com> Reviewed-by: Jakub Kicinski <jakub.kicinski@netronome.com> Signed-off-by: David S. Miller <davem@davemloft.net>
2018-10-15nfp: flower: fix multiple keys per pedit actionPieter Jansen van Vuuren
Previously we only allowed a single header key per pedit action to change the header. This used to result in the last header key in the pedit action to overwrite previous headers. We now keep track of them and allow multiple header keys per pedit action. Fixes: c0b1bd9a8b8a ("nfp: add set ipv4 header action flower offload") Fixes: 354b82bb320e ("nfp: add set ipv6 source and destination address") Fixes: f8b7b0a6b113 ("nfp: add set tcp and udp header action flower offload") Signed-off-by: Pieter Jansen van Vuuren <pieter.jansenvanvuuren@netronome.com> Reviewed-by: Jakub Kicinski <jakub.kicinski@netronome.com> Signed-off-by: David S. Miller <davem@davemloft.net>
2018-10-15nfp: flower: fix pedit set actions for multiple partial masksPieter Jansen van Vuuren
Previously we did not correctly change headers when using multiple pedit actions with partial masks. We now take this into account and no longer just commit the last pedit action. Fixes: c0b1bd9a8b8a ("nfp: add set ipv4 header action flower offload") Signed-off-by: Pieter Jansen van Vuuren <pieter.jansenvanvuuren@netronome.com> Reviewed-by: Jakub Kicinski <jakub.kicinski@netronome.com> Signed-off-by: David S. Miller <davem@davemloft.net>
2018-10-16RDMA/hns: Add FRMR support for hip08Yixian Liu
This patch adds fast register physical memory region (FRMR) support for hip08. Signed-off-by: Yixian Liu <liuyixian@huawei.com> Signed-off-by: Jason Gunthorpe <jgg@mellanox.com>
2018-10-15net: phy: merge phy_start_aneg and phy_start_aneg_privHeiner Kallweit
After commit 9f2959b6b52d ("net: phy: improve handling delayed work") the sync parameter isn't needed any longer in phy_start_aneg_priv(). This allows to merge phy_start_aneg() and phy_start_aneg_priv(). Signed-off-by: Heiner Kallweit <hkallweit1@gmail.com> Signed-off-by: David S. Miller <davem@davemloft.net>
2018-10-16RDMA/bnxt_re: Avoid resource leak in case the NQ registration failsSelvin Xavier
In case the NQ alloc/enable fails, free up the already allocated/enabled NQ before reporting failure. Also, track the alloc/enable using proper state checking. Signed-off-by: Selvin Xavier <selvin.xavier@broadcom.com> Signed-off-by: Jason Gunthorpe <jgg@mellanox.com>
2018-10-16RDMA/bnxt_re: Wait for delayed work to finish before device removalSelvin Xavier
Delayed work bnxt_re_worker would be still running even after cancel_delayed_work returns. This causes crash as the driver proceeds with device removal. To make sure that the work is finished before returning, use cancel_delayed_work_sync. Signed-off-by: Selvin Xavier <selvin.xavier@broadcom.com> Signed-off-by: Jason Gunthorpe <jgg@mellanox.com>
2018-10-16RDMA/bnxt_re: Limit max_pkey to 16 bit valueDevesh Sharma
Some FW versios return pkey values more than 0xFFFF. pkey_tbl_len of ib_port_attr is 16bit value. So restricting max_pkeys to 0xFFFF. Signed-off-by: Devesh Sharma <devesh.sharma@broadcom.com> Signed-off-by: Selvin Xavier <selvin.xavier@broadcom.com> Signed-off-by: Jason Gunthorpe <jgg@mellanox.com>
2018-10-16RDMA/bnxt_re: Fix qp async event reportingDevesh Sharma
Reports affiliated async event on the qp-async event channel instead of global event channel. Signed-off-by: Devesh Sharma <devesh.sharma@broadcom.com> Signed-off-by: Selvin Xavier <selvin.xavier@broadcom.com> Signed-off-by: Jason Gunthorpe <jgg@mellanox.com>
2018-10-16RDMA/bnxt_re: Report out of sequence hw countersSelvin Xavier
Expose out of sequence errors received from FW. This counter is a 32 bit counter and driver has to accumulate the counter. Stores the previous value for calculating the difference in the next query. Also, update the HW statistics structure with new fields. Signed-off-by: Selvin Xavier <selvin.xavier@broadcom.com> Signed-off-by: Jason Gunthorpe <jgg@mellanox.com>