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2020-10-06drm/i915: Add an encoder hook to sanitize its state during init/resumeImre Deak
Atm, if a full modeset is performed during the initial modeset the link training will happen with uninitialized max DP rate and lane count. Make sure the corresponding encoder state is initialized by adding an encoder hook called during driver init and system resume. A better alternative would be to store all states in the CRTC state and make this state available for the link re-training code. Also instead of the DPCD read in the hook there should be really a proper sink HW readout in place. Both of these require a bigger rework, so for now opting for this minimal fix to make at least full initial modesets work. The patch is based on https://patchwork.freedesktop.org/patch/101473/?series=10354&rev=3 v2: (Ville) - s/sanitize_state/sync_state/ - No point in calling the hook when CRTC is disabled, remove the call. - No point in calling the hook for MST, remove it. v3: Check only DPCD_REV to avoid clobbering intel_dp->dpcd. (Ville) Cc: Ville Syrjälä <ville.syrjala@linux.intel.com> Reviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com> Signed-off-by: Imre Deak <imre.deak@intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20201005230154.1477653-1-imre.deak@intel.com
2020-10-06drm/i915: Check for unsupported DP link rates during initial commitImre Deak
Some BIOSes set an unsupported/imprecise DP link rate (for instance on TGL A stepping). Make sure that we do an encoder recompute and a modeset in this case. Cc: Ville Syrjälä <ville.syrjala@linux.intel.com> Reviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com> Signed-off-by: Imre Deak <imre.deak@intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20201003001846.1271151-4-imre.deak@intel.com
2020-10-06drm/i915: Move the initial fastset commit check to encoder hooksImre Deak
Move the checks to decide whether a fastset is possible during the initial commit to an encoder hook. This check is really encoder specific and the next patch will also require this adding a DP encoder specific check. v2: Fix negated condition in gen11_dsi_initial_fastset_check(). v3: Make sure to call the hook for all encoders on the crtc. (Ville) Cc: Ville Syrjälä <ville.syrjala@linux.intel.com> Reviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com> Signed-off-by: Imre Deak <imre.deak@intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20201005215311.1475666-1-imre.deak@intel.com
2020-10-06drm/i915/skl: Work around incorrect BIOS WRPLL PDIV programmingImre Deak
The BIOS of at least one ASUS-Z170M system with an SKL I have programs the 101b WRPLL PDIV divider value, which is the encoding for PDIV=7 with bit#0 incorrectly set. This happens with the "3840x2160": 30 262750 3840 3888 3920 4000 2160 2163 2168 2191 0x48 0x9 HDMI mode (scaled from a 1024x768 src fb) set by BIOS and the ref_clock=24000, dco_integer=383, dco_fraction=5802, pdiv=7, qdiv=1, kdiv=1 WRPLL parameters (assuming PDIV=7 was the intended setting). This corresponds to 262749 PLL frequency/port clock. Later the driver sets the same mode for which it calculates the same dco_int/dco_frac/div WRPLL parameters (with the correct PDIV=7 encoding). Based on the above, let's assume that PDIV=7 was intended and the HW just ignores bit#0 in the PDIV register field for this setting, treating 100b and 101b encodings the same way. While at it add the MISSING_CASE() for the p0,p2 divider decodings. v2: (Ville) - Add a define for the incorrect divider value. - Emit only a debug message when detecting the incorrect divider value. - Use fallthrough from the incorrect divider value case. - Add the MISSING_CASE()s. v3: Return 0 freq for incorrect divider values. (Ville) Cc: Ville Syrjälä <ville.syrjala@linux.intel.com> Reviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com> Signed-off-by: Imre Deak <imre.deak@intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20201006013555.1488262-1-imre.deak@intel.com
2020-10-05drm/i915/dg1: Wait for pcode/uncore handshake at startupMatt Roper
DG1 does some additional pcode/uncore handshaking at boot time; this handshaking must complete before various other pcode commands are effective and before general work is submitted to the GPU. We need to poll a new pcode mailbox during startup until it reports that this handshaking is complete. The bspec doesn't give guidance on how long we may need to wait for this handshaking to complete. For now, let's just set a really long timeout; if we still don't get a completion status by the end of that timeout, we'll just continue on and hope for the best. v2 (Lucas): Rename macros to make clear the relation between command and result (requested by José) Bspec: 52065 Cc: Clinton Taylor <Clinton.A.Taylor@intel.com> Cc: Ville Syrjälä <ville.syrjala@linux.intel.com> Cc: Radhakrishna Sripada <radhakrishna.sripada@intel.com> Signed-off-by: Matt Roper <matthew.d.roper@intel.com> Signed-off-by: Lucas De Marchi <lucas.demarchi@intel.com> Reviewed-by: José Roberto de Souza <jose.souza@intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20201001063917.3133475-2-lucas.demarchi@intel.com
2020-10-05drm/i915: don't conflate is_dgfx with fake lmemLucas De Marchi
When using fake lmem for tests, we are overriding the setting in device info for dgfx devices. Current users of IS_DGFX() except one are correct. However, as we add support for DG1, we are going to use it in additional places to trigger dgfx-only code path. In future if we need we can use HAS_LMEM() instead of IS_DGFX() in the places that make sense to also contemplate fake lmem use. v2: update gen8_gmch_probe() to use HAS_LMEM(): we need to steal the mappable aperture later(which is fine since it doesn't exist on "DGFX"), and use it as a substitute for LMEMBAR. The !mappable aperture property is also useful since it exercises some other parts of the code too. (Matthew Auld) Signed-off-by: Lucas De Marchi <lucas.demarchi@intel.com> Reviewed-by: Matthew Auld <matthew.auld@intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20201001063917.3133475-1-lucas.demarchi@intel.com
2020-10-02drm/i915: Make lspcon_init() staticVille Syrjälä
Make lspcon_init() static since it's no longer needed outside the compilation unit. This was correct in Kai-Heng's lspcon patch, but I fumbled this when applying it. Cc: Kai-Heng Feng <kai.heng.feng@canonical.com> Reported-by: kernel test robot <lkp@intel.com> Fixes: f542d671ffce ("drm/i915: Init lspcon after HPD in intel_dp_detect()") Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20201002090446.21104-1-ville.syrjala@linux.intel.com Reviewed-by: Chris Wilson <chris@chris-wilson.co.uk>
2020-10-01drm/i915: Init lspcon after HPD in intel_dp_detect()Kai-Heng Feng
On HP 800 G4 DM, if HDMI cable isn't plugged before boot, the HDMI port becomes useless and never responds to cable hotplugging: [ 3.031904] [drm:lspcon_init [i915]] *ERROR* Failed to probe lspcon [ 3.031945] [drm:intel_ddi_init [i915]] *ERROR* LSPCON init failed on port D Seems like the lspcon chip on the system only gets powered after the cable is plugged. Consilidate lspcon_init() into lspcon_resume() to dynamically init lspcon chip, and make HDMI port work. v6: - Rebase on latest for-linux-next. v5: - Consolidate lspcon_resume() with lspcon_init(). - Move more logic into lspcon code. v4: - Trust VBT in intel_infoframe_init(). - Init lspcon in intel_dp_detect(). v3: - Make sure it's handled under long HPD case. v2: - Move lspcon_init() inside of intel_dp_hpd_pulse(). Closes: https://gitlab.freedesktop.org/drm/intel/-/issues/203 Signed-off-by: Kai-Heng Feng <kai.heng.feng@canonical.com> Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20200610075542.12882-1-kai.heng.feng@canonical.com
2020-10-01drm/i915: Eliminate intel_dp.regs.dp_tp_{ctl,status}Ville Syrjälä
Now that we've plumbed the crtc state all the way down we can eliminate the DP_TP_{CTL,STATUS} register offsets from intel_dp, and instead we derive them directly from the crtc state. And thus we can get rid of the nasty hack in intel_ddi_get_config() which mutates intel_dp during the readout. Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20200929233449.32323-12-ville.syrjala@linux.intel.com Reviewed-by: Imre Deak <imre.deak@intel.com>
2020-10-01drm/i915: Plumb crtc_state to link trainingVille Syrjälä
Get rid of mode crtc->config usage, and some ad-hoc intel_dp state usage by plumbing the crtc state all the way down to the link training code. Unfortunately we do have to keep some cached state in intel_dp so that we can do the "does the link need retraining?" checks from the short hpd handler. v2: Add intel_crtc_state forward declaration v3: Don't kill the PHY test code totally since it's now in the hotplug work where we can get at the states v4: Don't resurrect the debug scrambling disable bit (Imre) Use intel_dp_mst_is_master_trans() (Imre) Reviewed-by: Imre Deak <imre.deak@intel.com> Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20201001111053.24451-1-ville.syrjala@linux.intel.com
2020-10-01drm/i915: Split TGL DKL PHY buf trans per output typeVille Syrjälä
Make the mess inside the buf trans funcs a bit more manageable by splitting along the lines of output type. Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20200929233449.32323-10-ville.syrjala@linux.intel.com Reviewed-by: Imre Deak <imre.deak@intel.com>
2020-10-01drm/i915: Split TGL combo PHY buf trans per output typeVille Syrjälä
Make the mess inside the buf trans funcs a bit more manageable by splitting along the lines of output type. Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20200929233449.32323-9-ville.syrjala@linux.intel.com Reviewed-by: Imre Deak <imre.deak@intel.com>
2020-10-01drm/i915: Split EHL combo PHY buf trans per output typeVille Syrjälä
Make the mess inside the buf trans funcs a bit more manageable by splitting along the lines of output type. Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20200929233449.32323-8-ville.syrjala@linux.intel.com Reviewed-by: Imre Deak <imre.deak@intel.com>
2020-10-01drm/i915: Split ICL MG PHY buf trans per output typeVille Syrjälä
Make the mess inside the buf trans funcs a bit more manageable by splitting along the lines of output type. Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20200929233449.32323-7-ville.syrjala@linux.intel.com Reviewed-by: Imre Deak <imre.deak@intel.com>
2020-10-01drm/i915: Split ICL combo PHY buf trans per output typeVille Syrjälä
Make the mess inside the buf trans funcs a bit more manageable by splitting along the lines of output type. Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20200929233449.32323-6-ville.syrjala@linux.intel.com Reviewed-by: Imre Deak <imre.deak@intel.com>
2020-10-01drm/i915: Shove the PHY test into the hotplug workVille Syrjälä
Doing any kind modeset stuff from the short hpd handler is verboten. The ad-hoc PHY test modeset code violates this. And by calling various link training related functions it's now blocking further work to plumb the crtc state down into the link training code. Let's hack around that by pushing the PHY test stuff into the hotplug work where it's less of a problem. Still not great but at least acceptable. We take a few pages from the link retraining handbook to handle the locking and whatnot. v2: Fix the intel_dp_hotplug() return value Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20200930100412.9313-1-ville.syrjala@linux.intel.com Reviewed-by: Imre Deak <imre.deak@intel.com>
2020-10-01drm/i915: Make intel_dp_process_phy_request() staticVille Syrjälä
intel_dp_process_phy_request() has no business being externally visible. Make it static. Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20200929233449.32323-4-ville.syrjala@linux.intel.com Reviewed-by: Imre Deak <imre.deak@intel.com>
2020-10-01drm/i915: s/old_crtc_state/crtc_state/Ville Syrjälä
intel_dp_enable_port() is called during the enable sequence, so there is nothing old about the passed in crtc state. Rename it. Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20200929233449.32323-3-ville.syrjala@linux.intel.com Reviewed-by: Imre Deak <imre.deak@intel.com>
2020-10-01drm/i915: s/pre_empemph/preemph/Ville Syrjälä
I managed to fumble some functions names. Fix them. Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20200929233449.32323-2-ville.syrjala@linux.intel.com Reviewed-by: Imre Deak <imre.deak@intel.com>
2020-10-01drm/i915: Fix TGL DKL PHY DP vswing handlingVille Syrjälä
The HDMI vs. not-HDMI check got inverted whem the bogus encoder->type checks were eliminated. So now we're using 0 as the link rate on DP and potentially non-zero on HDMI, which is exactly the opposite of what we want. The original bogus check actually worked more correctly by accident since if would always evaluate to true. Due to this we now always use the RBR/HBR1 vswing table and never ever the HBR2+ vswing table. That is probably not a good way to get a high quality signal at HBR2+ rates. Fix the check so we pick the right table. Cc: stable@vger.kernel.org Cc: Vandita Kulkarni <vandita.kulkarni@intel.com> Cc: Uma Shankar <uma.shankar@intel.com> Fixes: 94641eb6c696 ("drm/i915/display: Fix the encoder type check") Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20200930223642.28565-1-ville.syrjala@linux.intel.com Reviewed-by: José Roberto de Souza <jose.souza@intel.com> Reviewed-by: Vandita Kulkarni <vandita.kulkarni@intel.com>
2020-10-01drm/i915: Implement display WA #1142:kbl,cfl,cmlVille Syrjälä
Implement display w/a #1142. This supposedly fixes some underruns with FBC+VTd. Bspec says we should use the same programming regardless of circumstances. Apparently we should flip the magic bits before turning on any planes so let's put this into the early w/as. Cc: Lee Shawn C <shawn.c.lee@intel.com> Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20200924194810.10293-1-ville.syrjala@linux.intel.com Reviewed-by: José Roberto de Souza <jose.souza@intel.com>
2020-09-30drm/i915: Read DIMM size in Gb rather than GBVille Syrjälä
CNL+ can report DIMM sizes in .5 GB units. In order to not trauncate away the .5 GB let's switch to storing the DIMM size in Gb units. Cc: Swati Sharma <swati2.sharma@intel.com> Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com> Reviewed-by: José Roberto de Souza <jose.souza@intel.com> Signed-off-by: José Roberto de Souza <jose.souza@intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20200929131312.12999-1-ville.syrjala@linux.intel.com
2020-09-28drm/i915/dsi: Enable software vblank counterVandita Kulkarni
In case of DSI cmd mode, we get hw vblank counter updated after the TE comes in, if we try to read the hw vblank counter in te handler we wouldnt have the udpated vblank counter yet. This will lead to a state where we would send the vblank event to the user space in the next te, though the frame update would have completed in the first TE duration itself. Hence switch to using software timestamp based vblank counter. v2: Use mode_flags from crtc_state (Ville) Acked-by: Ville Syrjälä <ville.syrjala@linux.intel.com> Signed-off-by: Vandita Kulkarni <vandita.kulkarni@intel.com> Signed-off-by: Jani Nikula <jani.nikula@intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20200924124209.17916-6-vandita.kulkarni@intel.com
2020-09-28drm/i915/dsi: Initiate frame request in cmd modeVandita Kulkarni
In TE Gate mode or TE NO_GATE mode on every flip we need to set the frame update request bit. After this bit is set transcoder hardware will automatically send the frame data to the panel in case of TE NO_GATE mode, where it sends after it receives the TE event in case of TE_GATE mode. Once the frame data is sent to the panel, we see the frame counter updating. v2: Use intel_de_read/write v3: remove the usage of private_flags v4: Use icl_dsi in func names if non static, fix code formatting issues. (Jani) v5: Send frame update request at the beginning of pipe_update_end, use crtc_state mode_flags (Ville) v6: Add platform and dsi checks (Ville) Acked-by: Ville Syrjälä <ville.syrjala@linux.intel.com> Signed-off-by: Vandita Kulkarni <vandita.kulkarni@intel.com> Signed-off-by: Jani Nikula <jani.nikula@intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20200928110834.15077-1-vandita.kulkarni@intel.com
2020-09-28drm/i915/dsi: Add TE handler for dsi cmd mode.Vandita Kulkarni
In case of dual link, we get the TE on slave. So clear the TE on slave DSI IIR. If we are operating in TE_GATE mode, after we do a frame update, the transcoder will send the frame data to the panel, after it receives a TE. Whereas if we are operating in NO_GATE mode then the transcoder will immediately send the frame data to the panel. We are not dealing with the periodic command mode here. v2: Pass only relevant masked bits to the handler (Jani) v3: Fix the check for cmd mode in TE handler function. v4: Use intel_handle_vblank instead of drm_handle_vblank (Jani) v3: Use static on handler func (Jani) Acked-by: Ville Syrjälä <ville.syrjala@linux.intel.com> Signed-off-by: Vandita Kulkarni <vandita.kulkarni@intel.com> Signed-off-by: Jani Nikula <jani.nikula@intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20200924124209.17916-4-vandita.kulkarni@intel.com
2020-09-28i915/dsi: Configure TE interrupt for cmd modeVandita Kulkarni
Configure TE interrupt as part of the vblank enable call flow. v2: Hide the private flags check inside configure_te (Jani) v3: Fix the position of masking de_port_masked for DSI_TE. v4: Simplify the caller of configure_te (Jani) v5: Clear IIR, remove the usage of private_flags v6: including icl_dsi header is not needed Acked-by: Ville Syrjälä <ville.syrjala@linux.intel.com> Signed-off-by: Vandita Kulkarni <vandita.kulkarni@intel.com> Signed-off-by: Jani Nikula <jani.nikula@intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20200924124209.17916-3-vandita.kulkarni@intel.com
2020-09-28drm/i915/dsi: Add details about TE in get_configVandita Kulkarni
We need details about enabling TE on which port before we enable TE through vblank enable path. This is based on the configuration that we receive from the VBT wrt ports, dual_link. Reviewed-by: Jani Nikula <jani.nikula@intel.com> Acked-by: Ville Syrjälä <ville.syrjala@linux.intel.com> Signed-off-by: Vandita Kulkarni <vandita.kulkarni@intel.com> Signed-off-by: Jani Nikula <jani.nikula@intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20200924124209.17916-2-vandita.kulkarni@intel.com
2020-09-28drm/i915: Replace some gamma_mode ifs with switchesVille Syrjälä
Since gamma_mode can have more than two values on ilk+ let's use switch statements when interpreting them. v2: Fix typo (Uma) Reviewed-by: Uma Shankar <uma.shankar@intel.com> Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20200925131656.10022-10-ville.syrjala@linux.intel.com
2020-09-28drm/i915: Polish bdw_read_lut_10() a bitVille Syrjälä
Since bdw_read_lut_10() uses the auto-increment mode we must have an equal number of entries in the software LUT and the hardware LUT. WARN if that is not the case. Reviewed-by: Uma Shankar <uma.shankar@intel.com> Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20200925131656.10022-9-ville.syrjala@linux.intel.com
2020-09-28drm/i915: Relocate CHV CGM gamma masksVille Syrjälä
CGM_PIPE_GAMMA_RED_MASK & co. are misplaced. Move then below the relevant register. And while at it add the degamma counterparts. Reviewed-by: Uma Shankar <uma.shankar@intel.com> Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20200925131656.10022-8-ville.syrjala@linux.intel.com
2020-09-28drm/i915: Shuffle chv_cgm_gamma_pack() around a bitVille Syrjälä
Move chv_cgm_gamma_pack() next to the other CGM gamma functions. Right now it's stuck in the middle of the CGM degamma functions. Reviewed-by: Uma Shankar <uma.shankar@intel.com> Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20200925131656.10022-7-ville.syrjala@linux.intel.com
2020-09-28drm/i915: Reset glk degamma index after programming/readoutVille Syrjälä
Just for some extra consistency let's reset the glk degamma LUT index back to 0 after we're dong trawling the LUT. Reviewed-by: Uma Shankar <uma.shankar@intel.com> Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20200925131656.10022-6-ville.syrjala@linux.intel.com
2020-09-28drm/i915: s/glk_read_lut_10/bdw_read_lut_10/Ville Syrjälä
glk_read_lut_10() works just fine for all bdw+ platforms, so rename it. Reviewed-by: Uma Shankar <uma.shankar@intel.com> Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20200925131656.10022-5-ville.syrjala@linux.intel.com
2020-09-28drm/i915: Include the LUT sizes in the state dumpVille Syrjälä
Dump the sizes of the software LUTs in the state dump. Makes it a bit easier to see which is present without having to decode it from the gamma_mode and other bits of state. v2: Drop a spurious "is" in commit msg (Uma) Reviewed-by: Uma Shankar <uma.shankar@intel.com> Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20200925131656.10022-4-ville.syrjala@linux.intel.com
2020-09-28drm/i915: Move MST master transcoder dump earlierVille Syrjälä
Move the MST master transcoder dump next to the other transcoder bits. Reviewed-by: Uma Shankar <uma.shankar@intel.com> Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20200925131656.10022-3-ville.syrjala@linux.intel.com
2020-09-28drm/i915: Fix state checker hw.active/hw.enable readoutVille Syrjälä
Previously intel_dump_pipe_config() used to dump the full crtc state whether or not the crtc was logically enabled or not. As that meant occasionally dumping confusing stale garbage I changed it to check whether the crtc is logically enabled or not. However I did not realize that the state checker readout code does not populate crtc_state.hw.{active,enabled}. Hence the state checker dump would only give us a full dump of the sw state but not the hw state. Fix that by populating those bits of the hw state as well. Reviewed-by: Uma Shankar <uma.shankar@intel.com> Fixes: 10d75f5428fd ("drm/i915: Fix plane state dumps") Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20200925131656.10022-2-ville.syrjala@linux.intel.com
2020-09-28drm/i915: Don't hide the intel_crtc_atomic_check() callVille Syrjälä
Move the intel_crtc_atomic_check() call out from the variable declarations to a place where we can actually see it. Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20200925121749.708-2-ville.syrjala@linux.intel.com Reviewed-by: José Roberto de Souza <jose.souza@intel.com>
2020-09-28drm/i915: Make intel_{enable,disable}_sagv() staticVille Syrjälä
intel_{enable,disable}_sagv() are no longer needed outside the compilation unit. Make them static. Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20200925121749.708-1-ville.syrjala@linux.intel.com Reviewed-by: José Roberto de Souza <jose.souza@intel.com>
2020-09-28drm/i915: Enable async flips in i915Karthik B S
Enable asynchronous flips in i915 for gen9+ platforms. v2: -Async flip enablement should be a stand alone patch (Paulo) v3: -Move the patch to the end of the series (Paulo) v4: -Rebased. v5: -Rebased. v6: -Rebased. v7: -Rebased. v8: -Rebased. v9: -Rebased. v10: -Rebased. Signed-off-by: Karthik B S <karthik.b.s@intel.com> Signed-off-by: Vandita Kulkarni <vandita.kulkarni@intel.com> Reviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com> Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20200921110210.21182-9-karthik.b.s@intel.com
2020-09-28Documentation/gpu: Add asynchronous flip documentation for i915Karthik B S
Add the details of the implementation of asynchronous flips for i915. v7: -Rebased. v8: -Rebased. v9: -Rebased. v10: Move all documentation changes to this patch. (Ville) Signed-off-by: Karthik B S <karthik.b.s@intel.com> Signed-off-by: Vandita Kulkarni <vandita.kulkarni@intel.com> Reviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com> Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20200921110210.21182-8-karthik.b.s@intel.com
2020-09-28drm/i915: WA for platforms with double buffered address update enable bitKarthik B S
In Gen 9 and Gen 10 platforms, async address update enable bit is double buffered. Due to this, during the transition from async flip to sync flip we have to wait until this bit is updated before continuing with the normal commit for sync flip. v9: -Rename skl_toggle_async_sync() to skl_disable_async_flip_wa(). (Ville) -Place the declarations appropriately as per need. (Ville) -Take the lock before the reg read. (Ville) -Fix comment and formatting. (Ville) -Use IS_GEN_RANGE() for gen check. (Ville) -Move skl_disable_async_flip_wa() to intel_pre_plane_update(). (Ville) v10: -Rebased. Signed-off-by: Karthik B S <karthik.b.s@intel.com> Signed-off-by: Vandita Kulkarni <vandita.kulkarni@intel.com> Reviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com> Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20200921110210.21182-7-karthik.b.s@intel.com
2020-09-28drm/i915: Add dedicated plane hook for async flip caseKarthik B S
This hook is added to avoid writing other plane registers in case of async flips, so that we do not write the double buffered registers during async surface address update. v7: -Plane ctl needs bits from skl_plane_ctl_crtc as well. (Ville) -Add a vfunc for skl_program_async_surface_address and call it from intel_update_plane. (Ville) v8: -Rebased. v9: -Use if-else instead of return in intel_update_plane(). (Ville) -Rename 'program_async_surface_address' to 'async_flip'. (Ville) v10: -Check if async_flip hook is present before calling it. Otherwise it will OOPS during legacy cursor updates. (Ville) v11: -Rename skl_program_async_surface_address(). (Ville) Signed-off-by: Karthik B S <karthik.b.s@intel.com> Signed-off-by: Vandita Kulkarni <vandita.kulkarni@intel.com> Reviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com> Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20200921110210.21182-6-karthik.b.s@intel.com
2020-09-28drm/i915: Do not call drm_crtc_arm_vblank_event in async flipsKarthik B S
Since the flip done event will be sent in the flip_done_handler, no need to add the event to the list and delay it for later. v2: -Moved the async check above vblank_get as it was causing issues for PSR. v3: -No need to wait for vblank to pass, as this wait was causing a 16ms delay once every few flips. v4: -Rebased. v5: -Rebased. v6: -Rebased. v7: -No need of irq disable if we are not doing vblank evade. (Ville) v8: -Rebased. v9: -Move the return in intel_pipe_update_end before tracepoint. (Ville) v10: Rebased. Signed-off-by: Karthik B S <karthik.b.s@intel.com> Signed-off-by: Vandita Kulkarni <vandita.kulkarni@intel.com> Reviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com> Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20200921110210.21182-5-karthik.b.s@intel.com
2020-09-28drm/i915: Add checks specific to async flipsKarthik B S
If flip is requested on any other plane, reject it. Make sure there is no change in fbc, offset and framebuffer modifiers when async flip is requested. If any of these are modified, reject async flip. v2: -Replace DRM_ERROR (Paulo) -Add check for changes in OFFSET, FBC, RC(Paulo) v3: -Removed TODO as benchmarking tests have been run now. v4: -Added more state checks for async flip (Ville) -Moved intel_atomic_check_async to the end of intel_atomic_check as the plane checks needs to pass before this. (Ville) -Removed crtc_state->enable_fbc check. (Ville) -Set the I915_MODE_FLAG_GET_SCANLINE_FROM_TIMESTAMP flag for async flip case as scanline counter is not reliable here. v5: -Fix typo and other check patch errors seen in CI in 'intel_atomic_check_async' function. v6: -Don't call intel_atomic_check_async multiple times. (Ville) -Remove the check for n_planes in intel_atomic_check_async -Added documentation for async flips. (Paulo) v7: -Replace 'intel_plane' with 'plane'. (Ville) -Replace all uapi.foo as hw.foo. (Ville) -Do not use intel_wm_need_update function. (Ville) -Add destination coordinate check. (Ville) -Do not allow async flip with linear buffer on older hw as it has issues with this. (Ville) -Remove break after intel_atomic_check_async. (Ville) v8: -Rebased. v9: -Replace DRM_DEBUG_KMS with drm_dbg_kms(). (Ville) -Fix comment formatting. (Ville) -Remove gen specific checks. (Ville) -Remove irrelevant FB size check. (Ville) -Add missing stride check. (Ville) -Use drm_rect_equals() instead of individual checks. (Ville) -Call intel_atomic_check_async before state dump. (Ville) v10: -Fix the checkpatch errors seen on CI. v11: -Use const for all plane/crtc states. (Ville) -Use 'switch' instead of 'if' for modifier check. (Ville) -Move documentation changes to a single patch. (Ville) Signed-off-by: Karthik B S <karthik.b.s@intel.com> Signed-off-by: Vandita Kulkarni <vandita.kulkarni@intel.com> Reviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com> Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20200921110210.21182-4-karthik.b.s@intel.com
2020-09-28drm/i915: Add support for async flips in I915Karthik B S
Set the Async Address Update Enable bit in plane ctl when async flip is requested. v2: -Move the Async flip enablement to individual patch (Paulo) v3: -Rebased. v4: -Add separate plane hook for async flip case (Ville) v5: -Rebased. v6: -Move the plane hook to separate patch. (Paulo) -Remove the early return in skl_plane_ctl. (Paulo) v7: -Move async address update enable to skl_plane_ctl_crtc() (Ville) v8: -Rebased. v9: -Rebased. v10: -Rebased. Signed-off-by: Karthik B S <karthik.b.s@intel.com> Signed-off-by: Vandita Kulkarni <vandita.kulkarni@intel.com> Reviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com> Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20200921110210.21182-3-karthik.b.s@intel.com
2020-09-28drm/i915: Add enable/disable flip done and flip done handlerKarthik B S
Add enable/disable flip done functions and the flip done handler function which handles the flip done interrupt. Enable the flip done interrupt in IER. Enable flip done function is called before writing the surface address register as the write to this register triggers the flip done interrupt Flip done handler is used to send the page flip event as soon as the surface address is written as per the requirement of async flips. The interrupt is disabled after the event is sent. v2: -Change function name from icl_* to skl_* (Paulo) -Move flip handler to this patch (Paulo) -Remove vblank_put() (Paulo) -Enable flip done interrupt for gen9+ only (Paulo) -Enable flip done interrupt in power_well_post_enable hook (Paulo) -Removed the event check in flip done handler to handle async flips without pageflip events. v3: -Move skl_disable_flip_done out of interrupt handler (Paulo) -Make the pending vblank event NULL in the beginning of flip_done_handler to remove sporadic WARN_ON that is seen. v4: -Calculate timestamps using flip done time stamp and current timestamp for async flips (Ville) v5: -Fix the sparse warning by making the function 'g4x_get_flip_counter' static.(Reported-by: kernel test robot <lkp@intel.com>) -Fix the typo in commit message. v6: -Revert back to old time stamping code. -Remove the break while calling skl_enable_flip_done. (Paulo) v7: -Rebased. v8: -Rebased. v9: -Use struct drm_i915_private *i915 in new code. (Ville) -Use intel_crtc instead of drm_crtc. (Ville) -Do not mix the flip done and vblank hooks. (Ville) v10: -Rebased. Signed-off-by: Karthik B S <karthik.b.s@intel.com> Signed-off-by: Vandita Kulkarni <vandita.kulkarni@intel.com> Reviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com> Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20200921110210.21182-2-karthik.b.s@intel.com
2020-09-24drm/i915: Use the correct bpp when validating "4:2:0 only" modesVille Syrjälä
When validating a "YCbCr 4:2:0 only" mode we must take into account the fact that we're going to be outputting YCbCr 4:2:0 or 4:4:4 (when a DP->HDMI protocol converter is doing the 4:2:0 downsampling). For YCbCr 4:4:4 the minimum output bpc is 8, for YCbCr 4:2:0 it'll be half that. The currently hardcoded 6bpc is only correct for RGB 4:4:4, which we will never use with these kinds of modes. Figure out what we're going to output and use the correct min bpp value to validate whether the link has sufficient bandwidth. Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20200917214335.3569-3-ville.syrjala@linux.intel.com Reviewed-by: Manasi Navare <manasi.d.navare@intel.com> Reviewed-by: Vandita Kulkarni <vandita.kulkarni@intel.com>
2020-09-24drm/i915: Decouple intel_dp_{min,output}_bpp() from crtc_stateVille Syrjälä
Pass the output_format directly to intel_dp_{min,output}_bpp() rather than passing in the crtc_state and digging out the output_format inside the functions. This will allow us to reuse the functions for mode validation purposes. Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20200917214335.3569-2-ville.syrjala@linux.intel.com Reviewed-by: Manasi Navare <manasi.d.navare@intel.com> Reviewed-by: Vandita Kulkarni <vandita.kulkarni@intel.com>
2020-09-24drm/i915: Extract intel_dp_output_format()Ville Syrjälä
Refactor the output_format calculation into a helper so that we can reuse it for mode validation as well. Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20200917214335.3569-1-ville.syrjala@linux.intel.com Reviewed-by: Vandita Kulkarni <vandita.kulkarni@intel.com>
2020-09-24drm/i915: dont retry stream management at seq_num_m roll overRamalingam C
When roll over detected for seq_num_m, we shouldn't continue with stream management with rolled over value. So we are terminating the stream management retry, on roll over of the seq_num_m. v2: using drm_dbg_kms instead of DRM_DEBUG_KMS [Anshuman] v3: dev_priv is used as i915 [JaniN] v4: roll over is detected at the start of the stream management. Signed-off-by: Ramalingam C <ramalingam.c@intel.com> Reviewed-by: Anshuman Gupta <anshuman.gupta@intel.com> [v3] Tested-by: Anshuman Gupta <anshuman.gupta@intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20200923132435.17039-3-anshuman.gupta@intel.com
generated by cgit (git 2.34.1) at 2025-09-22 16:33:58 +0000