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2021-06-23remoteproc: qcom_q6v5: Use devm_qcom_smem_state_get() to fix missing put()Stephan Gerhold
qcom_q6v5 is requesting a smem state with qcom_smem_state_get() but qcom_smem_state_put() is not called anywhere. Use the new devm_() variant to fix this without making the code more complicated. Fixes: 051fb70fd4ea ("remoteproc: qcom: Driver for the self-authenticating Hexagon v5") Signed-off-by: Stephan Gerhold <stephan@gerhold.net> Link: https://lore.kernel.org/r/20210618111556.53416-2-stephan@gerhold.net Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
2021-06-23soc: qcom: smem_state: Add devm_qcom_smem_state_get()Stephan Gerhold
It is easy to forget to call qcom_smem_state_put() after a qcom_smem_state_get(). Introduce a devm_qcom_smem_state_get() helper function that automates this so that qcom_smem_state_put() is automatically called when a device is removed. Signed-off-by: Stephan Gerhold <stephan@gerhold.net> Reviewed-by: Bjorn Andersson <bjorn.andersson@linaro.org> Link: https://lore.kernel.org/r/20210618111556.53416-1-stephan@gerhold.net Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
2021-06-23Merge tag 'spi-fix-v5.13-rc7' of ↵Linus Torvalds
git://git.kernel.org/pub/scm/linux/kernel/git/broonie/spi Pull spi fixes from Mark Brown: "A couple of small, driver specific fixes that arrived in the past few weeks" * tag 'spi-fix-v5.13-rc7' of git://git.kernel.org/pub/scm/linux/kernel/git/broonie/spi: spi: spi-nxp-fspi: move the register operation after the clock enable spi: tegra20-slink: Ensure SPI controller reset is deasserted
2021-06-23Merge tag 'iwlwifi-next-for-kalle-2021-06-22' of ↵Kalle Valo
git://git.kernel.org/pub/scm/linux/kernel/git/iwlwifi/iwlwifi-next iwlwifi patches for v5.14 * Some robustness improvements in the PCI code; * Remove some duplicate and unused declarations; * Improve PNVM load robustness by increasing the timeout a bit; * Support for a new HW; * Suport for BIOS control of 11ax enablement in Russia; * Support UNII4 enablement from BIOS; * Support LMR feedback; * Fix in TWT; * Some fixes in IML (image loader) DMA handling; * Fixes in WoWLAN; * Updates in the WoWLAN FW commands; * Add one new device to the PCI ID lists; * Support reading PNVM from a UEFI variable; * Bump the supported FW API version; * Some other small fixes, clean-ups and improvements. # gpg: Signature made Tue 22 Jun 2021 05:19:19 PM EEST # gpg: using RSA key 1772CD7E06F604F5A6EBCB26A1479CA21A3CC5FA # gpg: Good signature from "Luciano Roth Coelho (Luca) <luca@coelho.fi>" [full] # gpg: aka "Luciano Roth Coelho (Intel) <luciano.coelho@intel.com>" [full]
2021-06-23brcmfmac: Silence error messages about unsupported firmware featuresDmitry Osipenko
KMSG is flooded with error messages about unsupported firmware features of BCM4329 chip. The GET_ASSOCLIST error became especially noisy with a newer NetworkManager version of Ubuntu 21.04. Turn the noisy error messages into info messages and print them out only once. Signed-off-by: Dmitry Osipenko <digetx@gmail.com> Signed-off-by: Kalle Valo <kvalo@codeaurora.org> Link: https://lore.kernel.org/r/20210511211549.30571-2-digetx@gmail.com
2021-06-23cpufreq: Make cpufreq_online() call driver->offline() on errorsRafael J. Wysocki
In the CPU removal path the ->offline() callback provided by the driver is always invoked before ->exit(), but in the cpufreq_online() error path it is not, so ->exit() is expected to somehow know the context in which it has been called and act accordingly. That is less than straightforward, so make cpufreq_online() invoke the driver's ->offline() callback, if present, on errors before ->exit() too. This only potentially affects intel_pstate. Fixes: 91a12e91dc39 ("cpufreq: Allow light-weight tear down and bring up of CPUs") Signed-off-by: Rafael J. Wysocki <rafael.j.wysocki@intel.com> Acked-by: Viresh Kumar <viresh.kumar@linaro.org>
2021-06-23Merge ath-next from git://git.kernel.org/pub/scm/linux/kernel/git/kvalo/ath.gitKalle Valo
ath.git patches for v5.14. Major changes: ath11k * enable support for QCN9074 PCI devices
2021-06-23RDMA/hns: Fix incorrect vlan enable bit in QPCWeihang Li
The QPC_RQ/SQ_VLAN_EN bit in QPC should be enabled, not the QPC mask. Fixes: f0cb411aad23 ("RDMA/hns: Use new interface to modify QP context") Link: https://lore.kernel.org/r/1624438201-11915-1-git-send-email-liweihang@huawei.com Signed-off-by: Weihang Li <liweihang@huawei.com> Signed-off-by: Jason Gunthorpe <jgg@nvidia.com>
2021-06-23software node: Handle software node injection to an existing device properlyHeikki Krogerus
The function software_node_notify() - the function that creates and removes the symlinks between the node and the device - was called unconditionally in device_add_software_node() and device_remove_software_node(), but it needs to be called in those functions only in the special case where the node is added to a device that has already been registered. This fixes NULL pointer dereference that happens if device_remove_software_node() is used with device that was never registered. Fixes: b622b24519f5 ("software node: Allow node addition to already existing device") Reported-and-tested-by: Dominik Brodowski <linux@dominikbrodowski.net> Reviewed-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Signed-off-by: Heikki Krogerus <heikki.krogerus@linux.intel.com> Signed-off-by: Rafael J. Wysocki <rafael.j.wysocki@intel.com>
2021-06-23ACPI: PM: postpone bringing devices to D0 unless we need themDmitry Torokhov
Currently ACPI power domain brings devices into D0 state in the "resume early" phase. Normally this does not cause any issues, as powering up happens quickly. However there are peripherals that have certain timing requirements for powering on, for example some models of Elan touchscreens need 300msec after powering up/releasing reset line before they can accept commands from the host. Such devices will dominate the time spent in early resume phase and cause increase in overall resume time as we wait for early resume to complete before we can proceed to the normal resume stage. There are ways for a driver to indicate that it can tolerate device being in the low power mode and that it knows how to power the device back up when resuming, bit that requires changes to individual drivers that may not really care about details of ACPI controlled power management. This change attempts to solve this issue at ACPI power domain level, by postponing powering up device until we get to the normal resume stage, unless there is early resume handler defined for the device, or device does not declare any resume handlers, in which case we continue powering up such devices early. This allows us to shave off several hundred milliseconds of resume time on affected systems. Signed-off-by: Dmitry Torokhov <dmitry.torokhov@gmail.com> Signed-off-by: Rafael J. Wysocki <rafael.j.wysocki@intel.com>
2021-06-23ACPI: tables: Add custom DSDT file as makefile prerequisiteRichard Fitzgerald
A custom DSDT file is mostly used during development or debugging, and in that case it is quite likely to want to rebuild the kernel after changing ONLY the content of the DSDT. This patch adds the custom DSDT as a prerequisite to tables.o to ensure a rebuild if the DSDT file is updated. Make will merge the prerequisites from multiple rules for the same target. Signed-off-by: Richard Fitzgerald <rf@opensource.cirrus.com> Signed-off-by: Rafael J. Wysocki <rafael.j.wysocki@intel.com>
2021-06-23ACPI: bgrt: Use sysfs_emitNathan Chancellor
sysfs_emit is preferred to snprintf for emitting values after commit 2efc459d06f1 ("sysfs: Add sysfs_emit and sysfs_emit_at to format sysfs output"). Signed-off-by: Nathan Chancellor <nathan@kernel.org> Reviewed-by: Kees Cook <keescook@chromium.org> Signed-off-by: Rafael J. Wysocki <rafael.j.wysocki@intel.com>
2021-06-23ACPI: bgrt: Fix CFI violationNathan Chancellor
clang's Control Flow Integrity requires that every indirect call has a valid target, which is based on the type of the function pointer. The *_show() functions in this file are written as if they will be called from dev_attr_show(); however, they will be called from sysfs_kf_seq_show() because the files were created by sysfs_create_group() and the sysfs ops are based on kobj_sysfs_ops because of kobject_add_and_create(). Because the *_show() functions do not match the type of the show() member in struct kobj_attribute, there is a CFI violation. $ cat /sys/firmware/acpi/bgrt/{status,type,version,{x,y}offset}} 1 0 1 522 307 $ dmesg | grep "CFI failure" [ 267.761825] CFI failure (target: type_show.d5e1ad21498a5fd14edbc5c320906598.cfi_jt+0x0/0x8): [ 267.762246] CFI failure (target: xoffset_show.d5e1ad21498a5fd14edbc5c320906598.cfi_jt+0x0/0x8): [ 267.762584] CFI failure (target: status_show.d5e1ad21498a5fd14edbc5c320906598.cfi_jt+0x0/0x8): [ 267.762973] CFI failure (target: yoffset_show.d5e1ad21498a5fd14edbc5c320906598.cfi_jt+0x0/0x8): [ 267.763330] CFI failure (target: version_show.d5e1ad21498a5fd14edbc5c320906598.cfi_jt+0x0/0x8): Convert these functions to the type of the show() member in struct kobj_attribute so that there is no more CFI violation. Because these functions are all so similar, combine them into a macro. Fixes: d1ff4b1cdbab ("ACPI: Add support for exposing BGRT data") Link: https://github.com/ClangBuiltLinux/linux/issues/1406 Signed-off-by: Nathan Chancellor <nathan@kernel.org> Reviewed-by: Kees Cook <keescook@chromium.org> Signed-off-by: Rafael J. Wysocki <rafael.j.wysocki@intel.com>
2021-06-23i2c: davinci: Simplify with dev_err_probe()Krzysztof Kozlowski
Common pattern of handling deferred probe can be simplified with dev_err_probe(). Less code and the error value gets printed. Signed-off-by: Krzysztof Kozlowski <krzk@kernel.org> Signed-off-by: Wolfram Sang <wsa@kernel.org>
2021-06-23i2c: cadence: Simplify with dev_err_probe()Krzysztof Kozlowski
Common pattern of handling deferred probe can be simplified with dev_err_probe(). Less code and the error value gets printed. Signed-off-by: Krzysztof Kozlowski <krzk@kernel.org> Acked-by: Michal Simek <michal.simek@xilinx.com> Signed-off-by: Wolfram Sang <wsa@kernel.org>
2021-06-23i2c: xiic: Simplify with dev_err_probe()Krzysztof Kozlowski
Common pattern of handling deferred probe can be simplified with dev_err_probe(). Less code and the error value gets printed. Signed-off-by: Krzysztof Kozlowski <krzk@kernel.org> Acked-by: Michal Simek <michal.simek@xilinx.com> Signed-off-by: Wolfram Sang <wsa@kernel.org>
2021-06-23i2c: cadence: Clear HOLD bit before xfer_size register rolls overRaviteja Narayanam
On Xilinx zynq SOC if the delay between address register write and control register write in cdns_mrecv function is more, the xfer size register rolls over and controller is stuck. This is an IP bug and is resolved in later versions of IP. To avoid this scenario, disable the interrupts on the current processor core between the two register writes and enable them later. This can help achieve the timing constraint. Signed-off-by: Raviteja Narayanam <raviteja.narayanam@xilinx.com> Acked-by: Michal Simek <michal.simek@xilinx.com> Signed-off-by: Wolfram Sang <wsa@kernel.org>
2021-06-23Merge remote-tracking branch 'regulator/for-5.14' into regulator-nextMark Brown
2021-06-23Merge remote-tracking branch 'regulator/for-5.13' into regulator-linusMark Brown
2021-06-23Merge series "Support ROCKCHIP SPI new feature" from Jon Lin ↵Mark Brown
<jon.lin@rock-chips.com>: Changes in v10: - The internal CS inactive function is only supported after VER 0x00110002 Changes in v9: - Conver to use CS GPIO description Changes in v8: - There is a problem with the version 7 mail format. resend it Changes in v7: - Fall back "rockchip,rv1126-spi" to "rockchip,rk3066-spi" Changes in v6: - Consider to compatibility, the "rockchip,rk3568-spi" is removed in Series-changes v5, so the commit massage should also remove the corresponding information Changes in v5: - Change to leave one compatible id rv1126, and rk3568 is compatible with rv1126 Changes in v4: - Adjust the order patches - Simply commit massage like redundancy "application" content Changes in v3: - Fix compile error which is find by Sascha in [v2,2/8] Jon Lin (6): dt-bindings: spi: spi-rockchip: add description for rv1126 spi: rockchip: add compatible string for rv1126 spi: rockchip: Set rx_fifo interrupt waterline base on transfer item spi: rockchip: Wait for STB status in slave mode tx_xfer spi: rockchip: Support cs-gpio spi: rockchip: Support SPI_CS_HIGH .../devicetree/bindings/spi/spi-rockchip.yaml | 1 + drivers/spi/spi-rockchip.c | 55 ++++++++++++++----- 2 files changed, 41 insertions(+), 15 deletions(-) -- 2.17.1
2021-06-23spi: spi-sh-msiof: : use proper DMAENGINE API for terminationWolfram Sang
dmaengine_terminate_all() is deprecated in favor of explicitly saying if it should be sync or async. Here, we want dmaengine_terminate_sync() because there is no other synchronization code in the driver to handle an async case. Signed-off-by: Wolfram Sang <wsa+renesas@sang-engineering.com> Link: https://lore.kernel.org/r/20210623095843.3228-3-wsa+renesas@sang-engineering.com Signed-off-by: Mark Brown <broonie@kernel.org>
2021-06-23spi: spi-rspi: : use proper DMAENGINE API for terminationWolfram Sang
dmaengine_terminate_all() is deprecated in favor of explicitly saying if it should be sync or async. Here, we want dmaengine_terminate_sync() because there is no other synchronization code in the driver to handle an async case. Signed-off-by: Wolfram Sang <wsa+renesas@sang-engineering.com> Link: https://lore.kernel.org/r/20210623095843.3228-2-wsa+renesas@sang-engineering.com Signed-off-by: Mark Brown <broonie@kernel.org>
2021-06-23Merge series "ASoC: tlv320aic32x4: Add support for TAS2505" from Claudius ↵Mark Brown
Heine <ch@denx.de>: Hi, this is v2 from my patchset that add support for the TAS2505 to the tlv320aic32x4 driver. kind regards, Claudius Changes from v1: - clarified commit message of first patch, which add the type value to the struct - removed unnecessary code to put and get speaker volume - removed 'Gain' from 'HP Driver Playback Volume' control - fixed rebase issues Claudius Heine (3): ASoC: tlv320aic32x4: add type to device private data struct ASoC: tlv320aic32x4: add support for TAS2505 ASoC: tlv320aic32x4: dt-bindings: add TAS2505 to compatible .../bindings/sound/tlv320aic32x4.txt | 1 + sound/soc/codecs/tlv320aic32x4-i2c.c | 22 ++- sound/soc/codecs/tlv320aic32x4-spi.c | 23 ++- sound/soc/codecs/tlv320aic32x4.c | 139 +++++++++++++++++- sound/soc/codecs/tlv320aic32x4.h | 10 ++ 5 files changed, 186 insertions(+), 9 deletions(-) base-commit: 70585216fe7730d9fb5453d3e2804e149d0fe201 -- 2.32.0
2021-06-23drm/msm/mdp5: provide dynamic bandwidth managementDmitry Baryshkov
Instead of using static bandwidth setup, manage bandwidth dynamically, depending on the amount of allocated planes, their format and resolution. Co-developed-with: James Willcox <jwillcox@squareup.com> Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Reported-by: kernel test robot <lkp@intel.com> Link: https://lore.kernel.org/r/20210525131316.3117809-8-dmitry.baryshkov@linaro.org Signed-off-by: Rob Clark <robdclark@chromium.org>
2021-06-23drm/msm/mdp5: add perf blocks for holding fudge factorsJames Willcox
Prior downstream kernels had "fudge factors" in devicetree which would be applied to things like interconnect bandwidth calculations. Bring some of those values back here. Signed-off-by: James Willcox <jwillcox@squareup.com> [DB: changed _ff to _inefficiency, fixed patch description] Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Link: https://lore.kernel.org/r/20210525131316.3117809-7-dmitry.baryshkov@linaro.org Signed-off-by: Rob Clark <robdclark@chromium.org>
2021-06-23drm/msm/mdp5: switch to standard zpos propertyDmitry Baryshkov
Instead of implemeting zpos property on our own, use standard zpos property support. Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Link: https://lore.kernel.org/r/20210525131316.3117809-6-dmitry.baryshkov@linaro.org Signed-off-by: Rob Clark <robdclark@chromium.org>
2021-06-23drm/msm/mdp5: add support for alpha/blend_mode propertiesDmitry Baryshkov
Hook alpha and pixel blend mode support to be exported as proper DRM plane properties. This allows using this functionality from the userspace. Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Link: https://lore.kernel.org/r/20210525131316.3117809-5-dmitry.baryshkov@linaro.org Signed-off-by: Rob Clark <robdclark@chromium.org>
2021-06-23drm/msm/mdp5: use drm_plane_state for pixel blend modeDmitry Baryshkov
Use drm_plane_state's 'pixel_blend_mode' field rather than using 'premultiplied' field to mdp5_plane_state. Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Link: https://lore.kernel.org/r/20210525131316.3117809-4-dmitry.baryshkov@linaro.org Signed-off-by: Rob Clark <robdclark@chromium.org>
2021-06-23drm/msm/mdp5: use drm_plane_state for storing alpha valueDmitry Baryshkov
Use drm_plane_state's 'alpha' field rather than adding extra 'alpha' field to mdp5_plane_state. Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Link: https://lore.kernel.org/r/20210525131316.3117809-3-dmitry.baryshkov@linaro.org Signed-off-by: Rob Clark <robdclark@chromium.org>
2021-06-23drm/msm/mdp5: use drm atomic helpers to handle base drm plane stateDmitry Baryshkov
Use generic helpers code to manage drm_plane_state part of mdp5_plane state instead of manually coding all the details. Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Link: https://lore.kernel.org/r/20210525131316.3117809-2-dmitry.baryshkov@linaro.org Signed-off-by: Rob Clark <robdclark@chromium.org>
2021-06-23drm/msm/dsi: do not enable PHYs when called for the slave DSI interfaceDmitry Baryshkov
Move the call to dsi_mgr_phy_enable after checking whether the DSI interface is slave, so that PHY enablement happens together with the host enablement. Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Link: https://lore.kernel.org/r/20210609211211.2561090-1-dmitry.baryshkov@linaro.org Signed-off-by: Rob Clark <robdclark@chromium.org>
2021-06-23drm/msm: Add debugfs to trigger shrinkerRob Clark
Just for the purposes of testing. Write to it the # of objects to scan, read back the # freed. Signed-off-by: Rob Clark <robdclark@chromium.org> Link: https://lore.kernel.org/r/20210614150618.729610-1-robdclark@gmail.com Signed-off-by: Rob Clark <robdclark@chromium.org>
2021-06-23drm/msm/dpu: Avoid ABBA deadlock between IRQ modulesBjorn Andersson
Handling of the interrupt callback lists is done in dpu_core_irq.c, under the "cb_lock" spinlock. When these operations results in the need for enableing or disabling the IRQ in the hardware the code jumps to dpu_hw_interrupts.c, which protects its operations with "irq_lock" spinlock. When an interrupt fires, dpu_hw_intr_dispatch_irq() inspects the hardware state while holding the "irq_lock" spinlock and jumps to dpu_core_irq_callback_handler() to invoke the registered handlers, which traverses the callback list under the "cb_lock" spinlock. As such, in the event that these happens concurrently we'll end up with a deadlock. Prior to '1c1e7763a6d4 ("drm/msm/dpu: simplify IRQ enabling/disabling")' the enable/disable of the hardware interrupt was done outside the "cb_lock" region, optimitically by using an atomic enable-counter for each interrupt and an warning print if someone changed the list between the atomic_read and the time the operation concluded. Rather than re-introducing the large array of atomics, this change embraces the fact that dpu_core_irq and dpu_hw_interrupts are deeply entangled and make them share the single "irq_lock". Following this step it's suggested that we squash the two parts into a single irq handling thing. Fixes: 1c1e7763a6d4 ("drm/msm/dpu: simplify IRQ enabling/disabling") Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org> Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Link: https://lore.kernel.org/r/20210611170003.3539059-1-bjorn.andersson@linaro.org Signed-off-by: Rob Clark <robdclark@chromium.org>
2021-06-23drm/msm: devcoredump iommu fault supportRob Clark
Wire up support to stall the SMMU on iova fault, and collect a devcore- dump snapshot for easier debugging of faults. Currently this is a6xx-only, but mostly only because so far it is the only one using adreno-smmu-priv. Signed-off-by: Rob Clark <robdclark@chromium.org> Acked-by: Jordan Crouse <jordan@cosmicpenguin.net> Link: https://lore.kernel.org/r/20210610214431.539029-6-robdclark@gmail.com Signed-off-by: Rob Clark <robdclark@chromium.org>
2021-06-23iommu/arm-smmu-qcom: Add stall supportRob Clark
Add, via the adreno-smmu-priv interface, a way for the GPU to request the SMMU to stall translation on faults, and then later resume the translation, either retrying or terminating the current translation. This will be used on the GPU side to "freeze" the GPU while we snapshot useful state for devcoredump. Signed-off-by: Rob Clark <robdclark@chromium.org> Acked-by: Jordan Crouse <jordan@cosmicpenguin.net> Reviewed-by: Bjorn Andersson <bjorn.andersson@linaro.org> Link: https://lore.kernel.org/r/20210610214431.539029-5-robdclark@gmail.com Signed-off-by: Rob Clark <robdclark@chromium.org>
2021-06-23drm/msm: Improve the a6xx page fault handlerJordan Crouse
Use the new adreno-smmu-priv fault info function to get more SMMU debug registers and print the current TTBR0 to debug per-instance pagetables and figure out which GPU block generated the request. Signed-off-by: Jordan Crouse <jcrouse@codeaurora.org> Signed-off-by: Rob Clark <robdclark@chromium.org> Acked-by: Bjorn Andersson <bjorn.andersson@linaro.org> Link: https://lore.kernel.org/r/20210610214431.539029-4-robdclark@gmail.com Signed-off-by: Rob Clark <robdclark@chromium.org>
2021-06-23iommu/arm-smmu-qcom: Add an adreno-smmu-priv callback to get pagefault infoJordan Crouse
Add a callback in adreno-smmu-priv to read interesting SMMU registers to provide an opportunity for a richer debug experience in the GPU driver. Signed-off-by: Jordan Crouse <jcrouse@codeaurora.org> Signed-off-by: Rob Clark <robdclark@chromium.org> Reviewed-by: Bjorn Andersson <bjorn.andersson@linaro.org> Link: https://lore.kernel.org/r/20210610214431.539029-3-robdclark@gmail.com Signed-off-by: Rob Clark <robdclark@chromium.org>
2021-06-23iommu/arm-smmu: Add support for driver IOMMU fault handlersJordan Crouse
Call report_iommu_fault() to allow upper-level drivers to register their own fault handlers. Signed-off-by: Jordan Crouse <jcrouse@codeaurora.org> Signed-off-by: Rob Clark <robdclark@chromium.org> Acked-by: Will Deacon <will@kernel.org> Reviewed-by: Bjorn Andersson <bjorn.andersson@linaro.org> Link: https://lore.kernel.org/r/20210610214431.539029-2-robdclark@gmail.com Signed-off-by: Rob Clark <robdclark@chromium.org>
2021-06-23drm/msm: export hangcheck_period in debugfsSamuel Iglesias Gonsalvez
While keeping the previous default value for hangcheck period, we allow now the possibility of configuring its value via debugfs. Signed-off-by: Samuel Iglesias Gonsalvez <siglesias@igalia.com> Link: https://lore.kernel.org/r/20210607104441.184700-1-siglesias@igalia.com Signed-off-by: Rob Clark <robdclark@chromium.org>
2021-06-23drm/msm/a6xx: add support for Adreno 660 GPUJonathan Marek
Add adreno_is_{a660,a650_family} helpers and convert update existing adreno_is_a650 usage based on downstream driver's logic (changing into adreno_is_a650_family or adding adreno_is_a660). And add the remaining changes required for A660, again based on the downstream driver: missing GMU allocations, additional register init, dummy hfi BW table, cp protect list, entry in gpulist table, hwcg table, updated a6xx_ucode_check_version check. Signed-off-by: Jonathan Marek <jonathan@marek.ca> Link: https://lore.kernel.org/r/20210608172808.11803-6-jonathan@marek.ca Signed-off-by: Rob Clark <robdclark@chromium.org>
2021-06-23drm/msm/a6xx: add missing PC_DBG_ECO_CNTL bit for a640/a650Jonathan Marek
See downstream's "disable_tseskip" flag. Signed-off-by: Jonathan Marek <jonathan@marek.ca> Link: https://lore.kernel.org/r/20210608172808.11803-5-jonathan@marek.ca Signed-off-by: Rob Clark <robdclark@chromium.org>
2021-06-23drm/msm/a6xx: add GMU_CX_GMU_CX_FALNEXT_INTF write for a650Jonathan Marek
downstream msm-5.14 kernel added a write to this register, so match that. Signed-off-by: Jonathan Marek <jonathan@marek.ca> Link: https://lore.kernel.org/r/20210608172808.11803-4-jonathan@marek.ca Signed-off-by: Rob Clark <robdclark@chromium.org>
2021-06-23drm/msm/a6xx: use AOP-initialized PDC for a650Jonathan Marek
SM8250 AOP firmware already sets up PDC registers for us, and it only needs to be enabled. This path will be used for other newer GPUs. Signed-off-by: Jonathan Marek <jonathan@marek.ca> Link: https://lore.kernel.org/r/20210608172808.11803-3-jonathan@marek.ca Signed-off-by: Rob Clark <robdclark@chromium.org>
2021-06-23drm/msm: remove unused icc_path/ocmem_icc_pathJonathan Marek
These aren't used by anything anymore. Signed-off-by: Jonathan Marek <jonathan@marek.ca> Reviewed-by: Akhil P Oommen <akhilpo@codeaurora.org> Link: https://lore.kernel.org/r/20210608172808.11803-2-jonathan@marek.ca Signed-off-by: Rob Clark <robdclark@chromium.org>
2021-06-23drm/msm: Generated register updateRob Clark
Based on mesa commit daa2ccff7a0201941db3901780d179e2634057d5 Small bit of .c churn in the phy code to adapt to split up of phy related registers. Signed-off-by: Rob Clark <robdclark@chromium.org>
2021-06-23drm/msm/dpu: hw_blk: make dpu_hw_blk empty opaque structureDmitry Baryshkov
The code does not really use dpu_hw_blk fields, so drop them, making dpu_hw_blk empty structure. Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Link: https://lore.kernel.org/r/20210515190909.1809050-5-dmitry.baryshkov@linaro.org Reviewed-by: Abhinav Kumar <abhinavk@codeaurora.org> Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Signed-off-by: Rob Clark <robdclark@chromium.org>
2021-06-23drm/msm/dpu: use struct dpu_hw_merge_3d in dpu_hw_pingpongDmitry Baryshkov
Use struct dpu_hw_merge_3d pointer in struct dpu_hw_pingpong rather than using struct dpu_hw_blk. This is the only user of dpu_hw_blk.id, which will be cleaned in the next patch. Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Link: https://lore.kernel.org/r/20210515190909.1809050-4-dmitry.baryshkov@linaro.org Reviewed-by: Abhinav Kumar <abhinavk@codeaurora.org> Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Signed-off-by: Rob Clark <robdclark@chromium.org>
2021-06-23drm/msm/dpu: drop dpu_hw_blk_destroy functionDmitry Baryshkov
The dpu_hw_blk_destroy() function is empty, so we can drop it now. Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Link: https://lore.kernel.org/r/20210515190909.1809050-3-dmitry.baryshkov@linaro.org Reviewed-by: Abhinav Kumar <abhinavk@codeaurora.org> Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Signed-off-by: Rob Clark <robdclark@chromium.org>
2021-06-23drm/msm/dpu: remove unused dpu_hw_blk featuresDmitry Baryshkov
Remove all unused dpu_hw_blk features and functions: - dpu_hw_blk_get()/_put() and respective refcounting, - global list of all dpu_hw_blk instances, - dpu_hw_blk_ops and empty implementation inside each hw_blk subdriver. This leaves dpu_hw_blk as a placeholder with just type and index. Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Link: https://lore.kernel.org/r/20210515190909.1809050-2-dmitry.baryshkov@linaro.org Reviewed-by: Abhinav Kumar <abhinavk@codeaurora.org> Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Signed-off-by: Rob Clark <robdclark@chromium.org>
2021-06-23drm/msm/dsi: print error code when MIPI DSI host registration failsDmitry Baryshkov
In order to ease debugging of DSI host registration issues, print return code of dsi_mgr_setup_components(). Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Reviewed-by: Abhinav Kumar <abhinavk@codeaurora.org> Signed-off-by: Rob Clark <robdclark@chromium.org>
generated by cgit (git 2.34.1) at 2025-09-18 02:09:27 +0000