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2021-02-11net/mlx5: Disable devlink reload for lag devicesShay Drory
Devlink reload can't be allowed on lag devices since reloading one lag device will cause traffic on the bond to get stucked. Users who wish to reload a lag device, need to remove the device from the bond, and only then reload it. Fixes: 4383cfcc65e7 ("net/mlx5: Add devlink reload") Signed-off-by: Shay Drory <shayd@nvidia.com> Reviewed-by: Moshe Shemesh <moshe@nvidia.com> Signed-off-by: Saeed Mahameed <saeedm@nvidia.com>
2021-02-11net/mlx5: Disallow RoCE on lag deviceShay Drory
In lag mode, setting roce enabled/disable of lag device have no effect. e.g.: bond device (roce/vf_lag) roce status remain unchanged. Therefore disable it and add an error message. Fixes: cc9defcbb8fa ("net/mlx5: Handle "enable_roce" devlink param") Signed-off-by: Shay Drory <shayd@nvidia.com> Reviewed-by: Moshe Shemesh <moshe@nvidia.com> Signed-off-by: Saeed Mahameed <saeedm@nvidia.com>
2021-02-11net/mlx5: Disallow RoCE on multi port slave deviceShay Drory
In dual port mode, setting roce enabled/disable for the slave device have no effect. e.g.: the slave device roce status remain unchanged. Therefore disable it and add an error message. Enable or disable roce of the master device affect both master and slave devices. Fixes: cc9defcbb8fa ("net/mlx5: Handle "enable_roce" devlink param") Signed-off-by: Shay Drory <shayd@nvidia.com> Reviewed-by: Moshe Shemesh <moshe@nvidia.com> Signed-off-by: Saeed Mahameed <saeedm@nvidia.com>
2021-02-11net/mlx5: Disable devlink reload for multi port slave deviceShay Drory
Devlink reload can't be allowed on a multi port slave device, because reload of slave device doesn't take effect. The right flow is to disable devlink reload for multi port slave device. Hence, disabling it in mlx5_core probing. Fixes: 4383cfcc65e7 ("net/mlx5: Add devlink reload") Signed-off-by: Shay Drory <shayd@nvidia.com> Reviewed-by: Moshe Shemesh <moshe@nvidia.com> Signed-off-by: Saeed Mahameed <saeedm@nvidia.com>
2021-02-11net/mlx5e: kTLS, Use refcounts to free kTLS RX priv contextMaxim Mikityanskiy
wait_for_resync is unreliable - if it timeouts, priv_rx will be freed anyway. However, mlx5e_ktls_handle_get_psv_completion will be called sooner or later, leading to use-after-free. For example, it can happen if a CQ error happened, and ICOSQ stopped, but later on the queues are destroyed, and ICOSQ is flushed with mlx5e_free_icosq_descs. This patch converts the lifecycle of priv_rx to fully refcount-based, so that the struct won't be freed before the refcount goes to zero. Fixes: 0419d8c9d8f8 ("net/mlx5e: kTLS, Add kTLS RX resync support") Signed-off-by: Maxim Mikityanskiy <maximmi@mellanox.com> Reviewed-by: Tariq Toukan <tariqt@nvidia.com> Signed-off-by: Saeed Mahameed <saeedm@nvidia.com>
2021-02-11net/mlx5e: Fix CQ params of ICOSQ and async ICOSQMaxim Mikityanskiy
The commit mentioned below has split the parameters of ICOSQ and async ICOSQ, but it contained a typo: the CQ parameters were swapped for ICOSQ and async ICOSQ. Async ICOSQ is longer than the normal ICOSQ, and the CQ size must be the same as the size of the corresponding SQ, but due to this bug, the CQ of async ICOSQ was much shorter than async ICOSQ itself. It led to overflows of the CQ with such messages in dmesg, in particular, when running multiple kTLS-offloaded streams: mlx5_core 0000:08:00.0: cq_err_event_notifier:529:(pid 9422): CQ error on CQN 0x406, syndrome 0x1 mlx5_core 0000:08:00.0 eth2: mlx5e_cq_error_event: cqn=0x000406 event=0x04 This commit fixes the issue by using the corresponding parameters for ICOSQ and async ICOSQ. Fixes: c293ac927fbb ("net/mlx5e: Refactor build channel params") Signed-off-by: Maxim Mikityanskiy <maximmi@mellanox.com> Reviewed-by: Tariq Toukan <tariqt@nvidia.com> Signed-off-by: Saeed Mahameed <saeedm@nvidia.com>
2021-02-11net/mlx5e: Replace synchronize_rcu with synchronize_netMaxim Mikityanskiy
The commit cited below switched from using napi_synchronize to synchronize_rcu to have a guarantee that it will finish in finite time. However, on average, synchronize_rcu takes more time than napi_synchronize. Given that it's called multiple times per channel on deactivation, it accumulates to a significant amount, which causes timeouts in some applications (for example, when using bonding with NetworkManager). This commit replaces synchronize_rcu with synchronize_net, which is faster when called under rtnl_lock, allowing to speed up the described flow. Fixes: 9c25a22dfb00 ("net/mlx5e: Use synchronize_rcu to sync with NAPI") Signed-off-by: Maxim Mikityanskiy <maximmi@mellanox.com> Reviewed-by: Tariq Toukan <tariqt@nvidia.com> Signed-off-by: Saeed Mahameed <saeedm@nvidia.com>
2021-02-11net/mlx5: Fix health error state handlingShay Drory
Currently, when we discover a fatal error, we are queueing a work that will wait for a lock in order to enter the device to error state. Meanwhile, FW commands are still being processed, and gets timeouts. This can block the driver for few minutes before the work will manage to get the lock and enter to error state. Setting the device to error state before queueing health work, in order to avoid FW commands being processed while the work is waiting for the lock. Fixes: c1d4d2e92ad6 ("net/mlx5: Avoid calling sleeping function by the health poll thread") Signed-off-by: Shay Drory <shayd@nvidia.com> Reviewed-by: Moshe Shemesh <moshe@nvidia.com> Signed-off-by: Saeed Mahameed <saeedm@nvidia.com>
2021-02-11net/mlx5e: Change interrupt moderation channel params also when channels are ↵Maxim Mikityanskiy
closed struct mlx5e_params contains fields ({rx,tx}_cq_moderation) that depend on two things: whether DIM is enabled and the state of a private flag (MLX5E_PFLAG_{RX,TX}_CQE_BASED_MODER). Whenever the DIM state changes, mlx5e_reset_{rx,tx}_moderation is called to update the fields, however, only if the channels are open. The flow where the channels are closed misses the required update of the fields. This commit moves the calls of mlx5e_reset_{rx,tx}_moderation, so that they run in both flows. Fixes: ebeaf084ad5c ("net/mlx5e: Properly set default values when disabling adaptive moderation") Signed-off-by: Maxim Mikityanskiy <maximmi@mellanox.com> Reviewed-by: Tariq Toukan <tariqt@nvidia.com> Signed-off-by: Saeed Mahameed <saeedm@nvidia.com>
2021-02-11net/mlx5e: Don't change interrupt moderation params when DIM is enabledMaxim Mikityanskiy
When mlx5e_ethtool_set_coalesce doesn't change DIM state (enabled/disabled), it calls mlx5e_set_priv_channels_coalesce unconditionally, which in turn invokes a firmware command to set interrupt moderation parameters. It shouldn't happen while DIM manages those parameters dynamically (it might even be happening at the same time). This patch fixes it by splitting mlx5e_set_priv_channels_coalesce into two functions (for RX and TX) and calling them only when DIM is disabled (for RX and TX respectively). Fixes: cb3c7fd4f839 ("net/mlx5e: Support adaptive RX coalescing") Signed-off-by: Maxim Mikityanskiy <maximmi@mellanox.com> Reviewed-by: Tariq Toukan <tariqt@nvidia.com> Signed-off-by: Saeed Mahameed <saeedm@nvidia.com>
2021-02-11net/mlx5e: Enable XDP for Connect-X IPsec capable devicesRaed Salem
This limitation was inherited by previous Innova (FPGA) IPsec implementation, it uses its private set of RQ handlers which does not support XDP, for Connect-X this is no longer true. Fix by keeping this limitation only for Innova IPsec supporting devices, as otherwise this limitation effectively wrongly blocks XDP for all future Connect-X devices for all flows even if IPsec offload is not used. Fixes: 2d64663cd559 ("net/mlx5: IPsec: Add HW crypto offload support") Signed-off-by: Raed Salem <raeds@nvidia.com> Reviewed-by: Alaa Hleihel <alaa@nvidia.com> Reviewed-by: Tariq Toukan <tariqt@nvidia.com> Signed-off-by: Saeed Mahameed <saeedm@nvidia.com>
2021-02-11net/mlx5e: Enable striding RQ for Connect-X IPsec capable devicesRaed Salem
This limitation was inherited by previous Innova (FPGA) IPsec implementation, it uses its private set of RQ handlers which does not support striding rq, for Connect-X this is no longer true. Fix by keeping this limitation only for Innova IPsec supporting devices, as otherwise this limitation effectively wrongly blocks striding RQs for all future Connect-X devices for all flows even if IPsec offload is not used. Fixes: 2d64663cd559 ("net/mlx5: IPsec: Add HW crypto offload support") Signed-off-by: Raed Salem <raeds@nvidia.com> Reviewed-by: Tariq Toukan <tariqt@nvidia.com> Signed-off-by: Saeed Mahameed <saeedm@nvidia.com>
2021-02-11net/mlx5e: E-switch, Fix rate calculation for overflowParav Pandit
rate_bytes_ps is a 64-bit field. It passed as 32-bit field to apply_police_params(). Due to this when police rate is higher than 4Gbps, 32-bit calculation ignores the carry. This results in incorrect rate configurationn the device. Fix it by performing 64-bit calculation. Fixes: fcb64c0f5640 ("net/mlx5: E-Switch, add ingress rate support") Signed-off-by: Parav Pandit <parav@nvidia.com> Reviewed-by: Eli Cohen <elic@nvidia.com> Signed-off-by: Saeed Mahameed <saeedm@nvidia.com>
2021-02-11net: phy: consider that suspend2ram may cut off PHY powerHeiner Kallweit
Claudiu reported that on his system S2R cuts off power to the PHY and after resuming certain PHY settings are lost. The PM folks confirmed that cutting off power to selected components in S2R is a valid case. Therefore resuming from S2R, same as from hibernation, has to assume that the PHY has power-on defaults. As a consequence use the restore callback also as resume callback. In addition make sure that the interrupt configuration is restored. Let's do this in phy_init_hw() and ensure that after this call actual interrupt configuration is in sync with phydev->interrupts. Currently, if interrupt was enabled before hibernation, we would resume with interrupt disabled because that's the power-on default. This fix applies cleanly only after the commit marked as fixed. I don't have an affected system, therefore change is compile-tested only. [0] https://lore.kernel.org/netdev/1610120754-14331-1-git-send-email-claudiu.beznea@microchip.com/ Fixes: 611d779af7ca ("net: phy: fix MDIO bus PM PHY resuming") Reported-by: Claudiu Beznea <claudiu.beznea@microchip.com> Signed-off-by: Heiner Kallweit <hkallweit1@gmail.com> Signed-off-by: David S. Miller <davem@davemloft.net>
2021-02-11r8169: handle tx before rx in napi pollHeiner Kallweit
Cleaning up tx descriptors first increases the chance that rtl_rx() can allocate new skb's from the cache. Signed-off-by: Heiner Kallweit <hkallweit1@gmail.com> Signed-off-by: David S. Miller <davem@davemloft.net>
2021-02-11dpaa2-eth: fix memory leak in XDP_REDIRECTIoana Ciornei
If xdp_do_redirect() fails, the calling driver should handle recycling or freeing of the page associated with the frame. The dpaa2-eth driver didn't do either of them and just incremented a counter. Fix this by trying to DMA map back the page and recycle it or, if the mapping fails, just free it. Fixes: d678be1dc1ec ("dpaa2-eth: add XDP_REDIRECT support") Signed-off-by: Ioana Ciornei <ioana.ciornei@nxp.com> Signed-off-by: David S. Miller <davem@davemloft.net>
2021-02-11net: fix dev_ifsioc_locked() race conditionCong Wang
dev_ifsioc_locked() is called with only RCU read lock, so when there is a parallel writer changing the mac address, it could get a partially updated mac address, as shown below: Thread 1 Thread 2 // eth_commit_mac_addr_change() memcpy(dev->dev_addr, addr->sa_data, ETH_ALEN); // dev_ifsioc_locked() memcpy(ifr->ifr_hwaddr.sa_data, dev->dev_addr,...); Close this race condition by guarding them with a RW semaphore, like netdev_get_name(). We can not use seqlock here as it does not allow blocking. The writers already take RTNL anyway, so this does not affect the slow path. To avoid bothering existing dev_set_mac_address() callers in drivers, introduce a new wrapper just for user-facing callers on ioctl and rtnetlink paths. Note, bonding also changes slave mac addresses but that requires a separate patch due to the complexity of bonding code. Fixes: 3710becf8a58 ("net: RCU locking for simple ioctl()") Reported-by: "Gong, Sishuai" <sishuai@purdue.edu> Cc: Eric Dumazet <eric.dumazet@gmail.com> Cc: Jakub Kicinski <kuba@kernel.org> Signed-off-by: Cong Wang <cong.wang@bytedance.com> Signed-off-by: David S. Miller <davem@davemloft.net>
2021-02-11enetc: auto select PHYLIB and MDIO_DEVRESTong Zhang
FSL_ENETC_MDIO use symbols from PHYLIB (MDIO_BUS) and MDIO_DEVRES, however there are no dependency specified in Kconfig ERROR: modpost: "__mdiobus_register" [drivers/net/ethernet/freescale/enetc/fsl-enetc-mdio.ko] undefined! ERROR: modpost: "mdiobus_unregister" [drivers/net/ethernet/freescale/enetc/fsl-enetc-mdio.ko] undefined! ERROR: modpost: "devm_mdiobus_alloc_size" [drivers/net/ethernet/freescale/enetc/fsl-enetc-mdio.ko] undefined! add depends on MDIO_DEVRES && MDIO_BUS Signed-off-by: Tong Zhang <ztong0001@gmail.com> Signed-off-by: David S. Miller <davem@davemloft.net>
2021-02-11net: mvpp2: fix interrupt mask/unmask skip conditionStefan Chulski
The condition should be skipped if CPU ID equal to nthreads. The patch doesn't fix any actual issue since nthreads = min_t(unsigned int, num_present_cpus(), MVPP2_MAX_THREADS). On all current Armada platforms, the number of CPU's is less than MVPP2_MAX_THREADS. Fixes: e531f76757eb ("net: mvpp2: handle cases where more CPUs are available than s/w threads") Reported-by: Russell King <rmk+kernel@armlinux.org.uk> Signed-off-by: Stefan Chulski <stefanc@marvell.com> Reviewed-by: Russell King <rmk+kernel@armlinux.org.uk> Signed-off-by: David S. Miller <davem@davemloft.net>
2021-02-11net: ti: am65-cpsw-nuss: Add switchdev supportVignesh Raghavendra
J721e, J7200 and AM64 have multi port switches which can work in multi mac mode and in switch mode. Add support for configuring this HW in switch mode using devlink and switchdev notifiers. Support is similar to existing CPSW switchdev implementation of TI's 32 bit platform like AM33/AM43/AM57. To enable switch mode: devlink dev param set platform/8000000.ethernet name switch_mode value true cmode runtime All configuration is implemented via switchdev API and notifiers. Supported: - SWITCHDEV_ATTR_ID_PORT_PRE_BRIDGE_FLAGS - SWITCHDEV_ATTR_ID_PORT_BRIDGE_FLAGS - SWITCHDEV_ATTR_ID_PORT_STP_STATE - SWITCHDEV_OBJ_ID_PORT_VLAN - SWITCHDEV_OBJ_ID_PORT_MDB - SWITCHDEV_OBJ_ID_HOST_MDB Hence AM65 CPSW switchdev driver supports: - FDB offloading - MDB offloading - VLAN filtering and offloading - STP Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com> Signed-off-by: David S. Miller <davem@davemloft.net>
2021-02-11net: ti: am65-cpsw-nuss: Add netdevice notifiersVignesh Raghavendra
Register netdevice notifiers in order to receive notification when individual MAC ports are added to the HW bridge. Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com> Signed-off-by: David S. Miller <davem@davemloft.net>
2021-02-11net: ti: am65-cpsw-nuss: Add devlink supportVignesh Raghavendra
AM65 NUSS ethernet switch on K3 devices can be configured to work either in independent mac mode where each port acts as independent network interface (multi mac) or switch mode. Add devlink hooks to provide a way to switch b/w these modes. Rationale to use devlink instead of defaulting to bridge mode is that SoC use cases require to support multiple independent MAC ports with no switching so that users can use software bridges with multi-mac configuration (e.g: to support LAG, HSR/PRP, etc). Also, switching between multi mac and switch mode requires significant Port and ALE reconfiguration, therefore is easier to be made as part of mode change devlink hooks. It also allows to keep user interface similar to what was implemented for the previous generation of TI CPSW IP (on AM33/AM43/AM57 SoCs). Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com> Signed-off-by: David S. Miller <davem@davemloft.net>
2021-02-12Merge tag 'drm-intel-fixes-2021-02-11' of ↵Dave Airlie
git://anongit.freedesktop.org/drm/drm-intel into drm-fixes drm/i915 fixes for v5.11 final: - Ensure Type-C FIA is powered when initializing - Fix overlay frontbuffer tracking Signed-off-by: Dave Airlie <airlied@redhat.com> From: Jani Nikula <jani.nikula@intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/87r1lnc78t.fsf@intel.com
2021-02-11net: broadcom: bcm4908_enet: fix endianness in xmit codeRafał Miłecki
Use le32_to_cpu() for reading __le32 struct field filled by hw. Signed-off-by: Rafał Miłecki <rafal@milecki.pl> Reviewed-by: Florian Fainelli <f.fainelli@gmail.com> Signed-off-by: David S. Miller <davem@davemloft.net>
2021-02-11net: broadcom: bcm4908_enet: fix received skb lengthRafał Miłecki
Use ETH_FCS_LEN instead of magic value and drop incorrect + 2 Signed-off-by: Rafał Miłecki <rafal@milecki.pl> Reviewed-by: Florian Fainelli <f.fainelli@gmail.com> Signed-off-by: David S. Miller <davem@davemloft.net>
2021-02-11net: broadcom: bcm4908_enet: fix minor typosRafał Miłecki
1. Fix "ensable" typo noticed by Andrew 2. Fix chipset name in the struct net_device_ops variable Suggested-by: Andrew Lunn <andrew@lunn.ch> Signed-off-by: Rafał Miłecki <rafal@milecki.pl> Reviewed-by: Andrew Lunn <andrew@lunn.ch> Reviewed-by: Florian Fainelli <f.fainelli@gmail.com> Signed-off-by: David S. Miller <davem@davemloft.net>
2021-02-11net: broadcom: bcm4908_enet: drop "inline" from C functionsRafał Miłecki
It seems preferred to let compiler optimize code if applicable. While at it drop unused enet_umac_maskset(). Suggested-by: Andrew Lunn <andrew@lunn.ch> Signed-off-by: Rafał Miłecki <rafal@milecki.pl> Reviewed-by: Andrew Lunn <andrew@lunn.ch> Reviewed-by: Florian Fainelli <f.fainelli@gmail.com> Signed-off-by: David S. Miller <davem@davemloft.net>
2021-02-11net: broadcom: bcm4908_enet: drop unneeded memset()Rafał Miłecki
dma_alloc_coherent takes care of zeroing allocated memory Suggested-by: Andrew Lunn <andrew@lunn.ch> Signed-off-by: Rafał Miłecki <rafal@milecki.pl> Reviewed-by: Andrew Lunn <andrew@lunn.ch> Reviewed-by: Florian Fainelli <f.fainelli@gmail.com> Signed-off-by: David S. Miller <davem@davemloft.net>
2021-02-11net: broadcom: rename BCM4908 driver & update DT bindingRafał Miłecki
compatible string was updated to match normal naming convention so update driver as well Signed-off-by: Rafał Miłecki <rafal@milecki.pl> Reviewed-by: Florian Fainelli <f.fainelli@gmail.com> Signed-off-by: David S. Miller <davem@davemloft.net>
2021-02-11Merge branch 'for-upstream' of git://git.kernel.org/pub/scm/linux/kernDavid S. Miller
el/git/bluetooth/bluetooth-next Johan Hedberg says: ==================== pull request: bluetooth-next 2021-02-11 Here's the main bluetooth-next pull request for 5.12: - Add support for advertising monitor offliading using Microsoft vendor extensions - Add firmware download support for MediaTek MT7921U USB devices - Suspend-related fixes for Qualcomm devices - Add support for Intel GarfieldPeak controller - Various other smaller fixes & cleanups Please let me know if there are any issues pulling. Thanks. ==================== Signed-off-by: David S. Miller <davem@davemloft.net>
2021-02-11octeontx2-af: cn10k: MAC internal loopback supportHariprasad Kelam
MAC on CN10K silicon support loopback for selftest or debug purposes. This patch does necessary configuration to loopback packets upon receiving request from LMAC mapped RVU PF's netdev via mailbox. Also MAC (CGX) on OcteonTx2 silicon variants and MAC (RPM) on OcteonTx3 CN10K are different and loopback needs to be configured differently. Upper layer interface between RVU AF and PF netdev is kept same. Based on silicon variant appropriate fn() pointer is called to config the MAC. Signed-off-by: Hariprasad Kelam <hkelam@marvell.com> Signed-off-by: Geetha sowjanya <gakula@marvell.com> Signed-off-by: Sunil Goutham <sgoutham@marvell.com> Reported-by: kernel test robot <lkp@intel.com> Signed-off-by: David S. Miller <davem@davemloft.net>
2021-02-11octeontx2-af: cn10k: Add RPM Rx/Tx stats supportHariprasad Kelam
RPM supports below list of counters as an extension to existing counters * class based flow control pause frames * vlan/jabber/fragmented packets * fcs/alignment/oversized error packets This patch adds support to display supported RPM counters via debugfs and define new mbox rpm_stats to read all support counters. Signed-off-by: Hariprasad Kelam <hkelam@marvell.com> Signed-off-by: Geetha sowjanya <gakula@marvell.com> Signed-off-by: Sunil Kovvuri Goutham <Sunil.Goutham@cavium.com> Signed-off-by: David S. Miller <davem@davemloft.net>
2021-02-11octeontx2-af: cn10k: Add RPM LMAC pause frame supportRakesh Babu
Flow control configuration is different for CGX(Octeontx2) and RPM(CN10K) functional blocks. This patch adds the necessary changes for RPM to support 802.3 pause frames configuration on cn10k platforms. Signed-off-by: Rakesh Babu <rsaladi2@marvell.com> Signed-off-by: Geetha sowjanya <gakula@marvell.com> Signed-off-by: Sunil Kovvuri Goutham <Sunil.Goutham@cavium.com> Signed-off-by: David S. Miller <davem@davemloft.net>
2021-02-11octeontx2-pf: cn10k: Get max mtu supported from admin functionHariprasad Kelam
CN10K supports max MTU of 16K on LMAC links and 64k on LBK links and Octeontx2 silicon supports 9K mtu on both links. Get the same from nix_get_hw_info mbox message in netdev probe. This patch also calculates receive buffer size required based on the MTU set. Signed-off-by: Hariprasad Kelam <hkelam@marvell.com> Signed-off-by: Subbaraya Sundeep <sbhatta@marvell.com> Signed-off-by: Geetha sowjanya <gakula@marvell.com> Signed-off-by: Sunil Goutham <sgoutham@marvell.com> Signed-off-by: David S. Miller <davem@davemloft.net>
2021-02-11octeontx2-af: cn10K: Add MTU configurationHariprasad Kelam
OcteonTx3 CN10K silicon supports bigger MTU when compared to 9216 MTU supported by OcteonTx2 silicon variants. Lookback interface supports upto 64K and RPM LMAC interfaces support upto 16K. This patch does the necessary configuration and adds support for PF/VF drivers to retrieve max packet size supported via mbox This patch also configures tx link credit by considering supported fifo size and max packet length for Octeontx3 silicon. This patch also removes platform specific name from the driver name. Signed-off-by: Hariprasad Kelam <hkelam@marvell.com> Signed-off-by: Geetha sowjanya <gakula@marvell.com> Signed-off-by: Sunil Goutham <sgoutham@marvell.com> Signed-off-by: David S. Miller <davem@davemloft.net>
2021-02-11octeontx2-af: cn10k: Add support for programmable channelsSubbaraya Sundeep
NIX uses unique channel numbers to identify the packet sources/sinks like CGX,LBK and SDP. The channel numbers assigned to each block are hardwired in CN9xxx silicon. The fixed channel numbers in CN9xxx are: 0x0 | a << 8 | b - LBK(0..3)_CH(0..63) 0x0 | a << 8 - Reserved 0x700 | a - SDP_CH(0..255) 0x800 | a << 8 | b << 4 | c - CGX(0..7)_LMAC(0..3)_CH(0..15) All the channels in the above fixed enumerator(with maximum number of blocks) are not required since some chips have less number of blocks. For CN10K silicon the channel numbers need to be programmed by software in each block with the base channel number and range of channels. This patch calculates and assigns the channel numbers to efficiently distribute the channel number range(0-4095) among all the blocks. The assignment is made based on the actual number of blocks present and also contiguously leaving no holes. The channel numbers remaining after the math are used as new CPT replay channels present in CN10K. Also since channel numbers are not fixed the transmit channel link number needed by AF consumers is calculated by AF and sent along with nix_lf_alloc mailbox response. Signed-off-by: Subbaraya Sundeep <sbhatta@marvell.com> Signed-off-by: Geetha sowjanya <gakula@marvell.com> Signed-off-by: Sunil Goutham <sgoutham@marvell.com> Signed-off-by: David S. Miller <davem@davemloft.net>
2021-02-11octeontx2-af: cn10k: Add RPM MAC supportHariprasad Kelam
OcteonTx2's next gen platform the CN10K has RPM MAC which has a different serdes when compared to CGX MAC. Though the underlying HW is different, the CSR interface has been designed largely inline with CGX MAC, with few exceptions though. So we are using the same CGX driver for RPM MAC as well and will have a different set of APIs for RPM where ever necessary. This patch adds initial support for CN10K's RPM MAC i.e. the driver registration, communication with firmware etc. For communication with firmware, RPM provides a different IRQ when compared to CGX. The CGX and RPM blocks support different features. Currently few features like ptp, flowcontrol and higig are not supported by RPM. This patch adds new mailbox message "CGX_FEATURES_GET" to get the list of features supported by underlying MAC. RPM has different implementations for RX/TX stats. Unlike CGX, bar offset of stat registers are different. This patch adds support to access the same and dump the values in debugfs. Signed-off-by: Hariprasad Kelam <hkelam@marvell.com> Signed-off-by: Subbaraya Sundeep <sbhatta@marvell.com> Signed-off-by: Geetha sowjanya <gakula@marvell.com> Signed-off-by: Sunil Goutham <sgoutham@marvell.com> Signed-off-by: David S. Miller <davem@davemloft.net>
2021-02-11octeontx2-pf: cn10k: Use LMTST lines for NPA/NIX operationsGeetha sowjanya
This patch adds support to use new LMTST lines for NPA batch free and burst SQE flush. Adds new dev_hw_ops structure to hold platform specific functions and create new files cn10k.c and cn10k.h. Signed-off-by: Geetha sowjanya <gakula@marvell.com> Signed-off-by: Sunil Goutham <sgoutham@marvell.com> Signed-off-by: David S. Miller <davem@davemloft.net>
2021-02-11octeontx2-pf: cn10k: Map LMTST regionGeetha sowjanya
On CN10K platform transmit/receive buffer alloc and free from/to hardware had changed to support burst operation. Whereas pervious silicon's only support single buffer free at a time. To Support the same firmware allocates a DRAM region for each PF/VF for storing LMTLINES. These LMTLINES are used for NPA batch free and for flushing SQE to the hardware. PF/VF LMTST region is accessed via BAR4. PFs LMTST region is followed by its VFs mbox memory. The size of region varies from 2KB to 256KB based on number of LMTLINES configured. This patch adds support for - Mapping PF/VF LMTST region. - Reserves 0-71 (RX + TX + XDP) LMTST lines for NPA batch free operation. - Reserves 72-512 LMTST lines for NIX SQE flush. Signed-off-by: Geetha sowjanya <gakula@marvell.com> Signed-off-by: Sunil Goutham <sgoutham@marvell.com> Signed-off-by: David S. Miller <davem@davemloft.net>
2021-02-11octeontx2-pf: cn10k: Initialise NIX contextGeetha sowjanya
On CN10K platform NIX RQ and SQ context structure got changed. This patch uses new mbox message "NIX_CN10K_AQ_ENQ" for NIX context initialization on CN10K platform. This patch also updates the nix_rx_parse_s and nix_sqe_sg_s structures to add packet steering bit feilds. Signed-off-by: Geetha sowjanya <gakula@marvell.com> Signed-off-by: Sunil Goutham <sgoutham@marvell.com> Signed-off-by: David S. Miller <davem@davemloft.net>
2021-02-11octeontx2-af: cn10k: Update NIX and NPA context in debugfsGeetha sowjanya
On CN10K platform NPA and NIX context structure bit fields had changed to support new features like bandwidth steering etc. This patch dumps approprate context for CN10K platform. Signed-off-by: Geetha sowjanya <gakula@marvell.com> Signed-off-by: Sunil Goutham <sgoutham@marvell.com> Signed-off-by: David S. Miller <davem@davemloft.net>
2021-02-11octeontx2-af: cn10k: Update NIX/NPA context structureGeetha sowjanya
NIX hardware context structure got changed to accommodate new features like bandwidth steering, L3/L4 outer/inner checksum enable/disable etc., on CN10K platform. This patch defines new mbox message NIX_CN10K_AQ_INST for new NIX context initialization. This patch also updates the NPA context structures to accommodate bit field changes made for CN10K platform. This patch also removes Big endian bit fields from existing structures as its support got deprecated in current and upcoming silicons. Signed-off-by: Geetha sowjanya <gakula@marvell.com> Signed-off-by: Sunil Goutham <sgoutham@marvell.com> Signed-off-by: David S. Miller <davem@davemloft.net>
2021-02-11octeontx2-pf: cn10k: Add mbox support for CN10KSubbaraya Sundeep
Firmware allocates memory regions for PFs and VFs in DRAM. The PFs memory region is used for AF-PF and PF-VF mailbox. This mbox facilitate communication between AF-PF and PF-VF. On CN10K platform: The DRAM region allocated to PF is enumerated as PF BAR4 memory. PF BAR4 contains AF-PF mbox region followed by its VFs mbox region. AF-PF mbox region base address is configured at RVU_AF_PFX_BAR4_ADDR PF-VF mailbox base address is configured at RVU_PF(x)_VF_MBOX_ADDR = RVU_AF_PF()_BAR4_ADDR+64KB. PF access its mbox region via BAR4, whereas VF accesses PF-VF DRAM mailboxes via BAR2 indirect access. On CN9XX platform: Mailbox region in DRAM is divided into two parts AF-PF mbox region and PF-VF mbox region i.e all PFs mbox region is contiguous similarly all VFs. The base address of the AF-PF mbox region is configured at RVU_AF_PF_BAR4_ADDR. AF-PF1 mbox address can be calculated as RVU_AF_PF_BAR4_ADDR * mbox size. The base address of PF-VF mbox region for each PF is configure at RVU_AF_PF(0..15)_VF_BAR4_ADDR.PF access its mbox region via BAR4 and its VF mbox regions from RVU_PF_VF_BAR4_ADDR register, whereas VF access its mbox region via BAR4. This patch changes mbox initialization to support both CN9XX and CN10K platform. The patch also adds new hw_cap flag to setting hw features like TSO etc and removes platform specific name from the PF/VF driver name to make it appropriate for all supported platforms This patch also removes platform specific name from the PF/VF driver name to make it appropriate for all supported platforms Signed-off-by: Subbaraya Sundeep <sbhatta@marvell.com> Signed-off-by: Geetha sowjanya <gakula@marvell.com> Signed-off-by: Sunil Goutham <sgoutham@marvell.com> Signed-off-by: David S. Miller <davem@davemloft.net>
2021-02-11octeontx2-af: cn10k: Add mbox support for CN10K platformSubbaraya Sundeep
Firmware allocates memory regions for PFs and VFs in DRAM. The PFs memory region is used for AF-PF and PF-VF mailbox. This mbox facilitates communication between AF-PF and PF-VF. On CN10K platform: The DRAM region allocated to PF is enumerated as PF BAR4 memory. PF BAR4 contains AF-PF mbox region followed by its VFs mbox region. AF-PF mbox region base address is configured at RVU_AF_PFX_BAR4_ADDR PF-VF mailbox base address is configured at RVU_PF(x)_VF_MBOX_ADDR = RVU_AF_PF()_BAR4_ADDR+64KB. PF access its mbox region via BAR4, whereas VF accesses PF-VF DRAM mailboxes via BAR2 indirect access. On CN9XX platform: Mailbox region in DRAM is divided into two parts AF-PF mbox region and PF-VF mbox region i.e all PFs mbox region is contiguous similarly all VFs. The base address of the AF-PF mbox region is configured at RVU_AF_PF_BAR4_ADDR. AF-PF1 mbox address can be calculated as RVU_AF_PF_BAR4_ADDR * mbox size. The base address of PF-VF mbox region for each PF is configure at RVU_AF_PF(0..15)_VF_BAR4_ADDR.PF access its mbox region via BAR4 and its VF mbox regions from RVU_PF_VF_BAR4_ADDR register, whereas VF access its mbox region via BAR4. This patch changes mbox initialization to support both CN9XX and CN10K platform. This patch also adds CN10K PTP subsystem and device IDs to ptp driver id table. Signed-off-by: Subbaraya Sundeep <sbhatta@marvell.com> Signed-off-by: Geetha sowjanya <gakula@marvell.com> Signed-off-by: Sunil Goutham <sgoutham@marvell.com> Signed-off-by: David S. Miller <davem@davemloft.net>
2021-02-11net: mvpp2: add TX FC firmware checkStefan Chulski
Patch check that TX FC firmware is running in CM3. If not, global TX FC would be disabled. Signed-off-by: Stefan Chulski <stefanc@marvell.com> Acked-by: Marcin Wojtas <mw@semihalf.com> Signed-off-by: David S. Miller <davem@davemloft.net>
2021-02-11net: mvpp2: set 802.3x GoP Flow Control modeStefan Chulski
This patch fix GMAC TX flow control autoneg. Flow control autoneg wrongly were disabled with enabled TX flow control. Signed-off-by: Stefan Chulski <stefanc@marvell.com> Acked-by: Marcin Wojtas <mw@semihalf.com> Signed-off-by: David S. Miller <davem@davemloft.net>
2021-02-11net: mvpp2: add PPv23 RX FIFO flow controlStefan Chulski
New FIFO flow control feature was added in PPv23. PPv2 FIFO polled by HW and trigger pause frame if FIFO fill level is below threshold. FIFO HW flow control enabled with CM3 RXQ&BM flow control with ethtool. Current FIFO thresholds is: 9KB for port with maximum speed 10Gb/s port 4KB for port with maximum speed 5Gb/s port 2KB for port with maximum speed 1Gb/s port Signed-off-by: Stefan Chulski <stefanc@marvell.com> Acked-by: Marcin Wojtas <mw@semihalf.com> Signed-off-by: David S. Miller <davem@davemloft.net>
2021-02-11net: mvpp2: add BM protection underrun feature supportStefan Chulski
The PP2v23 hardware supports a feature allowing to double the size of BPPI by decreasing number of pools from 16 to 8. Increasing of BPPI size protect BM drop from BPPI underrun. Underrun could occurred due to stress on DDR and as result slow buffer transition from BPPE to BPPI. New BPPI threshold recommended by spec is: BPPI low threshold - 640 buffers BPPI high threshold - 832 buffers Supported only in PPv23. Signed-off-by: Stefan Chulski <stefanc@marvell.com> Acked-by: Marcin Wojtas <mw@semihalf.com> Signed-off-by: David S. Miller <davem@davemloft.net>
2021-02-11net: mvpp2: add ethtool flow control configuration supportStefan Chulski
This patch add ethtool flow control configuration support. Tx flow control retrieved correctly by ethtool get function. FW per port ethtool configuration capability added. Patch also takes care about mtu change procedure, if PPv2 switch BM pools during mtu change. Signed-off-by: Stefan Chulski <stefanc@marvell.com> Acked-by: Marcin Wojtas <mw@semihalf.com> Signed-off-by: David S. Miller <davem@davemloft.net>
2021-02-11net: mvpp2: add RXQ flow control configurationsStefan Chulski
This patch adds RXQ flow control configurations. Flow control disabled by default. Minimum ring size limited to 1024 descriptors. Signed-off-by: Stefan Chulski <stefanc@marvell.com> Acked-by: Marcin Wojtas <mw@semihalf.com> Signed-off-by: David S. Miller <davem@davemloft.net>
generated by cgit (git 2.34.1) at 2025-09-13 01:48:28 +0000