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Pin groups mmc_data[14] are subsets of mmc_data8.
Treat mmc_data8_b the same for consistency. Note that there is no need
to define 1-bit and 4-bit wide subsets for the b-variant, as they're
identical to the normal variants.
This reduces kernel size by 40 bytes.
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Link: https://lore.kernel.org/r/be1f11c87e51224e043291f4d8e28b620811ac76.1640269757.git.geert+renesas@glider.be
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Pin groups mmc[01]_data[14] are subsets of mmc[01]_data8.
This reduces kernel size by 80 bytes.
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Link: https://lore.kernel.org/r/0990a63016ab87d16c19097bc43d79595c0c8b87.1640269757.git.geert+renesas@glider.be
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Pin groups mmc[01]_data[14] are subsets of mmc[01]_data8.
This reduces kernel size by 80 bytes.
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Link: https://lore.kernel.org/r/3484b3cd6b4ca19788fafc01f5ead4e067275e8d.1640269757.git.geert+renesas@glider.be
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Pin groups mmc_data[14] are subsets of mmc_data8.
This reduces kernel size by 40 bytes.
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Link: https://lore.kernel.org/r/d3bf7dfda2952a0265171f82024931d490d9178a.1640269757.git.geert+renesas@glider.be
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Pin groups mmc_data[14] and sdhi1_data[14] are subsets of mmc_data8.
Pin group sdhi1_ctrl can be an alias for mmc_ctrl.
This reduces kernel size by 96 bytes.
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Link: https://lore.kernel.org/r/e3d19e19f7666dbcefeec351a5096a86348404ae.1640269757.git.geert+renesas@glider.be
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Pin groups mmc0_data[14]_[01] are subsets of mmc0_data8_[01].
This reduces kernel size by 80 bytes.
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Link: https://lore.kernel.org/r/4b15d28bb8ac24417be83b1defe0bbb908abc1e6.1640269757.git.geert+renesas@glider.be
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Pin groups mmc[01]_data[14] are subsets of mmc[01]_data8.
This reduces kernel size by 80 bytes.
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Link: https://lore.kernel.org/r/ad30961d71631577c2bdbf8dfa4874c9585caba9.1640269757.git.geert+renesas@glider.be
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Pin groups lcd{,2}_data{8,9,12,16,18} are subsets of lcd{,2}_data24.
This reduces kernel size by 1008 bytes.
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Link: https://lore.kernel.org/r/32561ca31b590424f494351a737473200102bf8c.1640269757.git.geert+renesas@glider.be
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Pin groups lcd0_data{8,9,12,16,18} are subsets of lcd0_data24_0.
Pin groups lcd1_data{8,9,12,16,18} are subsets of lcd1_data24.
This reduces kernel size by 1008 bytes.
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Link: https://lore.kernel.org/r/2018113779b3084c4175b04bb32acf2de0557a37.1640269757.git.geert+renesas@glider.be
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Pin groups keysc_in[567] are subsets of keysc_in8.
This reduces kernel size by 144 bytes.
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Link: https://lore.kernel.org/r/6d11be0accdaf4a42ce2a64e64201ab0670d65db.1640269757.git.geert+renesas@glider.be
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Pin group hscif1_data_e can be an alias for hscif1_data_c.
This reduces kernel size by 16 bytes.
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Link: https://lore.kernel.org/r/5afdfcaa24d41ebc50af37ff5da055203744f8b5.1640269757.git.geert+renesas@glider.be
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Pin group cf_data8 is a subset of cf_data16.
This reduces kernel size by 64 bytes.
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Link: https://lore.kernel.org/r/370d823be136cc9ead7051915a1454252a57efc4.1640269757.git.geert+renesas@glider.be
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Pin groups bsc_data{8,16} are subsets of bsc_data32.
Pin groups bsc_rd_we{8,16} are subsets of bsc_rd_we32.
This reduces kernel size by 232 bytes.
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Link: https://lore.kernel.org/r/556873f8392b1a7d1a2cf9c10abb5e6c283f11cc.1640269757.git.geert+renesas@glider.be
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The VIN_DATA_PIN_GROUP() macro and vin_data{12,16,} unions are used to
define multiple VIN data groups with different numbers of lanes, while
referring to a single array of data pins, thus saving memory.
However, the same feature would be useful for other resizable buses,
like MMC, SDHI, QSPI, LCD, BSC, ...
Rework the mechanism for generic use:
- Use the new SH_PFC_PIN_GROUP_SUBSET() helper to remove the need for
bus-specific unions,
- Rename VIN_DATA_PIN_GROUP() to BUS_DATA_PIN_GROUP(),
- Rename the macro parameters to better reflect their purposes,
- Move the macro up, where it belongs.
Update all individual pin control drivers for the above changes.
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Link: https://lore.kernel.org/r/cccfcfd01eb8ab7a587b084c4ddbf97293bd7291.1640269757.git.geert+renesas@glider.be
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It is fairly common for the pins in a pin group to be a subset of the
pins in another pin group. Add a macro for defining a pin group that
refers to a subset of an array of pins. This allows pin groups to share
pin data, and thus save memory.
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Link: https://lore.kernel.org/r/b56c4257aee1eab698bae2cf7a08aa05775c0a77.1640269757.git.geert+renesas@glider.be
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Rename the arguments of the SH_PFC_PIN_GROUP_ALIAS() and
SH_PFC_PIN_GROUP() macros, to better reflect their purposes.
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Link: https://lore.kernel.org/r/495fd5cd910d59489f4c1336e4a02da3679b5ffb.1640269757.git.geert+renesas@glider.be
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Reformat all macros that define structure initializers, to visually
resemble structure definitions:
- Move the opening curly brace to the previous line,
- Move the closing curly brace to the first position,
- Reduce indentation of the block to a single TAB, decreasing the need
for line breaks,
- Align backslashes for line continuation to the last TAB block where
possible,
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Link: https://lore.kernel.org/r/03a1eed3c4f57d7b14ef53ab49e04de10d0e383c.1640269757.git.geert+renesas@glider.be
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Some instances of struct sh_pfc_soc_operations are called
"<soc>_pfc_ops", others are called "<soc>_pinmux_ops" or just
"pinmux_ops". Settle on the first variant, to avoid confusion with
"struct pinmux_ops" in the pinctrl core, and to increase consistency.
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Link: https://lore.kernel.org/r/2ab33ad1d6a20a57d16922678b78810fa55b7fc0.1640269757.git.geert+renesas@glider.be
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The second video-in channel on RZ/G1C has only 12 data lanes, but the
pin control driver uses the vin_data union, which is meant for 24 data
lanes, thus wasting space.
Fix this by using the vin_data12 union instead.
This reduces kernel size by 96 bytes.
Fixes: 50f3f2d73e3426ba ("pinctrl: sh-pfc: Reduce kernel size for narrow VIN channels")
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Link: https://lore.kernel.org/r/52716fa89139f6f92592633edb52804d4c5e18f0.1640269757.git.geert+renesas@glider.be
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The .pin_to_pocctrl() implementation for R-Car E2 does not perform a
full range check, unlike on all other SoCs. Add the range check, so the
checker can validate better the consistency of the pin control tables.
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Link: https://lore.kernel.org/r/d23767ad7152327654192d7191f4b8ae19493966.1640269510.git.geert+renesas@glider.be
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This driver, like several others, uses a chained IRQ for each GPIO bank,
and forwards .irq_set_wake to the GPIO bank's upstream IRQ. As a result,
a call to irq_set_irq_wake() needs to lock both the upstream and
downstream irq_desc's. Lockdep considers this to be a possible deadlock
when the irq_desc's share lockdep classes, which they do by default:
============================================
WARNING: possible recursive locking detected
5.17.0-rc3-00394-gc849047c2473 #1 Not tainted
--------------------------------------------
init/307 is trying to acquire lock:
c2dfe27c (&irq_desc_lock_class){-.-.}-{2:2}, at: __irq_get_desc_lock+0x58/0xa0
but task is already holding lock:
c3c0ac7c (&irq_desc_lock_class){-.-.}-{2:2}, at: __irq_get_desc_lock+0x58/0xa0
other info that might help us debug this:
Possible unsafe locking scenario:
CPU0
----
lock(&irq_desc_lock_class);
lock(&irq_desc_lock_class);
*** DEADLOCK ***
May be due to missing lock nesting notation
4 locks held by init/307:
#0: c1f29f18 (system_transition_mutex){+.+.}-{3:3}, at: __do_sys_reboot+0x90/0x23c
#1: c20f7760 (&dev->mutex){....}-{3:3}, at: device_shutdown+0xf4/0x224
#2: c2e804d8 (&dev->mutex){....}-{3:3}, at: device_shutdown+0x104/0x224
#3: c3c0ac7c (&irq_desc_lock_class){-.-.}-{2:2}, at: __irq_get_desc_lock+0x58/0xa0
stack backtrace:
CPU: 0 PID: 307 Comm: init Not tainted 5.17.0-rc3-00394-gc849047c2473 #1
Hardware name: Allwinner sun8i Family
unwind_backtrace from show_stack+0x10/0x14
show_stack from dump_stack_lvl+0x68/0x90
dump_stack_lvl from __lock_acquire+0x1680/0x31a0
__lock_acquire from lock_acquire+0x148/0x3dc
lock_acquire from _raw_spin_lock_irqsave+0x50/0x6c
_raw_spin_lock_irqsave from __irq_get_desc_lock+0x58/0xa0
__irq_get_desc_lock from irq_set_irq_wake+0x2c/0x19c
irq_set_irq_wake from irq_set_irq_wake+0x13c/0x19c
[tail call from sunxi_pinctrl_irq_set_wake]
irq_set_irq_wake from gpio_keys_suspend+0x80/0x1a4
gpio_keys_suspend from gpio_keys_shutdown+0x10/0x2c
gpio_keys_shutdown from device_shutdown+0x180/0x224
device_shutdown from __do_sys_reboot+0x134/0x23c
__do_sys_reboot from ret_fast_syscall+0x0/0x1c
However, this can never deadlock because the upstream and downstream
IRQs are never the same (nor do they even involve the same irqchip).
Silence this erroneous lockdep splat by applying what appears to be the
usual fix of moving the GPIO IRQs to separate lockdep classes.
Fixes: a59c99d9eaf9 ("pinctrl: sunxi: Forward calls to irq_set_irq_wake")
Reported-by: Guenter Roeck <linux@roeck-us.net>
Signed-off-by: Samuel Holland <samuel@sholland.org>
Reviewed-by: Jernej Skrabec <jernej.skrabec@gmail.com>
Tested-by: Guenter Roeck <linux@roeck-us.net>
Link: https://lore.kernel.org/r/20220216040037.22730-1-samuel@sholland.org
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
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Avoid printing an error message if getting a regulator fails with
EPROBE_DEFER. This can happen if, for example, a regulator supplying
one of the main banks is controlled by a PL pin.
Signed-off-by: Mans Rullgard <mans@mansr.com>
Acked-by: Chen-Yu Tsai <wens@csie.org>
Link: https://lore.kernel.org/r/20220217131737.10931-1-mans@mansr.com
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
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https://git.kernel.org/pub/scm/linux/kernel/git/pinctrl/samsung into devel
Samsung pinctrl drivers changes for v5.18
1. Fix OF reference leak in pinctrl driver probe error path.
2. Correct list of handlers for Exynos850 ALIVE and CMGP pin banks.
3. Accept devicetrees with GPIO pin bank definitions named with a
"-gpio-bank" suffix. This is necessary for later Samsung pinctrl
bindings dtschema.
4. Convert Samsung pinctrl bindings to dtschema.
5. Add support for Exynos850 and ExynosAutov9 wake-up interrupts.
6. Add support for Tesla FSD SoC.
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It adds the map of wakeup capable GPIOs and the pins at MPM wake
controller on QCM2290, so that these GPIOs can wake up the SoC from
vlow/vmin low power mode.
Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
Link: https://lore.kernel.org/r/20211122080938.20623-1-shawn.guo@linaro.org
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
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When egpio_enable bit is cleared, the gpio is driven by SSC/LPASS TLMM and
the APSS TLMM settings are ignored. Reflect that in the debugfs dump.
Signed-off-by: Jonathan Marek <jonathan@marek.ca>
Link: https://lore.kernel.org/r/20220210131210.24605-2-jonathan@marek.ca
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
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This mirrors egpio support added for sc7280. This change is necessary for
gpios 165 to 209 to be driven by APSS.
Signed-off-by: Jonathan Marek <jonathan@marek.ca>
Link: https://lore.kernel.org/r/20220210131210.24605-1-jonathan@marek.ca
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
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git://git.kernel.org/pub/scm/linux/kernel/git/geert/renesas-drivers into devel
pinctrl: renesas: Updates for v5.18
- Add MOST (MediaLB I/F) pins on R-Car E3 and D3,
- Add support for the new RZ/V2L SoC,
- Miscellaneous fixes and improvements.
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The name "DS" is defined in arch/x86/um/shared/sysdep/ptrace_64.h,
which results in a compiler warning when build-testing on ARCH=um.
Rename this driver's "DS" macro to DSTR so avoid this collision.
Reported-by: kernel test robot <lkp@intel.com>
Fixes: 3b588e43ee5c7 ("pinctrl: nuvoton: add NPCM7xx pinctrl and GPIO driver")
Signed-off-by: Jonathan Neuschäfer <j.neuschaefer@gmx.net>
Reviewed-by: Andy Shevchenko <andy.shevchenko@gmail.com>
Link: https://lore.kernel.org/r/20220205155332.1308899-3-j.neuschaefer@gmx.net
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
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When compile-testing on 64-bit architectures, GCC complains about the
mismatch of types between the %d format specifier and value returned by
ARRAY_LENGTH(). Use %zu, which is correct everywhere.
Reported-by: kernel test robot <lkp@intel.com>
Fixes: 3b588e43ee5c7 ("pinctrl: nuvoton: add NPCM7xx pinctrl and GPIO driver")
Signed-off-by: Jonathan Neuschäfer <j.neuschaefer@gmx.net>
Reviewed-by: Andy Shevchenko <andy.shevchenko@gmail.com>
Link: https://lore.kernel.org/r/20220205155332.1308899-2-j.neuschaefer@gmx.net
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
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drivers/pinctrl/pinctrl-starfive.c:1029:2-3: Unneeded semicolon
Remove unneeded semicolon.
Generated by: scripts/coccinelle/misc/semicolon.cocci
Reported-by: kernel test robot <lkp@intel.com>
Signed-off-by: kernel test robot <lkp@intel.com>
Reported-by: Abaci Robot <abaci@linux.alibaba.com>
Reported-by: Yang Li <yang.lee@linux.alibaba.com>
Link: https://lore.kernel.org/r/20220206003735.GA94316@d6598ff186c2
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
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Add USB device pinmux settings for PXs2 and PXs3 SoCs. Only pins for
ports 0 and 1 support USB device mode.
Signed-off-by: Kunihiko Hayashi <hayashi.kunihiko@socionext.com>
Link: https://lore.kernel.org/r/1643376903-18623-4-git-send-email-hayashi.kunihiko@socionext.com
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
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Current pinmux group for audio in/out assumes 4ch I2S case but the
UniPhier AIO hardware also supports 1ch and 2ch I2S. So divide current
ain1 group into ain1, ain1_dat2 and ain1_dat4 groups. Divide other
ain and aout in the same way.
Signed-off-by: Ryuta NAKANISHI <nakanishi.ryuta@socionext.com>
Signed-off-by: Kunihiko Hayashi <hayashi.kunihiko@socionext.com>
Link: https://lore.kernel.org/r/1643376903-18623-3-git-send-email-hayashi.kunihiko@socionext.com
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
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Add missing audio I/O pinmux settings for PXs2 SoC.
This adds ain1 4ch pins, ain3 and aout1.
Signed-off-by: Kunihiko Hayashi <hayashi.kunihiko@socionext.com>
Link: https://lore.kernel.org/r/1643376903-18623-2-git-send-email-hayashi.kunihiko@socionext.com
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
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The PM8226 provides 8 MPPs.
Add a compatible to support them.
Signed-off-by: Rayyan Ansari <rayyan@ansari.sh>
Reviewed-by: Bjorn Andersson <bjorn.andersson@linaro.org>
Link: https://lore.kernel.org/r/20220124171538.18088-2-rayyan@ansari.sh
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
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Update rzg2l_gpio_register() to use driver data for chip->names
and check for gpio-range. This allows reusing the driver for
SoC's with different port pin definitions(eg:- RZ/G2UL SoC has
fewer ports compared to RZ/G2L and port pin definitions are
different).
Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com>
Link: https://lore.kernel.org/r/20220206194614.13209-2-biju.das.jz@bp.renesas.com
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
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Move the msiof* pin groups where they belong.
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Link: https://lore.kernel.org/r/da1018c56134b910121b085b736fe7f664b96df1.1643199959.git.geert+renesas@glider.be
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Move the du* pin function where it belongs.
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Link: https://lore.kernel.org/r/f4eb545cedcd1a72f0f80ef85daf03e2e423e90f.1643199959.git.geert+renesas@glider.be
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Move the sdhi* pin functions where they belong.
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Link: https://lore.kernel.org/r/f69d05a760445c8d67bedcb39cf5959333c71a1f.1643199959.git.geert+renesas@glider.be
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Rename the MOD_SEL2_* definitions, to match the bitfield order in
IPxSRy_* definitions and in MOD_SEL* definitions in other drivers.
No changes in generated code.
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Reviewed-by: Kieran Bingham <kieran.bingham+renesas@ideasonboard.com>
Link: https://lore.kernel.org/r/4880e4cbc112ee26569bf29a21c070125461e58d.1642524603.git.geert+renesas@glider.be
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RZ/V2L uses the RZ/G2L GPIO and pinctrl driver.
Enable the RZ/G2L pinctrl driver if RZ/V2L is enabled.
Update the description for RZ/V2L pin control support.
Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com>
Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
Link: https://lore.kernel.org/r/20220110134659.30424-8-prabhakar.mahadev-lad.rj@bp.renesas.com
Link: https://lore.kernel.org/r/20220206194614.13209-1-biju.das.jz@bp.renesas.com
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
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This patch adds support for ServalT pinctrl, using the ocelot driver as
basis.
Signed-off-by: Horatiu Vultur <horatiu.vultur@microchip.com>
Link: https://lore.kernel.org/r/20220125131858.309237-3-horatiu.vultur@microchip.com
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
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Improve the wake irq message by also printing the bank name and hwirq
number that matches this irq number.
Signed-off-by: Martin Jücker <martin.juecker@gmail.com>
Link: https://lore.kernel.org/r/20220130232122.GA119248@adroid
Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@canonical.com>
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Add driver for Sunplus SP7021 SoC.
Signed-off-by: Wells Lu <wellslutw@gmail.com>
Link: https://lore.kernel.org/r/1642344734-27229-3-git-send-email-wellslutw@gmail.com
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
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Add new pinctrl driver for Amlogic's Meson-S4 SoC which share the
same register layout as the previous Meson-A1.
Acked-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com>
Signed-off-by: Qianggui Song <qianggui.song@amlogic.com>
Link: https://lore.kernel.org/r/20220113031044.2665-4-qianggui.song@amlogic.com
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
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Adds Tesla FSD SoC specific data to enable pinctrl.
FSD SoC has similar pinctrl controller as found in the most
Samsung/Exynos SoCs.
Cc: linux-fsd@tesla.com
Acked-by: Linus Walleij <linus.walleij@linaro.org>
Signed-off-by: Ajay Kumar <ajaykumar.rs@samsung.com>
Signed-off-by: Alim Akhtar <alim.akhtar@samsung.com>
Link: https://lore.kernel.org/r/20220124141644.71052-13-alim.akhtar@samsung.com
Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@canonical.com>
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BCM4908 has its own pins layout so it needs a custom binding and a Linux
driver.
Signed-off-by: Rafał Miłecki <rafal@milecki.pl>
Reviewed-by: Andy Shevchenko <andy.shevchenko@gmail.com>
Link: https://lore.kernel.org/r/20220124102243.14912-2-zajec5@gmail.com
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
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Some boards set the direct_irq_en flag in the conf0 register without
setting the correct trigger bits. The direct_irq_en flag just means that
the GPIO will send IRQs directly to the APIC instead of going through
the shared interrupt for the GPIO controller, in order for the pin to be
able to actually generate IRQs the trigger flags must configure the IRQ
as a level-high or level-low active IRQ.
Note testing shows that using edge trigger add the conf0 register level
does NOT work, instead edge triggering should be set at the IO-APIC level.
I believe that the direct_irq_en flag connects the output of the GPIO's IRQ
trigger block, which normally sets the status flag in the IRQ status reg at
0x800 to one of the IO-APIC pins according to the direct IRQ mux.
This means that the TRIG_LVL bit *must* be set, so that the GPIO's input
value is directly passed (1:1 or inverted) to the IO-APIC pin, if TRIG_LVL
is not set, selecting edge mode operation then on the first edge the
selected IO-APIC pin goes high, but since no write-to-clear write will be
done to the IRQ status reg at 0x800, the detected edge condition will never
get cleared.
This APIC pin stuck high condition can be observed with the pin configured
as level-high active, in the form of an interrupt storm. Clearing the
TRIG_MASK bits of conf0 stops the storm, reconfiguring them as edge again
results in a storm again as soon as the edge is triggered once.
Detect invalid trigger flags, log a FW_BUG warning when encountering this
and clear the direct_irq_en flag so that a driver can actually use the pin
as IRQ through gpiod_to_irq().
Specifically this allows the edt-ft5x06 touchscreen driver to use
INT33FC:02 pin 3 as touchscreen IRQ on the Nextbook Ares 8 tablet,
accompanied by the following new log message
byt_gpio INT33FC:02: [Firmware Bug]: pin 3: direct_irq_en set without trigger, clearing
The new byt_direct_irq_sanity_check() function also checks that the
pin is actually appointed to one of the 16 direct-IRQs which the GPIO
controller supports and on success prints debug messages like these:
byt_gpio INT33FC:02: Pin 0: uses direct IRQ 0 (IO-APIC 67)
byt_gpio INT33FC:02: Pin 15: uses direct IRQ 2 (IO-APIC 69)
This is useful to figure out the GPIO pin belonging to ACPI
resources like this one: "Interrupt () { 0x00000043 }" or
the other way around.
The strict checking of valid trigger flags this introduces does result in
FW_BUG messages on quite a few devices. E.g. on the Yoga Tablet 2 1051L:
byt_gpio INT33FC:00: [Firmware Bug]: pin 92: direct_irq_en set but no IRQ assigned, clearing
byt_gpio INT33FC:00: [Firmware Bug]: pin 93: direct_irq_en set but no IRQ assigned, clearing
These 2 also have mux set to 7 and fall + rise + level trigger bits set,
presumably something has written 0xffffffff to their conf0 registers
byt_gpio INT33FC:02: Pin 3: uses direct IRQ 1 (IO-APIC 68)
byt_gpio INT33FC:02: [Firmware Bug]: pin 3: direct_irq_en set without trigger (conf0: 2803cc00h), clearing
Most tablets seem to have this, looking at DSDTs this seems intended for
use with an I2C HID sensor-hub and is still set on devices without one.
To make sure this does not cause any regressions this has been tested,
including checking disabled direct-IRQs are not used in the DSDT,
on the following devices:
Asus ME176C
Asus TF103C
Chuwi Vi10 (with its Windows BIOS)
HP x2 10-n000nd
Lenovo Yoga Tablet 2 1050L (Android version, without EC, with buggy DSDT)
Lenovo Yoga Tablet 2 1051L (Windows version, with EC)
Suggested-by: Andy Shevchenko <andy@kernel.org>
Signed-off-by: Hans de Goede <hdegoede@redhat.com>
Acked-by: Mika Westerberg <mika.westerberg@linux.intel.com>
Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
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The commit af7e3eeb84e2 ("pinctrl: intel: Disable input and output buffer
when switching to GPIO") hadn't taken into account an update of the IRQ
flags scenario.
When updating the IRQ flags on the preconfigured line the ->irq_set_type()
is called again. In such case the sequential Rx buffer configuration
changes may trigger a falling or rising edge interrupt that may lead,
on some platforms, to an undesired event.
This may happen because each of intel_gpio_set_gpio_mode() and
__intel_gpio_set_direction() updates the pad configuration with a different
value of the GPIORXDIS bit. Notable, that the intel_gpio_set_gpio_mode() is
called only for the pads that are configured as an input. Due to this fact,
integrate the logic of __intel_gpio_set_direction() call into the
intel_gpio_set_gpio_mode() so that the Rx buffer won't be disabled and
immediately re-enabled.
Fixes: af7e3eeb84e2 ("pinctrl: intel: Disable input and output buffer when switching to GPIO")
Reported-by: Kane Chen <kane.chen@intel.com>
Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
Acked-by: Mika Westerberg <mika.westerberg@linux.intel.com>
Tested-by: Grace Kao <grace.kao@intel.com>
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ASUS Chromebook C223 with Celeron N3350 crashes sometimes during
cold booot. Inspection of the kernel log showed that it gets into
an inifite loop logging the following message:
->handle_irq(): 000000009cdb51e8, handle_bad_irq+0x0/0x251
->irq_data.chip(): 000000005ec212a7, 0xffffa043009d8e7
->action(): 00000
IRQ_NOPROBE set
unexpected IRQ trap at vector 7c
The issue happens during cold boot but only if cold boot happens
at most several dozen seconds after Chromebook is powered off. For
longer intervals between power off and power on (cold boot) the issue
does not reproduce. The unexpected interrupt is sourced from INT3452
GPIO pin which is used for SD card detect. Investigation relevealed
that when the interval between power off and power on (cold boot)
is less than several dozen seconds then values of INT3452 GPIO interrupt
enable and interrupt pending registers survive power off and power
on sequence and interrupt for SD card detect pin is enabled and pending
during probe of SD controller which causes the unexpected IRQ message.
"Intel Pentium and Celeron Processor N- and J- Series" volume 3 doc
mentions that GPIO interrupt enable and status registers default
value is 0x0.
The fix clears INT3452 GPIO interrupt enabled and interrupt pending
registers in its probe function.
Fixes: 7981c0015af2 ("pinctrl: intel: Add Intel Sunrisepoint pin controller and GPIO support")
Signed-off-by: Łukasz Bartosik <lb@semihalf.com>
Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
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Keep Makefile entries ordered in the same way as Kconfig ones.
Reported-by: Linus Torvalds <torvalds@linux-foundation.org>
Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
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