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Now that scaling is allowed on cursor planes, we can also allow YUV
formats.
Signed-off-by: Boris Brezillon <boris.brezillon@bootlin.com>
Reviewed-by: Eric Anholt <eric@anholt.net>
Link: https://patchwork.freedesktop.org/patch/msgid/20181130090254.594-6-boris.brezillon@bootlin.com
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Now that async update has been reworked to allow scaled planes to be
updated asynchronously when the scaling params do not change, we can
remove the NO_SCALING constraint on cursor planes.
Signed-off-by: Boris Brezillon <boris.brezillon@bootlin.com>
Reviewed-by: Eric Anholt <eric@anholt.net>
Link: https://patchwork.freedesktop.org/patch/msgid/20181130090254.594-5-boris.brezillon@bootlin.com
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vc4_plane_atomic_async_check() was only based on the
state->{crtc,src}_{w,h} which was fine since scaling was not allowed on
the cursor plane.
We are about to change that to properly support underscan, and, in order
to make the async check more reliable, we call vc4_plane_mode_set()
from there and check that only the pos0, pos2 and ptr0 entries in the
dlist have changed.
In vc4_plane_atomic_async_update(), we no longer call
vc4_plane_atomic_check() since vc4_plane_mode_set() has already been
called in vc4_plane_atomic_async_check(), and we don't need to allocate
a new LBM region (we reuse the one from the current state).
Note that we now have to manually update each field of the current
plane state since it's no longer updated in place (not sure we have
to sync all of them, but it's harmless if we do).
We also drop the vc4_plane_async_set_fb() call (ptr0 dlist entry has
been properly updated in vc4_plane_mode_set())
Signed-off-by: Boris Brezillon <boris.brezillon@bootlin.com>
Reviewed-by: Eric Anholt <eric@anholt.net>
Link: https://patchwork.freedesktop.org/patch/msgid/20181130090254.594-4-boris.brezillon@bootlin.com
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We are about to use vc4_plane_mode_set() in the async check path, but
async check can decide that async update is not possible and force the
driver to fallback to a sync update.
All the checks that have been done on the plane state during async check
stay valid, and checking it again is not necessary. Add a ->checked
field to vc4_plane_state, and use it to track the status of the state
(checked or not).
Signed-off-by: Boris Brezillon <boris.brezillon@bootlin.com>
Reviewed-by: Eric Anholt <eric@anholt.net>
Link: https://patchwork.freedesktop.org/patch/msgid/20181130090254.594-3-boris.brezillon@bootlin.com
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We are about to use vc4_plane_mode_set() in the async check path, and
async updates require that LBM size stay the same since they reuse the
LBM from the previous state. So we definitely don't want to allocate a
new LBM region that we know for sure will be free right away.
Move the LBM allocation out of vc4_plane_mode_set() and call the new
function (vc4_plane_update_lbm()) from vc4_plane_atomic_check().
Signed-off-by: Boris Brezillon <boris.brezillon@bootlin.com>
Reviewed-by: Eric Anholt <eric@anholt.net>
Link: https://patchwork.freedesktop.org/patch/msgid/20181130090254.594-2-boris.brezillon@bootlin.com
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LBM is not needed when vertical scaling is disabled. Return 0 in this
case to avoid allocating LBM memory that will anyway be unused.
While at it, drop the test on ->is_unity which is now redundant.
Signed-off-by: Boris Brezillon <boris.brezillon@bootlin.com>
Reviewed-by: Eric Anholt <eric@anholt.net>
Link: https://patchwork.freedesktop.org/patch/msgid/20181130090254.594-1-boris.brezillon@bootlin.com
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Set the suitable bits in DP_TP_CTL to stop
bit correction when DSC is disabled.
v2:
- rebased.
- Add additional check for compression state. (Gaurav)
v3: rebased.
v4:
- Move the code to the proper spot according to spec (Ville)
- Use proper checks (manasi)
v5: Remove unnecessary checks (Ville)
v6: Resolve warnings. Add crtc_state as an argument to
intel_disable_ddi_buf(). (Manasi)
Cc: dri-devel@lists.freedesktop.org
Cc: Gaurav K Singh <gaurav.k.singh@intel.com>
Cc: Jani Nikula <jani.nikula@linux.intel.com>
Cc: Ville Syrjala <ville.syrjala@linux.intel.com>
Cc: Manasi Navare <manasi.d.navare@intel.com>
Signed-off-by: Anusha Srivatsa <anusha.srivatsa@intel.com>
Signed-off-by: Manasi Navare <manasi.d.navare@intel.com>
Reviewed-by: Manasi Navare <manasi.d.navare@intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20181128202628.20238-17-manasi.d.navare@intel.com
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If FEC is supported, the corresponding
DP_TP_CTL register bits have to be configured.
The driver has to program the FEC_ENABLE in DP_TP_CTL[30] register
and wait till FEC_STATUS in DP_TP_CTL[28] is 1.
Also add the warn message to make sure that the control
register is already active while enabling FEC.
v2:
- Change commit message. Configure fec state after
link training (Manasi, Gaurav)
- Remove redundent checks (Manasi)
- Remove the registers that get added automagically (Anusha)
v3: s/intel_dp_set_fec_state()/intel_dp_enable_fec_state() (Gaurav)
v4: rebased.
v5:
- Move the code to the proper spot, according to spec.(Ville)
- Use fec state as a check too.
v6: Pass intel_encoder, instead of intel_dp. (Ville)
v7: Remove unwanted comments (Manasi)
Cc: dri-devel@lists.freedesktop.org
Cc: Gaurav K Singh <gaurav.k.singh@intel.com>
Cc: Jani Nikula <jani.nikula@linux.intel.com>
Cc: Ville Syrjala <ville.syrjala@linux.intel.com>
Cc: Manasi Navare <manasi.d.navare@intel.com>
Signed-off-by: Anusha Srivatsa <anusha.srivatsa@intel.com>
Signed-off-by: Manasi Navare <manasi.d.navare@intel.com>
Reviewed-by: Manasi Navare <manasi.d.navare@intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20181128202628.20238-16-manasi.d.navare@intel.com
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If the panel supports FEC, the driver has to
set the FEC_READY bit in the dpcd register:
FEC_CONFIGURATION.
This has to happen before link training.
v2: s/intel_dp_set_fec_ready/intel_dp_sink_set_fec_ready
- change commit message. (Gaurav)
v3: rebased. (r-b Manasi)
v4: Use fec crtc state, before setting FEC_READY
bit. (Anusha)
v5: Move to intel_ddi.c
- Make the function static (Anusha)
v6: Dont pass state as a separate argument (Ville)
v7: (From Manasi)
* Correct the debug print (Ville)
Cc: dri-devel@lists.freedesktop.org
Cc: Gaurav K Singh <gaurav.k.singh@intel.com>
Cc: Jani Nikula <jani.nikula@linux.intel.com>
Cc: Ville Syrjala <ville.syrjala@linux.intel.com>
Cc: Manasi Navare <manasi.d.navare@intel.com>
Signed-off-by: Anusha Srivatsa <anusha.srivatsa@intel.com>
Signed-off-by: Manasi Navare <manasi.d.navare@intel.com>
Reviewed-by: Manasi Navare <manasi.d.navare@intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20181128202628.20238-15-manasi.d.navare@intel.com
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For DP 1.4 and above, Display Stream compression can be
enabled only if Forward Error Correctin can be performed.
Add a crtc state for FEC. Currently, the state
is determined by platform, DP and DSC being
enabled. Moving forward we can use the state
to have error correction on other scenarios too
if needed.
v2:
- Control compression_enable with the fec_enable
parameter in crtc state and with intel_dp_supports_fec()
(Ville)
- intel_dp_can_fec()/intel_dp_supports_fec()(manasi)
v3: Check for FEC support along with setting crtc state.
v4: add checks to intel_dp_source_supports_dsc.(manasi)
- Move intel_dp_supports_fec() closer to
intel_dp_supports_dsc() (Anusha)
v5: Move fec check to intel_dp_supports_dsc(Ville)
v6: Remove warning. rebase.
v7: change crtc state to include DP sink and fec capability
of source.(Manasi)
v8: Set fec_enable in crtc in intel_dp_compute_config().
v9 (From Manasi):
* Combine the !edp and !fec_support check
* Derive dev_priv from intel_dp directly
v10 (From Manasi):
* Rebase
Suggested-by: Ville Syrjala <ville.syrjala@linux.intel.com>
Cc: dri-devel@lists.freedesktop.org
Cc: Ville Syrjala <ville.syrjala@linux.intel.com>
Cc: Jani Nikula <jani.nikula@linux.intel.com>
Cc: Manasi Navare <manasi.d.navare@intel.com>
Signed-off-by: Anusha Srivatsa <anusha.srivatsa@intel.com>
Signed-off-by: Manasi Navare <manasi.d.navare@intel.comk>
Reviewed-by: Manasi Navare <manasi.d.navare@intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20181128202628.20238-14-manasi.d.navare@intel.com
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A separate power well 2 (PG2) is required for VDSC on eDP transcoder
whereas all other transcoders use the power wells associated with the
transcoders for VDSC.
This patch adds a helper to obtain correct power domain depending on
transcoder being used and enables/disables the power wells during
VDSC enabling/disabling.
v4:
* Get VDSC power domain only if compression en is set
in crtc_state (Ville, Imre)
v3:
* Call it intel_dsc_power_domain, add to
intel_ddi_get_power_domains (Ville)
v2:
* Fix tabs, const crtc_state, fix comments (Ville)
Suggested-by: Ville Syrjala <ville.syrjala@linux.intel.com>
Cc: Ville Syrjala <ville.syrjala@linux.intel.com>
Cc: Imre Deak <imre.deak@intel.com>
Cc: Rodrigo Vivi <rodrigo.vivi@intel.com>
Signed-off-by: Manasi Navare <manasi.d.navare@intel.com>
Reviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20181128202628.20238-13-manasi.d.navare@intel.com
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1. Disable Left/right VDSC branch in DSS Ctrl reg
depending on the number of VDSC engines being used
2. Disable joiner in DSS Ctrl reg
v4:
* Remove encoder, make crtc_state const (Ville)
v3 (From Manasi):
* Add Disable PG2 for VDSC on eDP
v2 (From Manasi):
* Use old_crtc_state to find dsc params
* Add a condition to disable only if
dsc state compression is enabled
* Use correct DSS CTL regs
Cc: Jani Nikula <jani.nikula@linux.intel.com>
Cc: Ville Syrjala <ville.syrjala@linux.intel.com>
Cc: Anusha Srivatsa <anusha.srivatsa@intel.com>
Signed-off-by: Manasi Navare <manasi.d.navare@intel.com>
Signed-off-by: Gaurav K Singh <gaurav.k.singh@intel.com>
Reviewed-by: Anusha Srivatsa <anusha.srivatsa@intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20181128202628.20238-12-manasi.d.navare@intel.com
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Display Stream Splitter registers need to be programmed to enable
the joiner if two DSC engines are used and also to enable
the left and the right DSC engines. This happens as part of
the DSC enabling routine in the source in atomic commit.
v4:
* Remove redundant comment (Ville)
v3:
* Use cpu_transcoder instead of encoder->type (Ville)
v2:
* Rebase (Manasi)
Cc: Jani Nikula <jani.nikula@linux.intel.com>
Cc: Ville Syrjala <ville.syrjala@linux.intel.com>
Cc: Anusha Srivatsa <anusha.srivatsa@intel.com>
Signed-off-by: Manasi Navare <manasi.d.navare@intel.com>
Reviewed-by: Anusha Srivatsa <anusha.srivatsa@intelcom>
Link: https://patchwork.freedesktop.org/patch/msgid/20181128202628.20238-11-manasi.d.navare@intel.com
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DSC PPS secondary data packet infoframes are filled with
DSC picure parameter set metadata according to the DSC standard.
These infoframes are sent to the sink device and used during DSC
decoding.
v3:
* Rename to intel_dp_write_pps_sdp (Ville)
* Use const intel_crtc_state (Ville)
v2:
* Rebase ond drm-tip
Cc: Jani Nikula <jani.nikula@linux.intel.com>
Cc: Ville Syrjala <ville.syrjala@linux.intel.com>
Cc: Anusha Srivatsa <anusha.srivatsa@intel.com>
Signed-off-by: Manasi Navare <manasi.d.navare@intel.com>
Reviewed-by: Anusha Srivatsa <anusha.srivatsa@intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20181128202628.20238-10-manasi.d.navare@intel.com
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Infoframes are used to send secondary data packets. This patch
adds support for DSC Picture parameter set secondary data packets
in the existing write_infoframe helpers.
v3:
* Unused variables cleanup (Ville)
v2:
* Rebase on drm-tip (Manasi)
Cc: Jani Nikula <jani.nikula@linux.intel.com>
Cc: Ville Syrjala <ville.syrjala@linux.intel.com>
Cc: Anusha Srivatsa <anusha.srivatsa@intel.com>
Signed-off-by: Manasi Navare <manasi.d.navare@intel.com>
Reviewed-by: Anusha Srivatsa <anusha.srivatsa@intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20181128202628.20238-9-manasi.d.navare@intel.com
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After encoder->pre_enable() hook, after link training sequence is
completed, PPS registers for DSC encoder are configured using the
DSC state parameters in intel_crtc_state as part of DSC enabling
routine in the source. DSC enabling routine is called after
encoder->pre_enable() before enbaling the pipe and after
compression is enabled on the sink.
v7:
* Remove unnecessary comments, leftovers (Ville)
* No need for explicit val &= ~ (Ville)
v6:
intel_dsc_enable to be part of pre_enable hook (Ville)
v5:
* make crtc_state const (Ville)
v4:
* Use cpu_transcoder instead of encoder->type for using EDP transcoder
DSC registers(Ville)
* Keep all PSS regs together (Anusha)
v3:
* Configure Pic_width/2 for each VDSC engine when two VDSC engines per pipe
are used (Manasi)
* Add DSC slice_row_per_frame in PPS16 (Manasi)
v2:
* Enable PG2 power well for VDSC on eDP
Cc: Jani Nikula <jani.nikula@linux.intel.com>
Cc: Ville Syrjala <ville.syrjala@linux.intel.com>
Cc: Anusha Srivatsa <anusha.srivatsa@intel.com>
Signed-off-by: Manasi Navare <manasi.d.navare@intel.com>
[manasi: fixup the line longer than 100 chars while applying]
Reviewed-by: Anusha Srivatsa <anusha.srivatsa@intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20181128202628.20238-8-manasi.d.navare@intel.com
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On Icelake, a separate power well PG2 is created for
VDSC engine used for eDP/MIPI DSI. This patch adds a new
display power domain for Power well 2.
v3:
* Call it POWER_DOMAIN_TRANSCODER_EDP_VDSC (Ville)
* Move it around TRANSCODER power domain defs (Ville)
v2:
* Fix the power well mismatch CI error (Ville)
* Rename as VDSC_PIPE_A (Imre)
* Fix a whitespace (Anusha)
* Fix Comments (Imre)
Cc: Ville Syrjala <ville.syrjala@linux.intel.com>
Cc: Rodrigo Vivi <rodrigo.vivi@intel.com>
Cc: Imre Deak <imre.deak@intel.com>
Signed-off-by: Manasi Navare <manasi.d.navare@intel.com>
Reviewed-by: Ville Syrjala <ville.syrjala@linux.intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20181128202628.20238-7-manasi.d.navare@intel.com
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This patch enables decompression support in sink device
before link training and disables the same during the
DDI disabling.
v3 (From manasi):
* Pass bool state to enable/disable (Ville)
v2:(From Manasi)
* Change the enable/disable function to take crtc_state
instead of intel_dp as an argument (Manasi)
* Use the compression_enable flag as part of crtc_state (Manasi)
Cc: Jani Nikula <jani.nikula@linux.intel.com>
Cc: Ville Syrjala <ville.syrjala@linux.intel.com>
Cc: Anusha Srivatsa <anusha.srivatsa@intel.com>
Cc: Gaurav K Singh <gaurav.k.singh@intel.com>
Signed-off-by: Gaurav K Singh <gaurav.k.singh@intel.com>
Signed-off-by: Manasi Navare <manasi.d.navare@intel.com>
Reviewed-by: Anusha Srivatsa <anusha.srivatsa@intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20181128202628.20238-6-manasi.d.navare@intel.com
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This computation of RC params happens in the atomic commit phase
during compute_config() to validate if display stream compression
can be enabled for the requested mode.
v7 (From Manasi):
* Use DRM_DEBUG instead of DRM_ERROR (Ville)
* Use Error numberinstead of -1 (Ville)
v6 (From Manasi):
* Use 9 instead of 0x9 for consistency (Anusha)
v5 (From Manasi):
* Fix dim checkpatch warnings/checks
v4(From Gaurav):
* No change.Rebase on drm-tip
v3 (From Gaurav):
* Rebase on top of Manasi's latest series
* Return -ve value in case of failure scenarios (Manasi)
Fix review comments from Ville:
* Remove unnecessary comments
* Remove unnecessary paranthesis
* Add comments for few RC params calculations
v2 (From Manasi):
* Rebase Gaurav's patch from intel-gfx to gfx-internal
* Use struct drm_dsc_cfg instead of struct intel_dp
as a parameter
Cc: Manasi Navare <manasi.d.navare@intel.com>
Cc: Jani Nikula <jani.nikula@linux.intel.com>
Cc: Ville Syrjala <ville.syrjala@linux.intel.com>
Signed-off-by: Gaurav K Singh <gaurav.k.singh@intel.com>
Signed-off-by: Manasi Navare <manasi.d.navare@intel.com>
Reviewed-by: Anusha Srivatsa <anusha.srivatsa@intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20181128202628.20238-5-manasi.d.navare@intel.com
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This patches does the following:
1. This patch defines all the DSC parameters as per the VESA
DSC specification. These are stored in the encoder and used
to compute the PPS parameters to be sent to the Sink.
2. Compute all the DSC parameters which are derived from DSC
state of intel_crtc_state.
3. Compute all parameters that are VESA DSC specific
This computation happens in the atomic check phase during
compute_config() to validate if display stream compression
can be enabled for the requested mode.
v8 (From Manasi):
* DEBUG_KMS instead of DRM_ERROR for user triggerable
errors (Ville)
v7: (From Manasi)
* Dont use signed int for rc_range_params (Manasi)
* Mask the range_bpg_offset to use only 6 bits
* Add SPDX identifier (Chris Wilson)
v6 (From Manasi):
* Add a check for line_buf_depth return value (Anusha)
* Remove DRM DSC constants to different patch (Manasi)
v5 (From Manasi):
* Add logic to limit the max line buf depth for DSC 1.1 to 13
as per DSC 1.1 spec
* Fix dim checkpatch warnings/checks
v4 (From Gaurav):
* Rebase on latest drm tip
* rename variable name(Manasi)
* Populate linebuf_depth variable(Manasi)
v3 (From Gaurav):
* Rebase my previous patches on top of Manasi's latest patch
series
* Using >>n rather than /2^n (Manasi)
* Change the commit message to explain what the patch is doing(Gaurav)
Fixed review comments from Ville:
* Don't use macro TWOS_COMPLEMENT
* Mention in comment about the source of RC params
* Return directly from case statements
* Using single asssignment for assigning rc_range_params
* Using <<n rather than *2^n and removing the comments
about the fixed point numbers
v2 (From Manasi):
* Update logic for minor version to consider the dpcd value
and what supported by the HW platform
* Use DRM DSC config struct instead of intel_dp struct
* Move the DSC constants to DRM DSC header file
* Use u16, u8 where bigger data types not needed
* * Compute the DSC parameters as part of DSC compute config
since the computation can fail (Manasi)
Cc: Jani Nikula <jani.nikula@linux.intel.com>
Cc: Ville Syrjala <ville.syrjala@linux.intel.com>
Cc: Anusha Srivatsa <anusha.srivatsa@intel.com>
Cc: Gaurav K Singh <gaurav.k.singh@intel.com>
Signed-off-by: Gaurav K Singh <gaurav.k.singh@intel.com>
Signed-off-by: Manasi Navare <manasi.d.navare@intel.com>
Co-developed-by: Manasi Navare <manasi.d.navare@intel.com>
Reviewed-by: Anusha Srivatsa <anusha.srivatsa@intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20181129193827.7914-1-manasi.d.navare@intel.com
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If a eDP panel supports both PSR2 and VDSC, our HW cannot
support both at a time. Give priority to PSR2 if a requested
resolution can be supported without compression else enable
VDSC and keep PSR2 disabled.
v4:
Fix the unrealted stuff removed during rebase (Ville)
v3:
* Rebase
v2:
* Add warning for DSC and PSR2 enabled together (DK)
Cc: Rodrigo Vivi <rodrigo.vivi@intel.com>
Cc: Jani Nikula <jani.nikula@intel.com>
Cc: Ville Syrjälä <ville.syrjala@linux.intel.com>
Signed-off-by: Manasi Navare <manasi.d.navare@intel.com>
Reviewed-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20181128202628.20238-3-manasi.d.navare@intel.com
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DSC params like the enable, compressed bpp, slice count and
dsc_split are added to the intel_crtc_state. These parameters
are set based on the requested mode and available link parameters
during the pipe configuration in atomic check phase.
These values are then later used to populate the remaining DSC
and RC parameters before enbaling DSC in atomic commit.
v15:
* Rebase over drm-tip
v14:
Remove leftovers, use dsc_bpc, refine dsc_compute_config (Ville)
v13:
* Compute DSC bpc only when DSC is req to be enabled (Ville)
v12:
* Override bpp with dsc dpcd color depth (Manasi)
v11:
* Const crtc_state, reject DSC on DP without FEC (Ville)
* Dont set dsc_split to false (Ville)
v10:
* Add a helper for dp_dsc support (Ville)
* Set pipe_config to max bpp, link params for DSC for now (Ville)
* Compute bpp - use dp dsc support helper (Ville)
v9:
* Rebase on top of drm-tip that now uses fast_narrow config
for edp (Manasi)
v8:
* Check for DSC bpc not 0 (manasi)
v7:
* Fix indentation in compute_m_n (Manasi)
v6 (From Gaurav):
* Remove function call of intel_dp_compute_dsc_params() and
invoke intel_dp_compute_dsc_params() in the patch where
it is defined to fix compilation warning (Gaurav)
v5:
Add drm_dsc_cfg in intel_crtc_state (Manasi)
v4:
* Rebase on refactoring of intel_dp_compute_config on tip (Manasi)
* Add a comment why we need to check PSR while enabling DSC (Gaurav)
v3:
* Check PPR > max_cdclock to use 2 VDSC instances (Ville)
v2:
* Add if-else for eDP/DP (Gaurav)
Cc: Jani Nikula <jani.nikula@linux.intel.com>
Cc: Ville Syrjala <ville.syrjala@linux.intel.com>
Cc: Anusha Srivatsa <anusha.srivatsa@intel.com>
Cc: Gaurav K Singh <gaurav.k.singh@intel.com>
Signed-off-by: Manasi Navare <manasi.d.navare@intel.com>
Reviewed-by: Anusha Srivatsa <anusha.srivatsa@intel.com>
Reviewed-by: Ville Syrjala <ville.syrjala@linux.intel.com>
Acked-by: Jani Nikula <jani.nikula@linux.intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20181128213621.21391-1-manasi.d.navare@intel.com
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Basic DSC parameters and DSC configuration data needs to be computed
for each of the requested mode during atomic check. This is
required since for certain modes, valid DSC parameters and config
data might not be computed in which case compression cannot be
enabled for that mode.
For that reason we need to add these params and config structure
to the intel_crtc_state so that if valid this state information
can directly be used while enabling DSC in atomic commit.
v2:
* Rebase on drm-tip (Manasi)
Cc: Gaurav K Singh <gaurav.k.singh@intel.com>
Cc: Jani Nikula <jani.nikula@linux.intel.com>
Cc: Ville Syrjala <ville.syrjala@linux.intel.com>
Cc: Anusha Srivatsa <anusha.srivatsa@intel.com>
Signed-off-by: Manasi Navare <manasi.d.navare@intel.com>
Reviewed-by: Anusha Srivatsa <anusha.srivatsa@intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20181128202628.20238-1-manasi.d.navare@intel.com
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In the future framebuffer stride alignment requirements won't exactly
match the units in which skl+ plane stride is specified. So extract
the code for the skl+ stuff into a separate helper.
Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20180925193714.25280-3-ville.syrjala@linux.intel.com
Reviewed-by: Chris Wilson <chris@chris-wilson.co.uk>
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Let's try to make sure the fb offset computations never hit
an integer overflow by making sure the entire fb stays
below 32bits. framebuffer_check() in the core already does
the same check, but as it doesn't know about tiling some things
can slip through. Repeat the check in the driver with tiling
taken into account.
v2: Use add_overflows() after massaging it to work for me (Chris)
v3: Call it add_overflow_t() to match min_t() & co. (Chris)
Cc: Chris Wilson <chris@chris-wilson.co.uk>
Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20181023160201.9840-1-ville.syrjala@linux.intel.com
Reviewed-by: Chris Wilson <chris@chris-wilson.co.uk>
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Calculate preferred refresh rate only when preferred mode exists.
Signed-off-by: Jerry (Fangzhi) Zuo <Jerry.Zuo@amd.com>
Reviewed-by: Bhawanpreet Lakha <Bhawanpreet.Lakha@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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[Why]
More than 4x4K didn't lightup on Vega20 due to low dcfclk value.
Powerplay expects valid min requirement for dcfclk from DC.
[How]
Update min_dcfclock_khz based on min_engine_clock value.
Reviewed-by: Hersen Wu <hersenxs.wu@amd.com>
Reviewed-by: Feifei Xu <Feifei.Xu@amd.com>
Reviewed-by: Evan Quan <evan.quan@amd.com>
Acked-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Roman Li <Roman.Li@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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Display controllers that don't own any windows and which therefore
aren't currently being assigned a primary plane are not registered
as a CRTC with the DRM framework. They request neither a syncpoint
nor an interrupt because they don't use them, so avoid cleaning up
those resources.
Signed-off-by: Thierry Reding <treding@nvidia.com>
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The display architecture on Tegra186 and Tegra194 requires that there be
some valid clock on all domains before accessing any display register. A
further requirement is that in addition to the host1x, hub, disp and dsc
clocks, all the head clocks (pclk0-2 on Tegra186 or pclk0-3 on Tegra194)
must also be enabled.
Implement this logic within the display hub driver to ensure the clocks
are always enabled at the right time.
Signed-off-by: Thierry Reding <treding@nvidia.com>
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The Video Image Composer (VIC) generation found on Tegra194 is backwards
compatible with its predecessor found on Tegra186.
Reviewed-by: Mikko Perttunen <mperttunen@nvidia.com>
Signed-off-by: Thierry Reding <treding@nvidia.com>
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The host1x hardware found on Tegra194 is mostly backwards compatible
with the version found on Tegra186, with the notable exceptions of the
increased number of syncpoints and mlocks. In addition, some rarely
used features such as syncpoint wait bases were dropped and some
registers had to move around to accomodate the increased number of
syncpoints.
Signed-off-by: Thierry Reding <treding@nvidia.com>
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Before booting the Falcon processor, make sure to wait for memory
scrubbing to complete.
Signed-off-by: Thierry Reding <treding@nvidia.com>
|
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The ->alloc() callback in struct falcon_ops returns an ERR_PTR()-encoded
error code on failure, so it needs to be properly checked for, otherwise
subsequent code may dereference an invalid pointer.
Signed-off-by: Thierry Reding <treding@nvidia.com>
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Tegra supports generic PM domains on 64-bit ARM, and if that is enabled,
the power domain code will make sure that resets are asserted and
deasserted at appropriate points in time.
If generic PM domains are not implemented, such as on 32-bit Tegra, the
resets need to be asserted and deasserted explicitly by the driver.
Reviewed-by: Jon Hunter <jonathanh@nvidia.com>
Signed-off-by: Thierry Reding <treding@nvidia.com>
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This patch adds a couple of helpers to remove the boilerplate involved
in grabbing all of the modeset locks.
I've also converted the obvious cases in drm core to use the helpers.
The only remaining instance of drm_modeset_lock_all_ctx() is in
drm_framebuffer. It's complicated by the state clear that occurs on
deadlock. ATM, there's no way to inject code in the deadlock path with
the helpers, so it's unfit for conversion.
Changes in v2:
- Relocate ret argument to the end of the list (Daniel)
- Incorporate Daniel's doc suggestions (Daniel)
Suggested-by: Daniel Vetter <daniel@ffwll.ch>
Reviewed-by: Daniel Vetter <daniel@ffwll.ch>
Signed-off-by: Sean Paul <seanpaul@chromium.org>
Link: https://patchwork.freedesktop.org/patch/msgid/20181129150423.239081-4-sean@poorly.run
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drm_atomic_state_put doesn't require any locking, and this makes things
easier for switching to modeset_lock_all helpers in a future patch
Changes in v2:
- Moved state->acquire_ctx clear to a separate patch (Daniel)
Reviewed-by: Daniel Vetter <daniel@ffwll.ch>
Signed-off-by: Sean Paul <seanpaul@chromium.org>
Link: https://patchwork.freedesktop.org/patch/msgid/20181129150423.239081-3-sean@poorly.run
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Instead of always re-initializing the variables we need to clean up on
out, move the re-initialization into the branch that goes back to retry
label.
This is a lateral move right now, but will allow us to pull out the
modeset locking into common code. I kept this change separate to make
things easier to review.
Changes in v2:
- None
Reviewed-by: Daniel Vetter <daniel@ffwll.ch>
Signed-off-by: Sean Paul <seanpaul@chromium.org>
Link: https://patchwork.freedesktop.org/patch/msgid/20181129150423.239081-2-sean@poorly.run
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drm_atomic_helper_commit_duplicated_state()
drm_atomic_helper_commit_duplicated_state() sets state->acquire_ctx to
the context given in the argument and leaves it in state after it
quits. The lifetime of state and context are not guaranteed to be the
same, so we shouldn't leave that pointer hanging around. This patch
resets the context to NULL to avoid any oopses.
Changes in v2:
- Added to the set
Suggested-by: Daniel Vetter <daniel@ffwll.ch>
Reviewed-by: Daniel Vetter <daniel.vetter@ffwll.ch>
Signed-off-by: Sean Paul <seanpaul@chromium.org>
Link: https://patchwork.freedesktop.org/patch/msgid/20181129150423.239081-1-sean@poorly.run
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The CMA helper is already using the drm_fb_helper_generic_probe part of
the generic fbdev emulation. This patch makes full use of the generic
fbdev emulation by using its drm_client callbacks. This means that
drm_mode_config_funcs->output_poll_changed and drm_driver->lastclose are
now handled by the emulation code. Additionally fbdev unregister happens
automatically on drm_dev_unregister().
The drm_fbdev_generic_setup() call is put after drm_dev_register() in the
driver. This is done to highlight the fact that fbdev emulation is an
internal client that makes use of the driver, it is not part of the
driver as such. If fbdev setup fails, an error is printed, but the driver
succeeds probing.
drm_fbdev_generic_setup() handles mode_config.num_connector being zero.
In that case it retries fbdev setup on the next .output_poll_changed.
Cc: Laurent Pinchart <laurent.pinchart@ideasonboard.com>
Signed-off-by: Noralf Trønnes <noralf@tronnes.org>
Acked-by: Sam Ravnborg <sam@ravnborg.org>
Reviewed-by: Laurent Pinchart <laurent.pinchart@ideasonboard.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20181128212713.43500-4-noralf@tronnes.org
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Requested by Boris Brezillon for some vc4 fixes that are needed for future vc4 work.
Signed-off-by: Maarten Lankhorst <maarten.lankhorst@linux.intel.com>
|
|
Signed-off-by: Gerd Hoffmann <kraxel@redhat.com>
Reviewed-by: Robert Foss <robert.foss@collabora.com>
Link: http://patchwork.freedesktop.org/patch/msgid/20181128151021.29565-3-kraxel@redhat.com
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|
Since commit "9fdd90c0f4 drm/virtio: add virtio_gpu_alloc_fence()"
fences are not allocated any more by virtio_gpu_fence_emit(). So there
is no need to pass down a reference to the fence pointer, a plain
pointer is enough now.
Convert virtio_gpu_fence_emit() and callers.
Signed-off-by: Gerd Hoffmann <kraxel@redhat.com>
Reviewed-by: Robert Foss <robert.foss@collabora.com>
Link: http://patchwork.freedesktop.org/patch/msgid/20181128151021.29565-2-kraxel@redhat.com
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|
We need to handle allocation failures and bail out. While at it, tune
the allocation failures down to debug level.
syzbot injected an allocation failure and then hit this WARN_ON.
Reported-by: syzbot+eb6e5365f23c02517dda@syzkaller.appspotmail.com
Signed-off-by: Daniel Vetter <daniel.vetter@intel.com>
Cc: Haneen Mohammed <hamohammed.sa@gmail.com>
Cc: Sean Paul <seanpaul@chromium.org>
Cc: Daniel Vetter <daniel.vetter@ffwll.ch>
Cc: Rodrigo Siqueira <rodrigosiqueiramelo@gmail.com>
Cc: Gustavo Padovan <gustavo.padovan@collabora.com>
Reviewed-by: Eric Anholt <eric@anholt.net>
Link: https://patchwork.freedesktop.org/patch/msgid/20181128101033.4840-1-daniel.vetter@ffwll.ch
|
|
Requested by Boris Brezillon for some vc4 fixes that are needed for future vc4 work.
Signed-off-by: Dave Airlie <airlied@redhat.com>
|
|
git://anongit.freedesktop.org/drm/drm-misc into drm-next
drm-misc-next for v4.21:
Core Changes:
- Merge drm_info.c into drm_debugfs.c
- Complete the fake drm_crtc_commit's hw_done/flip_done sooner.
- Remove deprecated drm_obj_ref/unref functions. All drivers use get/put now.
- Decrease stack use of drm_gem_prime_mmap.
- Improve documentation for dumb callbacks.
Driver Changes:
- Add edid support to virtio.
- Wait on implicit fence in meson and sun4i.
- Add support for BGRX8888 to sun4i.
- Preparation patches for sun4i driver to start supporting linear and tiled YUV formats.
- Add support for HDMI 1.4 4k modes to meson, and support for VIC alternate timings.
- Drop custom dumb_map in vkms.
- Small fixes and cleanups to v3d.
Signed-off-by: Dave Airlie <airlied@redhat.com>
From: Maarten Lankhorst <maarten.lankhorst@linux.intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/151a3270-b1be-ed75-bd58-6b29d741f592@linux.intel.com
|
|
R-Car DU changes for v4.21:
- R8A7744 and R8A77470 support
- R8A77965 LVDS support
- Miscellaneous fixes
Signed-off-by: Dave Airlie <airlied@redhat.com>
From: Laurent Pinchart <laurent.pinchart@ideasonboard.com>
Link: https://patchwork.freedesktop.org/patch/msgid/3165107.GPE8tO0qUE@avalon
|
|
git://anongit.freedesktop.org/drm/drm-intel into drm-next
Changes outside i915:
- Connector property to limit max bpc (Radhakrishna)
- Fix LPE audio runtime PM and deinit (Ville)
- DP FEC prep work (Anusha)
- Mark pinned shmemfs pages as unevictable (Kuo-Hsin)
- Backmerge drm-next (Jani)
Inside i915:
- Revert OA UAPI change that lacks userspace (Joonas)
- Register macro cleanup (Jani)
- 32-bit build fixes on pin flags (Chris)
- Fix MG DP mode and PHY gating for HDMI (Imre)
- DP MST race, hpd and irq fixes (Lyude)
- Combo PHY fixes and cleanup (Imre, Lucas)
- Move display init and cleanup under modeset init and cleanup (José)
- PSR fixes (José)
- Subslice size fixes (Daniele)
- Abstract and clean up fixed point helpers (Jani)
- Plane input CSC for YUV to RGB conversion (Uma)
- Break long iterations for get/put shmemfs pages (Chris)
- Improve DDI encoder hw state readout sanity checks (Imre)
- Fix power well leaks for MST (José)
- Scaler fixes (Ville)
- Watermark fixes (Ville)
- Fix VLV/CHV DSI panel orientation readout (Ville)
- ICL rawclock fixes (Paulo)
- Workaround DMC power well request issues (Imre)
- Plane allocation fix (Maarten)
- Transcoder enum value/ordering robustness fixes (Imre)
- UTS_RELEASE build dependency fix (Hans Holmberg)
Signed-off-by: Dave Airlie <airlied@redhat.com>
From: Jani Nikula <jani.nikula@intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/87k1l4cesj.fsf@intel.com
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the type mem->start is unsigned long, so this can overflow on
32bit system, since the type addr is uint64_t.
Reviewed-by: Christian König <christian.koenig@amd.com>
Signed-off-by: Young Xiao <YangX92@hotmail.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
|
|
There are spelling mistakes in PP_ASSERT_WITH_CODE messages, fix these.
Signed-off-by: Colin Ian King <colin.king@canonical.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
|
|
As amd_uvd_resume() accesses the uvd ring, it must be initialised first
or else we trigger errors like:
[ 5.595963] [drm] Found UVD firmware Version: 1.87 Family ID: 17
[ 5.595969] [drm] PSP loading UVD firmware
[ 5.596266] ------------[ cut here ]------------
[ 5.596268] ODEBUG: assert_init not available (active state 0) object type: timer_list hint: (null)
[ 5.596285] WARNING: CPU: 0 PID: 507 at lib/debugobjects.c:329 debug_print_object+0x6a/0x80
[ 5.596286] Modules linked in: amdgpu(+) hid_logitech_hidpp(+) chash gpu_sched amd_iommu_v2 ttm drm_kms_helper crc32c_intel drm hid_sony ff_memless igb hid_logitech_dj nvme dca i2c_algo_bit nvme_core wmi pinctrl_amd uas usb_storage
[ 5.596299] CPU: 0 PID: 507 Comm: systemd-udevd Tainted: G W 4.20.0-0.rc1.git4.1.fc30.x86_64 #1
[ 5.596301] Hardware name: System manufacturer System Product Name/ROG STRIX X470-I GAMING, BIOS 0901 07/23/2018
[ 5.596303] RIP: 0010:debug_print_object+0x6a/0x80
[ 5.596305] Code: 8b 43 10 83 c2 01 8b 4b 14 4c 89 e6 89 15 e6 82 b0 02 4c 8b 45 00 48 c7 c7 60 fd 34 a6 48 8b 14 c5 a0 da 08 a6 e8 6a 6a b8 ff <0f> 0b 5b 83 05 d0 45 3e 01 01 5d 41 5c c3 83 05 c5 45 3e 01 01 c3
[ 5.596306] RSP: 0018:ffffa02ac863f8c0 EFLAGS: 00010282
[ 5.596307] RAX: 0000000000000000 RBX: ffffa02ac863f8e0 RCX: 0000000000000006
[ 5.596308] RDX: 0000000000000007 RSI: ffff9160e9a7bfe8 RDI: ffff9160f91d6c60
[ 5.596310] RBP: ffffffffa6742740 R08: 0000000000000002 R09: 0000000000000000
[ 5.596311] R10: 0000000000000000 R11: 0000000000000000 R12: ffffffffa634ff69
[ 5.596312] R13: 00000000000b79d0 R14: ffffffffa80f76d8 R15: 0000000000266000
[ 5.596313] FS: 00007f762abf7940(0000) GS:ffff9160f9000000(0000) knlGS:0000000000000000
[ 5.596314] CS: 0010 DS: 0000 ES: 0000 CR0: 0000000080050033
[ 5.596315] CR2: 000055fdc593f000 CR3: 00000007e999c000 CR4: 00000000003406f0
[ 5.596317] Call Trace:
[ 5.596321] debug_object_assert_init+0x14a/0x180
[ 5.596327] del_timer+0x2e/0x90
[ 5.596383] amdgpu_fence_process+0x47/0x100 [amdgpu]
[ 5.596430] amdgpu_uvd_resume+0xf6/0x120 [amdgpu]
[ 5.596475] uvd_v7_0_sw_init+0xe0/0x280 [amdgpu]
[ 5.596523] amdgpu_device_init.cold.30+0xf97/0x14b6 [amdgpu]
[ 5.596563] ? amdgpu_driver_load_kms+0x53/0x330 [amdgpu]
[ 5.596604] amdgpu_driver_load_kms+0x86/0x330 [amdgpu]
[ 5.596614] drm_dev_register+0x115/0x150 [drm]
[ 5.596654] amdgpu_pci_probe+0xbd/0x120 [amdgpu]
[ 5.596658] local_pci_probe+0x41/0x90
[ 5.596661] pci_device_probe+0x188/0x1a0
[ 5.596666] really_probe+0xf8/0x3b0
[ 5.596669] driver_probe_device+0xb3/0xf0
[ 5.596672] __driver_attach+0xe1/0x110
[ 5.596674] ? driver_probe_device+0xf0/0xf0
[ 5.596676] bus_for_each_dev+0x79/0xc0
[ 5.596679] bus_add_driver+0x155/0x230
[ 5.596681] ? 0xffffffffc07d9000
[ 5.596683] driver_register+0x6b/0xb0
[ 5.596685] ? 0xffffffffc07d9000
[ 5.596688] do_one_initcall+0x5d/0x2be
[ 5.596691] ? rcu_read_lock_sched_held+0x79/0x80
[ 5.596693] ? kmem_cache_alloc_trace+0x264/0x290
[ 5.596695] ? do_init_module+0x22/0x210
[ 5.596698] do_init_module+0x5a/0x210
[ 5.596701] load_module+0x2137/0x2430
[ 5.596703] ? lockdep_hardirqs_on+0xed/0x180
[ 5.596714] ? __do_sys_init_module+0x150/0x1a0
[ 5.596715] __do_sys_init_module+0x150/0x1a0
[ 5.596722] do_syscall_64+0x60/0x1f0
[ 5.596725] entry_SYSCALL_64_after_hwframe+0x49/0xbe
[ 5.596726] RIP: 0033:0x7f762b877dee
[ 5.596728] Code: 48 8b 0d 9d 20 0c 00 f7 d8 64 89 01 48 83 c8 ff c3 66 2e 0f 1f 84 00 00 00 00 00 90 f3 0f 1e fa 49 89 ca b8 af 00 00 00 0f 05 <48> 3d 01 f0 ff ff 73 01 c3 48 8b 0d 6a 20 0c 00 f7 d8 64 89 01 48
[ 5.596729] RSP: 002b:00007ffc777b8558 EFLAGS: 00000246 ORIG_RAX: 00000000000000af
[ 5.596730] RAX: ffffffffffffffda RBX: 000055fdc48da320 RCX: 00007f762b877dee
[ 5.596731] RDX: 00007f762b9f284d RSI: 00000000006c5fc6 RDI: 000055fdc527a060
[ 5.596732] RBP: 00007f762b9f284d R08: 0000000000000003 R09: 0000000000000002
[ 5.596733] R10: 000055fdc48ad010 R11: 0000000000000246 R12: 000055fdc527a060
[ 5.596734] R13: 000055fdc48dca20 R14: 0000000000020000 R15: 0000000000000000
[ 5.596740] irq event stamp: 134618
[ 5.596743] hardirqs last enabled at (134617): [<ffffffffa513d52e>] console_unlock+0x45e/0x610
[ 5.596744] hardirqs last disabled at (134618): [<ffffffffa50037e8>] trace_hardirqs_off_thunk+0x1a/0x1c
[ 5.596746] softirqs last enabled at (133146): [<ffffffffa5e00365>] __do_softirq+0x365/0x47c
[ 5.596748] softirqs last disabled at (133139): [<ffffffffa50c64f9>] irq_exit+0x119/0x120
[ 5.596749] ---[ end trace eaee508abfebccdc ]---
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=108709
Reviewed-by: Christian König <christian.koenig@amd.com>
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
Cc: Alex Deucher <alexdeucher@gmail.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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