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2022-07-29Merge ath-next from git://git.kernel.org/pub/scm/linux/kernel/git/kvalo/ath.gitKalle Valo
ath.git patches for v5.20. Major changes: ath11k: * fix WCN9074 to work again * revert rfkill support as it was causing problems
2022-07-29wifi: rtw88: check the return value of alloc_workqueue()William Dean
The function alloc_workqueue() in rtw_core_init() can fail, but there is no check of its return value. To fix this bug, its return value should be checked with new error handling code. Fixes: fe101716c7c9d ("rtw88: replace tx tasklet with work queue") Reported-by: Hacash Robot <hacashRobot@santino.com> Signed-off-by: William Dean <williamsukatube@gmail.com> Reviewed-by: Ping-Ke Shih <pkshih@realtek.com> Signed-off-by: Kalle Valo <kvalo@kernel.org> Link: https://lore.kernel.org/r/20220723063756.2956189-1-williamsukatube@163.com
2022-07-29wifi: rtw89: 8852a: adjust IMR for SER L1Zong-Zhe Yang
SER (system error recovery) L1 (level 1) has a step-by-step handshake process with FW. These handshakes still rely on B_AX_HS0ISR_IND_INT_EN. So, even already during recovery, we enable this bit in IMR. Signed-off-by: Zong-Zhe Yang <kevin_yang@realtek.com> Signed-off-by: Ping-Ke Shih <pkshih@realtek.com> Signed-off-by: Kalle Valo <kvalo@kernel.org> Link: https://lore.kernel.org/r/20220721074952.19676-1-pkshih@realtek.com
2022-07-29wifi: rtw89: 8852a: update RF radio A/B R56Ping-Ke Shih
Update to internal tag HALRF_027_00_060. Signed-off-by: Ping-Ke Shih <pkshih@realtek.com> Signed-off-by: Kalle Valo <kvalo@kernel.org> Link: https://lore.kernel.org/r/20220622091937.11325-1-pkshih@realtek.com
2022-07-29wifi: wcn36xx: Add debugfs entry to read firmware feature stringsBryan O'Donoghue
Add in the ability to easily find the firmware feature bits reported in the get feature exchange without having to compile-in debug prints. root@linaro-alip:~# cat /sys/kernel/debug/ieee80211/phy0/wcn36xx/firmware_feat_caps MCC P2P DOT11AC SLM_SESSIONIZATION DOT11AC_OPMODE SAP32STA TDLS P2P_GO_NOA_DECOUPLE_INIT_SCAN WLANACTIVE_OFFLOAD BEACON_OFFLOAD SCAN_OFFLOAD BCN_MISS_OFFLOAD STA_POWERSAVE STA_ADVANCED_PWRSAVE BCN_FILTER RTT RATECTRL WOW WLAN_ROAM_SCAN_OFFLOAD SPECULATIVE_PS_POLL IBSS_HEARTBEAT_OFFLOAD WLAN_SCAN_OFFLOAD WLAN_PERIODIC_TX_PTRN ADVANCE_TDLS BATCH_SCAN FW_IN_TX_PATH EXTENDED_NSOFFLOAD_SLOT CH_SWITCH_V1 HT40_OBSS_SCAN UPDATE_CHANNEL_LIST WLAN_MCADDR_FLT WLAN_CH144 TDLS_SCAN_COEXISTENCE LINK_LAYER_STATS_MEAS MU_MIMO EXTENDED_SCAN DYNAMIC_WMM_PS MAC_SPOOFED_SCAN FW_STATS WPS_PRBRSP_TMPL BCN_IE_FLT_DELTA Signed-off-by: Bryan O'Donoghue <bryan.odonoghue@linaro.org> Signed-off-by: Kalle Valo <quic_kvalo@quicinc.com> Link: https://lore.kernel.org/r/20220727161655.2286867-5-bryan.odonoghue@linaro.org
2022-07-29wifi: wcn36xx: Move capability bitmap to string translation function to ↵Bryan O'Donoghue
firmware.c Move wcn36xx_get_cap_name() function in main.c into firmware.c as wcn36xx_firmware_get_cap_name(). Reviewed-by: Loic Poulain <loic.poulain@linaro.org> Signed-off-by: Bryan O'Donoghue <bryan.odonoghue@linaro.org> Signed-off-by: Kalle Valo <quic_kvalo@quicinc.com> Link: https://lore.kernel.org/r/20220727161655.2286867-4-bryan.odonoghue@linaro.org
2022-07-29wifi: wcn36xx: Move firmware feature bit storage to dedicated firmware.c fileBryan O'Donoghue
The naming of the get/set/clear firmware feature capability bits doesn't really follow the established namespace pattern of wcn36xx_logicalblock_do_something(); The feature bits are accessed by smd.c and main.c. It would be nice to display the found feature bits in debugfs. To do so though we should tidy up the namespace a bit. Move the firmware feature exchange API to its own file - firmware.c giving us the opportunity to functionally decompose other firmware related accessors as appropriate in future. Reviewed-by: Loic Poulain <loic.poulain@linaro.org> Signed-off-by: Bryan O'Donoghue <bryan.odonoghue@linaro.org> Signed-off-by: Kalle Valo <quic_kvalo@quicinc.com> Link: https://lore.kernel.org/r/20220727161655.2286867-3-bryan.odonoghue@linaro.org
2022-07-29wifi: wcn36xx: Rename clunky firmware feature bit enumBryan O'Donoghue
The enum name "place_holder_in_cap_bitmap" is self descriptively asking to be changed to something else. Rename place_holder_in_cap_bitmap to wcn36xx_firmware_feat_caps so that the contents and intent of the enum is obvious. Reviewed-by: Loic Poulain <loic.poulain@linaro.org> Signed-off-by: Bryan O'Donoghue <bryan.odonoghue@linaro.org> Signed-off-by: Kalle Valo <quic_kvalo@quicinc.com> Link: https://lore.kernel.org/r/20220727161655.2286867-2-bryan.odonoghue@linaro.org
2022-07-29pwm: lpc18xx: Fix period handlingUwe Kleine-König
The calculation: val = (u64)NSEC_PER_SEC * LPC18XX_PWM_TIMER_MAX; do_div(val, lpc18xx_pwm->clk_rate); lpc18xx_pwm->max_period_ns = val; is bogus because with NSEC_PER_SEC = 1000000000, LPC18XX_PWM_TIMER_MAX = 0xffffffff and clk_rate < NSEC_PER_SEC this overflows the (on lpc18xx (i.e. ARM32) 32 bit wide) unsigned int .max_period_ns. This results (dependant of the actual clk rate) in an arbitrary limitation of the maximal period. E.g. for clkrate = 333333333 (Hz) we get max_period_ns = 9 instead of 12884901897. So make .max_period_ns an u64 and pass period and duty as u64 to not discard relevant digits. And also make use of mul_u64_u64_div_u64() which prevents all overflows assuming clk_rate < NSEC_PER_SEC. Fixes: 841e6f90bb78 ("pwm: NXP LPC18xx PWM/SCT driver") Signed-off-by: Uwe Kleine-König <u.kleine-koenig@pengutronix.de> Signed-off-by: Thierry Reding <thierry.reding@gmail.com>
2022-07-29pwm: lpc18xx: Convert to use dev_err_probe()Uwe Kleine-König
This has various upsides: - It emits the symbolic name of the error code - It is silent in the EPROBE_DEFER case and properly sets the defer reason - It reduces the number of code lines slightly Signed-off-by: Uwe Kleine-König <u.kleine-koenig@pengutronix.de> Signed-off-by: Thierry Reding <thierry.reding@gmail.com>
2022-07-29pwm: twl-led: Document some limitations and link to the reference manualUwe Kleine-König
I found these just from reading the reference manual and the driver source. It's unclear to me if there are glitches when updating the ON and OFF registers. Signed-off-by: Uwe Kleine-König <u.kleine-koenig@pengutronix.de> Signed-off-by: Thierry Reding <thierry.reding@gmail.com>
2022-07-29pwm: Add clock based PWM output driverNikita Travkin
Some systems have clocks exposed to external devices. If the clock controller supports duty-cycle configuration, such clocks can be used as pwm outputs. In fact PWM and CLK subsystems are interfaced with in a similar way and an "opposite" driver already exists (clk-pwm). Add a driver that would enable pwm devices to be used via clk subsystem. Acked-by: Uwe Kleine-König <u.kleine-koenig@pengutronix.de> Signed-off-by: Nikita Travkin <nikita@trvn.ru> Signed-off-by: Thierry Reding <thierry.reding@gmail.com>
2022-07-29pwm: sifive: Shut down hardware only after pwmchip_remove() completedUwe Kleine-König
The PWMs are expected to be functional until pwmchip_remove() is called. So disable the clks only afterwards. Fixes: 9e37a53eb051 ("pwm: sifive: Add a driver for SiFive SoC PWM") Signed-off-by: Uwe Kleine-König <u.kleine-koenig@pengutronix.de> Tested-by: Emil Renner Berthing <emil.renner.berthing@canonical.com> Signed-off-by: Thierry Reding <thierry.reding@gmail.com>
2022-07-29pwm: sifive: Ensure the clk is enabled exactly once per running PWMUwe Kleine-König
.apply() assumes the clk to be for a given PWM iff the PWM is enabled. So make sure this is the case when .probe() completes. And in .remove() disable the according number of times. This fixes a clk enable/disable imbalance, if some PWMs are already running at probe time. Fixes: 9e37a53eb051 (pwm: sifive: Add a driver for SiFive SoC PWM) Signed-off-by: Uwe Kleine-König <u.kleine-koenig@pengutronix.de> Tested-by: Emil Renner Berthing <emil.renner.berthing@canonical.com> Signed-off-by: Thierry Reding <thierry.reding@gmail.com>
2022-07-29pwm: sifive: Simplify clk handlingUwe Kleine-König
The clk is necessary for both register access and (enabled) operation of the PWM. Instead of clk_enable() update_hw() if pwm_got_enabled(): clk_enable() elif pwm_got_disabled(): clk_disable() clk_disable() which is some cases only calls clk_enable() to immediately afterwards call clk_disable again, do: if (!prev_state.enabled) clk_enable() # clk enabled exactly once update_hw() if (!next_state.enabled) clk_disable() which is much easier. Signed-off-by: Uwe Kleine-König <u.kleine-koenig@pengutronix.de> Tested-by: Emil Renner Berthing <emil.renner.berthing@canonical.com> Signed-off-by: Thierry Reding <thierry.reding@gmail.com>
2022-07-29pwm: sifive: Enable clk only after period check in .apply()Uwe Kleine-König
For the period check and the initial calculations of register values there is no hardware access needed. So delay enabling the clk a bit to simplify the code flow a bit. Signed-off-by: Uwe Kleine-König <u.kleine-koenig@pengutronix.de> Tested-by: Emil Renner Berthing <emil.renner.berthing@canonical.com> Signed-off-by: Thierry Reding <thierry.reding@gmail.com>
2022-07-29pwm: sifive: Reduce time the controller lock is heldUwe Kleine-König
The lock is only to serialize access and update to user_count and approx_period between different PWMs served by the same pwm_chip. So the lock needs only to be taken during the check if the (chip global) period can and/or needs to be changed. Signed-off-by: Uwe Kleine-König <u.kleine-koenig@pengutronix.de> Tested-by: Emil Renner Berthing <emil.renner.berthing@canonical.com> Signed-off-by: Thierry Reding <thierry.reding@gmail.com>
2022-07-29pwm: sifive: Fold pwm_sifive_enable() into its only callerUwe Kleine-König
There is only a single caller of pwm_sifive_enable() which only enables or disables the clk. Put this implementation directly into pwm_sifive_apply() which allows further simplification in the next change. There is no change in behaviour. Signed-off-by: Uwe Kleine-König <u.kleine-koenig@pengutronix.de> Tested-by: Emil Renner Berthing <emil.renner.berthing@canonical.com> Signed-off-by: Thierry Reding <thierry.reding@gmail.com>
2022-07-29pwm: sifive: Simplify offset calculation for PWMCMP registersUwe Kleine-König
Instead of explicitly using PWM_SIFIVE_PWMCMP0 + pwm->hwpwm * PWM_SIFIVE_SIZE_PWMCMP for each access to one of the PWMCMP registers, introduce a macro that takes the hwpwm id as parameter. For the register definition using a plain 4 instead of the cpp constant PWM_SIFIVE_SIZE_PWMCMP is easier to read, so define the offset macro without the constant. The latter can then be dropped as there are no users left. Signed-off-by: Uwe Kleine-König <u.kleine-koenig@pengutronix.de> Tested-by: Emil Renner Berthing <emil.renner.berthing@canonical.com> Signed-off-by: Thierry Reding <thierry.reding@gmail.com>
2022-07-29netdevsim: fib: Add debugfs knob to simulate route deletion failureIdo Schimmel
The previous patch ("netdevsim: fib: Fix reference count leak on route deletion failure") fixed a reference count leak that happens on route deletion failure. Such failures can only be simulated by injecting slab allocation failures, which cannot be surgically injected. In order to be able to specifically test this scenario, add a debugfs knob that allows user space to fail route deletion requests when enabled. Signed-off-by: Ido Schimmel <idosch@nvidia.com> Reviewed-by: Amit Cohen <amcohen@nvidia.com> Reviewed-by: David Ahern <dsahern@kernel.org> Signed-off-by: David S. Miller <davem@davemloft.net>
2022-07-29netdevsim: fib: Fix reference count leak on route deletion failureIdo Schimmel
As part of FIB offload simulation, netdevsim stores IPv4 and IPv6 routes and holds a reference on FIB info structures that in turn hold a reference on the associated nexthop device(s). In the unlikely case where we are unable to allocate memory to process a route deletion request, netdevsim will not release the reference from the associated FIB info structure, thereby preventing the associated nexthop device(s) from ever being removed [1]. Fix this by scheduling a work item that will flush netdevsim's FIB table upon route deletion failure. This will cause netdevsim to release its reference from all the FIB info structures in its table. Reported by Lucas Leong of Trend Micro Zero Day Initiative. Fixes: 0ae3eb7b4611 ("netdevsim: fib: Perform the route programming in a non-atomic context") Signed-off-by: Ido Schimmel <idosch@nvidia.com> Reviewed-by: Amit Cohen <amcohen@nvidia.com> Reviewed-by: David Ahern <dsahern@kernel.org> Signed-off-by: David S. Miller <davem@davemloft.net>
2022-07-29net: ethernet: mtk_eth_soc: add xdp tx return bulking supportLorenzo Bianconi
Convert mtk_eth_soc driver to xdp_return_frame_bulk APIs. Signed-off-by: Lorenzo Bianconi <lorenzo@kernel.org> Signed-off-by: David S. Miller <davem@davemloft.net>
2022-07-29net: ethernet: mtk_eth_soc: introduce xdp multi-frag supportLorenzo Bianconi
Add the capability to map non-linear xdp frames in XDP_TX and ndo_xdp_xmit callback. Signed-off-by: Lorenzo Bianconi <lorenzo@kernel.org> Signed-off-by: David S. Miller <davem@davemloft.net>
2022-07-29net: ethernet: mtk_eth_soc: introduce mtk_xdp_frame_map utility routineLorenzo Bianconi
This is a preliminary patch to add xdp multi-frag support to mtk_eth_soc driver Signed-off-by: Lorenzo Bianconi <lorenzo@kernel.org> Signed-off-by: David S. Miller <davem@davemloft.net>
2022-07-29vmxnet3: do not reschedule napi for rx processingRonak Doshi
Commit '2c5a5748105a ("vmxnet3: add support for out of order rx completion")' added support for out of order rx completion. Within that patch, an enhancement was done to reschedule napi for processing rx completions. However, it can lead to missing an interrupt. So, this patch reverts that part of the code. Fixes: 2c5a5748105a ("vmxnet3: add support for out of order rx completion") Signed-off-by: Ronak Doshi <doshir@vmware.com> Acked-by: Guolin Yang <gyang@vmware.com> Signed-off-by: David S. Miller <davem@davemloft.net>
2022-07-29crypto: hisilicon/zip - Use the bitmap API to allocate bitmapsChristophe JAILLET
Use bitmap_zalloc()/bitmap_free() instead of hand-writing them. It is less verbose and it improves the semantic. While at it, add an explicit include <linux/bitmap.h>. Signed-off-by: Christophe JAILLET <christophe.jaillet@wanadoo.fr> Signed-off-by: Herbert Xu <herbert@gondor.apana.org.au>
2022-07-29crypto: hisilicon/sec - fix auth key size errorKai Ye
The authentication algorithm supports a maximum of 128-byte keys. The allocated key memory is insufficient. Fixes: 2f072d75d1ab ("crypto: hisilicon - Add aead support on SEC2") Signed-off-by: Kai Ye <yekai13@huawei.com> Signed-off-by: Herbert Xu <herbert@gondor.apana.org.au>
2022-07-29crypto: ccree - Remove a useless dma_supported() callChristophe JAILLET
There is no point in calling dma_supported() before calling dma_set_coherent_mask(). This function already calls dma_supported() and returns an error (-EIO) if it fails. So remove the superfluous dma_supported() call. Moreover, setting a larger DMA mask will never fail when setting a smaller one will succeed, so the whole "while" loop can be removed as well. (see [1]) While at it, fix the name of the function reported in a dev_err(). [1]: https://lore.kernel.org/all/YteQ6Vx2C03UtCkG@infradead.org/ Suggested-by: Christoph Hellwig <hch@infradead.org> Signed-off-by: Christophe JAILLET <christophe.jaillet@wanadoo.fr> Acked-by: Gilad Ben-Yossef <gilad@benyossef.com> Signed-off-by: Herbert Xu <herbert@gondor.apana.org.au>
2022-07-29crypto: ccp - Add support for new CCP/PSP device IDMario Limonciello
Add a new CCP/PSP PCI device ID. This uses same register offsets as the previously supported structure. Signed-off-by: Mario Limonciello <mario.limonciello@amd.com> Acked-by: Tom Lendacky <thomas.lendacky@amd.com> Acked-by: Rijo Thomas <Rijo-john.Thomas@amd.com> Signed-off-by: Herbert Xu <herbert@gondor.apana.org.au>
2022-07-29crypto: inside-secure - Add missing MODULE_DEVICE_TABLE for ofPali Rohár
Without MODULE_DEVICE_TABLE, crypto_safexcel.ko module is not automatically loaded on platforms where inside-secure crypto HW is specified in device tree (e.g. Armada 3720). So add missing MODULE_DEVICE_TABLE for of. Fixes: 1b44c5a60c13 ("crypto: inside-secure - add SafeXcel EIP197 crypto engine driver") Signed-off-by: Pali Rohár <pali@kernel.org> Acked-by: Marek Behún <kabel@kernel.org> Signed-off-by: Herbert Xu <herbert@gondor.apana.org.au>
2022-07-29crypto: hisilicon/hpre - don't use GFP_KERNEL to alloc mem during softirqZhengchao Shao
The hpre encryption driver may be used to encrypt and decrypt packets during the rx softirq, it is not allowed to use GFP_KERNEL. Fixes: c8b4b477079d ("crypto: hisilicon - add HiSilicon HPRE accelerator") Signed-off-by: Zhengchao Shao <shaozhengchao@huawei.com> Signed-off-by: Herbert Xu <herbert@gondor.apana.org.au>
2022-07-29Merge branches 'arm/exynos', 'arm/mediatek', 'arm/msm', 'arm/smmu', ↵Joerg Roedel
'virtio', 'x86/vt-d', 'x86/amd' and 'core' into next
2022-07-29iommu/amd: Fix compile warning in init codeJoerg Roedel
A recent commit introduced these compile warnings: CC drivers/iommu/amd/init.o drivers/iommu/amd/init.c:938:12: error: ‘iommu_init_ga_log’ defined but not used [-Werror=unused-function] 938 | static int iommu_init_ga_log(struct amd_iommu *iommu) | ^~~~~~~~~~~~~~~~~ drivers/iommu/amd/init.c:902:12: error: ‘iommu_ga_log_enable’ defined but not used [-Werror=unused-function] 902 | static int iommu_ga_log_enable(struct amd_iommu *iommu) | ^~~~~~~~~~~~~~~~~~~ The warnings appear because both functions are defined when IRQ remapping is not enabled, but only used when IRQ remapping is enabled. Fix it by only defining the functions when IRQ remapping is enabled. Fixes: c5e1a1eb9279 ("iommu/amd: Simplify and Consolidate Virtual APIC (AVIC) Enablement") Signed-off-by: Joerg Roedel <jroedel@suse.de> Link: https://lore.kernel.org/r/20220729100432.22474-1-joro@8bytes.org
2022-07-29mlxsw: spectrum: Support ethtool 'get_ts_info' callback in Spectrum-2Danielle Ratson
The 'get_ts_info' callback is used for obtaining information about time stamping and PTP hardware clock capabilities of a network device. The existing function of Spectrum-1 is used to advertise the PHC capabilities and the supported RX and TX filters. Implement a similar function for Spectrum-2, expose that the supported 'rx_filters' are all PTP event packets, as for these packets the driver fills the time stamp from the CQE in the SKB. In the future, mlxsw driver will be extended to support one-step PTP in Spectrum-2 and newer ASICs. Then additional 'tx_types' will be supported. Signed-off-by: Danielle Ratson <danieller@nvidia.com> Signed-off-by: Amit Cohen <amcohen@nvidia.com> Reviewed-by: Petr Machata <petrm@nvidia.com> Signed-off-by: Ido Schimmel <idosch@nvidia.com> Signed-off-by: David S. Miller <davem@davemloft.net>
2022-07-29mlxsw: spectrum_ptp: Support SIOCGHWTSTAMP, SIOCSHWTSTAMP ioctlsDanielle Ratson
The SIOCSHWTSTAMP ioctl configures HW timestamping on a given port. In Spectrum-2 and above, each packet gets time stamp by default, but in order to provide an accurate time stamp, software should configure to update the correction field. In addition, the PTP traps are not enabled by default, software should enable it per port or for all ports. The switch behaves like a transparent clock between CPU port and each front panel port. If ingress correction is set on a port for a given packet type, then when such a packet is received via the port, the current time stamp is subtracted from the correction field. If egress correction is set on a port for a given packet type, then when such a packet is transmitted via the port, the current time stamp is added to the correction field. The result is that as the packet ingresses through a port with ingress correction enabled, and egresses through a port with egress correction enabled, the PTP correction field is updated to reflect the time that the packet spent in the ASIC. This can be used to update the correction field of trapped packets by enabling ingress correction on a port where time stamping was enabled, and egress correction on the CPU port. Similarly, for packets transmitted from the host, ingress correction should be enabled on the CPU port, and egress correction on a front-panel port. However, since the correction fields will be updated for all PTP packets crossing the CPU port, in order not to mangle the correction field, the front panel port involved in the packet transfer must have the corresponding correction enabled as well. Therefore, when HW timestamping is enabled on at least one port, we have to configure hardware to update the correction field and trap PTP event packets on all ports. Add reference count as part of 'struct mlxsw_sp_ptp_state', to maintain how many ports use HW timestamping. Handle the correction field configuration only when the first port enables time stamping and when the last port disables time stamping. Store the configuration as part of 'struct mlxsw_sp_ptp_state', as it is global for all ports. The SIOCGHWTSTAMP ioctl is a getter for the current configuration, implement it and use the global configuration. Signed-off-by: Danielle Ratson <danieller@nvidia.com> Signed-off-by: Amit Cohen <amcohen@nvidia.com> Reviewed-by: Petr Machata <petrm@nvidia.com> Signed-off-by: Ido Schimmel <idosch@nvidia.com> Signed-off-by: David S. Miller <davem@davemloft.net>
2022-07-29mlxsw: spectrum: Support time stamping on Spectrum-2Danielle Ratson
As opposed to Spectrum-1, in which time stamps arrive through a pair of dedicated events into a queue and later are being matched to the corresponding packets, in Spectrum-2 we are reading the time stamps directly from the CQE. Software can get the time stamp in UTC format using CQEv2. Add a time stamp field to 'struct mlxsw_skb_cb'. In mlxsw_pci_cqe_{rdq,sdq}_handle() extract the time stamp from the CQE into the new time stamp field. Note that the time stamp in the CQE is represented by 38 bits, which is a short representation of UTC time. Software should create the full time stamp using the global UTC clock. Read UTC clock from hardware only for PTP packets which were trapped to CPU with PTP0 trap ID (event packets). Use the time stamp from the SKB when packet is received or transmitted. Signed-off-by: Danielle Ratson <danieller@nvidia.com> Signed-off-by: Amit Cohen <amcohen@nvidia.com> Reviewed-by: Petr Machata <petrm@nvidia.com> Signed-off-by: Ido Schimmel <idosch@nvidia.com> Signed-off-by: David S. Miller <davem@davemloft.net>
2022-07-29mlxsw: Send PTP packets as data packets to overcome a limitationDanielle Ratson
In Spectrum-2 and Spectrum-3, the correction field of PTP packets which are sent as control packets is not updated at egress port. To overcome this limitation, PTP packets which require time stamp, should be sent as data packets with the following details: 1. FID valid = 1 2. FID value above the maximum FID 3. rx_router_port = 1 >From Spectrum-4 and on, this limitation will be solved. Extend the function which handles TX header, in case that the packet is a PTP packet, add TX header with type=data and all the above mentioned requirements. Add operation as part of 'struct mlxsw_sp_ptp_ops', to be able to separate the handling of PTP packets between different ASICs. Use the data packet solution only for Spectrum-2 and Spectrum-3. Therefore, add a dedicated operation structure for Spectrum-4, as it will be same to Spectrum-2 in PTP implementation, just will not have the limitation of control packets. Signed-off-by: Danielle Ratson <danieller@nvidia.com> Signed-off-by: Amit Cohen <amcohen@nvidia.com> Reviewed-by: Petr Machata <petrm@nvidia.com> Signed-off-by: Ido Schimmel <idosch@nvidia.com> Signed-off-by: David S. Miller <davem@davemloft.net>
2022-07-29mlxsw: spectrum_ptp: Add implementation for physical hardware clock operationsDanielle Ratson
Implement physical hardware clock operations. The main difference between the existing operations of Spectrum-1 and the new operations of Spectrum-2 is the usage of UTC hardware clock instead of FRC. Add support for init() and fini() functions for PTP clock in Spectrum-2. Signed-off-by: Danielle Ratson <danieller@nvidia.com> Signed-off-by: Amit Cohen <amcohen@nvidia.com> Reviewed-by: Petr Machata <petrm@nvidia.com> Signed-off-by: Ido Schimmel <idosch@nvidia.com> Signed-off-by: David S. Miller <davem@davemloft.net>
2022-07-29mlxsw: Query UTC sec and nsec PCI offsets and valuesDanielle Ratson
Query UTC sec and nsec PCI offsets during the pci_init(), to be able to read UTC time later. Implement functions to read UTC seconds and nanoseconds from the offset which was read as part of initialization. Signed-off-by: Danielle Ratson <danieller@nvidia.com> Signed-off-by: Amit Cohen <amcohen@nvidia.com> Reviewed-by: Petr Machata <petrm@nvidia.com> Signed-off-by: Ido Schimmel <idosch@nvidia.com> Signed-off-by: David S. Miller <davem@davemloft.net>
2022-07-29mlxsw: spectrum_ptp: Add PTP initialization / finalization for Spectrum-2Danielle Ratson
Lay the groundwork for Spectrum-2 support. On Spectrum-2, the packets get the time stamps from the CQE, which means that the time stamp is attached to its packet. Configure MTPTPT to set which message types should arrive under which PTP trap. PTP0 will be used for event message types, which means that the packets require time stamp. PTP1 will be used for other packets. Note that in Spectrum-2, all packets contain time stamp by default. The two types of traps (PTP0, PTP1) will be used to separate between PTP_EVENT traps and PTP_GENERAL traps, so then the driver will fill the time stamp as part of the SKB only for event message types. Later the driver will enable the traps using 'MTPCPC.ptp_trap_en' bit. Then, PTP packets start arriving through the PTP traps. Currently, the structure 'mlxsw_sp2_ptp_state' contains only the common structure, the next patches will extend it. Signed-off-by: Danielle Ratson <danieller@nvidia.com> Signed-off-by: Amit Cohen <amcohen@nvidia.com> Reviewed-by: Petr Machata <petrm@nvidia.com> Signed-off-by: Ido Schimmel <idosch@nvidia.com> Signed-off-by: David S. Miller <davem@davemloft.net>
2022-07-29mlxsw: Support CQEv2 for SDQ in Spectrum-2 and newer ASICsDanielle Ratson
Currently, Tx completions are reported using Completion Queue Element version 1 (CQEv1). These elements do not contain the Tx time stamp, which is fine as Spectrum-1 reads Tx time stamps via a dedicated FIFO and Spectrum-2 does not currently support PTP. In preparation for Spectrum-2 PTP support, use CQEv2 for Spectrum-2 and newer ASICs, as this CQE format encodes the Tx time stamp. Signed-off-by: Danielle Ratson <danieller@nvidia.com> Signed-off-by: Amit Cohen <amcohen@nvidia.com> Reviewed-by: Petr Machata <petrm@nvidia.com> Signed-off-by: Ido Schimmel <idosch@nvidia.com> Signed-off-by: David S. Miller <davem@davemloft.net>
2022-07-29mlxsw: spectrum_ptp: Add helper functions to configure PTP trapsAmit Cohen
MTPTPT register is used to set which message types should arrive under which PTP trap. Currently, PTP0 is used for event message types, which means that the packets require time stamp. PTP1 is used for other packets. This configuration will be same for Spectrum-2 and newer ASICs. In preparation for Spectrum-2 PTP support, add helper functions to configure PTP traps and use them for Spectrum-1. These functions will be used later also for Spectrum-2. Signed-off-by: Amit Cohen <amcohen@nvidia.com> Reviewed-by: Petr Machata <petrm@nvidia.com> Signed-off-by: Ido Schimmel <idosch@nvidia.com> Signed-off-by: David S. Miller <davem@davemloft.net>
2022-07-29iommu/amd: Add support for AVIC when SNP is enabledSuravee Suthikulpanit
In order to support AVIC on SNP-enabled system, The IOMMU driver needs to check EFR2[SNPAVICSup] and enables the support by setting SNPAVICEn bit in the IOMMU control register (MMIO offset 18h). For detail, please see section "SEV-SNP Guest Virtual APIC Support" of the AMD I/O Virtualization Technology (IOMMU) Specification. (https://www.amd.com/system/files/TechDocs/48882_IOMMU.pdf) Signed-off-by: Suravee Suthikulpanit <suravee.suthikulpanit@amd.com> Reviewed-by: Jerry Snitselaar <jsnitsel@redhat.com> Link: https://lore.kernel.org/r/20220726134348.6438-3-suravee.suthikulpanit@amd.com Signed-off-by: Joerg Roedel <jroedel@suse.de>
2022-07-29iommu/amd: Simplify and Consolidate Virtual APIC (AVIC) EnablementSuravee Suthikulpanit
Currently, enabling AVIC requires individually detect and enable GAM and GALOG features on each IOMMU, which is difficult to keep track on multi-IOMMU system, where the features needs to be enabled system-wide. In addition, these features do not need to be enabled in early stage. It can be delayed until after amd_iommu_init_pci(). Therefore, consolidate logic for detecting and enabling IOMMU GAM and GALOG features into a helper function, enable_iommus_vapic(), which uses the check_feature_on_all_iommus() helper function to ensure system-wide support of the features before enabling them, and postpone until after amd_iommu_init_pci(). The new function also check and clean up feature enablement residue from previous boot (e.g. in case of booting into kdump kernel), which triggers a WARN_ON (shown below) introduced by the commit a8d4a37d1bb9 ("iommu/amd: Restore GA log/tail pointer on host resume") in iommu_ga_log_enable(). [ 7.731955] ------------[ cut here ]------------ [ 7.736575] WARNING: CPU: 0 PID: 1 at drivers/iommu/amd/init.c:829 iommu_ga_log_enable.isra.0+0x16f/0x190 [ 7.746135] Modules linked in: [ 7.749193] CPU: 0 PID: 1 Comm: swapper/0 Tainted: G W -------- --- 5.19.0-0.rc7.53.eln120.x86_64 #1 [ 7.759706] Hardware name: Dell Inc. PowerEdge R7525/04D5GJ, BIOS 2.1.6 03/09/2021 [ 7.767274] RIP: 0010:iommu_ga_log_enable.isra.0+0x16f/0x190 [ 7.772931] Code: 20 20 00 00 8b 00 f6 c4 01 74 da 48 8b 44 24 08 65 48 2b 04 25 28 00 00 00 75 13 48 83 c4 10 5b 5d e9 f5 00 72 00 0f 0b eb e1 <0f> 0b eb dd e8 f8 66 42 00 48 8b 15 f1 85 53 01 e9 29 ff ff ff 48 [ 7.791679] RSP: 0018:ffffc90000107d20 EFLAGS: 00010206 [ 7.796905] RAX: ffffc90000780000 RBX: 0000000000000100 RCX: ffffc90000780000 [ 7.804038] RDX: 0000000000000001 RSI: ffffc90000780000 RDI: ffff8880451f9800 [ 7.811170] RBP: ffff8880451f9800 R08: ffffffffffffffff R09: 0000000000000000 [ 7.818303] R10: 0000000000000000 R11: 0000000000000000 R12: 0008000000000000 [ 7.825435] R13: ffff8880462ea900 R14: 0000000000000021 R15: 0000000000000000 [ 7.832572] FS: 0000000000000000(0000) GS:ffff888054a00000(0000) knlGS:0000000000000000 [ 7.840657] CS: 0010 DS: 0000 ES: 0000 CR0: 0000000080050033 [ 7.846400] CR2: ffff888054dff000 CR3: 0000000053210000 CR4: 0000000000350eb0 [ 7.853533] Call Trace: [ 7.855979] <TASK> [ 7.858085] amd_iommu_enable_interrupts+0x180/0x270 [ 7.863051] ? iommu_setup+0x271/0x271 [ 7.866803] state_next+0x197/0x2c0 [ 7.870295] ? iommu_setup+0x271/0x271 [ 7.874049] iommu_go_to_state+0x24/0x2c [ 7.877976] amd_iommu_init+0xf/0x29 [ 7.881554] pci_iommu_init+0xe/0x36 [ 7.885133] do_one_initcall+0x44/0x200 [ 7.888975] do_initcalls+0xc8/0xe1 [ 7.892466] kernel_init_freeable+0x14c/0x199 [ 7.896826] ? rest_init+0xd0/0xd0 [ 7.900231] kernel_init+0x16/0x130 [ 7.903723] ret_from_fork+0x22/0x30 [ 7.907306] </TASK> [ 7.909497] ---[ end trace 0000000000000000 ]--- Fixes: commit a8d4a37d1bb9 ("iommu/amd: Restore GA log/tail pointer on host resume") Reported-by: Jerry Snitselaar <jsnitsel@redhat.com> Cc: Joerg Roedel <joro@8bytes.org> Cc: Maxim Levitsky <mlevitsk@redhat.com> Cc: Will Deacon <will@kernel.org> (maintainer:IOMMU DRIVERS) Signed-off-by: Suravee Suthikulpanit <suravee.suthikulpanit@amd.com> Reviewed-by: Jerry Snitselaar <jsnitsel@redhat.com> Link: https://lore.kernel.org/r/20220726134348.6438-2-suravee.suthikulpanit@amd.com Signed-off-by: Joerg Roedel <jroedel@suse.de>
2022-07-29ACPI/IORT: Fix build error implicit-function-declarationRen Zhijie
If CONFIG_ACPI_IORT=y and CONFIG_IOMMU_API is not set, make ARCH=arm64 CROSS_COMPILE=aarch64-linux-gnu-, will be failed, like this: drivers/acpi/arm64/iort.c: In function ‘iort_get_rmr_sids’: drivers/acpi/arm64/iort.c:1406:2: error: implicit declaration of function ‘iort_iommu_rmr_get_resv_regions’; did you mean ‘iort_iommu_get_resv_regions’? [-Werror=implicit-function-declaration] iort_iommu_rmr_get_resv_regions(iommu_fwnode, NULL, head); ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ iort_iommu_get_resv_regions cc1: some warnings being treated as errors make[3]: *** [drivers/acpi/arm64/iort.o] Error 1 The function iort_iommu_rmr_get_resv_regions() is declared under CONFIG_IOMMU_API, and the callers of iort_get_rmr_sids() and iort_put_rmr_sids() would select IOMMU_API. To fix this error, move the definitions to #ifdef CONFIG_IOMMU_API. Fixes: e302eea8f497 ("ACPI/IORT: Add a helper to retrieve RMR info directly") Signed-off-by: Ren Zhijie <renzhijie2@huawei.com> Acked-by: Hanjun Guo <guohanjun@huawei.com> Link: https://lore.kernel.org/r/20220726033520.47865-1-renzhijie2@huawei.com Signed-off-by: Joerg Roedel <jroedel@suse.de>
2022-07-29can: etas_es58x: remove useless calls to usb_fill_bulk_urb()Vincent Mailhol
Aside of urb->transfer_buffer_length and urb->context which might change in the TX path, all the other URB parameters remains constant during runtime. So, there is no reasons to call usb_fill_bulk_urb() each time before submitting an URB. Make sure to initialize all the fields of the URB at allocation time. For the TX branch, replace the call usb_fill_bulk_urb() by an assignment of urb->context. urb->urb->transfer_buffer_length is already set by the caller functions, no need to set it again. For the RX branch, because all parameters are unchanged, simply remove the call to usb_fill_bulk_urb(). Signed-off-by: Vincent Mailhol <mailhol.vincent@wanadoo.fr> Link: https://lore.kernel.org/all/20220729080902.25839-1-mailhol.vincent@wanadoo.fr Signed-off-by: Marc Kleine-Budde <mkl@pengutronix.de>
2022-07-29staging: r8188eu: remove initializer from ret in rtw_pwr_wakeupPhillip Potter
Remove the success initializer from the ret variable in rtw_pwr_wakeup, as we set it later anyway in the success path, and also set on failure. This makes the function appear cleaner and more consistent. Suggested-by: Dan Carpenter <dan.carpenter@oracle.com> Tested-by: Philipp Hortmann <philipp.g.hortmann@gmail.com> Signed-off-by: Phillip Potter <phil@philpotter.co.uk> Link: https://lore.kernel.org/r/20220728231150.972-2-phil@philpotter.co.uk Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
2022-07-28net: dsa: qca8k: move read_switch_id function to common codeChristian Marangi
The same function to read the switch id is used by drivers based on qca8k family switch. Move them to common code to make them accessible also by other drivers. Signed-off-by: Christian Marangi <ansuelsmth@gmail.com> Reviewed-by: Vladimir Oltean <olteanv@gmail.com> Signed-off-by: Jakub Kicinski <kuba@kernel.org>
2022-07-28net: dsa: qca8k: move port LAG functions to common codeChristian Marangi
The same port LAG functions are used by drivers based on qca8k family switch. Move them to common code to make them accessible also by other drivers. Signed-off-by: Christian Marangi <ansuelsmth@gmail.com> Reviewed-by: Vladimir Oltean <olteanv@gmail.com> Signed-off-by: Jakub Kicinski <kuba@kernel.org>
2022-07-28net: dsa: qca8k: move port VLAN functions to common codeChristian Marangi
The same port VLAN functions are used by drivers based on qca8k family switch. Move them to common code to make them accessible also by other drivers. Also drop exposing busy_wait and make it static. Signed-off-by: Christian Marangi <ansuelsmth@gmail.com> Reviewed-by: Vladimir Oltean <olteanv@gmail.com> Signed-off-by: Jakub Kicinski <kuba@kernel.org>
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