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2023-02-23drm/amdgpu: Add convert_error_address function for umc v8_10Candice Li
Add convert_error_address for umc v8_10. Signed-off-by: Candice Li <candice.li@amd.com> Reviewed-by: Tao Zhou <tao.zhou1@amd.com> Reviewed-by: Stanley.Yang <Stanley.Yang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2023-02-23drm/amdgpu: add bad_page_threshold check in ras_eeprom_check_errTao Zhou
bad_page_threshold controls page retirement behavior and it should be also checked. v2: simplify the condition of bad page handling path. Signed-off-by: Tao Zhou <tao.zhou1@amd.com> Reviewed-by: Stanley.Yang <Stanley.Yang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2023-02-23drm/amdgpu: change default behavior of bad_page_threshold parameterTao Zhou
Ignore ras umc bad page threshold by default, GPU initialization won't be stopped in this mode. v2: refine the description of bad_page_threshold. Signed-off-by: Tao Zhou <tao.zhou1@amd.com> Reviewed-by: Stanley.Yang <Stanley.Yang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2023-02-23drm/amdgpu: exclude duplicate pages from UMC RAS UE countTao Zhou
If a UMC bad page is reserved but not freed by an application, the application may trigger uncorrectable error repeatly by accessing the page. v2: add specific function to do the check. v3: remove duplicate pages, calculate new added bad page number. v4: reuse save_bad_pages to calculate new added bad page number. Signed-off-by: Tao Zhou <tao.zhou1@amd.com> Reviewed-by: Stanley.Yang <Stanley.Yang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2023-02-23drm/amdgpu: add umc retire unit elementTao Zhou
It records how many bad pages are retired in one uncorrectable error. Signed-off-by: Tao Zhou <tao.zhou1@amd.com> Reviewed-by: Stanley.Yang <Stanley.Yang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2023-02-23drm/amd/pm: no pptable resetup on runpm exitingEvan Quan
It is assumed the pptable used before runpm is same as the one used afterwards. Thus, we can reuse the stored copy and do not need to resetup the pptable again. Signed-off-by: Evan Quan <evan.quan@amd.com> Reviewed-by: Feifei Xu <feifei.xu@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2023-02-23drm/amd/pm: correct the baco state setting for ArmD3 scenarioEvan Quan
The check for baco support relies on the correct baco state. Signed-off-by: Evan Quan <evan.quan@amd.com> Reviewed-by: Feifei Xu <feifei.xu@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2023-02-23drm/amdgpu: add more fields into device info, caches sizes, etc.Marek Olšák
AMDGPU_IDS_FLAGS_CONFORMANT_TRUNC_COORD: important for conformance on gfx11 Other fields are exposed from IP discovery. enabled_rb_pipes_mask_hi is added for future chips, currently 0. Mesa MR: https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21403 Signed-off-by: Marek Olšák <marek.olsak@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2023-02-23drm/amdkfd: Fix an illegal memory accessQu Huang
In the kfd_wait_on_events() function, the kfd_event_waiter structure is allocated by alloc_event_waiters(), but the event field of the waiter structure is not initialized; When copy_from_user() fails in the kfd_wait_on_events() function, it will enter exception handling to release the previously allocated memory of the waiter structure; Due to the event field of the waiters structure being accessed in the free_waiters() function, this results in illegal memory access and system crash, here is the crash log: localhost kernel: RIP: 0010:native_queued_spin_lock_slowpath+0x185/0x1e0 localhost kernel: RSP: 0018:ffffaa53c362bd60 EFLAGS: 00010082 localhost kernel: RAX: ff3d3d6bff4007cb RBX: 0000000000000282 RCX: 00000000002c0000 localhost kernel: RDX: ffff9e855eeacb80 RSI: 000000000000279c RDI: ffffe7088f6a21d0 localhost kernel: RBP: ffffe7088f6a21d0 R08: 00000000002c0000 R09: ffffaa53c362be64 localhost kernel: R10: ffffaa53c362bbd8 R11: 0000000000000001 R12: 0000000000000002 localhost kernel: R13: ffff9e7ead15d600 R14: 0000000000000000 R15: ffff9e7ead15d698 localhost kernel: FS: 0000152a3d111700(0000) GS:ffff9e855ee80000(0000) knlGS:0000000000000000 localhost kernel: CS: 0010 DS: 0000 ES: 0000 CR0: 0000000080050033 localhost kernel: CR2: 0000152938000010 CR3: 000000044d7a4000 CR4: 00000000003506e0 localhost kernel: Call Trace: localhost kernel: _raw_spin_lock_irqsave+0x30/0x40 localhost kernel: remove_wait_queue+0x12/0x50 localhost kernel: kfd_wait_on_events+0x1b6/0x490 [hydcu] localhost kernel: ? ftrace_graph_caller+0xa0/0xa0 localhost kernel: kfd_ioctl+0x38c/0x4a0 [hydcu] localhost kernel: ? kfd_ioctl_set_trap_handler+0x70/0x70 [hydcu] localhost kernel: ? kfd_ioctl_create_queue+0x5a0/0x5a0 [hydcu] localhost kernel: ? ftrace_graph_caller+0xa0/0xa0 localhost kernel: __x64_sys_ioctl+0x8e/0xd0 localhost kernel: ? syscall_trace_enter.isra.18+0x143/0x1b0 localhost kernel: do_syscall_64+0x33/0x80 localhost kernel: entry_SYSCALL_64_after_hwframe+0x44/0xa9 localhost kernel: RIP: 0033:0x152a4dff68d7 Allocate the structure with kcalloc, and remove redundant 0-initialization and a redundant loop condition check. Signed-off-by: Qu Huang <qu.huang@linux.dev> Signed-off-by: Felix Kuehling <Felix.Kuehling@amd.com> Reviewed-by: Felix Kuehling <Felix.Kuehling@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2023-02-23drm/amdgpu/vcn: set and use harvest configJane Jian
in early init to set harvest config if the vcn0/1 is disabled rather than hard-code the ring attributes as before did Signed-off-by: Jane Jian <Jane.Jian@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2023-02-23drm/amd: Don't allow s0ix on APUs older than RavenMario Limonciello
APUs before Raven didn't support s0ix. As we just relieved some of the safety checks for s0ix to improve power consumption on APUs that support it but that are missing BIOS support a new blind spot was introduced that a user could "try" to run s0ix. Plug this hole so that if users try to run s0ix on anything older than Raven it will just skip suspend of the GPU. Fixes: cf488dcd0ab7 ("drm/amd: Allow s0ix without BIOS support") Suggested-by: Alexander Deucher <Alexander.Deucher@amd.com> Signed-off-by: Mario Limonciello <mario.limonciello@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2023-02-23drm/amdgpu: fix incorrect active rb bitmap for gfx11Hawking Zhang
GFX v11 changes RB_BACKEND_DISABLE related registers from per SA to global ones. The approach to query active rb bitmap needs to be changed accordingly. Query per SE setting returns wrong active RB bitmap especially in the case when some of SA are disabled. With the new approach, driver will generate the active rb bitmap based on active SA bitmap and global active RB bitmap. Signed-off-by: Hawking Zhang <Hawking.Zhang@amd.com> Reviewed-by: Likun Gao <Likun.Gao@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2023-02-23drm/amdgpu: optimize VRAM allocation when using drm buddyShane Xiao
Since the VRAM manager changed from drm mm to drm buddy. It's not necessary to allocate 2MB aligned VRAM for more than 2MB unaligned size, and then do trim. This method improves the allocation efficiency and reduces memory fragmentation. v2: Correct the remainder operation Signed-off-by: Shane Xiao <shane.xiao@amd.com> Reviewed-by: Arunpravin Paneer Selvam <Arunpravin.PaneerSelvam@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2023-02-23drm/amdgpu: remove TOPDOWN flags when allocating VRAM in large bar systemShane Xiao
Since VRAM manager is changed from drm mm to drm buddy, the TOP_DOWN flag should not be set by default in the large bar system. Removing this flag helps improve drm buddy allocator efficiency and reduce the risk of splitting higher order block into lower order. Signed-off-by: Shane Xiao <shane.xiao@amd.com> Reviewed-by: Christian K�nig <christian.koenig@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2023-02-23drm/amdgpu: Select DRM_DISPLAY_HDCP_HELPER in amdgpuHarry Wentland
Keeps this selection with the rest of the DRM HELPER selection. Signed-off-by: Harry Wentland <harry.wentland@amd.com> Reviewed-by: Rodrigo Siqueira <Rodrigo.Siqueira@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2023-02-23drm/amd/display: only warn once in dce110_edp_wait_for_hpd_ready()Hamza Mahfooz
Since, hot plugging eDP displays isn't supported, it is sufficient for us to warn about the lack of a connected display once. So, use ASSERT() in dce110_edp_wait_for_hpd_ready() instead of DC_LOG_WARNING(). Reviewed-by: Harry Wentland <harry.wentland@amd.com> Signed-off-by: Hamza Mahfooz <hamza.mahfooz@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2023-02-23drm/amd/pm: re-enable ac/dc on smu_v13_0_0/10Kenneth Feng
re-enable ac/dc on smu_v13_0_0/10 Signed-off-by: Kenneth Feng <kenneth.feng@amd.com> Reviewed-by: Yang Wang <kevinyang.wang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2023-02-23drm/amdgpu: add tmz support for GC 10.3.6Jesse Zhang
this patch to add tmz support for GC 10.3.6 Signed-off-by: Jesse Zhang <Jesse.Zhang@amd.com> Reviewed-by: Yifan Zhang <yifan1.zhang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2023-02-23drm/amdkfd: To fix sdma page fault issue for GC 11Ruili Ji
For the MQD memory, KMD would always allocate 4K memory, and mes scheduler would write to the end of MQD for unmap flag. Signed-off-by: Ruili Ji <ruiliji2@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2023-02-23mailbox: qcom-apcs-ipc: add IPQ5332 APSS clock supportKathiravan T
IPQ5332 has the APSS clock controller utilizing the same register space as the APCS, so provide access to the APSS utilizing a child device like other IPQ chipsets. Like IPQ6018, the same controller and driver is used, so utilize IPQ6018 match data for IPQ5332. Signed-off-by: Kathiravan T <quic_kathirav@quicinc.com> Reviewed-by: Konrad Dybcio <konrad.dybcio@linaro.org> Signed-off-by: Jassi Brar <jaswinder.singh@linaro.org>
2023-02-23mailbox: qcom-apcs-ipc: enable APCS clock device for MSM8996Dmitry Baryshkov
MSM8996 also has the clock-related part of the APCS mailbox device. Follow the usual pattern and create a child device to handle these clocks. Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Signed-off-by: Jassi Brar <jaswinder.singh@linaro.org>
2023-02-23mailbox: zynq: Switch to flexible array to simplify codeChristophe JAILLET
Using flexible array is more straight forward. It - saves 1 pointer in the 'zynqmp_ipi_pdata' structure - saves an indirection when using this array - saves some LoC and avoids some always spurious pointer arithmetic Signed-off-by: Christophe JAILLET <christophe.jaillet@wanadoo.fr> Signed-off-by: Jassi Brar <jaswinder.singh@linaro.org>
2023-02-23powercap: RAPL: Add Power Limit4 support for Meteor Lake SoCSumeet Pawnikar
Add Meteor Lake SoC to the list of processor models for which Power Limit4 is supported by the Intel RAPL driver. Signed-off-by: Sumeet Pawnikar <sumeet.r.pawnikar@intel.com> Signed-off-by: Rafael J. Wysocki <rafael.j.wysocki@intel.com>
2023-02-23Merge branches 'clk-loongson' and 'clk-qcom' into clk-nextStephen Boyd
* clk-loongson: dt-bindings: clock: add loongson-2 clock dt-bindings: clock: add loongson-2 clock include file * clk-qcom: (143 commits) clk: qcom: apcs-msm8986: Include bitfield.h for FIELD_PREP clk: qcom: Revert sync_state based clk_disable_unused dt-bindings: clock: Merge qcom,gpucc-sm8350 into qcom,gpucc.yaml clk: qcom: gpucc-sdm845: fix clk_dis_wait being programmed for CX GDSC clk: qcom: gpucc-sc7180: fix clk_dis_wait being programmed for CX GDSC dt-bindings: clock: qcom,sa8775p-gcc: add the power-domains property clk: qcom: cpu-8996: add missing cputype include clk: qcom: gcc-sa8775p: remove unused variables clk: qcom: smd-rpm: provide RPM_SMD_XO_CLK_SRC on MSM8996 platform clk: qcom: add msm8996 Core Bus Framework (CBF) support dt-bindings: clock: qcom,msm8996-cbf: Describe the MSM8996 CBF clock controller clk: qcom: add the driver for the MSM8996 APCS clocks clk: qcom: gcc-qcs404: fix duplicate initializer warning clk: qcom: cpu-8996: change setup sequence to follow vendor kernel clk: qcom: cpu-8996: fix PLL clock ops clk: qcom: cpu-8996: fix ACD initialization clk: qcom: cpu-8996: fix PLL configuration sequence clk: qcom: cpu-8996: move qcom_cpu_clk_msm8996_acd_init call clk: qcom: cpu-8996: setup PLLs before registering clocks clk: qcom: cpu-8996: simplify the cpu_clk_notifier_cb ...
2023-02-23Merge branches 'clk-microchip', 'clk-allwinner', 'clk-mediatek', 'clk-imx' ↵Stephen Boyd
and 'clk-core' into clk-next - Various cleanups and improvements to Mediatek clk drivers to reduce code size and modernize the drivers - Support for Mediatek MT7891 SoC clks * clk-microchip: clk: at91: do not compile dt-compat.c for sama7g5 and sam9x60 clk: at91: mark ddr clocks as critical * clk-allwinner: clk: sunxi-ng: d1: Add CAN bus gates and resets dt-bindings: clock: Add D1 CAN bus gates and resets clk: sunxi-ng: d1: Mark cpux clock as critical clk: sunxi-ng: d1: Allow building for R528/T113 clk: sunxi-ng: Move SoC driver conditions to dependencies clk: sunxi-ng: Remove duplicate ARCH_SUNXI dependencies clk: sunxi-ng: Avoid computing the rate twice clk: sunxi-ng: h3/h5: Model H3 CLK_DRAM as a fixed clock clk: sunxi-ng: fix ccu_mmc_timing.c kernel-doc issues * clk-mediatek: (29 commits) clk: mediatek: clk-mtk: Remove unneeded semicolon clk: mediatek: remove MT8195 vppsys/0/1 simple_probe dt-bindings: arm: mediatek: migrate MT8195 vppsys0/1 to mtk-mmsys driver clk: mediatek: add MT7981 clock support dt-bindings: clock: mediatek: add mt7981 clock IDs dt-bindings: clock: Add compatibles for MT7981 clk: mediatek: clk-mt7986-topckgen: Migrate to mtk_clk_simple_probe() clk: mediatek: clk-mt7986-topckgen: Properly keep some clocks enabled clk: mediatek: clk-mt6795-topckgen: Migrate to mtk_clk_simple_probe() clk: mediatek: clk-mt8186-topckgen: Migrate to mtk_clk_simple_probe() clk: mediatek: clk-mt8192: Migrate topckgen to mtk_clk_simple_probe() clk: mediatek: clk-mtk: Register MFG notifier in mtk_clk_simple_probe() clk: mediatek: clk-mt8183: Join top_aud_muxes and top_aud_divs clk: mediatek: mt8186: Join top_adj_div and top_muxes clk: mediatek: mt8192: Join top_adj_divs and top_muxes clk: mediatek: clk-mt8192: Move CLK_TOP_CSW_F26M_D2 in top_divs clk: mediatek: mt8173: Migrate pericfg/topckgen to mtk_clk_simple_probe() clk: mediatek: clk-mtk: Extend mtk_clk_simple_probe() clk: mediatek: Switch to mtk_clk_simple_probe() where possible clk: mediatek: mt8173: Break down clock drivers and allow module build ... * clk-imx: clk: imx: pll14xx: fix recalc_rate for negative kdiv MAINTAINERS: clk: imx: Add Peng Fan as reviewer clk: imx: fix compile testing imxrt1050 clk: imx: set imx_clk_gpr_mux_ops storage-class-specifier to static clk: imx6ul: add ethernet refclock mux support clk: imx6ul: fix enet1 gate configuration clk: imx: add imx_obtain_fixed_of_clock() clk: imx6q: add ethernet refclock mux support clk: imx: add clk-gpr-mux driver dt-bindings: imx8ulp: clock: no spaces before tabs clk: imx6sll: add proper spdx license identifier clk: imx: imx93: invoke imx_register_uart_clocks clk: imx: remove clk_count of imx_register_uart_clocks clk: imx: get stdout clk count from device tree clk: imx: avoid memory leak * clk-core: clk: Honor CLK_OPS_PARENT_ENABLE in clk_core_is_enabled()
2023-02-23Merge branches 'clk-cleanup', 'clk-bindings', 'clk-renesas', 'clk-versa' and ↵Stephen Boyd
'clk-amlogic' into clk-next - Support for Versa 5P49V60 clks * clk-cleanup: clk: rs9: Drop unused pin_xin field clk: sprd: Add dependency for SPRD_UMS512_CLK clk: ralink: fix 'mt7621_gate_is_enabled()' function dt-bindings: clock: remove stih416 bindings drivers/clk: Remove "select SRCU" * clk-bindings: dt-bindings: clock: qcom,sm8450-camcc: constrain required-opps dt-bindings: clock: imx8m-clock: correct i.MX8MQ node name * clk-renesas: clk: renesas: rcar-gen3: Disable R-Car H3 ES1.* clk: renesas: r8a779g0: Add CAN-FD clocks clk: renesas: r8a779g0: Tidy up DMAC name on SYS-DMAC clk: renesas: r8a779a0: Tidy up DMAC name on SYS-DMAC clk: renesas: r8a779g0: Add custom clock for PLL2 clk: renesas: cpg-mssr: Remove superfluous check in resume code clk: renesas: r9a06g032: Handle h2mode setting based on USBF presence clk: renesas: cpg-mssr: Fix use after free if cpg_mssr_common_init() failed clk: renesas: r9a07g044: Add clock and reset entries for CRU clk: renesas: r9a09g011: Add SDHI/eMMC clock and reset entries clk: renesas: r9a09g011: Add USB clock and reset entries clk: renesas: r9a09g011: Add TIM clock and reset entries clk: renesas: r8a779g0: Add display related clocks clk: renesas: rcar-gen4: Restore PLL enum sort order clk: renesas: r8a779g0: Fix OSC predividers clk: renesas: r9a09g011: Add PWM clock and reset entries * clk-versa: dt-bindings: clock: versaclock5: Document 5P49V60 compatible string clk: vc5: Add support for 5P49V60 clk: vc5: Use `clamp()` to restrict PLL range * clk-amlogic: clk: meson: clk-cpu-dyndiv: switch from .round_rate to .determine_rate clk: meson: sclk-div: switch from .round_rate to .determine_rate clk: meson: dualdiv: switch from .round_rate to .determine_rate clk: meson: mpll: Switch from .round_rate to .determine_rate
2023-02-23cpufreq: amd-pstate: remove MODULE_LICENSE in non-modulesNick Alcock
Since commit 8b41fc4454e ("kbuild: create modules.builtin without Makefile.modbuiltin or tristate.conf"), MODULE_LICENSE declarations are used to identify modules. As a consequence, uses of the macro in non-modules will cause modprobe to misidentify their containing object file as a module when it is not (false positives), and modprobe might succeed rather than failing with a suitable error message. So remove it in amd-pstate.c which cannot be built as a module. Signed-off-by: Nick Alcock <nick.alcock@oracle.com> Suggested-by: Luis Chamberlain <mcgrof@kernel.org> [ rjw: Subject and changelog adjustments ] Signed-off-by: Rafael J. Wysocki <rafael.j.wysocki@intel.com>
2023-02-23cpufreq: amd-pstate: Let user know amd-pstate is disabledKai-Heng Feng
Commit 202e683df37c ("cpufreq: amd-pstate: add amd-pstate driver parameter for mode selection") changed the driver to be disabled by default, and this can surprise users. Let users know what happened so they can decide what to do next. Link: https://bugs.launchpad.net/bugs/2006942 Signed-off-by: Kai-Heng Feng <kai.heng.feng@canonical.com> Acked-by: Huang Rui <ray.huang@amd.com> Reviewed-by: Yuan Perry <Perry.Yuan@amd.com> Signed-off-by: Rafael J. Wysocki <rafael.j.wysocki@intel.com>
2023-02-23cpufreq: intel_pstate: Adjust balance_performance EPP for Sapphire RapidsSrinivas Pandruvada
While the majority of server OS distributions are deployed with the "performance" governor as the default, some distributions like Ubuntu use the "powersave" governor by default. While using the "powersave" governor in its default configuration on Sapphire Rapids systems leads to much lower power, the performance is lower by more than 25% for several workloads relative to the "performance" governor. A 37% difference has been reported by www.Phoronix.com [1]. This is a consequence of using a relatively high EPP value in the default configuration of the "powersave" governor and the performance can be made much closer to the "performance" governor's level by adjusting the default EPP value. Based on experiments, with EPP of 0x00, 0x10, 0x20, the performance delta between the "powersave" governor and the "performance" one is around 12%. However, the EPP of 0x20 reduces average power by 18% with respect to the lower EPP values. [Note that raising min_perf_pct in sysfs as high as 50% in addition to adjusting EPP does not improve the performance any further.] For this reason, change the EPP value corresponding to the the default balance_performance setting for Sapphire Rapids to 0x20, which is straightforward, because analogous default EPP adjustment has been applied to Alder Lake and there is a way to set the balance_performance EPP value in intel_pstate based on the processor model already. The goal here is to limit the mean performance delta between the "powersave" governor in the default configuration and the "performance" governor for a wide variety of server workloadsto to around 10-12%. For some bursty workloads, this delta can be still large, as the frequency ramp-up will still lag when the "powersave" governor is in use irrespective of the EPP setting, because the performance governor always requests the maximum possible frequency. Link: https://www.phoronix.com/review/centos-clear-spr/6 # [1] Signed-off-by: Srinivas Pandruvada <srinivas.pandruvada@linux.intel.com> [ rjw: Subject and changelog edits ] Signed-off-by: Rafael J. Wysocki <rafael.j.wysocki@intel.com>
2023-02-23net: sunhme: Fix region requestSean Anderson
devm_request_region is for I/O regions. Use devm_request_mem_region instead. This fixes the driver failing to probe since 99df45c9e0a4 ("sunhme: fix an IS_ERR() vs NULL check in probe"), which checked the result. Fixes: 914d9b2711dd ("sunhme: switch to devres") Signed-off-by: Sean Anderson <seanga2@gmail.com> Reviewed-by: Pavan Chebbi <pavan.chebbi@broadcom.com> Link: https://lore.kernel.org/r/20230222204242.2658247-1-seanga2@gmail.com Signed-off-by: Jakub Kicinski <kuba@kernel.org>
2023-02-23spi: tegra210-quad: set half duplex flagKrishna Yarlagadda
Tegra QSPI controller only supports half duplex transfers. Set half duplex constrain flag. Signed-off-by: Krishna Yarlagadda <kyarlagadda@nvidia.com> Link: https://lore.kernel.org/r/20230223162635.19747-3-kyarlagadda@nvidia.com Signed-off-by: Mark Brown <broonie@kernel.org>
2023-02-23drm/i915: Drop useless intel_dp_has_audio() argumentVille Syrjälä
intel_dp_has_audio() has no need for the crtc_state, so don't pass it in. Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20230220151731.6852-2-ville.syrjala@linux.intel.com Reviewed-by: Uma Shankar <uma.shankar@intel.com>
2023-02-23drm/i915: Fix audio ELD handling for DP MSTVille Syrjälä
I forgot to call intel_audio_compute_config() on DP MST, which means ELD doesn't get populated and passed to the audio driver. References: https://gitlab.freedesktop.org/drm/intel/-/issues/8097 Fixes: 5d986635e296 ("drm/i915/audio: Precompute the ELD") Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20230220151731.6852-1-ville.syrjala@linux.intel.com Reviewed-by: Uma Shankar <uma.shankar@intel.com>
2023-02-23HID: cp2112: Fix driver not registering GPIO IRQ chip as threadedDanny Kaehn
The CP2112 generates interrupts from a polling routine on a thread, and can only support threaded interrupts. This patch configures the gpiochip irq chip with this flag, disallowing consumers to request a hard IRQ from this driver, which resulted in a segfault previously. Signed-off-by: Danny Kaehn <kaehndan@gmail.com> Link: https://lore.kernel.org/r/20230210170044.11835-1-kaehndan@gmail.com Signed-off-by: Benjamin Tissoires <benjamin.tissoires@redhat.com>
2023-02-23Merge branch 'irq/core' into irq/urgentThomas Gleixner
Pull in the upstream changes so a fix for them can be applied.
2023-02-23drm/i915: Mask page table errors on gen2/3 with FBCVille Syrjälä
FBC on gen2/3 seems to trigger page table errors. No visual artifacts are visible, and essentially the same FBC code works on gen4 so these seem entirely spurious. There are also hints in gen3 bspec indicating that certain bits in PGTBL_ER are just not wired up correctly in the hardware. Ideally we'd want to mask out only the bogus bits, but sadly there is no mask for PGTBL_ER, and instead we are forced to mask out all page table errors via EMR :( Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20230125185234.21599-6-ville.syrjala@linux.intel.com Reviewed-by: Vinod Govindapillai <vinod.govindapillai@intel.com>
2023-02-23drm/i915: Extract {i9xx,i965)_error_mask()Ville Syrjälä
Pull the EMR calculation into small helpers. Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20230125185234.21599-5-ville.syrjala@linux.intel.com Reviewed-by: Vinod Govindapillai <vinod.govindapillai@intel.com>
2023-02-23drm/i915: Dump PGTBL_ER on gen2/3/4 error interruptVille Syrjälä
PGTBL_ER contains the individual reasons for the page table error interrupt. Dump it out. Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20230125185234.21599-4-ville.syrjala@linux.intel.com Reviewed-by: Vinod Govindapillai <vinod.govindapillai@intel.com>
2023-02-23drm/i915: Undo rmw damage to gen3 error interrupt handlerVille Syrjälä
The gen2/gen3 irq code is supposed to be identical apart from the 32bit vs. 16bit access width. The recent change to intel_de_rmw() ruined that symmetry. Restore it to avoid needless mental gymnastics when comparing the two codepaths. And while at it remove the extra eir!=0 check that somehow ended up in the gen2 codepath only. Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20230125185234.21599-3-ville.syrjala@linux.intel.com Reviewed-by: Vinod Govindapillai <vinod.govindapillai@intel.com>
2023-02-23drm/i915: Mark FIFO underrun disabled earlierVille Syrjälä
At least on some platforms (tested on ctg) the way vgacon does screen blanking seems to flag constant FIFO underruns, which means we have to be prepared for them while the driver is loading. Currently there is a time window between drm_crtc_init() and intel_sanitize_fifo_underrun_reporting() during which FIFO underrun reporting is in fact marked as enabled. Thus we may end up mistakenly detecting these bogus underruns during driver init. Close the race by marking FIFO underrun reporting as disabled prior to even registering the crtc. intel_sanitize_fifo_underrun_reporting()/etc. will re-enable it later if needed. Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20230125185234.21599-2-ville.syrjala@linux.intel.com Reviewed-by: Vinod Govindapillai <vinod.govindapillai@intel.com>
2023-02-23drm/i915/audio: Track audio state per-transcoderVille Syrjälä
The audio logic lives in the transcoder rather than the pipe, so start tracking it like that. This is only really important for bigjoiner cases where tracking by pipe doesn't work at all since intel_audio_codec_{enable,disable}() won't even be called for the slave pipe. This means the state checker won't find the ELD for the slave pipe and gets upset. The PD->has_audio readout does currently work since that gets read out from the same transcoder for both pipes. For other cases this doesn't actually matter since it's only the normal pipe transcoders that are audio capable, whereas the more special transcoders (EDP/DSI) are not. v2: Fix kernel docs Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20230222151454.24888-1-ville.syrjala@linux.intel.com Reviewed-by: Uma Shankar <uma.shankar@intel.com> Closes: https://gitlab.freedesktop.org/drm/intel/-/issues/8222
2023-02-23octeontx2-pf: Recalculate UDP checksum for ptp 1-step sync packetGeetha sowjanya
When checksum offload is disabled in the driver via ethtool, the PTP 1-step sync packets contain incorrect checksum, since the stack calculates the checksum before driver updates PTP timestamp field in the packet. This results in PTP packets getting dropped at the other end. This patch fixes the issue by re-calculating the UDP checksum after updating PTP timestamp field in the driver. Fixes: 2958d17a8984 ("octeontx2-pf: Add support for ptp 1-step mode on CN10K silicon") Signed-off-by: Geetha sowjanya <gakula@marvell.com> Signed-off-by: Hariprasad Kelam <hkelam@marvell.com> Signed-off-by: Sunil Kovvuri Goutham <sgoutham@marvell.com> Signed-off-by: Sai Krishna <saikrishnag@marvell.com> Link: https://lore.kernel.org/r/20230222113600.1965116-1-saikrishnag@marvell.com Signed-off-by: Paolo Abeni <pabeni@redhat.com>
2023-02-23net: phy: c45: genphy_c45_ethtool_set_eee: validate EEE link modesOleksij Rempel
Currently, it is possible to let some PHYs to advertise not supported EEE link modes. So, validate them before overwriting existing configuration. Signed-off-by: Oleksij Rempel <o.rempel@pengutronix.de> Reviewed-by: Russell King (Oracle) <rmk+kernel@armlinux.org.uk> Signed-off-by: Paolo Abeni <pabeni@redhat.com>
2023-02-23net: phy: do not force EEE supportOleksij Rempel
With following patches: commit 9b01c885be36 ("net: phy: c22: migrate to genphy_c45_write_eee_adv()") commit 5827b168125d ("net: phy: c45: migrate to genphy_c45_write_eee_adv()") we set the advertisement to potentially supported values. This behavior may introduce new regressions on systems where EEE was disabled by default (BIOS or boot loader configuration or by other ways.) At same time, with this patches, we would overwrite EEE advertisement configuration made over ethtool. To avoid this issues, we need to cache initial and ethtool advertisement configuration and store it for later use. Fixes: 9b01c885be36 ("net: phy: c22: migrate to genphy_c45_write_eee_adv()") Fixes: 5827b168125d ("net: phy: c45: migrate to genphy_c45_write_eee_adv()") Fixes: 022c3f87f88e ("net: phy: add genphy_c45_ethtool_get/set_eee() support") Signed-off-by: Oleksij Rempel <o.rempel@pengutronix.de> Reviewed-by: Russell King (Oracle) <rmk+kernel@armlinux.org.uk> Signed-off-by: Paolo Abeni <pabeni@redhat.com>
2023-02-23net: phy: c45: add genphy_c45_an_config_eee_aneg() functionOleksij Rempel
Add new genphy_c45_an_config_eee_aneg() function and replace some of genphy_c45_write_eee_adv() calls. This will be needed by the next patch. Signed-off-by: Oleksij Rempel <o.rempel@pengutronix.de> Reviewed-by: Russell King (Oracle) <rmk+kernel@armlinux.org.uk> Signed-off-by: Paolo Abeni <pabeni@redhat.com>
2023-02-23net: phy: c45: use "supported_eee" instead of supported for access validationOleksij Rempel
Make sure we use proper variable to validate access to potentially not supported registers. Otherwise we will get false read/write errors. Reported-by: kernel test robot <yujie.liu@intel.com> Link: https://lore.kernel.org/oe-lkp/202302211644.c12d19de-yujie.liu@intel.com Fixes: 022c3f87f88e ("net: phy: add genphy_c45_ethtool_get/set_eee() support") Signed-off-by: Oleksij Rempel <o.rempel@pengutronix.de> Reviewed-by: Russell King (Oracle) <rmk+kernel@armlinux.org.uk> Signed-off-by: Paolo Abeni <pabeni@redhat.com>
2023-02-23Merge tag 'gvt-next-fixes-2023-02-23' of https://github.com/intel/gvt-linux ↵Jani Nikula
into drm-intel-next-fixes gvt-next-fixes-2023-02-23 - use debugfs attribute for gvt debugfs entries (Deepak R Varma) - fix memory leak in vgpu destroy for debugfs_lookup() then remove (Greg KH) - fix DRM_I915_GVT kconfig symbol to unbreak menu presentation (Randy Dunlap) - fix typos (Deepak R Varma, Colin Ian King) Signed-off-by: Jani Nikula <jani.nikula@intel.com> From: Zhenyu Wang <zhenyuw@linux.intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/Y/co4cy10KM1/2uX@debian-scheme
2023-02-23drm/i915: Don't use BAR mappings for ring buffers with LLCJohn Harrison
Direction from hardware is that ring buffers should never be mapped via the BAR on systems with LLC. There are too many caching pitfalls due to the way BAR accesses are routed. So it is safest to just not use it. Signed-off-by: John Harrison <John.C.Harrison@Intel.com> Fixes: 9d80841ea4c9 ("drm/i915: Allow ringbuffers to be bound anywhere") Cc: Chris Wilson <chris@chris-wilson.co.uk> Cc: Joonas Lahtinen <joonas.lahtinen@linux.intel.com> Cc: Jani Nikula <jani.nikula@linux.intel.com> Cc: Rodrigo Vivi <rodrigo.vivi@intel.com> Cc: Tvrtko Ursulin <tvrtko.ursulin@linux.intel.com> Cc: intel-gfx@lists.freedesktop.org Cc: <stable@vger.kernel.org> # v4.9+ Tested-by: Jouni Högander <jouni.hogander@intel.com> Reviewed-by: Daniele Ceraolo Spurio <daniele.ceraolospurio@intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20230216011101.1909009-3-John.C.Harrison@Intel.com (cherry picked from commit 65c08339db1ada87afd6cfe7db8e60bb4851d919) Signed-off-by: Jani Nikula <jani.nikula@intel.com>
2023-02-23drm/i915: Don't use stolen memory for ring buffers with LLCJohn Harrison
Direction from hardware is that stolen memory should never be used for ring buffer allocations on platforms with LLC. There are too many caching pitfalls due to the way stolen memory accesses are routed. So it is safest to just not use it. Signed-off-by: John Harrison <John.C.Harrison@Intel.com> Fixes: c58b735fc762 ("drm/i915: Allocate rings from stolen") Cc: Chris Wilson <chris@chris-wilson.co.uk> Cc: Joonas Lahtinen <joonas.lahtinen@linux.intel.com> Cc: Jani Nikula <jani.nikula@linux.intel.com> Cc: Rodrigo Vivi <rodrigo.vivi@intel.com> Cc: Tvrtko Ursulin <tvrtko.ursulin@linux.intel.com> Cc: intel-gfx@lists.freedesktop.org Cc: <stable@vger.kernel.org> # v4.9+ Tested-by: Jouni Högander <jouni.hogander@intel.com> Reviewed-by: Daniele Ceraolo Spurio <daniele.ceraolospurio@intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20230216011101.1909009-2-John.C.Harrison@Intel.com (cherry picked from commit f54c1f6c697c4297f7ed94283c184acc338a5cf8) Signed-off-by: Jani Nikula <jani.nikula@intel.com>
2023-02-23drm/i915/quirks: Add inverted backlight quirk for HP 14-r206nvMavroudis Chatzilaridis
This laptop uses inverted backlight PWM. Thus, without this quirk, backlight brightness decreases as the brightness value increases and vice versa. Closes: https://gitlab.freedesktop.org/drm/intel/-/issues/8013 Cc: stable@vger.kernel.org Signed-off-by: Mavroudis Chatzilaridis <mavchatz@protonmail.com> Reviewed-by: Jani Nikula <jani.nikula@intel.com> Signed-off-by: Jani Nikula <jani.nikula@intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20230201184947.8835-1-mavchatz@protonmail.com (cherry picked from commit 83e7d6fd330d413cb2064e680ffea91b0512a520)
generated by cgit (git 2.34.1) at 2025-09-24 08:44:04 +0000