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2023-02-10Revert "PCI/ASPM: Save L1 PM Substates Capability for suspend/resume"Bjorn Helgaas
This reverts commit 4ff116d0d5fd8a025604b0802d93a2d5f4e465d1. Tasev Nikola and Mark Enriquez reported that resume from suspend was broken in v6.1-rc1. Tasev bisected to a47126ec29f5 ("PCI/PTM: Cache PTM Capability offset"), but we can't figure out how that could be related. Mark saw the same symptoms and bisected to 4ff116d0d5fd ("PCI/ASPM: Save L1 PM Substates Capability for suspend/resume"), which does have a connection: it restores L1 Substates configuration while ASPM L1 may be enabled: pci_restore_state pci_restore_aspm_l1ss_state aspm_program_l1ss pci_write_config_dword(PCI_L1SS_CTL1, ctl1) # L1SS restore pci_restore_pcie_state pcie_capability_write_word(PCI_EXP_LNKCTL, cap[i++]) # L1 restore which is a problem because PCIe r6.0, sec 5.5.4, requires that: If setting either or both of the enable bits for ASPM L1 PM Substates, both ports must be configured as described in this section while ASPM L1 is disabled. Separately, Thomas Witt reported that 5e85eba6f50d ("PCI/ASPM: Refactor L1 PM Substates Control Register programming") broke suspend/resume, and it depends on 4ff116d0d5fd. Revert 4ff116d0d5fd ("PCI/ASPM: Save L1 PM Substates Capability for suspend/resume") to fix the resume issue and enable revert of 5e85eba6f50d to fix the issue Thomas reported. Note that reverting 4ff116d0d5fd means L1 Substates config may be lost on suspend/resume. As far as we know the system will use more power but will still *work* correctly. Fixes: 4ff116d0d5fd ("PCI/ASPM: Save L1 PM Substates Capability for suspend/resume") Link: https://bugzilla.kernel.org/show_bug.cgi?id=216782 Link: https://bugzilla.kernel.org/show_bug.cgi?id=216877 Reported-by: Tasev Nikola <tasev.stefanoska@skynet.be> Reported-by: Mark Enriquez <enriquezmark36@gmail.com> Reported-by: Thomas Witt <kernel@witt.link> Tested-by: Mark Enriquez <enriquezmark36@gmail.com> Tested-by: Thomas Witt <kernel@witt.link> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com> Cc: stable@vger.kernel.org # v6.1+ Cc: Vidya Sagar <vidyas@nvidia.com>
2023-02-10Merge branches 'for-next/sysreg', 'for-next/sme', 'for-next/kselftest', ↵Catalin Marinas
'for-next/misc', 'for-next/sme2', 'for-next/tpidr2', 'for-next/scs', 'for-next/compat-hwcap', 'for-next/ftrace', 'for-next/efi-boot-mmu-on', 'for-next/ptrauth' and 'for-next/pseudo-nmi', remote-tracking branch 'arm64/for-next/perf' into for-next/core * arm64/for-next/perf: perf: arm_spe: Print the version of SPE detected perf: arm_spe: Add support for SPEv1.2 inverted event filtering perf: Add perf_event_attr::config3 drivers/perf: fsl_imx8_ddr_perf: Remove set-but-not-used variable perf: arm_spe: Support new SPEv1.2/v8.7 'not taken' event perf: arm_spe: Use new PMSIDR_EL1 register enums perf: arm_spe: Drop BIT() and use FIELD_GET/PREP accessors arm64/sysreg: Convert SPE registers to automatic generation arm64: Drop SYS_ from SPE register defines perf: arm_spe: Use feature numbering for PMSEVFR_EL1 defines perf/marvell: Add ACPI support to TAD uncore driver perf/marvell: Add ACPI support to DDR uncore driver perf/arm-cmn: Reset DTM_PMU_CONFIG at probe drivers/perf: hisi: Extract initialization of "cpa_pmu->pmu" drivers/perf: hisi: Simplify the parameters of hisi_pmu_init() drivers/perf: hisi: Advertise the PERF_PMU_CAP_NO_EXCLUDE capability * for-next/sysreg: : arm64 sysreg and cpufeature fixes/updates KVM: arm64: Use symbolic definition for ISR_EL1.A arm64/sysreg: Add definition of ISR_EL1 arm64/sysreg: Add definition for ICC_NMIAR1_EL1 arm64/cpufeature: Remove 4 bit assumption in ARM64_FEATURE_MASK() arm64/sysreg: Fix errors in 32 bit enumeration values arm64/cpufeature: Fix field sign for DIT hwcap detection * for-next/sme: : SME-related updates arm64/sme: Optimise SME exit on syscall entry arm64/sme: Don't use streaming mode to probe the maximum SME VL arm64/ptrace: Use system_supports_tpidr2() to check for TPIDR2 support * for-next/kselftest: (23 commits) : arm64 kselftest fixes and improvements kselftest/arm64: Don't require FA64 for streaming SVE+ZA tests kselftest/arm64: Copy whole EXTRA context kselftest/arm64: Fix enumeration of systems without 128 bit SME for SSVE+ZA kselftest/arm64: Fix enumeration of systems without 128 bit SME kselftest/arm64: Don't require FA64 for streaming SVE tests kselftest/arm64: Limit the maximum VL we try to set via ptrace kselftest/arm64: Correct buffer size for SME ZA storage kselftest/arm64: Remove the local NUM_VL definition kselftest/arm64: Verify simultaneous SSVE and ZA context generation kselftest/arm64: Verify that SSVE signal context has SVE_SIG_FLAG_SM set kselftest/arm64: Remove spurious comment from MTE test Makefile kselftest/arm64: Support build of MTE tests with clang kselftest/arm64: Initialise current at build time in signal tests kselftest/arm64: Don't pass headers to the compiler as source kselftest/arm64: Remove redundant _start labels from FP tests kselftest/arm64: Fix .pushsection for strings in FP tests kselftest/arm64: Run BTI selftests on systems without BTI kselftest/arm64: Fix test numbering when skipping tests kselftest/arm64: Skip non-power of 2 SVE vector lengths in fp-stress kselftest/arm64: Only enumerate power of two VLs in syscall-abi ... * for-next/misc: : Miscellaneous arm64 updates arm64/mm: Intercept pfn changes in set_pte_at() Documentation: arm64: correct spelling arm64: traps: attempt to dump all instructions arm64: Apply dynamic shadow call stack patching in two passes arm64: el2_setup.h: fix spelling typo in comments arm64: Kconfig: fix spelling arm64: cpufeature: Use kstrtobool() instead of strtobool() arm64: Avoid repeated AA64MMFR1_EL1 register read on pagefault path arm64: make ARCH_FORCE_MAX_ORDER selectable * for-next/sme2: (23 commits) : Support for arm64 SME 2 and 2.1 arm64/sme: Fix __finalise_el2 SMEver check kselftest/arm64: Remove redundant _start labels from zt-test kselftest/arm64: Add coverage of SME 2 and 2.1 hwcaps kselftest/arm64: Add coverage of the ZT ptrace regset kselftest/arm64: Add SME2 coverage to syscall-abi kselftest/arm64: Add test coverage for ZT register signal frames kselftest/arm64: Teach the generic signal context validation about ZT kselftest/arm64: Enumerate SME2 in the signal test utility code kselftest/arm64: Cover ZT in the FP stress test kselftest/arm64: Add a stress test program for ZT0 arm64/sme: Add hwcaps for SME 2 and 2.1 features arm64/sme: Implement ZT0 ptrace support arm64/sme: Implement signal handling for ZT arm64/sme: Implement context switching for ZT0 arm64/sme: Provide storage for ZT0 arm64/sme: Add basic enumeration for SME2 arm64/sme: Enable host kernel to access ZT0 arm64/sme: Manually encode ZT0 load and store instructions arm64/esr: Document ISS for ZT0 being disabled arm64/sme: Document SME 2 and SME 2.1 ABI ... * for-next/tpidr2: : Include TPIDR2 in the signal context kselftest/arm64: Add test case for TPIDR2 signal frame records kselftest/arm64: Add TPIDR2 to the set of known signal context records arm64/signal: Include TPIDR2 in the signal context arm64/sme: Document ABI for TPIDR2 signal information * for-next/scs: : arm64: harden shadow call stack pointer handling arm64: Stash shadow stack pointer in the task struct on interrupt arm64: Always load shadow stack pointer directly from the task struct * for-next/compat-hwcap: : arm64: Expose compat ARMv8 AArch32 features (HWCAPs) arm64: Add compat hwcap SSBS arm64: Add compat hwcap SB arm64: Add compat hwcap I8MM arm64: Add compat hwcap ASIMDBF16 arm64: Add compat hwcap ASIMDFHM arm64: Add compat hwcap ASIMDDP arm64: Add compat hwcap FPHP and ASIMDHP * for-next/ftrace: : Add arm64 support for DYNAMICE_FTRACE_WITH_CALL_OPS arm64: avoid executing padding bytes during kexec / hibernation arm64: Implement HAVE_DYNAMIC_FTRACE_WITH_CALL_OPS arm64: ftrace: Update stale comment arm64: patching: Add aarch64_insn_write_literal_u64() arm64: insn: Add helpers for BTI arm64: Extend support for CONFIG_FUNCTION_ALIGNMENT ACPI: Don't build ACPICA with '-Os' Compiler attributes: GCC cold function alignment workarounds ftrace: Add DYNAMIC_FTRACE_WITH_CALL_OPS * for-next/efi-boot-mmu-on: : Permit arm64 EFI boot with MMU and caches on arm64: kprobes: Drop ID map text from kprobes blacklist arm64: head: Switch endianness before populating the ID map efi: arm64: enter with MMU and caches enabled arm64: head: Clean the ID map and the HYP text to the PoC if needed arm64: head: avoid cache invalidation when entering with the MMU on arm64: head: record the MMU state at primary entry arm64: kernel: move identity map out of .text mapping arm64: head: Move all finalise_el2 calls to after __enable_mmu * for-next/ptrauth: : arm64 pointer authentication cleanup arm64: pauth: don't sign leaf functions arm64: unify asm-arch manipulation * for-next/pseudo-nmi: : Pseudo-NMI code generation optimisations arm64: irqflags: use alternative branches for pseudo-NMI logic arm64: add ARM64_HAS_GIC_PRIO_RELAXED_SYNC cpucap arm64: make ARM64_HAS_GIC_PRIO_MASKING depend on ARM64_HAS_GIC_CPUIF_SYSREGS arm64: rename ARM64_HAS_IRQ_PRIO_MASKING to ARM64_HAS_GIC_PRIO_MASKING arm64: rename ARM64_HAS_SYSREG_GIC_CPUIF to ARM64_HAS_GIC_CPUIF_SYSREGS
2023-02-10spi: intel: Update help text of PCI and Platform driversMauro Lima
Modern intel hardware uses controllers that work in hardware sequencing mode. In this mode, the controller exposes a subset of operations, like read, write and erase, making it easier and less error-prone for use. On the other hand, most of the controllers handled by the platform driver use software sequencing that exposes the entire set of operations i.e. exposes the low level SPI-NOR opcodes to the software for use. Update PCI and Platform help text with this information. Signed-off-by: Mauro Lima <mauro.lima@eclypsium.com> Acked-by: Mika Westerberg <mika.westerberg@linux.intel.com> Link: https://lore.kernel.org/r/20230210164158.211065-1-mauro.lima@eclypsium.com Signed-off-by: Mark Brown <broonie@kernel.org>
2023-02-10phy: qcom-qmp-combo: Add support for SM8550Abel Vesa
Add SM8550 specific register layout and table configs. Signed-off-by: Abel Vesa <abel.vesa@linaro.org> Reviewed-by: Johan Hovold <johan+linaro@kernel.org> Link: https://lore.kernel.org/r/20230208183421.2874423-7-abel.vesa@linaro.org Signed-off-by: Vinod Koul <vkoul@kernel.org>
2023-02-10phy: qcom-qmp: Add v6 DP register offsetsAbel Vesa
The new SM8550 SoC bumps up the HW version of QMP phy to v6. Add the new DP specific offsets in the generic qmp header file. Signed-off-by: Abel Vesa <abel.vesa@linaro.org> Link: https://lore.kernel.org/r/20230208183421.2874423-6-abel.vesa@linaro.org Signed-off-by: Vinod Koul <vkoul@kernel.org>
2023-02-10phy: qcom-qmp: pcs-usb: Add v6 register offsetsAbel Vesa
The new SM8550 SoC bumps up the HW version of QMP phy to v6 for USB. Add the new PCS USB specific offsets in a dedicated header file. Signed-off-by: Abel Vesa <abel.vesa@linaro.org> Link: https://lore.kernel.org/r/20230208183421.2874423-5-abel.vesa@linaro.org Signed-off-by: Vinod Koul <vkoul@kernel.org>
2023-02-10phy: qcom: Add QCOM SNPS eUSB2 driverAbel Vesa
The SM8550 SoC uses Synopsis eUSB2 PHY for USB 2.0. Add a new driver for it. The driver is based on a downstream implementation. Signed-off-by: Abel Vesa <abel.vesa@linaro.org> Link: https://lore.kernel.org/r/20230208183421.2874423-3-abel.vesa@linaro.org Signed-off-by: Vinod Koul <vkoul@kernel.org>
2023-02-10phy: qcom-qmp-pcie: Add support for SM8550 g3x2 and g4x2 PCIEsAbel Vesa
Add the SM8550 both g4 and g3 configurations. In addition, there is a new "lane shared" table that needs to be configured for g4, along with the No-CSR list of resets. The no-CSR allows resetting the PHY without actually dropping the PHY configuration. The no-CSR needs to be deasserted only after the PHY has been configured and the PLL has stabilized. Co-developed-by: Neil Armstrong <neil.armstrong@linaro.org> Signed-off-by: Neil Armstrong <neil.armstrong@linaro.org> Signed-off-by: Abel Vesa <abel.vesa@linaro.org> Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Reviewed-by: Johan Hovold <johan+linaro@kernel.org> Link: https://lore.kernel.org/r/20230208180020.2761766-9-abel.vesa@linaro.org Signed-off-by: Vinod Koul <vkoul@kernel.org>
2023-02-10phy: qcom-qmp: qserdes-lane-shared: Add v6 register offsetsAbel Vesa
The new SM8550 SoC bumps up the HW version of QMP phy to v6.20 for PCIE g4x2. Add the new lane shared PCIE specific offsets in a dedicated header file. Signed-off-by: Abel Vesa <abel.vesa@linaro.org> Link: https://lore.kernel.org/r/20230208180020.2761766-8-abel.vesa@linaro.org Signed-off-by: Vinod Koul <vkoul@kernel.org>
2023-02-10phy: qcom-qmp: qserdes-txrx: Add v6.20 register offsetsAbel Vesa
The new SM8550 SoC bumps up the HW version of QMP phy to v6.20 for PCIE g4x2. Add the new qserdes TX RX PCIE specific offsets in a dedicated header file. Signed-off-by: Abel Vesa <abel.vesa@linaro.org> Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Link: https://lore.kernel.org/r/20230208180020.2761766-7-abel.vesa@linaro.org Signed-off-by: Vinod Koul <vkoul@kernel.org>
2023-02-10phy: qcom-qmp: pcs-pcie: Add v6.20 register offsetsAbel Vesa
The new SM8550 SoC bumps up the HW version of QMP phy to v6.20 for PCIE g4x2. Add the new PCS PCIE specific offsets in a dedicated header file. Signed-off-by: Abel Vesa <abel.vesa@linaro.org> Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Link: https://lore.kernel.org/r/20230208180020.2761766-6-abel.vesa@linaro.org Signed-off-by: Vinod Koul <vkoul@kernel.org>
2023-02-10phy: qcom-qmp: pcs-pcie: Add v6 register offsetsAbel Vesa
The new SM8550 SoC bumps up the HW version of QMP phy to v6 for USB, UFS and PCIE g3x2. Add the new PCS PCIE specific offsets in a dedicated header file. Signed-off-by: Abel Vesa <abel.vesa@linaro.org> Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Link: https://lore.kernel.org/r/20230208180020.2761766-5-abel.vesa@linaro.org Signed-off-by: Vinod Koul <vkoul@kernel.org>
2023-02-10phy: qcom-qmp: pcs: Add v6.20 register offsetsAbel Vesa
The new SM8550 SoC bumps up the HW version of QMP phy to v6.20 for PCIE g4x2. Add the new PCS offsets in a dedicated header file. Signed-off-by: Abel Vesa <abel.vesa@linaro.org> Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Link: https://lore.kernel.org/r/20230208180020.2761766-4-abel.vesa@linaro.org Signed-off-by: Vinod Koul <vkoul@kernel.org>
2023-02-10phy: qcom-qmp: pcs: Add v6 register offsetsAbel Vesa
The new SM8550 SoC bumps up the HW version of QMP phy to v6 for USB, UFS and PCIE g3x2. Add the new PCS offsets in a dedicated header file. Signed-off-by: Abel Vesa <abel.vesa@linaro.org> Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Link: https://lore.kernel.org/r/20230208180020.2761766-3-abel.vesa@linaro.org Signed-off-by: Vinod Koul <vkoul@kernel.org>
2023-02-10phy: qcom: com-qmp-combo: add SM8350 & SM8450 supportNeil Armstrong
Copy the USB tables from the QMP USB3 PHY driver and add the missing DP tables from downstream to enable USB3/DP on the SM8350 and SM8450 platforms. Signed-off-by: Neil Armstrong <neil.armstrong@linaro.org> Link: https://lore.kernel.org/r/20230206-topic-sm8350-upstream-usb-dp-combo-phy-v1-2-ed849ae6b849@linaro.org Signed-off-by: Vinod Koul <vkoul@kernel.org>
2023-02-10Merge tag 'block-6.2-2023-02-10' of git://git.kernel.dk/linuxLinus Torvalds
Pull block fix from Jens Axboe: "A single fix for a smatch regression introduced in this merge window" * tag 'block-6.2-2023-02-10' of git://git.kernel.dk/linux: nvme-auth: mark nvme_auth_wq static
2023-02-10regulator: max597x: Remove unused variableNaresh Solanki
max597x_regmap_config isn't used & hence remove the same. Signed-off-by: Naresh Solanki <Naresh.Solanki@9elements.com> Link: https://lore.kernel.org/r/20230210163225.1208035-1-Naresh.Solanki@9elements.com Signed-off-by: Mark Brown <broonie@kernel.org>
2023-02-10platform: mellanox: Split initialization procedureVadim Pasternak
Split mlxplat_init() into two by adding mlxplat_pre_init(). Motivation is to prepare 'mlx-platform' driver to support systems equipped PCIe based programming logic device. Such systems are supposed to use different system resources, thus this commit separates resources allocation related code. Signed-off-by: Vadim Pasternak <vadimp@nvidia.com> Reviewed-by: Michael Shych <michaelsh@nvidia.com> Link: https://lore.kernel.org/r/20230208063331.15560-7-vadimp@nvidia.com Signed-off-by: Hans de Goede <hdegoede@redhat.com>
2023-02-10platform: mellanox: Introduce support of new Nvidia L1 switchVadim Pasternak
Add support for new L1 switch nodes providing L1 connectivity for multi-node networking chassis. The purpose is to provide compute server with full management and IO subsystems with connections to L1 switches. System contains the following components: - COMe module based on Intel Coffee Lake CPU - Switch baseboard with two ASICs, while 24 ports of each ASICs are connected to one backplane connector 32 ports of each ASIC are connected to 8 OSFPs - Integrated 60mm dual-rotor FANs inside L1 node (N+2 redundancy) - Support 48V or 54V DC input from the external power server. Add the structures related to the new systems to allow proper activation of the all required platform driver. Add poweroff callback to support deep power cycle flow, which should include special actions against CPLD device for performing graceful operation. Signed-off-by: Vadim Pasternak <vadimp@nvidia.com> Reviewed-by: Michael Shych <michaelsh@nvidia.com> Link: https://lore.kernel.org/r/20230208063331.15560-6-vadimp@nvidia.com Signed-off-by: Hans de Goede <hdegoede@redhat.com>
2023-02-10platform: mellanox: Introduce support for next-generation 800GB/s switchVadim Pasternak
Introduce support for Nvidia next-generation 800GB/s ethernet switch SN5600. SN5600 is 51.2 Tbps Ethernet switch based on Nvidia Spectrum-4 ASIC. It can provide up to 64x800Gb/s (ETH) full bidirectional bandwidth per port using PAM-4 modulations. The system supports 64 Belly to Belly 2x4 OSFP cages. The switch was designed to fit standard 2U racks. Features: - 64 OSFP ports support 800GbE - 10GbE speed. - Additional 25GbE - 1GbE service port on the front panel. - Air-cooled with 3 + 1 redundant fan units. - 1 + 1 redundant 3000W or 3600W PSUs. - System management board is based on Intel Coffee-lake CPU E-2276 with secure-boot support. Signed-off-by: Vadim Pasternak <vadimp@nvidia.com> Reviewed-by: Michael Shych <michaelsh@nvidia.com> Link: https://lore.kernel.org/r/20230208063331.15560-5-vadimp@nvidia.com Signed-off-by: Hans de Goede <hdegoede@redhat.com>
2023-02-10platform: mellanox: Cosmetic changes - rename to more common nameVadim Pasternak
Rename 'nvlink_blade' in several declaration to more common name "chassis_blade", since these names are going to be used for different kinds of blades. Fix 'swicth' to 'switch' in comment. Signed-off-by: Vadim Pasternak <vadimp@nvidia.com> Reviewed-by: Michael Shych <michaelsh@nvidia.com> Link: https://lore.kernel.org/r/20230208063331.15560-4-vadimp@nvidia.com Signed-off-by: Hans de Goede <hdegoede@redhat.com>
2023-02-10platform: mellanox: Change "reset_pwr_converter_fail" attributeVadim Pasternak
Change "reset_voltmon_upgrade_fail" attribute name to "reset_pwr_converter_fail". For systems using "mlxplat_mlxcpld_default_ng_regs_io_data", relevant CPLD 'register.bit' indicates the failure of power converter, while on older systems same 'register.bit' indicates failure of voltage monitor devices upgrade failure. Signed-off-by: Vadim Pasternak <vadimp@nvidia.com> Reviewed-by: Michael Shych <michaelsh@nvidia.com> Link: https://lore.kernel.org/r/20230208063331.15560-3-vadimp@nvidia.com Signed-off-by: Hans de Goede <hdegoede@redhat.com>
2023-02-10platform: mellanox: Introduce support for rack manager switchVadim Pasternak
The rack switch is designed to provide high bandwidth, low latency connectivity using optical fiber as the primary interconnect. System supports 32 OSFP ports, non-blocking switching capacity of 25.6Tbps. System equipped with: - 2 replaceable power supplies (AC) with 1+1 redundancy model. - 7 replaceable fan drawers with 6+1 redundancy model. - 2 External Root of Trust or EROT (Glacier) devices for securing ASICs firmware. Signed-off-by: Vadim Pasternak <vadimp@nvidia.com> Reviewed-by: Michael Shych <michaelsh@nvidia.com> Link: https://lore.kernel.org/r/20230208063331.15560-2-vadimp@nvidia.com Signed-off-by: Hans de Goede <hdegoede@redhat.com>
2023-02-10soc: sunxi: SUN20I_PPU should depend on PMRandy Dunlap
An $ARCH or a platform should select PM. Single device drivers should only depend on PM, not select it. Having SUN20I_PPU depend on PM removes a kconfig warning: WARNING: unmet direct dependencies detected for PM Depends on [n]: !MMU [=y] Selected by [y]: - SUN20I_PPU [=y] && (ARCH_SUNXI || COMPILE_TEST [=y]) Fixes: 0ad2185dcb5e ("soc: sunxi: select CONFIG_PM") Signed-off-by: Randy Dunlap <rdunlap@infradead.org> Cc: Chen-Yu Tsai <wens@csie.org> Cc: Jernej Skrabec <jernej.skrabec@gmail.com> Cc: Samuel Holland <samuel@sholland.org> Cc: linux-arm-kernel@lists.infradead.org Cc: linux-sunxi@lists.linux.dev Cc: Arnd Bergmann <arnd@arndb.de> Cc: Geert Uytterhoeven <geert@linux-m68k.org> Signed-off-by: Arnd Bergmann <arnd@arndb.de>
2023-02-10x86/platform/uv: Make kobj_type structure constantThomas Weißschuh
Since commit ee6d3dd4ed48 ("driver core: make kobj_type constant.") the driver core allows the usage of const struct kobj_type. Take advantage of this to constify the structure definition to prevent modification at runtime. Signed-off-by: Thomas Weißschuh <linux@weissschuh.net> Reviewed-by: Justin Ernst <justin.ernst@hpe.com> Link: https://lore.kernel.org/r/20230207-kobj_type-pdx86-v1-3-8e2c4fb83105@weissschuh.net Reviewed-by: Hans de Goede <hdegoede@redhat.com> Signed-off-by: Hans de Goede <hdegoede@redhat.com>
2023-02-10platform/x86: think-lmi: Make kobj_type structure constantThomas Weißschuh
Since commit ee6d3dd4ed48 ("driver core: make kobj_type constant.") the driver core allows the usage of const struct kobj_type. Take advantage of this to constify the structure definition to prevent modification at runtime. Signed-off-by: Thomas Weißschuh <linux@weissschuh.net> Reviewed-by: Mark Pearson <mpearson-lenovo@squebb.ca> Link: https://lore.kernel.org/r/20230207-kobj_type-pdx86-v1-2-8e2c4fb83105@weissschuh.net Reviewed-by: Hans de Goede <hdegoede@redhat.com> Signed-off-by: Hans de Goede <hdegoede@redhat.com>
2023-02-10platform/x86: dell-wmi-sysman: Make kobj_type structure constantThomas Weißschuh
Since commit ee6d3dd4ed48 ("driver core: make kobj_type constant.") the driver core allows the usage of const struct kobj_type. Take advantage of this to constify the structure definition to prevent modification at runtime. Signed-off-by: Thomas Weißschuh <linux@weissschuh.net> Link: https://lore.kernel.org/r/20230207-kobj_type-pdx86-v1-1-8e2c4fb83105@weissschuh.net Reviewed-by: Hans de Goede <hdegoede@redhat.com> Signed-off-by: Hans de Goede <hdegoede@redhat.com>
2023-02-10platform/x86/intel/vsec: Use mutex for ida_alloc() and ida_free()Srinivas Pandruvada
ID alloc and free functions don't have in built protection for parallel invocation of ida_alloc() and ida_free(). With the current flow in the vsec driver, there is no such scenario. But add mutex protection for potential future changes. Suggested-by: Hans de Goede <hdegoede@redhat.com> Signed-off-by: Srinivas Pandruvada <srinivas.pandruvada@linux.intel.com> Link: https://lore.kernel.org/r/20230207125821.3837799-1-srinivas.pandruvada@linux.intel.com Reviewed-by: Hans de Goede <hdegoede@redhat.com> Signed-off-by: Hans de Goede <hdegoede@redhat.com>
2023-02-10platform/x86/amd: pmc: Add line break for readabilityShyam Sundar S K
Add a line break for the code readability. Reviewed-by: Hans de Goede <hdegoede@redhat.com> Signed-off-by: Shyam Sundar S K <Shyam-sundar.S-k@amd.com> Link: https://lore.kernel.org/r/20230206150855.1938810-5-Shyam-sundar.S-k@amd.com Signed-off-by: Hans de Goede <hdegoede@redhat.com>
2023-02-10platform/x86/amd: pmc: differentiate STB/SMU messaging printsShyam Sundar S K
Modify the dynamic debug print to differentiate between the regular and spill to DRAM usage of the SMU message port. Suggested-by: Sanket Goswami <Sanket.Goswami@amd.com> Reviewed-by: Hans de Goede <hdegoede@redhat.com> Signed-off-by: Shyam Sundar S K <Shyam-sundar.S-k@amd.com> Link: https://lore.kernel.org/r/20230206150855.1938810-4-Shyam-sundar.S-k@amd.com Signed-off-by: Hans de Goede <hdegoede@redhat.com>
2023-02-10platform/x86/amd: pmc: Write dummy postcode into the STB DRAMShyam Sundar S K
Based on the recommendation from the PMFW team in order to get the recent telemetry data present on the STB DRAM the driver is required to send one dummy write to the STB buffer, so it internally triggers the PMFW to emit the latest telemetry data in the STB DRAM region. Reviewed-by: Hans de Goede <hdegoede@redhat.com> Signed-off-by: Shyam Sundar S K <Shyam-sundar.S-k@amd.com> Link: https://lore.kernel.org/r/20230206150855.1938810-3-Shyam-sundar.S-k@amd.com Signed-off-by: Hans de Goede <hdegoede@redhat.com>
2023-02-10platform/x86/amd: pmc: Add num_samples message id support to STBShyam Sundar S K
Recent PMFWs have the support for S2D_NUM_SAMPLES message ID that can tell the current number of samples present within the STB DRAM. num_samples returned would let the driver know the start of the read from the last push location. This way, the driver would emit the top most region of the STB DRAM. Co-developed-by: Sanket Goswami <Sanket.Goswami@amd.com> Signed-off-by: Sanket Goswami <Sanket.Goswami@amd.com> Signed-off-by: Shyam Sundar S K <Shyam-sundar.S-k@amd.com> Link: https://lore.kernel.org/r/20230206150855.1938810-2-Shyam-sundar.S-k@amd.com Reviewed-by: Hans de Goede <hdegoede@redhat.com> Signed-off-by: Hans de Goede <hdegoede@redhat.com>
2023-02-10platform/x86: int3472/discrete: add LEDS_CLASS dependencyArnd Bergmann
int3472 now fails to link when the LED support is disabled: x86_64-linux-ld: drivers/platform/x86/intel/int3472/led.o: in function `skl_int3472_register_pled': led.c:(.text+0xf4): undefined reference to `led_classdev_register_ext' x86_64-linux-ld: led.c:(.text+0x131): undefined reference to `led_add_lookup' x86_64-linux-ld: drivers/platform/x86/intel/int3472/led.o: in function `skl_int3472_unregister_pled': led.c:(.text+0x16b): undefined reference to `led_remove_lookup' x86_64-linux-ld: led.c:(.text+0x177): undefined reference to `led_classdev_unregister' Add an explicit Kconfig dependency. Fixes: 5ae20a8050d0 ("platform/x86: int3472/discrete: Create a LED class device for the privacy LED") Signed-off-by: Arnd Bergmann <arnd@arndb.de> Reviewed-by: Sakari Ailus <sakari.ailus@linux.intel.com> Link: https://lore.kernel.org/r/20230208163658.2129009-1-arnd@kernel.org Reviewed-by: Hans de Goede <hdegoede@redhat.com> Signed-off-by: Hans de Goede <hdegoede@redhat.com>
2023-02-10ipmi: ipmb: Fix the MODULE_PARM_DESC associated to 'retry_time_ms'Christophe JAILLET
'This should be 'retry_time_ms' instead of 'max_retries'. Fixes: 63c4eb347164 ("ipmi:ipmb: Add initial support for IPMI over IPMB") Signed-off-by: Christophe JAILLET <christophe.jaillet@wanadoo.fr> Message-Id: <0d8670cff2c656e99a832a249e77dc90578f67de.1675591429.git.christophe.jaillet@wanadoo.fr> Cc: stable@vger.kernel.org Signed-off-by: Corey Minyard <cminyard@mvista.com>
2023-02-10ipmi:ssif: Add a timer between request retriesCorey Minyard
The IPMI spec has a time (T6) specified between request retries. Add the handling for that. Reported by: Tony Camuso <tcamuso@redhat.com> Cc: stable@vger.kernel.org Signed-off-by: Corey Minyard <cminyard@mvista.com>
2023-02-10ipmi:ssif: Remove rtc_us_timerCorey Minyard
It was cruft left over from older handling of run to completion. Cc: stable@vger.kernel.org Signed-off-by: Corey Minyard <cminyard@mvista.com>
2023-02-10ipmi_ssif: Rename idle state and checkCorey Minyard
Rename the SSIF_IDLE() to IS_SSIF_IDLE(), since that is more clear, and rename SSIF_NORMAL to SSIF_IDLE, since that's more accurate. Cc: stable@vger.kernel.org Signed-off-by: Corey Minyard <cminyard@mvista.com>
2023-02-10ipmi:ssif: resend_msg() cannot failCorey Minyard
The resend_msg() function cannot fail, but there was error handling around using it. Rework the handling of the error, and fix the out of retries debug reporting that was wrong around this, too. Cc: stable@vger.kernel.org Signed-off-by: Corey Minyard <cminyard@mvista.com>
2023-02-10drm/ast: Fix start address computationJocelyn Falempe
During the driver conversion to shmem, the start address for the scanout buffer was set to the base PCI address. In most cases it works because only the lower 24bits are used, and due to alignment it was almost always 0. But on some unlucky hardware, it's not the case, and some uninitialized memory is displayed on the BMC. With shmem, the primary plane is always at offset 0 in GPU memory. * v2: rewrite the patch to set the offset to 0. (Thomas Zimmermann) * v3: move the change to plane_init() and also fix the cursor plane. (Jammy Huang) Tested on a sr645 affected by this bug. Fixes: f2fa5a99ca81 ("drm/ast: Convert ast to SHMEM") Signed-off-by: Jocelyn Falempe <jfalempe@redhat.com> Reviewed-by: Thomas Zimmermann <tzimmermann@suse.de> Reviewed-by: Jammy Huang <jammy_huang@aspeedtech.com> Link: https://patchwork.freedesktop.org/patch/msgid/20230209094417.21630-1-jfalempe@redhat.com
2023-02-10HID: logitech-hidpp: Add more debug statementsBastien Nocera
This should help us figure out some hairy problems with some devices. Signed-off-by: Bastien Nocera <hadess@hadess.net> Link: https://lore.kernel.org/r/20230206221256.129198-1-hadess@hadess.net Signed-off-by: Benjamin Tissoires <benjamin.tissoires@redhat.com>
2023-02-10HID: Add support for Logitech G923 Xbox Edition steering wheelWalt Holman
We get the same level of features as the regular G920. Signed-off-by: Walt Holman <waltholman09@gmail.com> Link: https://lore.kernel.org/r/20230207195051.16373-1-waltholman09@gmail.com Signed-off-by: Benjamin Tissoires <benjamin.tissoires@redhat.com>
2023-02-10HID: logitech-hidpp: Add Signature M650Bastien Nocera
Add support for HID++ over Bluetooth for the Logitech Signature M650 mouse. It comes with a dongle but can also be used over Bluetooth without one. Signed-off-by: Bastien Nocera <hadess@hadess.net> Link: https://lore.kernel.org/r/20220404100311.3304-1-hadess@hadess.net Signed-off-by: Benjamin Tissoires <benjamin.tissoires@redhat.com>
2023-02-10HID: logitech-hidpp: Remove HIDPP_QUIRK_NO_HIDINPUT quirkBastien Nocera
HIDPP_QUIRK_NO_HIDINPUT isn't used by any devices but still happens to work as HIDPP_QUIRK_DELAYED_INIT is defined to the same value. Remove HIDPP_QUIRK_NO_HIDINPUT and use HIDPP_QUIRK_DELAYED_INIT everywhere instead. Tested on a T650 which requires that quirk, and a number of unifying and Bluetooth devices that don't. Signed-off-by: Bastien Nocera <hadess@hadess.net> Link: https://lore.kernel.org/r/20230125121723.3122-2-hadess@hadess.net Signed-off-by: Benjamin Tissoires <benjamin.tissoires@redhat.com>
2023-02-10HID: logitech-hidpp: Don't restart communication if not necessaryBastien Nocera
Don't stop and restart communication with the device unless we need to modify the connect flags used because of a device quirk. Signed-off-by: Bastien Nocera <hadess@hadess.net> Link: https://lore.kernel.org/r/20230125121723.3122-1-hadess@hadess.net Signed-off-by: Benjamin Tissoires <benjamin.tissoires@redhat.com>
2023-02-10HID: logitech-hidpp: Add constants for HID++ 2.0 error codesBastien Nocera
Add constants for HID++ 2.0 error codes listed in "Protocol HID++2.0 essential features" chapter, page 3, in logitech_hidpp_2.0_specification_draft_2012-06-04.pdf Signed-off-by: Bastien Nocera <hadess@hadess.net> Link: https://lore.kernel.org/r/20221207100033.64095-1-hadess@hadess.net Signed-off-by: Benjamin Tissoires <benjamin.tissoires@redhat.com>
2023-02-10Revert "HID: logitech-hidpp: add a module parameter to keep firmware gestures"Bastien Nocera
Now that we're in 2022, and the majority of desktop environments can and should support touchpad gestures through libinput, remove the legacy module parameter that made it possible to use gestures implemented in firmware. This will eventually allow simplifying the driver's initialisation code. This reverts commit 9188dbaed68a4b23dc96eba165265c08caa7dc2a. Signed-off-by: Bastien Nocera <hadess@hadess.net> Signed-off-by: Benjamin Tissoires <benjamin.tissoires@redhat.com> Link: https://lore.kernel.org/r/20221220154345.474596-1-hadess@hadess.net
2023-02-10HID: logitech-hidpp: Hard-code HID++ 1.0 fast scroll supportBastien Nocera
HID++ 1.0 devices only export whether Fast Scrolling is enabled, not whether they are capable of it. Reinstate the original quirks for the 3 supported mice so fast scrolling works again on those devices. Fixes: 908d325e1665 ("HID: logitech-hidpp: Detect hi-res scrolling support") Link: https://bugzilla.kernel.org/show_bug.cgi?id=216903 Signed-off-by: Bastien Nocera <hadess@hadess.net> Signed-off-by: Benjamin Tissoires <benjamin.tissoires@redhat.com> Link: https://lore.kernel.org/r/20230116130937.391441-1-hadess@hadess.net
2023-02-10devtmpfs: add debug info to handle()Longlong Xia
Because handle() is the core function for processing devtmpfs requests, Let's add some debug info in handle() to help users know why failed. Signed-off-by: Longlong Xia <xialonglong1@huawei.com> Link: https://lore.kernel.org/r/20230210095444.4067307-3-xialonglong1@huawei.com Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
2023-02-10driver core: add error handling for devtmpfs_create_node()Longlong Xia
In some cases, devtmpfs_create_node() can return error value. So, make use of it. Signed-off-by: Longlong Xia <xialonglong1@huawei.com> Link: https://lore.kernel.org/r/20230210095444.4067307-2-xialonglong1@huawei.com Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
2023-02-10driver core: bus: update my copyright noticeGreg Kroah-Hartman
There's been some work done recently to the drivers/base/bus.c file so update the copyright notice in it to make those who track those types of things have an easier job. Cc: "Rafael J. Wysocki" <rafael@kernel.org> Link: https://lore.kernel.org/r/20230210091318.733561-1-gregkh@linuxfoundation.org Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
generated by cgit (git 2.34.1) at 2025-09-24 16:24:40 +0000