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2018-11-05drm/amd/display: rename cstate_pstate_watermarks_st1Bhawanpreet Lakha
cstate_pstate_watermarks_st1 -> cstate_pstate_watermarks_st Signed-off-by: vikrant mhaske <vikrant.mhaske@amd.com> Signed-off-by: Bhawanpreet Lakha <Bhawanpreet.Lakha@amd.com> Reviewed-by: Charlene Liu <Charlene.Liu@amd.com> Acked-by: Bhawanpreet Lakha <Bhawanpreet.Lakha@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2018-11-05drm/amd/display: explicit uint64_t castingBhawanpreet Lakha
explicitly cast uint64_t in div64_u64_rem() Signed-off-by: vikrant mhaske <vikrant.mhaske@amd.com> Signed-off-by: Bhawanpreet Lakha <Bhawanpreet.Lakha@amd.com> Reviewed-by: Charlene Liu <Charlene.Liu@amd.com> Acked-by: Bhawanpreet Lakha <Bhawanpreet.Lakha@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2018-11-05drm/amd/display: dc 3.2.02SivapiriyanKumarasamy
Signed-off-by: SivapiriyanKumarasamy <sivapiriyan.kumarasamy@amd.com> Reviewed-by: Harry Wentland <harry.wentland@amd.com> Acked-by: Bhawanpreet Lakha <Bhawanpreet.Lakha@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2018-11-05drm/amd/display: add dccg blockDmytro Laktyushkin
This adds the hw block as well as hooks up dppclk dto programming Signed-off-by: Dmytro Laktyushkin <Dmytro.Laktyushkin@amd.com> Reviewed-by: Charlene Liu <Charlene.Liu@amd.com> Acked-by: Bhawanpreet Lakha <Bhawanpreet.Lakha@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2018-11-05drm/amd/display: rename dccg to clk_mgrDmytro Laktyushkin
In preparation for adding the actual dccg block since the current implementation of dccg is mor eof a clock manager than a hw block Signed-off-by: Dmytro Laktyushkin <Dmytro.Laktyushkin@amd.com> Reviewed-by: Charlene Liu <Charlene.Liu@amd.com> Acked-by: Bhawanpreet Lakha <Bhawanpreet.Lakha@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2018-11-05drm/amd/display: Retiring set_display_requirements in dm_pp_smu.h - part2Fatemeh Darbehani
[Why] In DCN we want direct DAL to SMU calls, with as little as possible interference by pplib. The reason for each pp_smu interface mapping to 1 SMU message is so we can have the sequencing of different SMU message in dal and shared across different OS. This will also simplify debugging as DAL owns this interaction and there's no confusion about division of ownership. [How] Part 2: Separate set_min_deep_sleep_dcfclk message from the SMU messages that are sent as part of dm_pp_apply_clock_for_voltage_request. Directly notify min dcfclk to smu Signed-off-by: Fatemeh Darbehani <fatemeh.darbehani@amd.com> Reviewed-by: Tony Cheng <Tony.Cheng@amd.com> Acked-by: Bhawanpreet Lakha <Bhawanpreet.Lakha@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2018-11-05drm/amd/display: Retiring set_display_requirements in dm_pp_smu.h - part1Fatemeh Darbehani
[Why] In DCN we want direct DAL to SMU calls, with as little as possible interference by pplib. The reason for each pp_smu interface mapping to 1 SMU message is so we can have the sequencing of different SMU message in dal and shared across different OS. This will also simplify debugging as DAL owns this interaction and there's no confusion about division of ownership. [How] Part 1: Separate set_min_deep_Sleep_dcfclk message from the SMU messages that are sent as part of dcn10_pplib_apply_display_requirements. Notify deep sleep dcfclk to smu directly Signed-off-by: Fatemeh Darbehani <fatemeh.darbehani@amd.com> Reviewed-by: Charlene Liu <Charlene.Liu@amd.com> Acked-by: Bhawanpreet Lakha <Bhawanpreet.Lakha@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2018-11-05drm/amd/display: Add link encoder dp_ycbcr420_supported feature flagEric Bernstein
[Why] Need separate feature flag for DP 4:2:0 support, since existing flag is used for HDMI [How] Added dp_ycbcr420_supported to struct encoder_feature_support Signed-off-by: Eric Bernstein <eric.bernstein@amd.com> Reviewed-by: Tony Cheng <Tony.Cheng@amd.com> Acked-by: Bhawanpreet Lakha <Bhawanpreet.Lakha@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2018-11-05drm/amd/display: fix report display count logicEric Yang
[Why] Previous logic to update display count in commit_planes_do_stream_update doesn't cover all cases. [How] Update display count as part of clock updates. Count virtual stream as active to work around headless situation. Signed-off-by: Eric Yang <Eric.Yang2@amd.com> Reviewed-by: Dmytro Laktyushkin <Dmytro.Laktyushkin@amd.com> Acked-by: Bhawanpreet Lakha <Bhawanpreet.Lakha@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2018-11-05drm/amd/display: expose hwseq functions and add registersNevenko Stupar
Make these functions non static and define registers for future use is_lower_pipe_tree_visible(); is_upper_pipe_tree_visible(); is_pipe_tree_visible(); dcn10_program_pte_vm(); set_hdr_multiplier(); update_dchubp_dpp() find_top_pipe_for_stream() Signed-off-by: Nevenko Stupar <Nevenko.Stupar@amd.com> Reviewed-by: Charlene Liu <Charlene.Liu@amd.com> Acked-by: Bhawanpreet Lakha <Bhawanpreet.Lakha@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2018-11-05drm/amd/display: initialize dc_transfer_func->ctxDavid Francis
[Why] dc_transfer_func structs were being passed around with a null pointer, waiting for unsuspecting programmers to dereference it. [How] Initialize it Signed-off-by: David Francis <David.Francis@amd.com> Reviewed-by: Charlene Liu <Charlene.Liu@amd.com> Acked-by: Bhawanpreet Lakha <Bhawanpreet.Lakha@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2018-11-05drm/amd/display: Add support for Freesync 2 HDR and Content to Display MappingSivapiriyanKumarasamy
[Why] Freesync 2 HDR and support for HDR content outside the range of the HDR display require implementation on Dal 3 to better match Dal2. [How] Add support for Freesync HDR and mapping of source content to display ranges for better representation of HDR content. Signed-off-by: SivapiriyanKumarasamy <sivapiriyan.kumarasamy@amd.com> Reviewed-by: Anthony Koo <Anthony.Koo@amd.com> Acked-by: Bhawanpreet Lakha <Bhawanpreet.Lakha@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2018-11-05drm/amd/display: split dccg clock manager into asic foldersDmytro Laktyushkin
Currently dccg contains code related to every dcn revision in a single file. This change splits out the dcn parts of code into correct folders Signed-off-by: Dmytro Laktyushkin <Dmytro.Laktyushkin@amd.com> Reviewed-by: Charlene Liu <Charlene.Liu@amd.com> Acked-by: Bhawanpreet Lakha <Bhawanpreet.Lakha@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2018-11-05drm/amd/display: clean up base dccg structDmytro Laktyushkin
Move things not accessed outside dccg block into dce specific struct Signed-off-by: Dmytro Laktyushkin <Dmytro.Laktyushkin@amd.com> Reviewed-by: Tony Cheng <Tony.Cheng@amd.com> Acked-by: Bhawanpreet Lakha <Bhawanpreet.Lakha@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2018-11-05drm/amd/display: Freesync does not engage on some displaysHarmanprit Tatla
[Why] Current render margin time is not sufficient to compute exit frame time for most monitors. [How] Declared render margin in FPS to compute a exit frame rate that is 4 FPS above the minimum FPS required to engage FreeSync. Also did code clean-up to remove redundancies. Signed-off-by: Harmanprit Tatla <htatla@amd.com> Reviewed-by: Anthony Koo <Anthony.Koo@amd.com> Acked-by: Bhawanpreet Lakha <Bhawanpreet.Lakha@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2018-11-05drm/amd/display: remove safe_to_lower flag from dc, use 2 functions insteadDmytro Laktyushkin
This is done to keep things more readable, avoids a true/false flag in dc interface layer. Signed-off-by: Dmytro Laktyushkin <Dmytro.Laktyushkin@amd.com> Reviewed-by: Tony Cheng <Tony.Cheng@amd.com> Acked-by: Bhawanpreet Lakha <Bhawanpreet.Lakha@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2018-11-05drm/amd/display: move pplib/smu notification to dccg blockDmytro Laktyushkin
This is done to clear up the clock programming sequence since the only time we need to notify pplib is after clock update. This also renames the clk block to dccg, at the moment this block contains both clock management and dccg functionality. Signed-off-by: Dmytro Laktyushkin <Dmytro.Laktyushkin@amd.com> Reviewed-by: Tony Cheng <Tony.Cheng@amd.com> Acked-by: Bhawanpreet Lakha <Bhawanpreet.Lakha@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2018-11-05drm/amd/display: handle max_vstartup larger than vblank_endDmytro Laktyushkin
When vstartup is larger than vblank end we need to set v_fp2 to allow for this early start Signed-off-by: Dmytro Laktyushkin <Dmytro.Laktyushkin@amd.com> Reviewed-by: Tony Cheng <Tony.Cheng@amd.com> Acked-by: Bhawanpreet Lakha <Bhawanpreet.Lakha@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2018-11-05drm/amd/display: dc 3.2.01Fatemeh Darbehani
Signed-off-by: Fatemeh Darbehani <fatemeh.darbehani@amd.com> Reviewed-by: Steven Chiu <Steven.Chiu@amd.com> Acked-by: Bhawanpreet Lakha <Bhawanpreet.Lakha@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2018-11-05drm/amdgpu: fix sdma doorbell comments typoFrank.Min
Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Frank.Min <Frank.Min@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2018-11-05drm/radeon/r300: Mark expected switch fall-throughsGustavo A. R. Silva
In preparation to enabling -Wimplicit-fallthrough, mark switch cases where we are expecting to fall through. Notice that in this particular case, I replaced "Pass through." with "Fall through.", which is what GCC is expecting to find. Addresses-Coverity-ID: 114734 ("Missing break in switch") Addresses-Coverity-ID: 114735 ("Missing break in switch") Signed-off-by: Gustavo A. R. Silva <gustavo@embeddedor.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2018-11-05drm/radeon/r420: mark expected switch fall-throughGustavo A. R. Silva
In preparation to enabling -Wimplicit-fallthrough, mark switch cases where we are expecting to fall through. Addresses-Coverity-ID: 1357317 ("Missing break in switch") Signed-off-by: Gustavo A. R. Silva <gustavo@embeddedor.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2018-11-05drm/amdkfd: Use kmemdup instead of duplicating its functionzhong jiang
kmemdup has implemented the function that kmalloc() + memcpy(). We prefer to kmemdup rather than code opened implementation. Signed-off-by: zhong jiang <zhongjiang@huawei.com> Reviewed-by: Felix Kuehling <Felix.Kuehling@amd.com> Signed-off-by: Felix Kuehling <Felix.Kuehling@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2018-11-05drm/etnaviv: fix bogus fence complete check in timeout handlerLucas Stach
The GPU hardware fences and the job out-fences are on different timelines so it's wrong to compare them. Fix this by only looking at the out-fence. Cc: <stable@vger.kernel.org> Fixes: 2c83a726d6fb (drm/etnaviv: bring back progress check in job timeout handler) Signed-off-by: Lucas Stach <l.stach@pengutronix.de>
2018-11-05drm/vgem: Fix typo in driver feature flagsImre Deak
Fix typo in struct field initializer. Fixes: 3a6eb795641c ("drm/vgem: create a render node for vgem") Cc: Emil Velikov <emil.velikov@collabora.com> Cc: David Airlie <airlied@linux.ie> Cc: Daniel Vetter <daniel.vetter@ffwll.ch> Cc: dri-devel@lists.freedesktop.org Signed-off-by: Imre Deak <imre.deak@intel.com> Reviewed-by: Emil Velikov <emil.velikov@collabora.com> Signed-off-by: Emil Velikov <emil.l.velikov@gmail.com> Link: https://patchwork.freedesktop.org/patch/msgid/20181105145428.5590-1-imre.deak@intel.com
2018-11-05drm/i915/gen9_lp: Fix DMC DC counter debugfs outputImre Deak
On GEN9 LP (BXT/GLK) DC6 is not supported, so don't print the counter on those platforms. So far we did this on GLK too. While at it warn if we forgot to adjust the printout properly for a new platform. (Rodrigo) Testcase: igt/pm_dc/dc6-dpms Cc: Jyoti Yadav <jyoti.r.yadav@intel.com> Cc: Rodrigo Vivi <rodrigo.vivi@intel.com> Signed-off-by: Imre Deak <imre.deak@intel.com> Reviewed-by: Rodrigo Vivi <rodrigo.vivi@intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20181031200220.11608-1-imre.deak@intel.com
2018-11-05vga_switcheroo: Fix missing gpu_bound call at audio client registrationTakashi Iwai
The commit 37a3a98ef601 ("ALSA: hda - Enable runtime PM only for discrete GPU") added a new ops gpu_bound to be called when GPU gets bound. The patch overlooked, however, that vga_switcheroo_enable() is called only once at GPU is bound. When an audio client is registered after that point, it would miss the gpu_bound call. This leads to the unexpected lack of runtime PM in HD-audio side. For addressing that regression, just call gpu_bound callback manually at vga_switcheroo_register_audio_client() when the GPU was already bound. Bugzilla: https://bugzilla.kernel.org/show_bug.cgi?id=201615 Fixes: 37a3a98ef601 ("ALSA: hda - Enable runtime PM only for discrete GPU") Cc: <stable@vger.kernel.org> Reviewed-by: Lukas Wunner <lukas@wunner.de> Signed-off-by: Takashi Iwai <tiwai@suse.de>
2018-11-05drm/imx: ipuv3-plane: add IDMAC timeout warningPhilipp Zabel
ipu_plane_disable should never be called while the plane IDMAC channel is active. The busy wait is just a safety net that should never time out. Signed-off-by: Philipp Zabel <p.zabel@pengutronix.de>
2018-11-05drm/i915/icl: Configure MG DP mode for HDMI ports tooImre Deak
The MG DP mode needs to be configured for Type C static/fixed/legacy HDMI ports too, the same way as it's configured for Type C static/fixed/legacy, fix this. Bspec: 4232, 21735 Cc: Vandita Kulkarni <vandita.kulkarni@intel.com> Cc: Paulo Zanoni <paulo.r.zanoni@intel.com> Cc: Maarten Lankhorst <maarten.lankhorst@linux.intel.com> Signed-off-by: Imre Deak <imre.deak@intel.com> Reviewed-by: José Roberto de Souza <jose.souza@intel.com> Tested-by: José Roberto de Souza <jose.souza@intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20181102192656.4472-3-imre.deak@intel.com
2018-11-05drm/i915/icl: Configure MG PHY gating for HDMI ports tooImre Deak
The MG PHY clock gating needs to be configured for Type C static/fixed/legacy HDMI ports the same way it's configured for Type C static/fixed/legacy and aternate mode DP ports, fix this. Bspec: 4232, 21735 Cc: Vandita Kulkarni <vandita.kulkarni@intel.com> Cc: Paulo Zanoni <paulo.r.zanoni@intel.com> Cc: Maarten Lankhorst <maarten.lankhorst@linux.intel.com> Cc: Manasi Navare <manasi.d.navare@intel.com> Signed-off-by: Imre Deak <imre.deak@intel.com> Reviewed-by: José Roberto de Souza <jose.souza@intel.com> Tested-by: José Roberto de Souza <jose.souza@intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20181102192656.4472-2-imre.deak@intel.com
2018-11-05gpu: ipu-v3: image-convert: allow three rows or columnsPhilipp Zabel
If width or height are in the [2049, 3072] range, allow to use just three tiles in this dimension, instead of four. Signed-off-by: Philipp Zabel <p.zabel@pengutronix.de> Acked-by: Steve Longerbeam <slongerbeam@gmail.com> Tested-by: Steve Longerbeam <slongerbeam@gmail.com>
2018-11-05gpu: ipu-v3: image-convert: disable double buffering if necessaryPhilipp Zabel
Double-buffering only works if tile sizes are the same and the resizing coefficient does not change between tiles, even for non-planar formats. Signed-off-by: Philipp Zabel <p.zabel@pengutronix.de> Acked-by: Steve Longerbeam <slongerbeam@gmail.com> Tested-by: Steve Longerbeam <slongerbeam@gmail.com>
2018-11-05gpu: ipu-v3: image-convert: add some ASCII art to the expositionPhilipp Zabel
Visualize the scaling and rotation pipeline with some ASCII art diagrams. Remove the FIXME comment about missing seam prevention. Signed-off-by: Philipp Zabel <p.zabel@pengutronix.de> Acked-by: Steve Longerbeam <slongerbeam@gmail.com>
2018-11-05gpu: ipu-v3: image-convert: fix bytesperline adjustmentPhilipp Zabel
For planar formats, bytesperline does not depend on BPP. It must always be larger than width and aligned to tile width alignment restrictions. The input bytesperline to ipu_image_convert_adjust() may be uninitialized, so don't rely on input bytesperline as the minimum value for clamp_align(). Use 2 << w_align as the minimum instead. Signed-off-by: Philipp Zabel <p.zabel@pengutronix.de> [slongerbeam@gmail.com: clamp input bytesperline] Signed-off-by: Steve Longerbeam <slongerbeam@gmail.com> Signed-off-by: Philipp Zabel <p.zabel@pengutronix.de>
2018-11-05gpu: ipu-v3: image-convert: relax alignment restrictionsPhilipp Zabel
For the planar but U/V-packed formats NV12 and NV16, 8 pixel width alignment is good enough to fulfill the 8 byte stride requirement. If we allow the input 8-pixel DMA bursts to overshoot the end of the line, the only input alignment restrictions are dictated by the pixel format and 8-byte aligned line start address. Since different tile sizes are allowed, the output tile with / height alignment doesn't need to be multiplied by number of columns / rows. Signed-off-by: Philipp Zabel <p.zabel@pengutronix.de> [slongerbeam@gmail.com: Bring in the fixes to format width and height alignment restrictions from imx-media-mem2mem.c.] Signed-off-by: Steve Longerbeam <slongerbeam@gmail.com> Signed-off-by: Philipp Zabel <p.zabel@pengutronix.de>
2018-11-05gpu: ipu-v3: image-convert: fix debug output for varying tile sizesPhilipp Zabel
Since tile dimensions now vary between tiles, add debug output for each tile's position and dimensions. Signed-off-by: Philipp Zabel <p.zabel@pengutronix.de> Acked-by: Steve Longerbeam <slongerbeam@gmail.com> Tested-by: Steve Longerbeam <slongerbeam@gmail.com>
2018-11-05gpu: ipu-v3: image-convert: select optimal seam positionsPhilipp Zabel
Select seam positions that minimize distortions during seam hiding while satifying input and output IDMAC, rotator, and image format constraints. This code looks for aligned output seam positions that minimize the difference between the fractional corresponding ideal input positions and the input positions rounded to alignment requirements. Since now tiles can be sized differently, alignment restrictions of the complete image can be relaxed in the next step. Signed-off-by: Philipp Zabel <p.zabel@pengutronix.de> Acked-by: Steve Longerbeam <slongerbeam@gmail.com> Tested-by: Steve Longerbeam <slongerbeam@gmail.com>
2018-11-05gpu: ipu-v3: image-convert: move tile alignment helpersPhilipp Zabel
Move tile_width_align and tile_height_align up so they can be used by the tile edge position calculation code. Signed-off-by: Philipp Zabel <p.zabel@pengutronix.de> Acked-by: Steve Longerbeam <slongerbeam@gmail.com> Tested-by: Steve Longerbeam <slongerbeam@gmail.com>
2018-11-05gpu: ipu-v3: image-convert: calculate tile dimensions and offsets outside ↵Philipp Zabel
fill_image This will allow to calculate seam positions after initializing the ipu_image base structure but before calculating tile dimensions. Signed-off-by: Philipp Zabel <p.zabel@pengutronix.de> Acked-by: Steve Longerbeam <slongerbeam@gmail.com> Tested-by: Steve Longerbeam <slongerbeam@gmail.com>
2018-11-05gpu: ipu-v3: image-convert: store tile top/left positionPhilipp Zabel
Store tile top/left position in pixels in the tile structure. This will allow overlapping tiles with different sizes later. Signed-off-by: Philipp Zabel <p.zabel@pengutronix.de> Acked-by: Steve Longerbeam <slongerbeam@gmail.com> Tested-by: Steve Longerbeam <slongerbeam@gmail.com>
2018-11-05gpu: ipu-v3: image-convert: reconfigure IC per tilePhilipp Zabel
For differently sized tiles or if the resizing coefficients change, we have to stop, reconfigure, and restart the IC between tiles. Signed-off-by: Philipp Zabel <p.zabel@pengutronix.de> Acked-by: Steve Longerbeam <slongerbeam@gmail.com> Tested-by: Steve Longerbeam <slongerbeam@gmail.com>
2018-11-05gpu: ipu-v3: image-convert: calculate per-tile resize coefficientsPhilipp Zabel
Slightly modifying resize coefficients per-tile allows to completely hide the seams between tiles and to sample the correct input pixels at the bottom and right edges of the image. Tiling requires a bilinear interpolator reset at each tile start, which causes the image to be slightly shifted if the starting pixel should not have been sampled from an integer pixel position in the source image according to the full image resizing ratio. To work around this hardware limitation, calculate per-tile resizing coefficients that make sure that the correct input pixels are sampled at the tile end. Signed-off-by: Philipp Zabel <p.zabel@pengutronix.de> Acked-by: Steve Longerbeam <slongerbeam@gmail.com> Tested-by: Steve Longerbeam <slongerbeam@gmail.com>
2018-11-05gpu: ipu-v3: image-convert: prepare for per-tile configurationPhilipp Zabel
Let convert_start start from a given tile index, allocate intermediate tile with maximum tile size. Signed-off-by: Philipp Zabel <p.zabel@pengutronix.de> Acked-by: Steve Longerbeam <slongerbeam@gmail.com> Tested-by: Steve Longerbeam <slongerbeam@gmail.com>
2018-11-05gpu: ipu-v3: image-convert: Catch unaligned tile offsetsSteve Longerbeam
Catch calculated tile offsets that are not 8-byte aligned as required by the IDMAC engine and return error in calc_tile_offsets(). Signed-off-by: Steve Longerbeam <slongerbeam@gmail.com> Tested-by: Philipp Zabel <p.zabel@pengutronix.de> Signed-off-by: Philipp Zabel <p.zabel@pengutronix.de>
2018-11-05gpu: ipu-v3: image-convert: Remove need_abort flagSteve Longerbeam
The need_abort flag is not really needed anymore in __ipu_image_convert_abort(), remove it. No functional changes. Signed-off-by: Steve Longerbeam <slongerbeam@gmail.com> Tested-by: Philipp Zabel <p.zabel@pengutronix.de> Signed-off-by: Philipp Zabel <p.zabel@pengutronix.de>
2018-11-05gpu: ipu-v3: image-convert: Allow reentrancy into abortSteve Longerbeam
Allow reentrancy into ipu_image_convert_abort(), by moving re-init of ctx->aborted completion under the spin lock, and only if there is an active run, and complete all waiters do_bh(). Note: ipu_image_convert_unprepare() is still _not_ reentrant, and can't be made reentrant. Signed-off-by: Steve Longerbeam <slongerbeam@gmail.com> Tested-by: Philipp Zabel <p.zabel@pengutronix.de> Signed-off-by: Philipp Zabel <p.zabel@pengutronix.de>
2018-11-05gpu: ipu-v3: image-convert: Only wait for abort completion if active runSteve Longerbeam
Only wait for the ctx->aborted completion if there is an active run in progress, otherwise the wait will just timeout after 10 seconds. If there is no active run in progress, the done queue just needs to be emptied. Signed-off-by: Steve Longerbeam <slongerbeam@gmail.com> Tested-by: Philipp Zabel <p.zabel@pengutronix.de> Signed-off-by: Philipp Zabel <p.zabel@pengutronix.de>
2018-11-05gpu: ipu-v3: image-convert: Prevent race between run and unprepareSteve Longerbeam
Prevent possible race by parallel threads between ipu_image_convert_run() and ipu_image_convert_unprepare(). This involves setting ctx->aborting to true unconditionally so that no new job runs can be queued during unprepare, and holding the ctx->aborting flag until the context is freed. Note that the "normal" ipu_image_convert_abort() case (e.g. not during context unprepare) should clear the ctx->aborting flag after aborting any active run and clearing the context's pending queue. This is because it should be possible to continue to use the conversion context and queue more runs after an abort. Signed-off-by: Steve Longerbeam <slongerbeam@gmail.com> Tested-by: Philipp Zabel <p.zabel@pengutronix.de> Signed-off-by: Philipp Zabel <p.zabel@pengutronix.de>
2018-11-05gpu: ipu-v3: ipu-ic: allow to manually set resize coefficientsPhilipp Zabel
For tiled scaling, we want to compute the scaling coefficients externally in such a way that the interpolation overshoots tile boundaries and samples up to the first pixel of the next tile. Prepare to override the resizing coefficients from the image conversion code. Signed-off-by: Philipp Zabel <p.zabel@pengutronix.de> Acked-by: Steve Longerbeam <slongerbeam@gmail.com> Tested-by: Steve Longerbeam <slongerbeam@gmail.com>
2018-11-05gpu: ipu-v3: Add chroma plane offset overrides to ipu_cpmem_set_image()Steve Longerbeam
Allow the caller of ipu_cpmem_set_image() to override the latters calculation of the chroma plane offsets, by adding override U/V plane offsets to 'struct ipu_image'. Signed-off-by: Steve Longerbeam <slongerbeam@gmail.com> Tested-by: Philipp Zabel <p.zabel@pengutronix.de> Signed-off-by: Philipp Zabel <p.zabel@pengutronix.de>
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