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2017-02-10mtd: fsl-quadspi: Rename SEQID_QUAD_READ to SEQID_READYunhui Cui
There are some read modes for flash, such as NORMAL, FAST, QUAD, DDR QUAD. These modes will use the identical lut table base So rename SEQID_QUAD_READ to SEQID_READ. Signed-off-by: Yunhui Cui <B56489@freescale.com> Signed-off-by: Yunhui Cui <yunhui.cui@nxp.com> Acked-by: Han xu <han.xu@nxp.com> Signed-off-by: Cyrille Pitchen <cyrille.pitchen@atmel.com>
2017-02-10mtd:fsl-quadspi:use the property fields of SPI-NORYunhui Cui
We can get the read/write/erase opcode from the spi nor framework directly. This patch uses the information stored in the SPI-NOR to remove the hardcode in the fsl_qspi_init_lut(). Signed-off-by: Yunhui Cui <B56489@freescale.com> Signed-off-by: Yunhui Cui <yunhui.cui@nxp.com> Acked-by: Han xu <han.xu@nxp.com> Signed-off-by: Cyrille Pitchen <cyrille.pitchen@atmel.com>
2017-02-10mtd: spi-nor: Add support for gd25q16Kamal Dasu
Add GigaDevice GD25Q16 (16M-bit) to supported list. Signed-off-by: Kamal Dasu <kdasu.kdev@gmail.com> Acked-by: Marek Vasut <marek.vasut@gmail.com> Signed-off-by: Cyrille Pitchen <cyrille.pitchen@atmel.com>
2017-02-10mtd: spi-nor: Fix S3AN addressing calculationRicardo Ribalda
The page calculation under spi_nor_s3an_addr_convert() was wrong. On Default Address Mode we need to perform a divide by page_size. Signed-off-by: Ricardo Ribalda Delgado <ricardo.ribalda@gmail.com> Acked-by: Marek Vasut <marek.vasut@gmail.com> Signed-off-by: Cyrille Pitchen <cyrille.pitchen@atmel.com>
2017-02-10mtd: aspeed: fix compile warning in aspeed_smc_read_from_ahb()Cédric Le Goater
The first argument of ioread32_rep() and ioread8_rep is not const. Change aspeed_smc_read_from_ahb() prototype to fix compile warning : drivers/mtd/spi-nor/aspeed-smc.c: In function 'aspeed_smc_read_from_ahb': drivers/mtd/spi-nor/aspeed-smc.c:212:16: warning: passing argument 1 of 'ioread32_rep' discards 'const' qualifier from pointer target type [-Wdiscarded-qualifiers] ioread32_rep(src, buf, len >> 2); Signed-off-by: Cédric Le Goater <clg@kaod.org> Reviewed-by: Marek Vasut <marek.vasut@gmail.com> Signed-off-by: Cyrille Pitchen <cyrille.pitchen@atmel.com>
2017-02-10mtd: spi-nor: add dt support for Everspin MRAMsUwe Kleine-König
The MR25 family doesn't support JEDEC, so they need explicit mentioning in the list of supported spi IDs. This makes it possible to add these using for example: compatible = "everspin,mr25h40"; There was already an entry for mr25h256. Move that one out of the "keep for compatibility" section and put in a new group for Everspin MRAMs. Signed-off-by: Uwe Kleine-König <u.kleine-koenig@pengutronix.de> Acked-by: Rob Herring <robh@kernel.org> Signed-off-by: Cyrille Pitchen <cyrille.pitchen@atmel.com>
2017-02-10Merge tag 'ib-mfd-mtd-v4.11' of ↵Cyrille Pitchen
git://git.kernel.org/pub/scm/linux/kernel/git/lee/mfd From Lee Jones: """ Immutable branch between MFD and MTD due for the v4.11 merge window """
2017-02-10mtd: spi-nor: Add lock/unlock support for f25l32paVictor Shyba
This chip has write protection enabled on power-up, so this flag is necessary to support write operations. Signed-off-by: Victor Shyba <victor1984@riseup.net> Acked-by: Marek Vasut <marek.vasut@gmail.com> Signed-off-by: Cyrille Pitchen <cyrille.pitchen@atmel.com>
2017-02-10mtd: spi-nor: add a stateless method to support memory size above 128MibCyrille Pitchen
This patch provides an alternative mean to support memory above 16MiB (128Mib) by replacing 3byte address op codes by their associated 4byte address versions. Using the dedicated 4byte address op codes doesn't change the internal state of the SPI NOR memory as opposed to using other means such as updating a Base Address Register (BAR) and sending command to enter/leave the 4byte mode. Hence when a CPU reset occurs, early bootloaders don't need to be aware of BAR value or 4byte mode being enabled: they can still access the first 16MiB of the SPI NOR memory using the regular 3byte address op codes. Signed-off-by: Cyrille Pitchen <cyrille.pitchen@atmel.com> Tested-by: Vignesh R <vigneshr@ti.com> Acked-by: Marek Vasut <marek.vasut@gmail.com>
2017-02-10mtd: spi-nor: rename SPINOR_OP_* macros of the 4-byte address op codesCyrille Pitchen
This patch renames the SPINOR_OP_* macros of the 4-byte address instruction set so the new names all share a common pattern: the 4-byte address name is built from the 3-byte address name appending the "_4B" suffix. The patch also introduces new op codes to support other SPI protocols such as SPI 1-4-4 and SPI 1-2-2. This is a transitional patch and will help a later patch of spi-nor.c to automate the translation from the 3-byte address op codes into their 4-byte address version. Signed-off-by: Cyrille Pitchen <cyrille.pitchen@atmel.com> Acked-by: Mark Brown <broonie@kernel.org> Acked-by: Marek Vasut <marek.vasut@gmail.com>
2017-02-10mtd: m25p80: consider max message size in m25p80_readHeiner Kallweit
Consider a message size limit when calculating the maximum amount of data that can be read. The message size limit has been introduced with 4.9, so cc it to stable. Signed-off-by: Heiner Kallweit <hkallweit1@gmail.com> Signed-off-by: Cyrille Pitchen <cyrille.pitchen@atmel.com>
2017-02-10mtd: aspeed: add memory controllers for the Aspeed AST2400 SoCCédric Le Goater
This driver adds mtd support for the Aspeed AST2400 SoC static memory controllers: * New Static Memory Controller (referred as FMC) . BMC firmware . AST2500 compatible register set . 5 chip select pins (CE0 ∼ CE4) . supports NOR flash, NAND flash and SPI flash memory. * SPI Flash Controller (SPI) . host Firmware . slightly different register set, between AST2500 and the legacy controller . supports SPI flash memory . 1 chip select pin (CE0) The legacy static memory controller (referred as SMC) is not supported, as well as types other than SPI. Signed-off-by: Cédric Le Goater <clg@kaod.org> Reviewed-by: Joel Stanley <joel@jms.id.au> Signed-off-by: Cyrille Pitchen <cyrille.pitchen@atmel.com>
2017-02-10mtd: spi-nor: add memory controllers for the Aspeed AST2500 SoCCédric Le Goater
This driver adds mtd support for the Aspeed AST2500 SoC static memory controllers : * Firmware SPI Memory Controller (FMC) . BMC firmware . 3 chip select pins (CE0 ~ CE2) . supports SPI type flash memory (CE0-CE1) . CE2 can be of NOR type flash but this is not supported by the driver * SPI Flash Controller (SPI1 and SPI2) . host firmware . 2 chip select pins (CE0 ~ CE1) . supports SPI type flash memory Each controller has a memory range on which it maps its flash module slaves. Each slave is assigned a memory window for its mapping that can be changed at bootime with the Segment Address Register. Each SPI flash slave can then be accessed in two modes: Command and User. When in User mode, accesses to the memory segment of the slaves are translated in SPI transfers. When in Command mode, the HW generates the SPI commands automatically and the memory segment is accessed as if doing a MMIO. Currently, only the User mode is supported. Command mode needs a little more work to check that the memory window on the AHB bus fits the module size. Based on previous work from Milton D. Miller II <miltonm@us.ibm.com> Signed-off-by: Cédric Le Goater <clg@kaod.org> Reviewed-by: Joel Stanley <joel@jms.id.au> Reviewed-by: Marek Vasut <marek.vasut@gmail.com> Signed-off-by: Cyrille Pitchen <cyrille.pitchen@atmel.com>
2017-02-10mtd: spi-nor: remove WARN_ONCE() message in spi_nor_write()Cyrille Pitchen
This patch removes the WARN_ONCE() test in spi_nor_write(). This macro triggers the display of a warning message almost every time we use a UBI file-system because a write operation is performed at offset 64, which is in the middle of the SPI NOR memory page. This is a valid operation for ubifs. Hence this warning is pretty annoying and useless so we just remove it. Signed-off-by: Cyrille Pitchen <cyrille.pitchen@atmel.com> Suggested-by: Richard Weinberger <richard@nod.at> Suggested-by: Andras Szemzo <szemzo.andras@gmail.com> Acked-by: Boris Brezillon <boris.brezillon@free-electrons.com>
2017-02-10mtd: spi-nor: improve macronix_quad_enable()Cyrille Pitchen
The patch checks whether the Quad Enable bit is already set in the Status Register. If so, the function exits immediately with a successful return code. Signed-off-by: Cyrille Pitchen <cyrille.pitchen@atmel.com> Reviewed-by: Jagan Teki <jagan@openedev.com> Acked-by: Marek Vasut <marek.vasut@gmail.com>
2017-02-10mtd: spi-nor: Add support for S3AN spi-nor devicesRicardo Ribalda
Xilinx Spartan-3AN FPGAs contain an In-System Flash where they keep their configuration data and (optionally) some user data. The protocol of this flash follows most of the spi-nor standard. With the following differences: - Page size might not be a power of two. - The address calculation (default addressing mode). - The spi nor commands used. Protocol is described on Xilinx User Guide UG333 Signed-off-by: Ricardo Ribalda Delgado <ricardo.ribalda@gmail.com> Cc: Boris Brezillon <boris.brezillon@free-electrons.com> Cc: Brian Norris <computersforpeace@gmail.com> Cc: Marek Vasut <marek.vasut@gmail.com> Reviewed-by: Marek Vasut <marek.vasut@gmail.com> Signed-off-by: Cyrille Pitchen <cyrille.pitchen@atmel.com>
2017-02-10iommu/mediatek: Make use of iommu_device_register interfaceJoerg Roedel
Register individual Mediatek IOMMUs to the iommu core and add sysfs entries. Cc: Matthias Brugger <matthias.bgg@gmail.com> Cc: linux-arm-kernel@lists.infradead.org Cc: linux-mediatek@lists.infradead.org Signed-off-by: Joerg Roedel <jroedel@suse.de>
2017-02-10iommu/msm: Make use of iommu_device_register interfaceJoerg Roedel
Register the MSM IOMMUs to the iommu core and add sysfs entries for that driver. Signed-off-by: Joerg Roedel <jroedel@suse.de>
2017-02-10iommu/arm-smmu: Make use of the iommu_register interfaceJoerg Roedel
Also add the smmu devices to sysfs. Signed-off-by: Joerg Roedel <jroedel@suse.de>
2017-02-10iommu: Make iommu_device_link/unlink take a struct iommu_deviceJoerg Roedel
This makes the interface more consistent with iommu_device_sysfs_add/remove. Signed-off-by: Joerg Roedel <jroedel@suse.de>
2017-02-10iommu: Add sysfs bindings for struct iommu_deviceJoerg Roedel
There is currently support for iommu sysfs bindings, but those need to be implemented in the IOMMU drivers. Add a more generic version of this by adding a struct device to struct iommu_device and use that for the sysfs bindings. Also convert the AMD and Intel IOMMU driver to make use of it. Signed-off-by: Joerg Roedel <jroedel@suse.de>
2017-02-10iommu: Introduce new 'struct iommu_device'Joerg Roedel
This struct represents one hardware iommu in the iommu core code. For now it only has the iommu-ops associated with it, but that will be extended soon. The register/unregister interface is also added, as well as making use of it in the Intel and AMD IOMMU drivers. Signed-off-by: Joerg Roedel <jroedel@suse.de>
2017-02-10iommu: Rename struct iommu_deviceJoerg Roedel
The struct is used to link devices to iommu-groups, so 'struct group_device' is a better name. Further this makes the name iommu_device available for a struct representing hardware iommus. Signed-off-by: Joerg Roedel <jroedel@suse.de>
2017-02-10iommu: Rename iommu_get_instance()Joerg Roedel
Rename the function to iommu_ops_from_fwnode(), because that is what the function actually does. The new name is much more descriptive about what the function does. Signed-off-by: Joerg Roedel <jroedel@suse.de>
2017-02-10Merge branch 'i2c-mux/for-next' of https://github.com/peda-r/i2c-mux into ↵Wolfram Sang
i2c/for-4.11
2017-02-10ohci-hub: fix typo in dbg_port macroJelle Martijn Kok
The "dbg_port" macro uses the "outside" parameter (="temp") instead of the parameters (="value") given in the macro. As the macro can look outside its definition this causes no direct problem. Signed-off-by: Jelle Martijn Kok <jmkok@youcom.nl> Acked-by: Alan Stern <stern@rowland.harvard.edu> Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
2017-02-10drm/i915/gvt: fix crash at function release_shadow_wa_ctxChangbin Du
In function dispatch_workload(), if it fail before calling intel_gvt_scan_and_shadow_wa_ctx(), the indirect ctx will not be shadowed so no cleaup need. wa_ctx->indirect_ctx.obj indicate whether indirect_ctx is shadowed. The obj is null if it is unshadowed. BUG: unable to handle kernel NULL pointer dereference at 00000000000001a0 IP: complete_execlist_workload+0x2c9/0x3e0 [i915] Oops: 0002 [#1] SMP task: ffff939546d2d880 task.stack: ffffbd9b82ac4000 RIP: 0010:complete_execlist_workload+0x2c9/0x3e0 [i915] RSP: 0018:ffffbd9b82ac7dd8 EFLAGS: 00010202 RAX: 0000000000000000 RBX: ffff9393c725b540 RCX: 0000000000000006 RDX: 0000000000000007 RSI: 0000000000000202 RDI: ffff939559c8dd00 RBP: ffffbd9b82ac7e18 R08: 0000000000000001 R09: 000000000120dd8f R10: 0000000000000000 R11: 000000000120dd8f R12: ffff9393c725b540 R13: ffff9393c725b618 R14: ffffbd9b81f0d000 R15: ffff939520e0e000 FS: 0000000000000000(0000) GS:ffff939559c80000(0000) knlGS:0000000000000000 CS: 0010 DS: 0000 ES: 0000 CR0: 0000000080050033 CR2: 00000000000001a0 CR3: 000000043d664000 CR4: 00000000003426e0 DR0: 0000000000000000 DR1: 0000000000000000 DR2: 0000000000000000 DR3: 0000000000000000 DR6: 00000000fffe0ff0 DR7: 0000000000000400 Call Trace: workload_thread+0x312/0xd70 [i915] ? __wake_up_sync+0x20/0x20 ? wake_atomic_t_function+0x60/0x60 kthread+0x101/0x140 Signed-off-by: Changbin Du <changbin.du@intel.com> Signed-off-by: Zhenyu Wang <zhenyuw@linux.intel.com>
2017-02-10thermal: use cpumask_var_t for on-stack cpu masksArnd Bergmann
Putting a bare cpumask structure on the stack produces a warning on large SMP configurations: drivers/thermal/cpu_cooling.c: In function 'cpufreq_state2power': drivers/thermal/cpu_cooling.c:644:1: warning: the frame size of 1056 bytes is larger than 1024 bytes [-Wframe-larger-than=] drivers/thermal/cpu_cooling.c: In function '__cpufreq_cooling_register': drivers/thermal/cpu_cooling.c:898:1: warning: the frame size of 1104 bytes is larger than 1024 bytes [-Wframe-larger-than=] The recommended workaround is to use cpumask_var_t, which behaves just like a normal cpu mask in most cases, but turns into a dynamic allocation when CONFIG_CPUMASK_OFFSTACK is set. Signed-off-by: Arnd Bergmann <arnd@arndb.de> Acked-by: Viresh Kumar <viresh.kumar@linaro.org> Signed-off-by: Zhang Rui <rui.zhang@intel.com>
2017-02-10drm/sti: debug fps resetVincent Abriou
Reset the fps debug information when 'fps_show' is updated. Signed-off-by: Fabien Dessenne <fabien.dessenne@st.com>
2017-02-10drm/sti: hdmi: automatically check DVI/HDMI modeVincent Abriou
Remove the hdmi_mode_property and use drm_detect_hdmi_monitor function to check whether the connected monitor is HDMI capable or DVI only. Signed-off-by: Vincent Abriou <vincent.abriou@st.com>
2017-02-10drm/sti: unbind all components while driver cleanupVincent Abriou
Unbind all the components when the STI driver is unregistered. Signed-off-by: Vincent Abriou <vincent.abriou@st.com>
2017-02-10drm/sti: do not post GDP command if no updateVincent Abriou
Do not process update requests with unmodified parameters. This typically happens when the driver is called with legacy (non-atomic) IOCTL : in that case atomic_update() is called multiple times with the same parameters. Signed-off-by: Vincent Abriou <vincent.abriou@st.com>
2017-02-10drm/sti: do not set gdp pixel clock rate if mode is not setVincent Abriou
Fix a division by 0 case : in some cases, when the GDP plane is being disabled atomic_check() is called with "mode->clock = 0". In that case, do not set parent and pixel clock rate. Signed-off-by: Vincent Abriou <vincent.abriou@st.com>
2017-02-10drm/sti: enable gdp pixel clock in atomic_updateVincent Abriou
Set gdp pix clock rate and parent in atomic_check function and enable it in the atomic_update only the first time. Signed-off-by: Vincent Abriou <vincent.abriou@st.com>
2017-02-10drm/sti: remove deprecated legacy vtg slaveVincent Abriou
stih416 chip family is no more supported in Linux v4.9. It is then useless to keep vtg slave field since it not used at all for the stih407/10 chip family supported by sti driver. Signed-off-by: Vincent Abriou <vincent.abriou@st.com>
2017-02-10drm/sti: remove deprecated sink_term configVincent Abriou
stih416 chip family is no more supported in Linux v4.9. Then sink_term config becomes useless. The field of the register it was referring to is tag as reserved for stih410 chip family. Signed-off-by: Vincent Abriou <vincent.abriou@st.com>
2017-02-10drm/sti: do not check hw scaling if mode is not setFabien DESSENNE
Fix a division by 0 case : in some cases, when the HQVDP plane is being disabled atomic_check() is called with "mode->clock = 0". In that case, do not check for scaling capabilities. Signed-off-by: Fabien Dessenne <fabien.dessenne@st.com> Acked-by: Vincent Abriou <vincent.abriou@st.com>
2017-02-10drm/sti: Fix up crtc_state->event handlingFabien DESSENNE
Use drm-core to handle event. This is required to be able to use the nonblocking helpers. Signed-off-by: Fabien Dessenne <fabien.dessenne@st.com> Acked-by: Vincent Abriou <vincent.abriou@st.com>
2017-02-10drm/sti: use atomic_helper for commitFabien DESSENNE
Since nonblocking atomic commits are now supported, the driver can now use drm_atomic_helper_commit(). Signed-off-by: Fabien Dessenne <fabien.dessenne@st.com> Acked-by: Vincent Abriou <vincent.abriou@st.com>
2017-02-10lkdtm: Convert to refcount_t testingKees Cook
Since we'll be using refcount_t instead of atomic_t for refcounting, change the LKDTM tests to reflect the new interface and test conditions. Signed-off-by: Kees Cook <keescook@chromium.org> Signed-off-by: Peter Zijlstra (Intel) <peterz@infradead.org> Cc: Hans Liljestrand <ishkamiel@gmail.com> Cc: Linus Torvalds <torvalds@linux-foundation.org> Cc: Peter Zijlstra <peterz@infradead.org> Cc: Thomas Gleixner <tglx@linutronix.de> Cc: arnd@arndb.de Cc: dhowells@redhat.com Cc: dwindsor@gmail.com Cc: elena.reshetova@intel.com Cc: gregkh@linuxfoundation.org Cc: h.peter.anvin@intel.com Cc: kernel-hardening@lists.openwall.com Cc: will.deacon@arm.com Link: http://lkml.kernel.org/r/1486164412-7338-3-git-send-email-keescook@chromium.org Signed-off-by: Ingo Molnar <mingo@kernel.org>
2017-02-10i2c: mux: pca954x: Add interrupt controller supportPhil Reid
Various muxes can aggregate multiple interrupts from each i2c bus. All of the muxes with interrupt support combine the active low irq lines using an internal 'and' function and generate a combined active low output. The muxes do provide the ability to read a control register to determine which irq is active. By making the mux an irq controller isr latency can potentially be reduced by reading the status register and then only calling the registered isr on that bus segment. As there is no irq masking on the mux irq are disabled until irq_unmask is called at least once. Signed-off-by: Phil Reid <preid@electromag.com.au> Signed-off-by: Peter Rosin <peda@axentia.se>
2017-02-10i2c: mux: pca954x: Add missing pca9542 definition to chip_descPhil Reid
The spec for the pca954x was missing. This chip is the same as the pca9540 except that it has interrupt lines. While the i2c_device_id table mapped the pca9542 to the pca9540 definition the compatible table did not. In preparation for irq support add the pca9542 definition. Signed-off-by: Phil Reid <preid@electromag.com.au> Signed-off-by: Peter Rosin <peda@axentia.se>
2017-02-09Merge remote-tracking branch 'mkp-scsi/4.10/scsi-fixes' into fixesJames Bottomley
2017-02-09net/ena: update driver version to 1.1.2Netanel Belgazal
Signed-off-by: Netanel Belgazal <netanel@annapurnalabs.com> Signed-off-by: David S. Miller <davem@davemloft.net>
2017-02-09net/ena: change condition for host attribute configurationNetanel Belgazal
Move the host info config to be the first admin command that is executed. This change require the driver to remove the 'feature check' from host info configuration flow. The check is removed since the supported features bitmask field is retrieved only after calling ENA_ADMIN_DEVICE_ATTRIBUTES admin command. If set host info is not supported an error will be returned by the device. Signed-off-by: Netanel Belgazal <netanel@annapurnalabs.com> Signed-off-by: David S. Miller <davem@davemloft.net>
2017-02-09net/ena: change driver's default timeoutsNetanel Belgazal
The timeouts were too agressive and sometimes cause false alarms. Signed-off-by: Netanel Belgazal <netanel@annapurnalabs.com> Signed-off-by: David S. Miller <davem@davemloft.net>
2017-02-09net/ena: reduce the severity of ena printoutsNetanel Belgazal
Signed-off-by: Netanel Belgazal <netanel@annapurnalabs.com> Signed-off-by: David S. Miller <davem@davemloft.net>
2017-02-09net/ena: use READ_ONCE to access completion descriptorsNetanel Belgazal
Completion descriptors are accessed from the driver and from the device. To avoid reading the old value, use READ_ONCE macro. Signed-off-by: Netanel Belgazal <netanel@annapurnalabs.com> Signed-off-by: David S. Miller <davem@davemloft.net>
2017-02-09net/ena: use napi_complete_done() return valueNetanel Belgazal
Do not unamsk interrupts if we are in busy poll mode. Signed-off-by: Netanel Belgazal <netanel@annapurnalabs.com> Signed-off-by: David S. Miller <davem@davemloft.net>
2017-02-09net/ena: fix potential access to freed memory during device resetNetanel Belgazal
If the ena driver detects that the device is not behave as expected, it tries to reset the device. The reset flow calls ena_down, which will frees all the resources the driver allocates and then it will reset the device. This flow can cause memory corruption if the device is still writes to the driver's memory space. To overcome this potential race, move the reset before the device resources are freed. Signed-off-by: Netanel Belgazal <netanel@annapurnalabs.com> Signed-off-by: David S. Miller <davem@davemloft.net>
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