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2025-09-09spi: cadence-quadspi: Use BIT() macros where possibleVignesh Raghavendra
Convert few open coded bit shifts to BIT() macro for better readability. No functional changes intended. Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com> Signed-off-by: Santhosh Kumar K <s-k6@ti.com> Message-ID: <20250905185958.3575037-5-s-k6@ti.com> Signed-off-by: Mark Brown <broonie@kernel.org>
2025-09-09spi: cadence-quadspi: Fix cqspi_setup_flash()Santhosh Kumar K
The 'max_cs' stores the largest chip select number. It should only be updated when the current 'cs' is greater than existing 'max_cs'. So, fix the condition accordingly. Also, return failure if there are no flash device declared. Fixes: 0f3841a5e115 ("spi: cadence-qspi: report correct number of chip-select") CC: stable@vger.kernel.org Reviewed-by: Pratyush Yadav <pratyush@kernel.org> Reviewed-by: Théo Lebrun <theo.lebrun@bootlin.com> Signed-off-by: Santhosh Kumar K <s-k6@ti.com> Message-ID: <20250905185958.3575037-4-s-k6@ti.com> Signed-off-by: Mark Brown <broonie@kernel.org>
2025-09-09spi: cadence-quadspi: Flush posted register writes before DAC accessPratyush Yadav
cqspi_read_setup() and cqspi_write_setup() program the address width as the last step in the setup. This is likely to be immediately followed by a DAC region read/write. On TI K3 SoCs the DAC region is on a different endpoint from the register region. This means that the order of the two operations is not guaranteed, and they might be reordered at the interconnect level. It is possible that the DAC read/write goes through before the address width update goes through. In this situation if the previous command used a different address width the OSPI command is sent with the wrong number of address bytes, resulting in an invalid command and undefined behavior. Read back the size register to make sure the write gets flushed before accessing the DAC region. Fixes: 140623410536 ("mtd: spi-nor: Add driver for Cadence Quad SPI Flash Controller") CC: stable@vger.kernel.org Reviewed-by: Pratyush Yadav <pratyush@kernel.org> Signed-off-by: Pratyush Yadav <pratyush@kernel.org> Signed-off-by: Santhosh Kumar K <s-k6@ti.com> Message-ID: <20250905185958.3575037-3-s-k6@ti.com> Signed-off-by: Mark Brown <broonie@kernel.org>
2025-09-09spi: cadence-quadspi: Flush posted register writes before INDAC accessPratyush Yadav
cqspi_indirect_read_execute() and cqspi_indirect_write_execute() first set the enable bit on APB region and then start reading/writing to the AHB region. On TI K3 SoCs these regions lie on different endpoints. This means that the order of the two operations is not guaranteed, and they might be reordered at the interconnect level. It is possible for the AHB write to be executed before the APB write to enable the indirect controller, causing the transaction to be invalid and the write erroring out. Read back the APB region write before accessing the AHB region to make sure the write got flushed and the race condition is eliminated. Fixes: 140623410536 ("mtd: spi-nor: Add driver for Cadence Quad SPI Flash Controller") CC: stable@vger.kernel.org Reviewed-by: Pratyush Yadav <pratyush@kernel.org> Signed-off-by: Pratyush Yadav <pratyush@kernel.org> Signed-off-by: Santhosh Kumar K <s-k6@ti.com> Message-ID: <20250905185958.3575037-2-s-k6@ti.com> Signed-off-by: Mark Brown <broonie@kernel.org>
2025-09-09drm/xe/debugfs: Make residencies definitions constMichal Wajdeczko
No need to keep them non-const. Also fix declaration of .name member, as it points to the const string. This translates to: add/remove: 1/0 grow/shrink: 0/2 up/down: 80/-248 (-168) Function old new delta residencies - 80 +80 dgfx_pcie_link_residencies_show 365 263 -102 dgfx_pkg_residencies_show 454 308 -146 Total: Before=2821548, After=2821380, chg -0.01% Signed-off-by: Michal Wajdeczko <michal.wajdeczko@intel.com> Cc: Soham Purkait <soham.purkait@intel.com> Cc: Jonathan Cavitt <jonathan.cavitt@intel.com> Cc: Karthik Poosa <karthik.poosa@intel.com> Cc: Riana Tauro <riana.tauro@intel.com> Reviewed-by: Lucas De Marchi <lucas.demarchi@intel.com> Link: https://lore.kernel.org/r/20250905180225.8434-1-michal.wajdeczko@intel.com Signed-off-by: Lucas De Marchi <lucas.demarchi@intel.com>
2025-09-09s390/hmcdrv: Replace kmalloc() + copy_from_user() with memdup_user_nul()Thorsten Blum
Replace kmalloc() followed by copy_from_user() with memdup_user_nul() to improve and simplify hmcdrv_dev_write(). Remove the manual NUL-termination. No functional changes intended. Signed-off-by: Thorsten Blum <thorsten.blum@linux.dev> Signed-off-by: Alexander Gordeev <agordeev@linux.ibm.com>
2025-09-09drm/xe/i2c: Enable bus masteringRaag Jadav
Enable bus mastering for I2C controller to support device initiated in-band transactions. Signed-off-by: Raag Jadav <raag.jadav@intel.com> Reviewed-by: Heikki Krogerus <heikki.krogerus@linux.intel.com> Link: https://lore.kernel.org/r/20250908055320.2549722-1-raag.jadav@intel.com Signed-off-by: Lucas De Marchi <lucas.demarchi@intel.com>
2025-09-09PCI/MSI: Remove the conditional parent [un]mask logicThomas Gleixner
Now that msi_lib_init_dev_msi_info() overwrites the irq_[un]mask() callbacks when the MSI_FLAG_PCI_MSI_MASK_PARENT flag is set by the parent domain, the conditional [un]mask logic is obsolete. Remove it. Signed-off-by: Thomas Gleixner <tglx@linutronix.de> Tested-by: Marc Zyngier <maz@kernel.org> Acked-by: Bjorn Helgaas <bhelgaas@google.com> Acked-by: Marc Zyngier <maz@kernel.org> Link: https://lore.kernel.org/all/20250903135433.444329373@linutronix.de
2025-09-09irqchip/msi-lib: Honor the MSI_FLAG_PCI_MSI_MASK_PARENT flagMarc Zyngier
For systems that implement interrupt masking at the interrupt controller level, the MSI library offers MSI_FLAG_PCI_MSI_MASK_PARENT. It indicates that it isn't enough to only unmask the interrupt at the PCI device level, but that the interrupt controller must also be involved. However, the way this is currently done is less than optimal, as the masking/unmasking is done on both sides, always. It would be far cheaper to unmask both at the start of times, and then only deal with the interrupt controller mask, which is cheaper than a round-trip to the PCI endpoint. Now that the PCI/MSI layer implements irq_startup() and irq_shutdown() callbacks, which [un]mask at the PCI level and honor the request to [un]mask the parent, this can be trivially done. Overwrite the irq_mask/unmask() callbacks of the device domain interrupt chip with irq_[un]mask_parent() when the parent domain asks for it. [ tglx: Adopted to the PCI/MSI changes ] Signed-off-by: Marc Zyngier <maz@kernel.org> Signed-off-by: Thomas Gleixner <tglx@linutronix.de> Tested-by: Marc Zyngier <maz@kernel.org> Acked-by: Marc Zyngier <maz@kernel.org> Link: https://lore.kernel.org/all/20250903135433.380783272@linutronix.de
2025-09-09hwmon: sy7636a: add aliasAndreas Kemnade
Add module alias to have it autoloaded. Signed-off-by: Andreas Kemnade <andreas@kemnade.info> Link: https://lore.kernel.org/r/20250909080249.30656-1-andreas@kemnade.info Signed-off-by: Guenter Roeck <linux@roeck-us.net>
2025-09-09hwmon: (sht21) Add devicetree supportKurt Borja
Add DT support for sht2x chips. Signed-off-by: Kurt Borja <kuurtb@gmail.com> Link: https://lore.kernel.org/r/20250908-sht2x-v4-4-bc15f68af7de@gmail.com Signed-off-by: Guenter Roeck <linux@roeck-us.net>
2025-09-09cpufreq: intel_pstate: Adjust frequency percentage computationsRafael J. Wysocki
Adjust frequency percentage computations in update_cpu_qos_request() to avoid going above the exact numerical percentage in the FREQ_QOS_MAX case. Signed-off-by: Rafael J. Wysocki <rafael.j.wysocki@intel.com> Acked-by: Zihuan Zhang <zhangzihuan@kylinos.cn> Link: https://patch.msgid.link/3395556.44csPzL39Z@rafael.j.wysocki [ rjw: Rename "cpu" to "cpudata" and "cpunum" to "cpu" ] Signed-off-by: Rafael J. Wysocki <rafael.j.wysocki@intel.com>
2025-09-09cpufreq: intel_pstate: Rearrange freq QoS updates using __free()Rafael J. Wysocki
Move the code from the for_each_possible_cpu() loop in update_qos_request() to a separate function and use __free() for cpufreq policy reference counting in it to avoid having to call cpufreq_cpu_put() repeatedly (or using goto). While at it, rename update_qos_request() to update_qos_requests() because it updates multiple requests in one go. No intentional functional impact. Link: https://lore.kernel.org/linux-pm/CAJZ5v0gN1T5woSF0tO=TbAh+2-sWzxFjWyDbB7wG2TFCOU01iQ@mail.gmail.com/ Signed-off-by: Rafael J. Wysocki <rafael.j.wysocki@intel.com> Reviewed-by: Zihuan Zhang <zhangzihuan@kylinos.cn> Link: https://patch.msgid.link/3026597.e9J7NaK4W3@rafael.j.wysocki [ rjw: Rename "cpu" to "cpudata" and "cpunum" to "cpu" in new code ] Signed-off-by: Rafael J. Wysocki <rafael.j.wysocki@intel.com>
2025-09-09cpufreq: intel_pstate: Fix object lifecycle issue in update_qos_request()Rafael J. Wysocki
The cpufreq_cpu_put() call in update_qos_request() takes place too early because the latter subsequently calls freq_qos_update_request() that indirectly accesses the policy object in question through the QoS request object passed to it. Fortunately, update_qos_request() is called under intel_pstate_driver_lock, so this issue does not matter for changing the intel_pstate operation mode, but it theoretically can cause a crash to occur on CPU device hot removal (which currently can only happen in virt, but it is formally supported nevertheless). Address this issue by modifying update_qos_request() to drop the reference to the policy later. Fixes: da5c504c7aae ("cpufreq: intel_pstate: Implement QoS supported freq constraints") Cc: 5.4+ <stable@vger.kernel.org> # 5.4+ Signed-off-by: Rafael J. Wysocki <rafael.j.wysocki@intel.com> Reviewed-by: Zihuan Zhang <zhangzihuan@kylinos.cn> Link: https://patch.msgid.link/2255671.irdbgypaU6@rafael.j.wysocki
2025-09-09wifi: iwlwifi: fix 130/1030 configsJohannes Berg
The 130/1030 devices are really derivatives of 6030, with some small differences not pertaining to the MAC, so they must use the 6030 MAC config. Closes: https://bugzilla.kernel.org/show_bug.cgi?id=220472 Closes: https://bugzilla.kernel.org/show_bug.cgi?id=220517 Fixes: 35ac275ebe0c ("wifi: iwlwifi: cfg: finish config split") Cc: stable@vger.kernel.org Signed-off-by: Johannes Berg <johannes.berg@intel.com> Signed-off-by: Miri Korenblit <miriam.rachel.korenblit@intel.com> Link: https://patch.msgid.link/20250909121728.8e4911f12528.I3aa7194012a4b584fbd5ddaa3a77e483280f1de4@changeid Signed-off-by: Miri Korenblit <miriam.rachel.korenblit@intel.com>
2025-09-09media: pwm-ir-tx: Avoid direct access to hrtimer clockbaseThomas Weißschuh
The field timer->base->get_time is a private implementation detail and should not be accessed outside of the hrtimer core. Switch to an equivalent higher-level helper. Signed-off-by: Thomas Weißschuh <thomas.weissschuh@linutronix.de> Signed-off-by: Thomas Gleixner <tglx@linutronix.de> Acked-by: Peter Zijlstra (Intel) <peterz@infradead.org> Acked-by: Sean Young <sean@mess.org> Link: https://lore.kernel.org/all/20250821-hrtimer-cleanup-get_time-v2-6-3ae822e5bfbd@linutronix.de
2025-09-09firmware: arm_scmi: imx: Discover MISC board info from the system managerPeng Fan
The i.MX SCMI MISC protocol can report board information from the System Manager (SM), including a board name and board-specific attributes. Query this during protocol initialization. If the firmware does not implement BOARD_INFO, handle -EOPNOTSUPP gracefully and continue. Reviewed-by: Cristian Marussi <cristian.marussi@arm.com> Signed-off-by: Peng Fan <peng.fan@nxp.com> Message-Id: <20250904-sm-misc-api-v1-v4-4-0bf10eaabdf1@nxp.com> Signed-off-by: Sudeep Holla <sudeep.holla@arm.com>
2025-09-09irqchip/aspeed-scu-ic: Add support for AST2700 SCU interrupt controllersRyan Chen
AST2700 continues the multi-instance SCU interrupt controller model introduced in the AST2600, with four independent interrupt domains (scu-ic0 to 3). Unlike earlier generations which combine interrupt enable and status bits into a single register, AST2700 separates these into distinct IER and ISR registers. Support for this layout is implemented by using register offsets and separate chained IRQ handlers. The variant table is extended to cover AST2700 IC instances, enabling shared initialization logic while preserving support for previous SoCs. [ tglx: Simplified the logic and cleaned up coding style ] Signed-off-by: Ryan Chen <ryan_chen@aspeedtech.com> Signed-off-by: Thomas Gleixner <tglx@linutronix.de> Link: https://lore.kernel.org/all/20250908011812.1033858-5-ryan_chen@aspeedtech.com
2025-09-09irqchip/aspeed-scu-ic: Refactor driver to support variant-based initializationRyan Chen
The SCU IC driver handles each AST2600 instance with separate initialization functions and hardcoded register definitions, which is inflexible and creates duplicated code. Consolidate the implementation by introducing a variant-based structure, selected via compatible string, and use a unified init path and MMIO access via of_iomap(). This simplifies the code and prepares for upcoming SoCs like AST2700, which require split register handling. [ tglx: Cleaned up coding style and massaged change log ] Signed-off-by: Ryan Chen <ryan_chen@aspeedtech.com> Signed-off-by: Thomas Gleixner <tglx@linutronix.de> Link: https://lore.kernel.org/all/20250908011812.1033858-2-ryan_chen@aspeedtech.com
2025-09-09irqchip/gic-v5: Fix error handling in gicv5_its_irq_domain_alloc()Dan Carpenter
Code in gicv5_its_irq_domain_alloc() has two issues: - it checks the wrong return value/variable when calling gicv5_alloc_lpi() - The cleanup code does not take previous loop iterations into account Fix both issues at once by adding the right gicv5_alloc_lpi() variable check and by reworking the function cleanup code to take into account current and previous iterations. [ lpieralisi: Reworded commit message ] Fixes: 57d72196dfc8 ("irqchip/gic-v5: Add GICv5 ITS support") Signed-off-by: Dan Carpenter <dan.carpenter@linaro.org> Signed-off-by: Lorenzo Pieralisi <lpieralisi@kernel.org> Signed-off-by: Thomas Gleixner <tglx@linutronix.de> Reviewed-by: Zenghui Yu <yuzenghui@huawei.com> Link: https://lore.kernel.org/all/20250908082745.113718-4-lpieralisi@kernel.org
2025-09-09irqchip/gic-v5: Fix loop in gicv5_its_create_itt_two_level() cleanup pathDan Carpenter
The "i" variable in gicv5_its_create_itt_two_level() needs to be signed otherwise it can cause a forever loop in the function's cleanup path. [ lpieralisi: Reworded commit message ] Fixes: 57d72196dfc8 ("irqchip/gic-v5: Add GICv5 ITS support") Signed-off-by: Dan Carpenter <dan.carpenter@linaro.org> Signed-off-by: Lorenzo Pieralisi <lpieralisi@kernel.org> Signed-off-by: Thomas Gleixner <tglx@linutronix.de> Reviewed-by: Zenghui Yu <yuzenghui@huawei.com> Link: https://lore.kernel.org/all/20250908082745.113718-3-lpieralisi@kernel.org
2025-09-09irqchip/gic-v5: Delete a stray tabDan Carpenter
Delete a stray tab that is indenting the code erroneously. [ lpieralisi: Reworded commit message] Signed-off-by: Dan Carpenter <dan.carpenter@linaro.org> Signed-off-by: Lorenzo Pieralisi <lpieralisi@kernel.org> Signed-off-by: Thomas Gleixner <tglx@linutronix.de> Reviewed-by: Zenghui Yu <yuzenghui@huawei.com> Link: https://lore.kernel.org/all/20250908082745.113718-2-lpieralisi@kernel.org
2025-09-09gpio: loongson-64bit: Remove unneeded semicolonChen Ni
Remove unnecessary semicolons reported by Coccinelle/coccicheck and the semantic patch at scripts/coccinelle/misc/semicolon.cocci. Signed-off-by: Chen Ni <nichen@iscas.ac.cn> Link: https://lore.kernel.org/r/20250909065913.4011133-1-nichen@iscas.ac.cn Signed-off-by: Bartosz Golaszewski <bartosz.golaszewski@linaro.org>
2025-09-09drm/xe/vf: Move VF CCS debugfs attributeMichal Wajdeczko
The VF CCS handling is per-device so its debugfs file should not be exposed on per-GT basis. Move it up to the device level. Signed-off-by: Michal Wajdeczko <michal.wajdeczko@intel.com> Cc: Satyanarayana K V P <satyanarayana.k.v.p@intel.com> Reviewed-by: Satyanarayana K V P <satyanarayana.k.v.p@intel.com> Link: https://lore.kernel.org/r/20250908123025.747-8-michal.wajdeczko@intel.com
2025-09-09drm/xe/vf: Move VF CCS data to xe_deviceMichal Wajdeczko
We only need single set of VF CCS contexts, they are not per-tile as initial implementation might suggest. Move all VF CCS data from xe_tile.sriov.vf to xe_device.sriov.vf. Also rename some structs to align with the usage and fix their kernel-doc. Signed-off-by: Michal Wajdeczko <michal.wajdeczko@intel.com> Cc: Satyanarayana K V P <satyanarayana.k.v.p@intel.com> Reviewed-by: Satyanarayana K V P <satyanarayana.k.v.p@intel.com> Link: https://lore.kernel.org/r/20250908123025.747-7-michal.wajdeczko@intel.com
2025-09-09drm/xe/bo: Add xe_bo_has_valid_ccs_bb helperMichal Wajdeczko
This will allow as to drop ugly IS_VF_CCS_BB_VALID macro. Signed-off-by: Michal Wajdeczko <michal.wajdeczko@intel.com> Cc: Satyanarayana K V P <satyanarayana.k.v.p@intel.com> Cc: Matthew Brost <matthew.brost@intel.com> Reviewed-by: Matthew Brost <matthew.brost@intel.com> Reviewed-by: Satyanarayana K V P <satyanarayana.k.v.p@intel.com> Link: https://lore.kernel.org/r/20250908123025.747-6-michal.wajdeczko@intel.com
2025-09-09drm/xe/vf: Use single check when calling VF CCS functionsMichal Wajdeczko
All xe_sriov_vf_ccs() functions but init() expect to be called when initialization was successful and CCS handling is ready. Update IS_VF_CCS_READY macro and use it as single entry guard. Signed-off-by: Michal Wajdeczko <michal.wajdeczko@intel.com> Cc: Satyanarayana K V P <satyanarayana.k.v.p@intel.com> Cc: Matthew Brost <matthew.brost@intel.com> Reviewed-by: Satyanarayana K V P <satyanarayana.k.v.p@intel.com> Link: https://lore.kernel.org/r/20250908123025.747-5-michal.wajdeczko@intel.com
2025-09-09drm/xe/vf: Drop IS_VF_CCS_INIT_NEEDED macroMichal Wajdeczko
We only use this macro once and we can open-code it to explicitly show relevant conditions and avoid duplications. Signed-off-by: Michal Wajdeczko <michal.wajdeczko@intel.com> Cc: Satyanarayana K V P <satyanarayana.k.v.p@intel.com> Reviewed-by: Matthew Brost <matthew.brost@intel.com> Reviewed-by: Satyanarayana K V P <satyanarayana.k.v.p@intel.com> Link: https://lore.kernel.org/r/20250908123025.747-4-michal.wajdeczko@intel.com
2025-09-09drm/xe/guc: Use proper flag definitions when registering contextMichal Wajdeczko
In H2G action context type is specified in flags dword in bits 2:1. Use generic FIELD_PREP macro instead of misleading BIT logic. Signed-off-by: Michal Wajdeczko <michal.wajdeczko@intel.com> Cc: Matthew Brost <matthew.brost@intel.com> Reviewed-by: Matthew Brost <matthew.brost@intel.com> Link: https://lore.kernel.org/r/20250908123025.747-3-michal.wajdeczko@intel.com
2025-09-09drm/xe/guc: Rename xe_guc_register_exec_queueMichal Wajdeczko
This function is dedicated for use by the VFs, we shouldn't use name that might suggests it's general purpose. While there, update asserts to better reflect intended usage. Signed-off-by: Michal Wajdeczko <michal.wajdeczko@intel.com> Cc: Satyanarayana K V P <satyanarayana.k.v.p@intel.com> Cc: Matthew Brost <matthew.brost@intel.com> Reviewed-by: Satyanarayana K V P <satyanarayana.k.v.p@intel.com> Link: https://lore.kernel.org/r/20250908123025.747-2-michal.wajdeczko@intel.com
2025-09-09wifi: iwlwifi: mld: CHANNEL_SURVEY_NOTIF is always supportedMiri Korenblit
This notification is supported in FW since API 100. Since we don't support any API older than that, we don't need to check whether the notification is supported. Reviewed-by: Emmanuel Grumbach <emmanuel.grumbach@intel.com> Signed-off-by: Miri Korenblit <miriam.rachel.korenblit@intel.com> Link: https://patch.msgid.link/20250909061931.b43f7da0d63b.I7386aeef5fae70dc4b0901cfb650eeaecb4c1575@changeid
2025-09-09wifi: iwlwifi: mld: remove support of iwl_esr_mode_notif version 1Miri Korenblit
The last FW API that supports version 5 is 99. Since this API is no longer supported on any device that loads iwlmld, we can remove support of it. Reviewed-by: Emmanuel Grumbach <emmanuel.grumbach@intel.com> Signed-off-by: Miri Korenblit <miriam.rachel.korenblit@intel.com> Link: https://patch.msgid.link/20250909061931.e15a7fa15c70.Ibb8636e826136c8c31931e77f5ffa853372b4301@changeid
2025-09-09wifi: iwlwifi: mld: remove support from of sta cmd version 1Miri Korenblit
The last FW API that supports version 1 is 99. Since this API is no longer supported on any device that loads iwlmld, we can remove support of it. Reviewed-by: Emmanuel Grumbach <emmanuel.grumbach@intel.com> Signed-off-by: Miri Korenblit <miriam.rachel.korenblit@intel.com> Link: https://patch.msgid.link/20250909061931.4d6689d5c4b2.I5d2bf7302eea8ac7a805f58e4e60e527d6f5b346@changeid
2025-09-09wifi: iwlwifi: mld: remove support of roc cmd version 5Miri Korenblit
The last FW API that supports version 5 is 97. Since this API is no longer supported on any device that loads iwlmld, we can remove support of it. Reviewed-by: Emmanuel Grumbach <emmanuel.grumbach@intel.com> Signed-off-by: Miri Korenblit <miriam.rachel.korenblit@intel.com> Link: https://patch.msgid.link/20250909061931.e53bd8553360.I6978c216b52b818b879d076a85c5f9edafcf2e99@changeid
2025-09-09wifi: iwlwifi: mld: remove support of mac cmd ver 2Miri Korenblit
The last FW API that supported ver 2 is API 99 (core 96) Since we no longer support it in any device that loads iwlmld, we can remove support of it. Reviewed-by: Emmanuel Grumbach <emmanuel.grumbach@intel.com> Signed-off-by: Miri Korenblit <miriam.rachel.korenblit@intel.com> Link: https://patch.msgid.link/20250909061931.a56bf370d31a.Ie1e93654ce9ee52e6ae3fda9bc898d611456ec41@changeid
2025-09-09wifi: iwlwifi: mld: don't consider phy cmd version 5Miri Korenblit
It was planed that iwlmld will be loaded also for HR and GF, which has versions < 6. But eventually it was decided to keep use iwlmvm for those devices, so iwlmld doesn't need to support those versions. Reviewed-by: Emmanuel Grumbach <emmanuel.grumbach@intel.com> Signed-off-by: Miri Korenblit <miriam.rachel.korenblit@intel.com> Link: https://patch.msgid.link/20250909061931.42501c7b0baa.I207ff53d259cc90781a0082320e2646b35925e5f@changeid
2025-09-09wifi: iwlwifi: implement wowlan status notification API updateRotem Kerem
Add per key status indication in the WOWLAN status notification. This update is required for fips. Each key entry now includes a status field. Keys are now processed as follows: 0: no key, ignore entry 1: old, use only metadata 2: new, use key material and metadata While at it, fix tid_offloaded_tx error message to print the actual variable being validated in iwl_mld_handle_wowlan_info_notif. Signed-off-by: Rotem Kerem <rotem.kerem@intel.com> Signed-off-by: Miri Korenblit <miriam.rachel.korenblit@intel.com> Link: https://patch.msgid.link/20250909061931.0a2e7a62504c.Id195c9c83f9f767d1e3e458468af2d933774daa1@changeid
2025-09-09wifi: iwlwifi: fw: Add ASUS to PPAG and TAS listNidhish A N
Add ASUS to the list of OEMs that are allowed to use the PPAG and TAS feature. Signed-off-by: Nidhish A N <nidhish.a.n@intel.com> Reviewed-by: Pagadala Yesu Anjaneyulu <pagadala.yesu.anjaneyulu@intel.com> Signed-off-by: Miri Korenblit <miriam.rachel.korenblit@intel.com> Link: https://patch.msgid.link/20250909061931.499af6568e89.Iafb2cb1c83ff82712c0e9d5529f76bc226ed12dd@changeid
2025-09-09wifi: iwlwifi: add kunit tests for nvm parsePagadala Yesu Anjaneyulu
nvm flags is part of nvm parse. Add test for VLP AP/CLIENT enable/disable scenarios. Signed-off-by: Pagadala Yesu Anjaneyulu <pagadala.yesu.anjaneyulu@intel.com> Signed-off-by: Miri Korenblit <miriam.rachel.korenblit@intel.com> Link: https://patch.msgid.link/20250909061931.a7a4713fbfee.Ia0caf8865e63b40826c9b66084bd20438554f15c@changeid
2025-09-09wifi: iwlwifi: api: add a flag to iwl_link_ctx_modify_flagsMiri Korenblit
Add a new flag which, when set, will indicate that the UHR parameters in the link command have changed. Reviewed-by: Emmanuel Grumbach <emmanuel.grumbach@intel.com> Signed-off-by: Miri Korenblit <miriam.rachel.korenblit@intel.com> Link: https://patch.msgid.link/20250909061931.b399aebbc384.I8a5a2728e71d92db67d4a4e0f4c358ca7b16ff51@changeid
2025-09-09wifi: iwlwifi: pcie: move ltr_enabled to the specific transportMiri Korenblit
Currently it is under iwl_trans, which is the bus agnostic part of the transport. But really it is relevant for pcie only, so move it to the iwl_trans_pcie and export it via an API to the opmode. Reviewed-by: Emmanuel Grumbach <emmanuel.grumbach@intel.com> Signed-off-by: Miri Korenblit <miriam.rachel.korenblit@intel.com> Link: https://patch.msgid.link/20250909061931.9f9dc80ab06c.I3eeca8b17abeba6ed30f0d681518c81ede0acf30@changeid
2025-09-09wifi: iwlwifi: pcie: move pm_support to the specific transportMiri Korenblit
Currently it is under iwl_trans, which is the bus agnostic part of the transport. But really it is relevant for pcie only, so move it to the iwl_trans_pcie and export it via an API to the opmode. Reviewed-by: Emmanuel Grumbach <emmanuel.grumbach@intel.com> Signed-off-by: Miri Korenblit <miriam.rachel.korenblit@intel.com> Link: https://patch.msgid.link/20250909061931.997193cabd04.Ic6648f040430c94150d0fa11601f50a6a630b862@changeid
2025-09-09wifi: iwlwifi: rename iwl_finish_nic_initMiri Korenblit
The function is called so because for older devices it sets a bit called "init_done". But for the latest devices it sets a different bit, "mac_init". Since this name is not clear anyway, rename it such that it indicates the logic of the newer devices. Also add the 'trans' prefix so iw will be clear from the name that this is a transport API. Reviewed-by: Emmanuel Grumbach <emmanuel.grumbach@intel.com> Signed-off-by: Miri Korenblit <miriam.rachel.korenblit@intel.com> Link: https://patch.msgid.link/20250909061931.a1de688e574b.Ibd41b0c8f7fbae77026e76dbbc085df3eecec538@changeid
2025-09-09wifi: iwlwifi: replace SUPPRESS_CMD_ERROR_ONCE status bit with a booleanRotem Kerem
Convert STATUS_SUPPRESS_CMD_ERROR_ONCE from a status bit to a simple bool field in struct iwl_trans, as atomicity is not needed. Signed-off-by: Rotem Kerem <rotem.kerem@intel.com> Signed-off-by: Miri Korenblit <miriam.rachel.korenblit@intel.com> Link: https://patch.msgid.link/20250909061931.b33366c11a45.I75aac05afd8c4d8ef217d03327c1a027d6e7667e@changeid
2025-09-09wifi: iwlwifi: add STATUS_FW_ERROR APIRotem Kerem
Add iwl_trans_notify_fw_error() and iwl_trans_is_fw_error() for use by op modes. These helpers provide a clean interface for marking and checking firmware error state. This hides the trans internal implementation details from callers. Signed-off-by: Rotem Kerem <rotem.kerem@intel.com> Signed-off-by: Miri Korenblit <miriam.rachel.korenblit@intel.com> Link: https://patch.msgid.link/20250909061931.23f5160b3265.Iba325ffa4c6c6f7fc3a702fb6c1827b0857d0db3@changeid
2025-09-09bonding: support aggregator selection based on port priorityHangbin Liu
Add a new ad_select policy 'port_priority' that uses the per-port actor priority values (set via ad_actor_port_prio) to determine aggregator selection. This allows administrators to influence which ports are preferred for aggregation by assigning different priority values, providing more flexible load balancing control in LACP configurations. Signed-off-by: Hangbin Liu <liuhangbin@gmail.com> Link: https://patch.msgid.link/20250902064501.360822-3-liuhangbin@gmail.com Signed-off-by: Paolo Abeni <pabeni@redhat.com>
2025-09-09bonding: add support for per-port LACP actor priorityHangbin Liu
Introduce a new netlink attribute 'actor_port_prio' to allow setting the LACP actor port priority on a per-slave basis. This extends the existing bonding infrastructure to support more granular control over LACP negotiations. The priority value is embedded in LACPDU packets and will be used by subsequent patches to influence aggregator selection policies. Signed-off-by: Hangbin Liu <liuhangbin@gmail.com> Link: https://patch.msgid.link/20250902064501.360822-2-liuhangbin@gmail.com Signed-off-by: Paolo Abeni <pabeni@redhat.com>
2025-09-09crypto: atmel-aes: make it selectable for ARCH_MICROCHIPRobert Marko
LAN969x uses the Atmel crypto, so make it selectable for ARCH_MICROCHIP to avoid needing to update depends in future if other Microchip SoC-s use it as well. Signed-off-by: Robert Marko <robert.marko@sartura.hr> Acked-by: Herbert Xu <herbert@gondor.apana.org.au> Acked-by: Daniel Machon <daniel.machon@microchip.com> Signed-off-by: Nicolas Ferre <nicolas.ferre@microchip.com>
2025-09-09char: hw_random: atmel: make it selectable for ARCH_MICROCHIPRobert Marko
LAN969x uses the Atmel HWRNG, so make it selectable for ARCH_MICROCHIP to avoid needing to update depends in future if other Microchip SoC-s use it as well. Signed-off-by: Robert Marko <robert.marko@sartura.hr> Acked-by: Daniel Machon <daniel.machon@microchip.com> Signed-off-by: Nicolas Ferre <nicolas.ferre@microchip.com>
2025-09-09i2c: at91: make it selectable for ARCH_MICROCHIPRobert Marko
LAN969x uses the Atmel TWI I2C, so make it selectable for ARCH_MICROCHIP to avoid needing to update depends in future if other Microchip SoC-s use it as well. Signed-off-by: Robert Marko <robert.marko@sartura.hr> Acked-by: Wolfram Sang <wsa+renesas@sang-engineering.com> Acked-by: Daniel Machon <daniel.machon@microchip.com> Signed-off-by: Nicolas Ferre <nicolas.ferre@microchip.com>
generated by cgit (git 2.34.1) at 2025-10-03 19:09:50 +0000