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Renesas RZ/T2H and RZ/N2H SDHI Clock DT Binding Definitions
SDHI clock DT binding definitions for the Renesas RZ/T2H (R9A09G077) and
RZ/N2H (R9A09G087) SoCs, shared by driver and DT source files.
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Add the SDHI high-speed clock (SDHI_CLKHS) definition for the Renesas
RZ/T2H (R9A09G077) and RZ/N2H (R9A09G087) SoCs. SDHI_CLKHS is used as
a core clock for the SDHI IP and operates at 800MHz.
Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
Link: https://lore.kernel.org/20250625141705.151383-2-prabhakar.mahadev-lad.rj@bp.renesas.com
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
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Add XSPI core clock definitions to the clock bindings for the Renesas
R9A09G056 and R9A09G057 SoCs. These clocks IDs are used to support XSPI
interface.
Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
Link: https://lore.kernel.org/20250627204237.214635-2-prabhakar.mahadev-lad.rj@bp.renesas.com
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
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Introduces a reset controller driver for the Kendryte K230 SoC,
resposible for managing the reset functionality of the CPUs and
various sub-modules.
Reviewed-by: Conor Dooley <conor.dooley@microchip.com>
Reviewed-by: Chen Wang <unicorn_wang@outlook.com>
Signed-off-by: Junhui Liu <junhui.liu@pigmoral.tech>
Link: https://lore.kernel.org/r/20250613-k230-reset-v4-1-e5266d2be440@pigmoral.tech
Signed-off-by: Philipp Zabel <p.zabel@pengutronix.de>
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In addition to GPIO synchronization, The AD7768-1 also supports
synchronization over SPI, which use is recommended when the GPIO
cannot provide a pulse synchronous with the base MCLK signal. It
consists of looping back the SYNC_OUT to the SYNC_IN pin and send
a command via SPI to trigger the synchronization.
Introduce the 'trigger-sources' property to enable SPI-based
synchronization via SYNC_OUT pin, along with additional optional
entries for GPIO3 and DRDY pins.
Also create #trigger-source-cells property to differentiate the trigger
sources provided by the ADC. To improve readability, create a
adi,ad7768-1.h header with the macros for the cell values.
While at it, add description to the interrupts property.
Acked-by: Conor Dooley <conor.dooley@microchip.com>
Reviewed-by: David Lechner <dlechner@baylirbe.com>
Signed-off-by: Jonathan Santos <Jonathan.Santos@analog.com>
Link: https://patch.msgid.link/713fd786010c75858700efaec8bb285274e7057e.1749569957.git.Jonathan.Santos@analog.com
Signed-off-by: Jonathan Cameron <Jonathan.Cameron@huawei.com>
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There is a PPU0 reset control bit in the same register as the PPU1
reset control. This missing reset control is for the PCK-600 unit
in the SoC. Manual tests show that the reset control indeed exists,
and if not configured, the system will hang when the PCK-600 registers
are accessed.
Add a reset entry for it at the end of the existing ones.
Fixes: 52dbf84857f0 ("dt-bindings: clk: sunxi-ng: document two Allwinner A523 CCUs")
Acked-by: Conor Dooley <conor.dooley@microchip.com>
Acked-by: Stephen Boyd <sboyd@kernel.org>
Reviewed-by: Andre Przywara <andre.przywara@arm.com>
Link: https://patch.msgid.link/20250619171025.3359384-2-wens@kernel.org
Signed-off-by: Chen-Yu Tsai <wens@csie.org>
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Renesas RZ/N2H DT Binding Definitions
DT bindings and binding definitions for the Renesas RZ/N2H (R9A09G087)
SoC, shared by driver and DT source files.
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Renesas RZ/T2H PCLKL Clock DT Binding Definition
Peripheral Module Clock L (PCLKL) DT binding definition for the Renesas
RZ/T2H (R9A09G077) SoC, shared by driver and DT source files.
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Document support for Module Standby and Software Reset found on the
Renesas RZ/N2H (R9A09G087) SoC. The Module Standby and Software Reset
IP is similar to that found on the RZ/T2H SoC.
Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
Acked-by: Conor Dooley <conor.dooley@microchip.com>
Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
Link: https://lore.kernel.org/20250609203656.333138-4-prabhakar.mahadev-lad.rj@bp.renesas.com
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
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Add the Peripheral Module Clock L (PCLKL) core clock ID for the RZ/T2H
(R9A09G077) SoC. This clock is used by peripherals such as IIC, WDT,
and others.
Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
Link: https://lore.kernel.org/20250617155757.149597-3-prabhakar.mahadev-lad.rj@bp.renesas.com
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
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into clk-for-6.17
Merge the IPQ5424 CMN PLL binding through a topic branch, to allow the
newly introduced clock constants to be made available to the DeviceTree
branch as well.
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The CMN PLL block in the IPQ5424 SoC takes 48 MHZ as the reference
input clock. The output clocks are the same as IPQ9574 SoC, except
for the clock rate of output clocks to PPE and NSS.
Also, add the new header file to export the CMN PLL output clock
specifiers for IPQ5424 SoC.
Acked-by: Rob Herring (Arm) <robh@kernel.org>
Signed-off-by: Luo Jie <quic_luoj@quicinc.com>
Link: https://lore.kernel.org/r/20250610-qcom_ipq5424_cmnpll-v3-1-ceada8165645@quicinc.com
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
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Add the compatible string and power domains for RK3528 SoC.
Signed-off-by: Jonas Karlman <jonas@kwiboo.se>
Acked-by: Conor Dooley <conor.dooley@microchip.com>
Link: https://lore.kernel.org/r/20250518220707.669515-2-jonas@kwiboo.se
Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
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Add device tree bindings for the clock generator found in RP1 multi
function device, and relative entries in MAINTAINERS file.
Signed-off-by: Andrea della Porta <andrea.porta@suse.com>
Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Reviewed-by: Florian Fainelli <florian.fainelli@broadcom.com>
Link: https://lore.kernel.org/r/20250529135052.28398-1-andrea.porta@suse.com
Signed-off-by: Florian Fainelli <florian.fainelli@broadcom.com>
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Add device tree clock binding definitions for CMU_HSI2
Signed-off-by: Raghav Sharma <raghav.s@samsung.com>
Reviewed-by: Alim Akhtar <alim.akhtar@samsung.com>
Acked-by: Rob Herring (Arm) <robh@kernel.org>
Link: https://lore.kernel.org/r/20250529112640.1646740-3-raghav.s@samsung.com
Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
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Add device tree bindings for the camera clock controller on
Qualcomm SC8180X platform.
Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Signed-off-by: Satya Priya Kakitapalli <quic_skakitap@quicinc.com>
Link: https://lore.kernel.org/r/20250512-sc8180x-camcc-support-v4-2-8fb1d3265f52@quicinc.com
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
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The multi-media AHB clocks are needed to create HW dependency in
the multimedia CC dt blocks and avoid any issues. They were not
defined in the initial bindings. Add all the missing clock bindings
for gcc-sc8180x.
Signed-off-by: Satya Priya Kakitapalli <quic_skakitap@quicinc.com>
Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Link: https://lore.kernel.org/r/20250512-sc8180x-camcc-support-v4-1-8fb1d3265f52@quicinc.com
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
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Since the configuration order between the individual MSTOP and CLKON
bits cannot be preserved with the power domain abstraction, drop the
power domain IDs. The corresponding code has also been removed.
Currently, there are no device tree users for these IDs.
Acked-by: "Rob Herring (Arm)" <robh@kernel.org>
Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
Signed-off-by: Claudiu Beznea <claudiu.beznea.uj@bp.renesas.com>
Link: https://lore.kernel.org/20250527112403.1254122-8-claudiu.beznea.uj@bp.renesas.com
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
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Renesas RZ/T2H DT Binding Definitions
DT bindings and binding definitions for the Renesas RZ/T2H (R9A09G077)
SoC, shared by driver and DT source files.
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Add device tree bindings for the clock generator found in RP1 multi
function device, and relative entries in MAINTAINERS file.
Signed-off-by: Andrea della Porta <andrea.porta@suse.com>
Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Reviewed-by: Florian Fainelli <florian.fainelli@broadcom.com>
Link: https://lore.kernel.org/r/20250529135052.28398-1-andrea.porta@suse.com
Signed-off-by: Florian Fainelli <florian.fainelli@broadcom.com>
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Make the PWM mode on the buck controllers configurable from devicetree.
Some boards require forced PWM mode to keep the supply ripple within
acceptable limits under light load conditions.
Signed-off-by: Martijn de Gouw <martijn.de.gouw@prodrive-technologies.com>
Acked-by: Conor Dooley <conor.dooley@microchip.com>
Link: https://patch.msgid.link/20250525071823.819342-1-martijn.de.gouw@prodrive-technologies.com
Signed-off-by: Mark Brown <broonie@kernel.org>
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git://git.kernel.org/pub/scm/linux/kernel/git/gregkh/usb
Pull USB / Thunderbolt updates from Greg KH:
"Here is the big set of USB and Thunderbolt changes for 6.16-rc1.
Included in here are the following:
- USB offload support for audio devices.
I think this takes the record for the most number of patch series
(30+) over the longest period of time (2+ years) to get merged
properly.
Many props go to Wesley Cheng for seeing this effort through, they
took a major out-of-tree hacked-up-monstrosity that was created by
multiple vendors for their specific devices, got it all merged into
a semi-coherent set of changes, and got all of the different major
subsystems to agree on how this should be implemented both with
changes to their code as well as userspace apis, AND wrangled the
hardware companies into agreeing to go forward with this, despite
making them all redo work they had already done in their private
device trees.
This feature offers major power savings on embedded devices where a
USB audio stream can continue to flow while the rest of the system
is sleeping, something that devices running on battery power really
care about. There are still some more small tweaks left to be done
here, and those patches are still out for review and arguing among
the different hardware companies, but this is a major step forward
and a great example of how to do upstream development well.
- small number of thunderbolt fixes and updates, things seem to be
slowing down here (famous last words...)
- xhci refactors and reworking to try to handle some rough corner
cases in some hardware implementations where things don't always
work properly
- typec driver updates
- USB3 power management reworking and updates
- Removal of some old and orphaned UDC gadget drivers that had not
been used in a very long time, dropping over 11 thousand lines from
the tree, always a nice thing, making up for the 12k lines added
for the USB offload feature.
- lots of little updates and fixes in different drivers
All of these have been in linux-next for over 2 weeks, the USB offload
logic has been in there for 8 weeks now, with no reported issues"
* tag 'usb-6.16-rc1' of git://git.kernel.org/pub/scm/linux/kernel/git/gregkh/usb: (172 commits)
ALSA: usb-audio: qcom: fix USB_XHCI dependency
ASoC: qdsp6: fix compile-testing without CONFIG_OF
usb: misc: onboard_usb_dev: fix build warning for CONFIG_USB_ONBOARD_DEV_USB5744=n
usb: typec: tipd: fix typo in TPS_STATUS_HIGH_VOLAGE_WARNING macro
USB: typec: fix const issue in typec_match()
USB: gadget: udc: fix const issue in gadget_match_driver()
USB: gadget: fix up const issue with struct usb_function_instance
USB: serial: pl2303: add new chip PL2303GC-Q20 and PL2303GT-2AB
USB: serial: bus: fix const issue in usb_serial_device_match()
usb: usbtmc: Fix timeout value in get_stb
usb: usbtmc: Fix read_stb function and get_stb ioctl
ALSA: qc_audio_offload: try to reduce address space confusion
ALSA: qc_audio_offload: avoid leaking xfer_buf allocation
ALSA: qc_audio_offload: rename dma/iova/va/cpu/phys variables
ALSA: usb-audio: qcom: Fix an error handling path in qc_usb_audio_probe()
usb: misc: onboard_usb_dev: Fix usb5744 initialization sequence
dt-bindings: usb: ti,usb8041: Add binding for TI USB8044 hub controller
usb: misc: onboard_usb_dev: Add support for TI TUSB8044 hub
usb: gadget: lpc32xx_udc: Use USB API functions rather than constants
usb: gadget: epautoconf: Use USB API functions rather than constants
...
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git://git.kernel.org/pub/scm/linux/kernel/git/gregkh/char-misc
Pull char / misc / iio driver updates from Greg KH:
"Here is the big char/misc/iio and other small driver subsystem pull
request for 6.16-rc1.
Overall, a lot of individual changes, but nothing major, just the
normal constant forward progress of new device support and cleanups to
existing subsystems. Highlights in here are:
- Large IIO driver updates and additions and device tree changes
- Android binder bugfixes and logfile fixes
- mhi driver updates
- comedi driver updates
- counter driver updates and additions
- coresight driver updates and additions
- echo driver removal as there are no in-kernel users of it
- nvmem driver updates
- spmi driver updates
- new amd-sbi driver "subsystem" and drivers added
- rust miscdriver binding documentation fix
- other small driver fixes and updates (uio, w1, acrn, hpet,
xillybus, cardreader drivers, fastrpc and others)
All of these have been in linux-next for quite a while with no
reported problems"
* tag 'char-misc-6.16-rc1' of git://git.kernel.org/pub/scm/linux/kernel/git/gregkh/char-misc: (390 commits)
binder: fix yet another UAF in binder_devices
counter: microchip-tcb-capture: Add watch validation support
dt-bindings: iio: adc: Add ROHM BD79100G
iio: adc: add support for Nuvoton NCT7201
dt-bindings: iio: adc: add NCT7201 ADCs
iio: chemical: Add driver for SEN0322
dt-bindings: trivial-devices: Document SEN0322
iio: adc: ad7768-1: reorganize driver headers
iio: bmp280: zero-init buffer
iio: ssp_sensors: optimalize -> optimize
HID: sensor-hub: Fix typo and improve documentation
iio: admv1013: replace redundant ternary operator with just len
iio: chemical: mhz19b: Fix error code in probe()
iio: adc: at91-sama5d2: use IIO_DECLARE_BUFFER_WITH_TS
iio: accel: sca3300: use IIO_DECLARE_BUFFER_WITH_TS
iio: adc: ad7380: use IIO_DECLARE_DMA_BUFFER_WITH_TS
iio: adc: ad4695: rename AD4695_MAX_VIN_CHANNELS
iio: adc: ad4695: use IIO_DECLARE_DMA_BUFFER_WITH_TS
iio: introduce IIO_DECLARE_BUFFER_WITH_TS macros
iio: make IIO_DMA_MINALIGN minimum of 8 bytes
...
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Pull SoC devicetree updates from Arnd Bergmann:
"There are 11 newly supported SoCs, but these are all either new
variants of existing designs, or straight reuses of the existing chip
in a new package:
- RK3562 is a new chip based on the old Cortex-A53 core, apparently a
low-cost version of the Cortex-A55 based RK3568/RK3566.
- NXP i.MX94 is a minor variation of i.MX93/i.MX95 with a different
set of on-chip peripherals.
- Renesas RZ/V2N (R9A09G056) is a new member of the larger RZ/V2
family
- Amlogic S6/S7/S7D
- Samsung Exynos7870 is an older chip similar to Exynos7885
- WonderMedia wm8950 is a minor variation on the wm8850 chip
- Amlogic s805y is almost idential to s805x
- Allwinner A523 is similar to A527 and T527
- Qualcomm MSM8926 is a variant of MSM8226
- Qualcomm Snapdragon X1P42100 is related to R1E80100
There are also 65 boards, including reference designs for the chips
above, this includes
- 12 new boards based on TI K3 series chips, most of them from
Toradex
- 10 devices using Rockchips RK35xx and PX30 chips
- 2 phones and 2 laptops based on Qualcomm Snapdragon designs
- 10 NXP i.MX8/i.MX9 boards, mostly for embedded/industrial uses
- 3 Samsung Galaxy phones based on Exynos7870
- 5 Allwinner based boards using a variety of ARMv8 chips
- 9 32-bit machines, each based on a different SoC family
Aside from the new hardware, there is the usual set of cleanups and
newly added hardware support on existing machines, for a total of 965
devicetree changesets"
* tag 'soc-dt-6.16' of git://git.kernel.org/pub/scm/linux/kernel/git/soc/soc: (956 commits)
MAINTAINERS, mailmap: update Sven Peter's email address
arm64: dts: renesas: rzg3e-smarc-som: Reduce I2C2 clock frequency
arm64: dts: nuvoton: Add pinctrl
ARM: dts: samsung: sp5v210-aries: Align wifi node name with bindings
arm64: dts: blaize-blzp1600: Enable GPIO support
dt-bindings: clock: socfpga: convert to yaml
arm64: dts: rockchip: move rk3562 pinctrl node outside the soc node
arm64: dts: rockchip: fix rk3562 pcie unit addresses
arm64: dts: rockchip: move rk3528 pinctrl node outside the soc node
arm64: dts: rockchip: remove a double-empty line from rk3576 core dtsi
arm64: dts: rockchip: move rk3576 pinctrl node outside the soc node
arm64: dts: rockchip: fix rk3576 pcie unit addresses
arm64: dts: rockchip: Drop assigned-clock* from cpu nodes on rk3588
arm64: dts: rockchip: Add missing SFC power-domains to rk3576
Revert "arm64: dts: mediatek: mt8390-genio-common: Add firmware-name for scp0"
arm64: dts: mediatek: mt8188: Address binding warnings for MDP3 nodes
arm64: dts: mt6359: Rename RTC node to match binding expectations
arm64: dts: mt8365-evk: Add goodix touchscreen support
arm64: dts: mediatek: mt8188: Add missing #reset-cells property
arm64: dts: airoha: en7581: Add PCIe nodes to EN7581 SoC evaluation board
...
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git://git.kernel.org/pub/scm/linux/kernel/git/soc/soc
Pull SoC driver updates from Arnd Bergmann:
"Updates are across the usual driver subsystems with SoC specific
drivers:
- added soc specicific drivers for sophgo cv1800 and sg2044, qualcomm
sm8750, and amlogic c3 and s4 chips.
- cache controller updates for sifive chips, plus binding changes for
other cache descriptions.
- memory controller drivers for mediatek mt6893, stm32 and cleanups
for a few more drivers
- reset controller drivers for T-Head TH1502, Sophgo sg2044 and
Renesas RZ/V2H(P)
- SCMI firmware updates to better deal with buggy firmware, plus
better support for Qualcomm X1E and NXP i.MX specific interfaces
- a new platform driver for the crypto firmware on Cznic Turris
Omnia/MOX
- cleanups for the TEE firmware subsystem and amdtee driver
- minor updates and fixes for freescale/nxp, qualcomm, google,
aspeed, wondermedia, ti, nxp, renesas, hisilicon, mediatek,
broadcom and samsung SoCs"
* tag 'soc-drivers-6.16' of git://git.kernel.org/pub/scm/linux/kernel/git/soc/soc: (133 commits)
soc: aspeed: Add NULL check in aspeed_lpc_enable_snoop()
soc: aspeed: lpc: Fix impossible judgment condition
ARM: aspeed: Don't select SRAM
docs: firmware: qcom_scm: Fix kernel-doc warning
soc: fsl: qe: Consolidate chained IRQ handler install/remove
firmware: qcom: scm: Allow QSEECOM for HP EliteBook Ultra G1q
dt-bindings: mfd: qcom,tcsr: Add compatible for ipq5018
dt-bindings: cache: add QiLai compatible to ax45mp
memory: stm32_omm: Fix error handling in stm32_omm_disable_child()
dt-bindings: cache: Convert marvell,tauros2-cache to DT schema
dt-bindings: cache: Convert marvell,{feroceon,kirkwood}-cache to DT schema
soc: samsung: exynos-pmu: enable CPU hotplug support for gs101
MAINTAINERS: Add google,gs101-pmu-intr-gen.yaml binding file
dt-bindings: soc: samsung: exynos-pmu: gs101: add google,pmu-intr-gen phandle
dt-bindings: soc: google: Add gs101-pmu-intr-gen binding documentation
bus: fsl-mc: Use strscpy() instead of strscpy_pad()
soc: fsl: qbman: Remove const from portal->cgrs allocation type
bus: fsl_mc: Fix driver_managed_dma check
bus: fsl-mc: increase MC_CMD_COMPLETION_TIMEOUT_MS value
bus: fsl-mc: drop useless cleanup
...
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git://git.kernel.org/pub/scm/linux/kernel/git/iommu/linux
Pull iommu updates from Joerg Roedel:
"Core:
- Introduction of iommu-pages infrastructure to consolitate
page-table allocation code among hardware drivers. This is
ground-work for more generalization in the future
- Remove IOMMU_DEV_FEAT_SVA and IOMMU_DEV_FEAT_IOPF feature flags
- Convert virtio-iommu to domain_alloc_paging()
- KConfig cleanups
- Some small fixes for possible overflows and race conditions
Intel VT-d driver:
- Restore WO permissions on second-level paging entries
- Use ida to manage domain id
- Miscellaneous cleanups
AMD-Vi:
- Make sure notifiers finish running before module unload
- Add support for HTRangeIgnore feature
- Allow matching ACPI HID devices without matching UIDs
ARM-SMMU:
- SMMUv2:
- Recognise the compatible string for SAR2130P MDSS in the
Qualcomm driver, as this device requires an identity domain
- Fix Adreno stall handling so that GPU debugging is more robust
and doesn't e.g. result in deadlock
- SMMUv3:
- Fix ->attach_dev() error reporting for unrecognised domains
- IO-pgtable:
- Allow clients (notably, drivers that process requests from
userspace) to silence warnings when mapping an already-mapped
IOVA
S390:
- Add support for additional table regions
Mediatek:
- Add support for MT6893 MM IOMMU
And some smaller fixes and improvements in various other drivers"
* tag 'iommu-updates-v6.16' of git://git.kernel.org/pub/scm/linux/kernel/git/iommu/linux: (75 commits)
iommu/vt-d: Restore context entry setup order for aliased devices
iommu/mediatek: Fix compatible typo for mediatek,mt6893-iommu-mm
iommu/arm-smmu-qcom: Make set_stall work when the device is on
iommu/arm-smmu: Move handing of RESUME to the context fault handler
iommu/arm-smmu-qcom: Enable threaded IRQ for Adreno SMMUv2/MMU500
iommu/io-pgtable-arm: Add quirk to quiet WARN_ON()
iommu: Clear the freelist after iommu_put_pages_list()
iommu/vt-d: Change dmar_ats_supported() to return boolean
iommu/vt-d: Eliminate pci_physfn() in dmar_find_matched_satc_unit()
iommu/vt-d: Replace spin_lock with mutex to protect domain ida
iommu/vt-d: Use ida to manage domain id
iommu/vt-d: Restore WO permissions on second-level paging entries
iommu/amd: Allow matching ACPI HID devices without matching UIDs
iommu: make inclusion of arm/arm-smmu-v3 directory conditional
iommu: make inclusion of riscv directory conditional
iommu: make inclusion of amd directory conditional
iommu: make inclusion of intel directory conditional
iommu: remove duplicate selection of DMAR_TABLE
iommu/fsl_pamu: remove trailing space after \n
iommu/arm-smmu-qcom: Add SAR2130P MDSS compatible
...
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git://git.kernel.org/pub/scm/linux/kernel/git/clk/linux
Pull clk updates from Stephen Boyd:
"This has been a semi-quiet cycle. The core framework remains unchanged
this time around.
In terms of shiny new code though, we have support for the SpacemiT K1
SoC, Sophgo SG2044, and T-HEAD TH1520 VO clk drivers joining the usual
silicon players like Qualcomm, Samsung, Allwinner, and Renesas.
Surprisingly, the Qualcomm pile was smaller than usual but that is
likely because they put one SoC support inside a driver for a
different SoC that is very similar.
Other than all those new clk drivers there are the usual clk data
updates to fix parents, frequency tables, and add missing clks along
with some Kconfig changes to make compile testing simpler and even
more DT binding conversions to boot.
The exciting part is still the new SoC support like SpacemiT and
Sophgo support though, which really dominate the diffstat because they
introduce a whole new silicon vendor clk driver.
New Drivers:
- Camera clock controller driver for Qualcomm QCS8300
- DE (display engine) 3.3 clocks on Allwinner H616
- Samsung ExynosAutov920 CPU cluster CL0, CL1 and CL2 clock controllers
- Video Output (VO) subsystem clk controller in the T-HEAD TH1520 SoC
- Clock driver for Sophgo SG2044
- Clock driver for SpacemiT K1 SoC
- Renesas RZ/V2N (R9A09G056) SoC clk driver
Updates:
- Correct data in various SoC clk drivers
- Allow clkaN to be optional in the Qualcomm RPMh clock controller
driver if command db doesn't define it
- Change Kconfig options to not enable by default during compile
testing
- Add missing clks in various SoC clk drivers
- Remove some duplicate clk DT bindings and convert some more to
YAML"
* tag 'clk-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/clk/linux: (93 commits)
clk: qcom: gcc-x1e80100: Set FORCE MEM CORE for UFS clocks
clk: qcom: gcc: Set FORCE_MEM_CORE_ON for gcc_ufs_axi_clk for 8650/8750
clk: qcom: rpmh: make clkaN optional
clk: qcom: Add support for Camera Clock Controller on QCS8300
clk: rockchip: rk3528: add slab.h header include
clk: rockchip: rk3576: add missing slab.h include
clk: meson: Do not enable by default during compile testing
clk: meson-g12a: add missing fclk_div2 to spicc
clk: qcom: gcc-msm8939: Fix mclk0 & mclk1 for 24 MHz
clk: rockchip: rename gate-grf clk file
clk: rockchip: rename branch_muxgrf to branch_grf_mux
clk: sunxi-ng: ccu: add Display Engine 3.3 (DE33) support
dt-bindings: allwinner: add H616 DE33 clock binding
clk: samsung: correct clock summary for hsi1 block
dt-bindings: clock: add SM6350 QCOM video clock bindings
clk: rockchip: Pass NULL as reg pointer when registering GRF MMC clocks
clk: sunxi-ng: h616: Add LVDS reset for LCD TCON
dt-bindings: clock: sun50i-h616-ccu: Add LVDS reset
clk: rockchip: rk3036: mark ddrphy as critical
clk: rockchip: rk3036: fix implementation of usb480m clock mux
...
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into clk-next
* clk-amlogic:
clk: meson: Do not enable by default during compile testing
clk: meson-g12a: add missing fclk_div2 to spicc
* clk-allwinner:
clk: sunxi-ng: ccu: add Display Engine 3.3 (DE33) support
dt-bindings: allwinner: add H616 DE33 clock binding
clk: sunxi-ng: h616: Add LVDS reset for LCD TCON
dt-bindings: clock: sun50i-h616-ccu: Add LVDS reset
clk: sunxi: Do not enable by default during compile testing
clk: sunxi-ng: Do not enable by default during compile testing
* clk-rockchip:
clk: rockchip: rk3528: add slab.h header include
clk: rockchip: rk3576: add missing slab.h include
clk: rockchip: rename gate-grf clk file
clk: rockchip: rename branch_muxgrf to branch_grf_mux
clk: rockchip: Pass NULL as reg pointer when registering GRF MMC clocks
clk: rockchip: rk3036: mark ddrphy as critical
clk: rockchip: rk3036: fix implementation of usb480m clock mux
dt-bindings: clock: rk3036: add SCLK_USB480M clock-id
clk: rockchip: rk3528: Add SD/SDIO tuning clocks in GRF region
clk: rockchip: Support MMC clocks in GRF region
dt-bindings: clock: Add GRF clock definition for RK3528
clk: rockchip: add GATE_GRFs for SAI MCLKOUT to rk3576
clk: rockchip: introduce GRF gates
clk: rockchip: introduce auxiliary GRFs
dt-bindings: clock: rk3576: add IOC gated clocks
clk: rockchip: rk3568: Add PLL rate for 33.3MHz
clk: rockchip: Drop empty init callback for rk3588 PLL type
clk: rockchip: rk3588: Add PLL rate for 1500 MHz
* clk-qcom:
clk: qcom: gcc-x1e80100: Set FORCE MEM CORE for UFS clocks
clk: qcom: gcc: Set FORCE_MEM_CORE_ON for gcc_ufs_axi_clk for 8650/8750
clk: qcom: rpmh: make clkaN optional
clk: qcom: Add support for Camera Clock Controller on QCS8300
clk: qcom: gcc-msm8939: Fix mclk0 & mclk1 for 24 MHz
dt-bindings: clock: add SM6350 QCOM video clock bindings
clk: qcom: gpucc-sm6350: Add *_wait_val values for GDSCs
clk: qcom: gcc-sm6350: Add *_wait_val values for GDSCs
clk: qcom: dispcc-sm6350: Add *_wait_val values for GDSCs
clk: qcom: camcc-sm6350: Add *_wait_val values for GDSCs
clk: qcom: Fix missing error check for dev_pm_domain_attach()
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into clk-next
* clk-socfpga:
clk: socfpga: stratix10: Optimize local variables
clk: socfpga: clk-pll: Optimize local variables
* clk-sophgo:
clk: sophgo: Add clock controller support for SG2044 SoC
clk: sophgo: Add PLL clock controller support for SG2044 SoC
dt-bindings: clock: sophgo: add clock controller for SG2044
dt-bindings: soc: sophgo: Add SG2044 top syscon device
clk: sophgo: Add support for newly added precise compatible
dt-bindings: clock: sophgo: Use precise compatible for CV1800 series SoC
* clk-thead:
clk: thead: Add clock support for VO subsystem in T-HEAD TH1520 SoC
dt-bindings: clock: thead: Add TH1520 VO clock controller
* clk-samsung:
clk: samsung: correct clock summary for hsi1 block
clk: samsung: exynosautov920: Fix incorrect CLKS_NR_CPUCL0 definition
clk: samsung: exynosautov920: add cpucl1/2 clock support
dt-bindings: clock: exynosautov920: add cpucl1/2 clock definitions
clk: samsung: exynosautov920: add cpucl0 clock support
dt-bindings: clock: exynosautov920: add cpucl0 clock definitions
clk: samsung: Use samsung CCF common function
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'clk-cleanup' into clk-next
* clk-bindings:
dt-bindings: clock: Drop st,stm32h7-rcc.txt
dt-bindings: clock: convert bcm2835-aux-clock to yaml
dt-bindings: clock: Drop maxim,max77686.txt
dt-bindings: clock: convert vf610-clock.txt to yaml format
* clk-renesas: (26 commits)
clk: renesas: r9a09g047: Add XSPI clock/reset
clk: renesas: r9a09g047: Add support for xspi mux and divider
dt-bindings: clock: renesas,r9a09g047-cpg: Add XSPI and GBETH PTP core clocks
clk: renesas: Use str_on_off() helper
clk: renesas: r9a09g057: Add clock and reset entries for USB2
dt-bindings: clock: renesas,r9a09g057-cpg: Add USB2 PHY and GBETH PTP core clocks
clk: renesas: rzv2h: Use both CLK_ON and CLK_MON bits for clock state validation
clk: renesas: rzv2h: Use str_on_off() helper in rzv2h_mod_clock_endisable()
clk: renesas: rzv2h: Support static dividers without RMW
clk: renesas: rzv2h: Add macro for defining static dividers
clk: renesas: rzv2h: Add support for static mux clocks
clk: renesas: r9a09g047: Add clock and reset entries for GE3D
clk: renesas: rzv2h: Fix a typo
clk: renesas: rzv2h: Add support for RZ/V2N SoC
clk: renesas: rzv2h: Sort compatible list based on SoC part number
dt-bindings: pinctrl: renesas: Document RZ/V2N SoC
dt-bindings: clock: renesas: Document RZ/V2N SoC CPG
dt-bindings: soc: renesas: Document SYS for RZ/V2N SoC
dt-bindings: soc: renesas: Document Renesas RZ/V2N SoC variants and EVK
clk: renesas: rzv2h: Simplify rzv2h_cpg_assert()/rzv2h_cpg_deassert()
...
* clk-spacemit:
clk: spacemit: k1: Add TWSI8 bus and function clocks
clk: spacemit: Add clock support for SpacemiT K1 SoC
dt-bindings: clock: spacemit: Add spacemit,k1-pll
dt-bindings: soc: spacemit: Add spacemit,k1-syscon
* clk-cleanup:
clk: test: Forward-declare struct of_phandle_args in kunit/clk.h
clk: davinci: Use of_get_available_child_by_name()
clk: bcm: rpi: Add NULL check in raspberrypi_clk_register()
clk: bcm: rpi: Drop module alias
clk: bcm: kona: Remove unused scaled_div_build
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git://git.kernel.org/pub/scm/linux/kernel/git/ulfh/linux-pm
Pull pmdomain updates from Ulf Hansson:
"pmdomain core:
- Add residency reflection for domain-idlestates to debugfs
- Add genpd helper to correct the usage/rejected counters
pmdomain providers:
- mediatek: Add support for Dimensity 1200 MT6893
- qcom: Add support for SM4450 power domains
- rockchip: Add support for RK3562 SoC
- sunxi: Add support for Allwinner H6/H616 PRCM PPU
- ti: Fix STANDBY handling of OMAP2+ PER power domain
cpuidle-psci:
- Correct the domain-idlestate statistics in debugfs"
* tag 'pmdomain-v6.16' of git://git.kernel.org/pub/scm/linux/kernel/git/ulfh/linux-pm: (23 commits)
pmdomain: ti: Fix STANDBY handling of PER power domain
pmdomain: amlogic: Constify some structures
pmdomain: core: Use genpd->opp_table to simplify error/remove path
pmdomain: core: Simplify return statement in genpd_power_off()
pmdomain: core: Convert genpd_power_off() to void
pmdomain: core: Convert to device_awake_path()
pmdomain: mediatek: Add error messages for missing regmaps
pmdomain: arm: Do not enable by default during compile testing
pmdomain: qcom: rpmhpd: Add SM4450 power domains
dt-bindings: power: qcom,rpmpd: Add SM4450 compatible
pmdomain: sunxi: add H6 PRCM PPU driver
dt-bindings: power: Add Allwinner H6/H616 PRCM PPU
pmdomain: bcm: bcm2835-power: Use devm_clk_get_optional
pmdomain: rockchip: Add support for RK3562 SoC
dt-bindings: power: rockchip: Add support for RK3562 SoC
pmdomain: mediatek: Add support for Dimensity 1200 MT6893
pmdomain: mediatek: Bump maximum bus protect data array elements
dt-bindings: power: mediatek: Support Dimensity 1200 MT6893 MTCMOS
pmdomain: core: Reset genpd->states to avoid freeing invalid data
pmdomain: core: Add residency reflection for domain-idlestates to debugfs
...
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Document RZ/T2H (a.k.a. r9a09g077) cpg-mssr (Clock Pulse Generator)
binding.
Reviewed-by: "Rob Herring (Arm)" <robh@kernel.org>
Signed-off-by: Thierry Bultel <thierry.bultel.yh@bp.renesas.com>
Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
Link: https://lore.kernel.org/20250515141828.43444-3-thierry.bultel.yh@bp.renesas.com
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
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ssh://gitolite.kernel.org/pub/scm/linux/kernel/git/djakov/icc into char-misc-next
Georgi writes:
interconnect changes for 6.16
This pull request contains the interconnect changes for the 6.16-rc1
merge window. The core and driver changes are listed below.
Core changes:
- Add support for dynamic id allocation, that allows creating
multiple instances of the same provider
Driver changes:
- Add driver for the EPSS L3 instances on SA8775P SoC
- Add QoS support for SM8650 SoC
- Add some missing nodes for SM8650
- Misc dt-binding style and indentation fixes
Signed-off-by: Georgi Djakov <djakov@kernel.org>
* tag 'icc-6.16-rc1' of ssh://gitolite.kernel.org/pub/scm/linux/kernel/git/djakov/icc:
interconnect: qcom: sm8650: remove regmap config for mc_virt & clk_virt
interconnect: qcom: sm8650: add the MASTER_APSS_NOC
dt-bindings: interconnect: sm8650: document the MASTER_APSS_NOC
interconnect: qcom: sm8650: enable QoS configuration
dt-bindings: interconnect: Correct indentation and style in DTS example
interconnect: qcom: sa8775p: Add dynamic icc node id support
interconnect: qcom: icc-rpmh: Add dynamic icc node id support
interconnect: qcom: Add multidev EPSS L3 support
interconnect: core: Add dynamic id allocation support
dt-bindings: interconnect: Add EPSS L3 compatible for SA8775P
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https://git.kernel.org/pub/scm/linux/kernel/git/mmind/linux-rockchip into soc/dt
New SoC the RK3562 (4xA53, Mali-G52) with one evaluation board.
New boards:
- Cobra and PP1516 from Theobroma-Systems (build around the PX30)
- Radxa Rock 5B+ (rk3588)
- Rockchip RK3399 industrial eval board
New peripherals:
- GMAC + SDMMC/SDIO on rk3528
- SAI + HDMI-audio on rk3576
Interesting general updates:
- move rk3528 i2c + uart aliases as requested
- rk3568 PCIe3 MSI to use GIC ITS
- update deprecated dwmac reset properties on some px30 boards
- updates for cypress usb hubs on some Theobroma boards
Binding taken with Greg's blessing
https://lore.kernel.org/all/2025051550-polish-prude-ed56@gregkh/
* tag 'v6.16-rockchip-dts64-2' of https://git.kernel.org/pub/scm/linux/kernel/git/mmind/linux-rockchip: (35 commits)
arm64: dts: rockchip: Improve LED config for NanoPi R5S
arm64: dts: rockchip: add px30-pp1516 base dtsi and board variants
dt-bindings: arm: rockchip: add PX30-PP1516 boards from Theobroma Systems
arm64: dts: rockchip: add px30-cobra base dtsi and board variants
dt-bindings: arm: rockchip: add PX30-Cobra boards from Theobroma Systems
arm64: dts: rockchip: move reset to dedicated eth-phy node on ringneck
arm64: dts: rockchip: add basic mdio node to px30
arm64: dts: rockchip: disable unrouted USB controllers and PHY on RK3399 Puma with Haikou
arm64: dts: rockchip: disable unrouted USB controllers and PHY on RK3399 Puma
arm64: dts: rockchip: fix internal USB hub instability on RK3399 Puma
dt-bindings: usb: cypress,hx3: Add support for all variants
arm64: dts: rockchip: move rk3528 i2c+uart aliases to board files
arm64: dts: rockchip: drop wrong spdif clock from edp1 on rk3588
arm64: dts: rockchip: Add RK3562 evb2 devicetree
arm64: dts: rockchip: add core dtsi for RK3562 SoC
dt-bindings: arm: rockchip: Add rk3562 evb2 board
dt-bindings: soc: rockchip: Add rk3562 syscon compatibles
dt-bindings: rockchip: pmu: Add rk3562 compatible
arm64: dts: rockchip: Enable Ethernet controller on Radxa E20C
arm64: dts: rockchip: Add GMAC nodes for RK3528
...
Link: https://lore.kernel.org/r/3998939.iIbC2pHGDl@phil
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
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https://git.kernel.org/pub/scm/linux/kernel/git/atorgue/stm32 into soc/dt
STM32 DT for v6.16, round 1
Highlights:
----------
- MCU:
- Add low power timer on STM32F746
- Add STM32H747 High end MCU support. It embeds:
- dual-core (Cortex-M7 + Cortex-M4)
- up to 2 Mbytes flash
- 1 Mbyte of internal RAM
- Add STM32H747i-disco board support. Detailed information can be
found at:
https://www.st.com/en/evaluation-tools/stm32h747i-disco.html
- MPU:
- STM32MP13:
- Add VREFINT calibration support based on ADC.
- STMP32MP15:
- Add new Ultratronik Fly board support:
- based on STM32MP157C SoC
- 1GB of DDR3
- Several connections are available on this boards:
2*USB2.0, 1*USB2.0 MiniUSB, Debug UART, 1*UART, 1*USART,
SDcard, RJ45, ...
- STM32MP25:
- Add OCTOSPI support on STM32MP25 SoCs
- Add SPI NOR flash support on STM32MP257F-EV1 connected to OSPI1
- Add Low power timer TIMER (LPTIM) on STM32MP25 SoCs and use
LPTIM3 as low power broadcast timer on STM32MP257F-EV1.
* tag 'stm32-dt-for-v6.16-1' of https://git.kernel.org/pub/scm/linux/kernel/git/atorgue/stm32: (22 commits)
ARM: dts: stm32: add initial support for stm32mp157-ultra-fly-sbc board
MAINTAINERS: Add entry for ULTRATRONIK BOARD SUPPORT
dt-bindings: arm: stm32: Document Ultratronik's Fly board DT binding
dt-bindings: vendor-prefixes: Add Ultratronik
arm64: dts: st: use lptimer3 as tick broadcast source on stm32mp257f-ev1
arm64: dts: st: add low-power timer nodes on stm32mp251
arm64: defconfig: enable STM32 LP timer clockevent driver
arm64: dts: st: Add SPI NOR flash support on stm32mp257f-ev1 board
arm64: dts: st: Add ospi port1 pinctrl entries in stm32mp25-pinctrl.dtsi
arm64: dts: st: Add OMM node on stm32mp251
ARM: dts: stm32: support STM32h747i-disco board
ARM: dts: stm32: add an extra pin map for USART1 on stm32h743
ARM: dts: stm32: add pin map for UART8 controller on stm32h743
ARM: dts: stm32: add uart8 node for stm32h743 MCU
dt-bindings: clock: stm32h7: rename USART{7,8}_CK to UART{7,8}_CK
ARM: stm32: add a new SoC - STM32H747
dt-bindings: arm: stm32: add compatible for stm32h747i-disco board
ARM: dts: stm32h7-pinctrl: add _a suffix to u[s]art_pins phandles
ARM: dts: st: stm32: Align wifi node name with bindings
ARM: dts: stm32: add low power timer on STM32F746
...
Link: https://lore.kernel.org/r/2f101efb-6d58-48d8-983a-57e30a34827c@foss.st.com
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
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into soc/dt
RISC-V SpacemiT DT changes for 6.16
- Add clock driver, fix for pinctrl/uart
- Add gpio support, enable LED heartbeat
* tag 'spacemit-dt-for-6.16-1' of https://github.com/spacemit-com/linux:
riscv: dts: spacemit: add gpio LED for system heartbeat
riscv: dts: spacemit: add gpio support for K1 SoC
riscv: dts: spacemit: Acquire clocks for UART
riscv: dts: spacemit: Acquire clocks for pinctrl
riscv: dts: spacemit: Add clock tree for SpacemiT K1
dt-bindings: clock: spacemit: Add spacemit,k1-pll
dt-bindings: soc: spacemit: Add spacemit,k1-syscon
Link: https://lore.kernel.org/r/20250514044841-GYA524674@gentoo
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
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https://git.kernel.org/pub/scm/linux/kernel/git/qcom/linux into soc/drivers
Qualcomm driver updates for v6.16
Allow list QSEECOM for EFI variable services on on the Asus Zenbook A14,
and block list TZMEM on the SM7150 platform to avoid issues with rmtfs.
Extend the last-level cache (llcc) driver to support version 6 of the
hardware and enable SM8750 support.
Also add socinfo for the SM8750 platform.
Re-enable UCSI support on SC8280XP, now that the reported crash has been
dealt with, and filter the altmode notifications to avoid spurious
hotplug events being propagated to user space.
Add SM7150 support to pd-mapper.
* tag 'qcom-drivers-for-6.16' of https://git.kernel.org/pub/scm/linux/kernel/git/qcom/linux:
soc: qcom: llcc-qcom: Add support for SM8750
soc: qcom: llcc-qcom: Add support for LLCC V6
dt-bindings: cache: qcom,llcc: Document SM8750 LLCC block
soc: qcom: socinfo: add SM8750 SoC ID
dt-bindings: arm: qcom,ids: add SoC ID for SM8750
dt-bindings: soc: qcom: qcom,rpm: add missing clock/-names properties
dt-bindings: soc: qcom,rpm: add missing clock-controller node
soc: qcom: smem: Update max processor count
firmware: qcom: tzmem: disable sm7150 platform
soc: qcom: pd-mapper: Add support for SM7150
soc: qcom: pmic_glink_altmode: fix spurious DP hotplug events
soc: qcom: smp2p: Fix fallback to qcom,ipc parse
soc: qcom: pmic_glink: enable UCSI on sc8280xp
firmware: qcom: scm: Allow QSEECOM on Asus Zenbook A14
dt-bindings: soc: qcom,rpmh-rsc: Limit power-domains requirement
Link: https://lore.kernel.org/r/20250513215656.44448-1-andersson@kernel.org
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
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As stated in the reference manual RM0433, the STM32H743 MCU has
USART1/2/3/6, UART4/5/7/8, and LPUART1. The patches make all the clock
macros for the serial ports consistent with the documentation.
Signed-off-by: Dario Binacchi <dario.binacchi@amarulasolutions.com>
Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Link: https://lore.kernel.org/r/20250427074404.3278732-5-dario.binacchi@amarulasolutions.com
Signed-off-by: Alexandre Torgue <alexandre.torgue@foss.st.com>
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Add the unique ID for Qualcomm SM8750 SoC.
This value is used to differentiate the SoC across qcom targets.
Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Signed-off-by: Mukesh Ojha <mukesh.ojha@oss.qualcomm.com>
Reviewed-by: Melody Olvera <melody.olvera@oss.qualcomm.com>
Link: https://lore.kernel.org/r/20250508134635.1627031-2-mukesh.ojha@oss.qualcomm.com
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
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Add device tree bindings for video clock controller for SM6350 SoCs.
Signed-off-by: Konrad Dybcio <konradybcio@kernel.org>
Co-developed-by: Luca Weiss <luca.weiss@fairphone.com>
Signed-off-by: Luca Weiss <luca.weiss@fairphone.com>
Acked-by: Rob Herring (Arm) <robh@kernel.org>
Link: https://lore.kernel.org/r/20250324-sm6350-videocc-v2-2-cc22386433f4@fairphone.com
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
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Add the required LVDS reset binding for the LCD TCON.
Signed-off-by: Chris Morgan <macromorgan@hotmail.com>
Signed-off-by: Ryan Walklin <ryan@testtoast.com>
Reviewed-by: Andre Przywara <andre.przywara@arm.com>
Link: https://patch.msgid.link/20250507201943.330111-2-macroalpha82@gmail.com
Signed-off-by: Chen-Yu Tsai <wens@csie.org>
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Contrary to how it is implemented right now, the usb480m clock is a
controllable mux that can switch between the 24MHz oscillator and the
clock output of the usb2phy.
Add the needed clock-id to allow setting this mux from DT.
Acked-by: Conor Dooley <conor.dooley@microchip.com>
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
Link: https://lore.kernel.org/r/20250503202532.992033-2-heiko@sntech.de
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Renesas RZ/G3E XSPI and GBETH Core DT Binding Definitions
XSPI and Gigabit Ethernet PTP reference core clock DT binding
definitions for the Renesas RZ/G3E (R9A09G047) SoC, shared by driver and
DT source files.
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Add definitions for XSPI core clock and Gigabit Ethernet PTP reference
core clocks in the R9A09G047 CPG DT bindings header file.
The clk_spi is modelled as a fixed divider clock with parent clk_spix2 and
factor two as both parent and child share same gating bit.
Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com>
Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
Link: https://lore.kernel.org/20250424081400.135028-2-biju.das.jz@bp.renesas.com
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
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These clocks are for SD/SDIO tuning purpose and come with registers
in GRF syscon.
Signed-off-by: Yao Zi <ziyao@disroot.org>
Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Link: https://lore.kernel.org/r/20250506092206.46143-2-ziyao@disroot.org
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
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Add device tree bindings for the TH1520 Video Output (VO) subsystem
clock controller. The VO sub-system manages clock gates for multimedia
components including HDMI, MIPI, and GPU.
Document the VIDEO_PLL requirements for the VO clock controller, which
receives its input from the AP clock controller. The VIDEO_PLL is a
Silicon Creations Sigma-Delta (integer) PLL typically running at 792 MHz
with maximum FOUTVCO of 2376 MHz.
This binding complements the existing AP sub-system clock controller
which manages CPU, DPU, GMAC and TEE PLLs.
Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Acked-by: Conor Dooley <conor.dooley@microchip.com>
Signed-off-by: Michal Wilczynski <m.wilczynski@samsung.com>
Reviewed-by: Drew Fustini <drew@pdp7.com>
Signed-off-by: Drew Fustini <drew@pdp7.com>
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The clock controller on the SG2044 provides common clock function
for all IPs on the SoC. This device requires PLL clock to function
normally.
Add definition for the clock controller of the SG2044 SoC.
Reviewed-by: Chen Wang <unicorn_wang@outlook.com>
Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Link: https://lore.kernel.org/r/20250418020325.421257-4-inochiama@gmail.com
Signed-off-by: Inochi Amaoto <inochiama@gmail.com>
Signed-off-by: Chen Wang <unicorn_wang@outlook.com>
Signed-off-by: Chen Wang <wangchen20@iscas.ac.cn>
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The SG2044 top syscon device provide PLL clock control and some other
misc feature of the SoC.
Add the compatible string for SG2044 top syscon device.
Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Link: https://lore.kernel.org/r/20250418020325.421257-2-inochiama@gmail.com
Signed-off-by: Inochi Amaoto <inochiama@gmail.com>
Signed-off-by: Chen Wang <unicorn_wang@outlook.com>
Signed-off-by: Chen Wang <wangchen20@iscas.ac.cn>
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Certain clocks on the RK3576 are additionally essentially "gated" behind
some bit toggles in the IOC GRF range. Downstream ungates these by
adding a separate clock driver that maps over the GRF range and leaks
their implementation of this into the DT.
Instead, define some new clock IDs for these, so that consumers of these
types of clocks can properly articulate which clock they're using, so
that we can then add them to the clock driver for SoCs that need them.
Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Signed-off-by: Nicolas Frattaroli <nicolas.frattaroli@collabora.com>
Link: https://lore.kernel.org/r/20250502-rk3576-sai-v3-1-376cef19dd7c@collabora.com
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
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Add cpucl1 and cpucl2 clock definitions.
CPUCL1/2 refer to CPU Cluster 1 and CPU Cluster 2,
which provide clock support for the CPUs on Exynosauto V920 SoC.
Signed-off-by: Shin Son <shin.son@samsung.com>
Link: https://lore.kernel.org/r/20250428113517.426987-2-shin.son@samsung.com
Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
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