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2021-04-07ACPICA: Add parsing for IVRS IVHD 40h and device entry F0hAlexander Monakov
ACPICA commit eefb865355514048380d921de5efcf30027d6b02 IVHD type 40h uses the same field layout as type 11h, but adds support for a new device entry type F0h (ACPI HID device entry). The new device entry type has variable length: after fixed-length fields occupying 22 bytes, there's a field of length up to 255 (as given by the preceding field). Link: https://github.com/acpica/acpica/commit/eefb8653 Signed-off-by: Alexander Monakov <amonakov@ispras.ru> Signed-off-by: Bob Moore <robert.moore@intel.com> Signed-off-by: Erik Kaneda <erik.kaneda@intel.com> Signed-off-by: Rafael J. Wysocki <rafael.j.wysocki@intel.com>
2021-04-07KVM: arm64: Add support for the KVM PTP serviceJianyong Wu
Implement the hypervisor side of the KVM PTP interface. The service offers wall time and cycle count from host to guest. The caller must specify whether they want the host's view of either the virtual or physical counter. Signed-off-by: Jianyong Wu <jianyong.wu@arm.com> Signed-off-by: Marc Zyngier <maz@kernel.org> Link: https://lore.kernel.org/r/20201209060932.212364-7-jianyong.wu@arm.com
2021-04-07clocksource: Add clocksource id for arm arch counterJianyong Wu
Add clocksource id to the ARM generic counter so that it can be easily identified from callers such as ptp_kvm. Cc: Mark Rutland <mark.rutland@arm.com> Reviewed-by: Andre Przywara <andre.przywara@arm.com> Signed-off-by: Jianyong Wu <jianyong.wu@arm.com> Signed-off-by: Marc Zyngier <maz@kernel.org> Link: https://lore.kernel.org/r/20201209060932.212364-6-jianyong.wu@arm.com
2021-04-07time: Add mechanism to recognize clocksource in time_get_snapshotThomas Gleixner
System time snapshots are not conveying information about the current clocksource which was used, but callers like the PTP KVM guest implementation have the requirement to evaluate the clocksource type to select the appropriate mechanism. Introduce a clocksource id field in struct clocksource which is by default set to CSID_GENERIC (0). Clocksource implementations can set that field to a value which allows to identify the clocksource. Store the clocksource id of the current clocksource in the system_time_snapshot so callers can evaluate which clocksource was used to take the snapshot and act accordingly. Signed-off-by: Thomas Gleixner <tglx@linutronix.de> Signed-off-by: Jianyong Wu <jianyong.wu@arm.com> Signed-off-by: Marc Zyngier <maz@kernel.org> Link: https://lore.kernel.org/r/20201209060932.212364-5-jianyong.wu@arm.com
2021-04-07ptp: Reorganize ptp_kvm.c to make it arch-independentJianyong Wu
Currently, the ptp_kvm module contains a lot of x86-specific code. Let's move this code into a new arch-specific file in the same directory, and rename the arch-independent file to ptp_kvm_common.c. Acked-by: Richard Cochran <richardcochran@gmail.com> Reviewed-by: Andre Przywara <andre.przywara@arm.com> Signed-off-by: Jianyong Wu <jianyong.wu@arm.com> Signed-off-by: Marc Zyngier <maz@kernel.org> Link: https://lore.kernel.org/r/20201209060932.212364-4-jianyong.wu@arm.com
2021-04-07Merge tag 'ti-k3-dt-for-v5.13' of ↵Arnd Bergmann
git://git.kernel.org/pub/scm/linux/kernel/git/nmenon/linux into arm/dt Devicetree changes for TI K3 platforms for v5.13 merge window: * New SoCs: - AM642 mean for industrial control, motor control, remote IO, IoT gateway etc. * New Boards: - AM65: Siemens SIMATIC IOT2050 advanced and basic boards - AM64: EVM and SK boards * New peripherals: - AM65: watchdog - AM65,J721E: ICSSG - J7200: OSPI, GPIO * Fixes: - AM65: pcie node fixup, ospi speed updates - J721e, J7200: MMC speed updates, ospi speed updates and compatibles fixups. * tag 'ti-k3-dt-for-v5.13' of git://git.kernel.org/pub/scm/linux/kernel/git/nmenon/linux: (39 commits) arm64: dts: ti: k3-am64-main: Fix ospi compatible arm64: dts: ti: k3-j7200-mcu: Fix ospi compatible arm64: dts: ti: k3-j721e-mcu: Fix ospi compatible arm64: dts: ti: k3-j7200: Add support for higher speed modes and update delay select values for MMCSD subsystems arm64: dts: ti: k3-j7200-common-proc-board: Disable unused gpio modules arm64: dts: ti: k3-j7200: Add gpio nodes arm64: dts: ti: k3-am642-evm/sk: Add IPC sub-mailbox nodes arm64: dts: ti: k3-am64-main: Add mailbox cluster nodes arm64: dts: ti: k3-am64-main: Add hwspinlock node arm64: dts: ti: k3-am642: reserve gpio in mcu domain for firmware usage arm64: dts: ti: k3-am64: Add GPIO DT nodes arm64: dts: ti: k3-am64-evm/sk: Add OSPI flash DT node arm64: dts: ti: k3-am64-main: Add OSPI node arm64: dts: ti: k3-am64-main: Add ADC nodes arm64: dts: ti: k3-am642-evm: Add USB support arm64: dts: ti: k3-am64-main: Add DT node for USB subsystem arm64: dts: ti: Add support for Siemens IOT2050 boards dt-bindings: arm: ti: Add bindings for Siemens IOT2050 boards dt-bindings: Add Siemens vendor prefix arm64: dts: ti: k3-am642-evm: Add support for SPI EEPROM ... Link: https://lore.kernel.org/r/20210405155336.smohb7uzkperqwuz@reflex Signed-off-by: Arnd Bergmann <arnd@arndb.de>
2021-04-07Merge tag 'phy-for-5.13' of ↵Greg Kroah-Hartman
git://git.kernel.org/pub/scm/linux/kernel/git/phy/linux-phy into char-misc-next Vinod writes: phy-for-5.13 - Updates: - Yaml conversion for mvebu-utmi binding, bcm-ns-usb2 and bcm-ns-usb3 bindings - Mediatek dsi and hdmi phy updates - TI j721e-wiz updates for AM64 - Cadence-torrent phy updates for SGMII/QSGMII - New support: - usb3-dp phy for Qualcomm SM8250 - UTMI phy for Armada CP110 - USB phy for Qualcomm SC7280 - Binding and driver for Sparx5 ethernet serdes * tag 'phy-for-5.13' of git://git.kernel.org/pub/scm/linux/kernel/git/phy/linux-phy: (75 commits) phy: fix resource_size.cocci warnings phy: Sparx5 Eth SerDes: Use direct register operations phy: hisilicon: Use the correct HiSilicon copyright phy: marvell: phy-mvebu-cp11i-utmi needs USB_COMMON phy: qcom-qmp: add support for sm8250-usb3-dp phy phy: qcom-qmp: rename common registers phy: qcom-qmp: move DP functions to callbacks dt-bindings: phy: qcom,qmp-usb3-dp: Add support for SM8250 dt-bindings: phy: qcom,qmp-usb3-dp-phy: move usb3 compatibles back to qcom,qmp-phy.yaml phy: ti: j721e-wiz: Configure 'p_standard_mode' only for DP/QSGMII dt-bindings: phy: fix dt_binding_check warning in mediatek, ufs-phy.yaml phy: zynqmp: Handle the clock enable/disable properly dt-bindings: phy: bcm-ns-usb3-phy: convert to yaml dt-bindings: phy: bcm-ns-usb2-phy: convert to yaml phy: microchip: PHY_SPARX5_SERDES should depend on ARCH_SPARX5 phy: cadence-torrent: Add delay for PIPE clock to be stable phy: cadence-torrent: Explicitly request exclusive reset control phy: cadence-torrent: Do not configure SERDES if it's already configured phy: cadence-torrent: Group reset APIs and clock APIs phy: ti: j721e-wiz: Do not configure wiz if its already configured ...
2021-04-07Merge tag 'soundwire-5.13-rc1' of ↵Greg Kroah-Hartman
git://git.kernel.org/pub/scm/linux/kernel/git/vkoul/soundwire into char-misc-next Vinod writes: soundwire updates for 5.13-rc1 Updates for v5.13-rc1 are: Core: - Ability to add quirks for masters - static checker cleanup for bus code Drivers: - DMI quirks for Intel controllers - static checker cleanup for drivers - add auto enumeration support qcom controller * tag 'soundwire-5.13-rc1' of git://git.kernel.org/pub/scm/linux/kernel/git/vkoul/soundwire: (45 commits) soundwire: intel_init: test link->cdns soundwire: qcom: handle return correctly in qcom_swrm_transport_params soundwire: qcom: cleanup internal port config indexing soundwire: qcom: wait for fifo space to be available before read/write soundwire: qcom: add static port map support soundwire: qcom: update port map allocation bit mask soundwire: add static port mapping support soundwire: stream: fix memory leak in stream config error path soundwire: qcom: use signed variable for error return soundwire: qcom: wait for enumeration to be complete in probe soundwire: qcom: add auto enumeration support soundwire: export sdw_compare_devid, sdw_extract_slave_id and sdw_slave_add soundwire: qcom: add support to new interrupts soundwire: qcom: update register read/write routine soundwire: qcom: start the clock during initialization soundwire: qcom: set continue execution flag for ignored commands soundwire: qcom: add support to missing transport params dt-bindings: soundwire: qcom: clarify data port bus parameters soundwire: cadence: only prepare attached devices on clock stop soundwire: generic_allocation: fix confusion between group and packing ...
2021-04-07irqdomain: Get rid of irq_create_identity_mapping()Marc Zyngier
The sole user of irq_create_identity_mapping() having been converted, get rid of the unused helper. Signed-off-by: Marc Zyngier <maz@kernel.org>
2021-04-07HID: input: map battery capacity (00850065)John Chen
This is the capacity in percentage, relative to design capacity. Specifically, it is present in Apple Magic Mouse 2. In contrast, usage 00850064 is also the capacity in percentage, but is relative to full capacity. It is not mapped here because I don't have such device. Signed-off-by: John Chen <johnchen902@gmail.com> Signed-off-by: Jiri Kosina <jkosina@suse.cz>
2021-04-07iommu/vt-d: Invalidate PASID cache when root/context entry changedLu Baolu
When the Intel IOMMU is operating in the scalable mode, some information from the root and context table may be used to tag entries in the PASID cache. Software should invalidate the PASID-cache when changing root or context table entries. Suggested-by: Ashok Raj <ashok.raj@intel.com> Fixes: 7373a8cc38197 ("iommu/vt-d: Setup context and enable RID2PASID support") Signed-off-by: Lu Baolu <baolu.lu@linux.intel.com> Link: https://lore.kernel.org/r/20210320025415.641201-4-baolu.lu@linux.intel.com Signed-off-by: Joerg Roedel <jroedel@suse.de>
2021-04-07iommu/amd: Move a few prototypes to include/linux/amd-iommu.hChristoph Hellwig
A few functions that were intentended for the perf events support are currently declared in arch/x86/events/amd/iommu.h, which mens they are not in scope for the actual function definition. Also amdkfd has started using a few of them using externs in a .c file. End that misery by moving the prototypes to the proper header. Signed-off-by: Christoph Hellwig <hch@lst.de> Link: https://lore.kernel.org/r/20210402143312.372386-5-hch@lst.de Signed-off-by: Joerg Roedel <jroedel@suse.de>
2021-04-07iommu/amd: Remove the unused device errata codeChristoph Hellwig
The device errata mechism is entirely unused, so remove it. Signed-off-by: Christoph Hellwig <hch@lst.de> Link: https://lore.kernel.org/r/20210402143312.372386-2-hch@lst.de Signed-off-by: Joerg Roedel <jroedel@suse.de>
2021-04-07iommu: remove iommu_domain_{get,set}_attrChristoph Hellwig
Remove the now unused iommu attr infrastructure. Signed-off-by: Christoph Hellwig <hch@lst.de> Acked-by: Will Deacon <will@kernel.org> Link: https://lore.kernel.org/r/20210401155256.298656-21-hch@lst.de Signed-off-by: Joerg Roedel <jroedel@suse.de>
2021-04-07iommu: remove DOMAIN_ATTR_IO_PGTABLE_CFGChristoph Hellwig
Use an explicit set_pgtable_quirks method instead that just passes the actual quirk bitmask instead. Signed-off-by: Christoph Hellwig <hch@lst.de> Acked-by: Will Deacon <will@kernel.org> Acked-by: Li Yang <leoyang.li@nxp.com> Link: https://lore.kernel.org/r/20210401155256.298656-20-hch@lst.de Signed-off-by: Joerg Roedel <jroedel@suse.de>
2021-04-07iommu: remove DOMAIN_ATTR_DMA_USE_FLUSH_QUEUERobin Murphy
Instead make the global iommu_dma_strict paramete in iommu.c canonical by exporting helpers to get and set it and use those directly in the drivers. This make sure that the iommu.strict parameter also works for the AMD and Intel IOMMU drivers on x86. As those default to lazy flushing a new IOMMU_CMD_LINE_STRICT is used to turn the value into a tristate to represent the default if not overriden by an explicit parameter. [ported on top of the other iommu_attr changes and added a few small missing bits] Signed-off-by: Robin Murphy <robin.murphy@arm.com>. Signed-off-by: Christoph Hellwig <hch@lst.de> Link: https://lore.kernel.org/r/20210401155256.298656-19-hch@lst.de Signed-off-by: Joerg Roedel <jroedel@suse.de>
2021-04-07iommu: remove DOMAIN_ATTR_NESTINGChristoph Hellwig
Use an explicit enable_nesting method instead. Signed-off-by: Christoph Hellwig <hch@lst.de> Acked-by: Will Deacon <will@kernel.org> Acked-by: Li Yang <leoyang.li@nxp.com> Link: https://lore.kernel.org/r/20210401155256.298656-17-hch@lst.de Signed-off-by: Joerg Roedel <jroedel@suse.de>
2021-04-07iommu: remove DOMAIN_ATTR_GEOMETRYChristoph Hellwig
The geometry information can be trivially queried from the iommu_domain struture. Signed-off-by: Christoph Hellwig <hch@lst.de> Acked-by: Will Deacon <will@kernel.org> Acked-by: Li Yang <leoyang.li@nxp.com> Link: https://lore.kernel.org/r/20210401155256.298656-16-hch@lst.de Signed-off-by: Joerg Roedel <jroedel@suse.de>
2021-04-07iommu: remove DOMAIN_ATTR_PAGINGChristoph Hellwig
DOMAIN_ATTR_PAGING is never used. Signed-off-by: Christoph Hellwig <hch@lst.de> Acked-by: Will Deacon <will@kernel.org> Acked-by: Li Yang <leoyang.li@nxp.com> Link: https://lore.kernel.org/r/20210401155256.298656-15-hch@lst.de Signed-off-by: Joerg Roedel <jroedel@suse.de>
2021-04-07iommu/fsl_pamu: enable the liodn when attaching a deviceChristoph Hellwig
Instead of a separate call to enable all devices from the list, just enable the liodn once the device is attached to the iommu domain. This also remove the DOMAIN_ATTR_FSL_PAMU_ENABLE iommu_attr. Signed-off-by: Christoph Hellwig <hch@lst.de> Acked-by: Will Deacon <will@kernel.org> Acked-by: Li Yang <leoyang.li@nxp.com> Link: https://lore.kernel.org/r/20210401155256.298656-11-hch@lst.de Signed-off-by: Joerg Roedel <jroedel@suse.de>
2021-04-07iommu/fsl_pamu: replace DOMAIN_ATTR_FSL_PAMU_STASH with a direct callChristoph Hellwig
Add a fsl_pamu_configure_l1_stash API that qman_portal can call directly instead of indirecting through the iommu attr API. Signed-off-by: Christoph Hellwig <hch@lst.de> Acked-by: Will Deacon <will@kernel.org> Acked-by: Li Yang <leoyang.li@nxp.com> Link: https://lore.kernel.org/r/20210401155256.298656-8-hch@lst.de Signed-off-by: Joerg Roedel <jroedel@suse.de>
2021-04-07iommu/fsl_pamu: remove ->domain_window_enableChristoph Hellwig
The only thing that fsl_pamu_window_enable does for the current caller is to fill in the prot value in the only dma_window structure, and to propagate a few values from the iommu_domain_geometry struture into the dma_window. Remove the dma_window entirely, hardcode the prot value and otherwise use the iommu_domain_geometry structure instead. Remove the now unused ->domain_window_enable iommu method. Signed-off-by: Christoph Hellwig <hch@lst.de> Acked-by: Li Yang <leoyang.li@nxp.com> Link: https://lore.kernel.org/r/20210401155256.298656-7-hch@lst.de Signed-off-by: Joerg Roedel <jroedel@suse.de>
2021-04-07iommu/fsl_pamu: remove support for multiple windowsChristoph Hellwig
The only domains allocated forces use of a single window. Remove all the code related to multiple window support, as well as the need for qman_portal to force a single window. Remove the now unused DOMAIN_ATTR_WINDOWS iommu_attr. Signed-off-by: Christoph Hellwig <hch@lst.de> Acked-by: Will Deacon <will@kernel.org> Acked-by: Li Yang <leoyang.li@nxp.com> Link: https://lore.kernel.org/r/20210401155256.298656-6-hch@lst.de Signed-off-by: Joerg Roedel <jroedel@suse.de>
2021-04-07iommu/fsl_pamu: remove fsl_pamu_get_domain_attrChristoph Hellwig
None of the values returned by this function are ever queried. Also remove the DOMAIN_ATTR_FSL_PAMUV1 enum value that is not otherwise used. Signed-off-by: Christoph Hellwig <hch@lst.de> Acked-by: Will Deacon <will@kernel.org> Acked-by: Li Yang <leoyang.li@nxp.com> Link: https://lore.kernel.org/r/20210401155256.298656-3-hch@lst.de Signed-off-by: Joerg Roedel <jroedel@suse.de>
2021-04-07iommu: remove the unused domain_window_disable methodChristoph Hellwig
domain_window_disable is wired up by fsl_pamu, but never actually called. Signed-off-by: Christoph Hellwig <hch@lst.de> Acked-by: Will Deacon <will@kernel.org> Acked-by: Li Yang <leoyang.li@nxp.com> Link: https://lore.kernel.org/r/20210401155256.298656-2-hch@lst.de Signed-off-by: Joerg Roedel <jroedel@suse.de>
2021-04-07iommu: Add a page fault handlerJean-Philippe Brucker
Some systems allow devices to handle I/O Page Faults in the core mm. For example systems implementing the PCIe PRI extension or Arm SMMU stall model. Infrastructure for reporting these recoverable page faults was added to the IOMMU core by commit 0c830e6b3282 ("iommu: Introduce device fault report API"). Add a page fault handler for host SVA. IOMMU driver can now instantiate several fault workqueues and link them to IOPF-capable devices. Drivers can choose between a single global workqueue, one per IOMMU device, one per low-level fault queue, one per domain, etc. When it receives a fault event, most commonly in an IRQ handler, the IOMMU driver reports the fault using iommu_report_device_fault(), which calls the registered handler. The page fault handler then calls the mm fault handler, and reports either success or failure with iommu_page_response(). After the handler succeeds, the hardware retries the access. The iopf_param pointer could be embedded into iommu_fault_param. But putting iopf_param into the iommu_param structure allows us not to care about ordering between calls to iopf_queue_add_device() and iommu_register_device_fault_handler(). Tested-by: Lu Baolu <baolu.lu@linux.intel.com> Reviewed-by: Eric Auger <eric.auger@redhat.com> Reviewed-by: Jacob Pan <jacob.jun.pan@linux.intel.com> Reviewed-by: Jonathan Cameron <Jonathan.Cameron@huawei.com> Reviewed-by: Lu Baolu <baolu.lu@linux.intel.com> Signed-off-by: Jean-Philippe Brucker <jean-philippe@linaro.org> Link: https://lore.kernel.org/r/20210401154718.307519-7-jean-philippe@linaro.org Signed-off-by: Joerg Roedel <jroedel@suse.de>
2021-04-07iommu: Separate IOMMU_DEV_FEAT_IOPF from IOMMU_DEV_FEAT_SVAJean-Philippe Brucker
Some devices manage I/O Page Faults (IOPF) themselves instead of relying on PCIe PRI or Arm SMMU stall. Allow their drivers to enable SVA without mandating IOMMU-managed IOPF. The other device drivers now need to first enable IOMMU_DEV_FEAT_IOPF before enabling IOMMU_DEV_FEAT_SVA. Enabling IOMMU_DEV_FEAT_IOPF on its own doesn't have any effect visible to the device driver, it is used in combination with other features. Reviewed-by: Eric Auger <eric.auger@redhat.com> Reviewed-by: Lu Baolu <baolu.lu@linux.intel.com> Signed-off-by: Jean-Philippe Brucker <jean-philippe@linaro.org> Link: https://lore.kernel.org/r/20210401154718.307519-4-jean-philippe@linaro.org Signed-off-by: Joerg Roedel <jroedel@suse.de>
2021-04-07iommu/arm-smmu-v3: Use device properties for pasid-num-bitsJean-Philippe Brucker
The pasid-num-bits property shouldn't need a dedicated fwspec field, it's a job for device properties. Add properties for IORT, and access the number of PASID bits using device_property_read_u32(). Suggested-by: Robin Murphy <robin.murphy@arm.com> Acked-by: Jonathan Cameron <Jonathan.Cameron@huawei.com> Acked-by: Will Deacon <will@kernel.org> Reviewed-by: Eric Auger <eric.auger@redhat.com> Signed-off-by: Jean-Philippe Brucker <jean-philippe@linaro.org> Acked-by: Hanjun Guo <guohanjun@huawei.com> Link: https://lore.kernel.org/r/20210401154718.307519-3-jean-philippe@linaro.org Signed-off-by: Joerg Roedel <jroedel@suse.de>
2021-04-07iommu: Fix comment for struct iommu_fwspecJean-Philippe Brucker
Commit 986d5ecc5699 ("iommu: Move fwspec->iommu_priv to struct dev_iommu") removed iommu_priv from fwspec and commit 5702ee24182f ("ACPI/IORT: Check ATS capability in root complex nodes") added @flags. Update the struct doc. Acked-by: Jonathan Cameron <Jonathan.Cameron@huawei.com> Acked-by: Will Deacon <will@kernel.org> Signed-off-by: Jean-Philippe Brucker <jean-philippe@linaro.org> Link: https://lore.kernel.org/r/20210401154718.307519-2-jean-philippe@linaro.org Signed-off-by: Joerg Roedel <jroedel@suse.de>
2021-04-07iommu: Delete iommu_dma_free_cpu_cached_iovas()John Garry
Function iommu_dma_free_cpu_cached_iovas() no longer has any caller, so delete it. With that, function free_cpu_cached_iovas() may be made static. Signed-off-by: John Garry <john.garry@huawei.com> Reviewed-by: Robin Murphy <robin.murphy@arm.com> Link: https://lore.kernel.org/r/1616675401-151997-4-git-send-email-john.garry@huawei.com Signed-off-by: Joerg Roedel <jroedel@suse.de>
2021-04-07iommu/vt-d: Remove IOVA domain rcache flushing for CPU offliningJohn Garry
Now that the core code handles flushing per-IOVA domain CPU rcaches, remove the handling here. Reviewed-by: Lu Baolu <baolu.lu@linux.intel.com> Signed-off-by: John Garry <john.garry@huawei.com> Link: https://lore.kernel.org/r/1616675401-151997-3-git-send-email-john.garry@huawei.com Signed-off-by: Joerg Roedel <jroedel@suse.de>
2021-04-07iova: Add CPU hotplug handler to flush rcachesJohn Garry
Like the Intel IOMMU driver already does, flush the per-IOVA domain CPU rcache when a CPU goes offline - there's no point in keeping it. Reviewed-by: Robin Murphy <robin.murphy@arm.com> Signed-off-by: John Garry <john.garry@huawei.com> Link: https://lore.kernel.org/r/1616675401-151997-2-git-send-email-john.garry@huawei.com Signed-off-by: Joerg Roedel <jroedel@suse.de>
2021-04-07iommu: Fix a boundary issue to avoid performance dropXiang Chen
After the change of patch ("iommu: Switch gather->end to the inclusive end"), the performace drops from 1600+K IOPS to 1200K in our kunpeng ARM64 platform. We find that the range [start1, end1) actually is joint from the range [end1, end2), but it is considered as disjoint after the change, so it needs more times of TLB sync, and spends more time on it. So fix the boundary issue to avoid performance drop. Fixes: 862c3715de8f ("iommu: Switch gather->end to the inclusive end") Signed-off-by: Xiang Chen <chenxiang66@hisilicon.com> Acked-by: Will Deacon <will@kernel.org> Link: https://lore.kernel.org/r/1616643504-120688-1-git-send-email-chenxiang66@hisilicon.com Signed-off-by: Joerg Roedel <jroedel@suse.de>
2021-04-07iommu/vt-d: Remove SVM_FLAG_PRIVATE_PASIDLu Baolu
The SVM_FLAG_PRIVATE_PASID has never been referenced in the tree, and there's no plan to have anything to use it. So cleanup it. Signed-off-by: Lu Baolu <baolu.lu@linux.intel.com> Reviewed-by: Christoph Hellwig <hch@lst.de> Link: https://lore.kernel.org/r/20210323010600.678627-4-baolu.lu@linux.intel.com Signed-off-by: Joerg Roedel <jroedel@suse.de>
2021-04-07iommu/vt-d: Remove svm_dev_opsLu Baolu
The svm_dev_ops has never been referenced in the tree, and there's no plan to have anything to use it. Remove it to make the code neat. Signed-off-by: Lu Baolu <baolu.lu@linux.intel.com> Reviewed-by: Christoph Hellwig <hch@lst.de> Link: https://lore.kernel.org/r/20210323010600.678627-3-baolu.lu@linux.intel.com Signed-off-by: Joerg Roedel <jroedel@suse.de>
2021-04-07iommu/vt-d: Remove unused dma map/unmap trace eventsLu Baolu
With commit c588072bba6b5 ("iommu/vt-d: Convert intel iommu driver to the iommu ops"), the trace events for dma map/unmap have no users any more. Cleanup them to make the code neat. Signed-off-by: Lu Baolu <baolu.lu@linux.intel.com> Reviewed-by: Christoph Hellwig <hch@lst.de> Link: https://lore.kernel.org/r/20210323010600.678627-2-baolu.lu@linux.intel.com Signed-off-by: Joerg Roedel <jroedel@suse.de>
2021-04-07Merge tag 'iio-for-5.13b-take2' of ↵Greg Kroah-Hartman
https://git.kernel.org/pub/scm/linux/kernel/git/jic23/iio into staging-next Jonathan writes: 2nd set of IIO features, cleanups etc for 5.13 Trying again as a wrong fixes tag managed to beat the checking script I was running. A few of these are fixes for major rework earlier in cycle. Bulk of patches are the ad7150 pre graduation cleanup, some link fixes in maintainers and set using the new IRQF_NO_AUTOEN flag. Note includes a merge of a tag from tip to get the IRQF_NO_AUTOEN support (one patch only from Barry Song) Staging graduation * adi,ad7150 CDC - A lot of precursor patches cleaning it up first. - Includes core support for timeout event ABI where after a time a adaptive threshold jumps to fix slow tracking problems. Cleanups and minor / late breaking fixes * core - Use sysfs_emit() and sysfs_emit_at() as appropriate - Fix a bug introduced in this cycle for iio_read_channel_processed_scale() - Fix handling of getfd ioctl as IIO_IOCTL_UNHANDLED is a valid ioctl number - Tidy up some pointless type conversion in string formatting and odd indentation. * dac - Use sysfs_emit() for powerdown attribute show() functions. * docs - Fix dead links due to txt to yaml binding conversions. * treewide - Use IRQF_NO_AUTOEN * various - Typo fixes in comments. * triggers/hr-timer-trigger - Fix an overflow handing issue. * ad,ad7923 - Device managed functions in probe() * ad,ad9467 - Fix kconfig dependency issue * adi,adis16201 - Fix a wrong axis assignment that stops the driver loading. * invensense,mpu6050 - Allow use as a standalone trigger (no channels enabled) - Drop unnecessary manual assignment of indio_dev->modes - Make device function in a basic way if no interrupt wired. - Sanity check scale writes. * semtech,sx9310 - Fix access to a variable length array in DT binding. - Sanity check input before writing debounce register. * st,stm32-dfsdm - Drop __func__ from dev_dbg() and pr_debug(). * yamaha,yas530 - Include asm/unaligned.h instead of be_byteshift.h - Fix an issue with return value on an error path. * tag 'iio-for-5.13b-take2' of https://git.kernel.org/pub/scm/linux/kernel/git/jic23/iio: (76 commits) iio: inv_mpu6050: Fully validate gyro and accel scale writes iio: sx9310: Fix write_.._debounce() iio: sx9310: Fix access to variable DT array iio: adc: Kconfig: make AD9467 depend on ADI_AXI_ADC symbol iio: magnetometer: yas530: Include right header iio: magnetometer: yas530: Fix return value on error path iio:cdc:ad7150: Fix use of uninitialized ret iio: hrtimer-trigger: Fix potential integer overflow in iio_hrtimer_store_sampling_frequency iio:adc: Fix trivial typo iio:adc:ad7476: Fix remove handling iio:adc:ad_sigma_delta: Use IRQF_NO_AUTOEN rather than request and disable iio:imu:adis: Use IRQF_NO_AUTOEN instead of irq request then disable iio:chemical:scd30: Use IRQF_NO_AUTOEN to avoid irq request then disable iio:adc:sun4i-gpadc: Use new IRQF_NO_AUTOEN flag instead of request then disable iio:adc:nau7802: Use IRQF_NO_AUTOEN instead of request then disable iio:adc:exynos-adc: Use new IRQF_NO_AUTOEN flag rather than separate irq_disable() iio:adc:ad7766: Use new IRQF_NO_AUTOEN to reduce boilerplate iio: buffer: use sysfs_attr_init() on allocated attrs iio: trigger: Fix strange (ladder-type) indentation iio: trigger: Replace explicit casting and wrong specifier with proper one ...
2021-04-07mtd: rawnand: Add support for secure regions in NAND memoryManivannan Sadhasivam
On a typical end product, a vendor may choose to secure some regions in the NAND memory which are supposed to stay intact between FW upgrades. The access to those regions will be blocked by a secure element like Trustzone. So the normal world software like Linux kernel should not touch these regions (including reading). The regions are declared using a NAND chip DT property, "secure-regions". So let's make use of this property in the raw NAND core and skip access to the secure regions present in a system. Signed-off-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org> Signed-off-by: Miquel Raynal <miquel.raynal@bootlin.com> Link: https://lore.kernel.org/linux-mtd/20210402150128.29128-4-manivannan.sadhasivam@linaro.org
2021-04-07Merge tag 'irq-no-autoen-2021-03-25' into togregJonathan Cameron
Tag for the input subsystem to pick up Picked up for IIO to allow similar changes.
2021-04-07dt-bindings:iio:dac: update microchip,mcp4725.yaml referenceMauro Carvalho Chehab
Changeset 6ced946a4bba ("dt-bindings:iio:dac:microchip,mcp4725 yaml conversion") renamed: Documentation/devicetree/bindings/iio/dac/mcp4725.txt to: Documentation/devicetree/bindings/iio/dac/microchip,mcp4725.yaml. Update its cross-reference accordingly. Fixes: 6ced946a4bba ("dt-bindings:iio:dac:microchip,mcp4725 yaml conversion") Signed-off-by: Mauro Carvalho Chehab <mchehab+huawei@kernel.org> Link: https://lore.kernel.org/r/82fb54974e8a22be15e64343260a6de39a18edda.1617279356.git.mchehab+huawei@kernel.org Signed-off-by: Jonathan Cameron <Jonathan.Cameron@huawei.com>
2021-04-07iio:event: Add timeout event info typeJonathan Cameron
For adaptive threshold events, the current value is compared with a (typically) low pass filtered version of the same signal that slowly tracks large scale changes. However, sometimes a step change can result in a large lag before the low pass filtered version begins to track the signal again. Timeouts can be used to made an instantaneous 'correction'. Documentation of this attribute is added in a later patch. Signed-off-by: Jonathan Cameron <Jonathan.Cameron@huawei.com> Reviewed-by: Alexandru Ardelean <alexandru.ardelean@analog.com> Link: https://lore.kernel.org/r/20210314181511.531414-11-jic23@kernel.org
2021-04-07Merge tag 'drm-misc-next-2021-04-01' of ↵Dave Airlie
git://anongit.freedesktop.org/drm/drm-misc into drm-next drm-misc-next for 5.13: UAPI Changes: Cross-subsystem Changes: Core Changes: - mst: Improve topology logging - edid: Rework and improvements for displayid Driver Changes: - anx7625: Regulators support - bridge: Support for the Chipone ICN6211, Lontium LT8912B - lt9611: Fix 4k panels handling Signed-off-by: Dave Airlie <airlied@redhat.com> From: Maxime Ripard <maxime@cerno.tech> Link: https://patchwork.freedesktop.org/patch/msgid/20210401110552.2b3yetlgsjtlotcn@gilmour
2021-04-07bus: mhi: Improve documentation on channel transfer setup APIsBhaumik Bhatt
The mhi_prepare_for_transfer() and mhi_unprepare_from_transfer() APIs could use better explanation. Add details on what MHI does when these APIs are used. Signed-off-by: Bhaumik Bhatt <bbhatt@codeaurora.org> Reviewed-by: Hemant Kumar <hemantk@codeaurora.org> Reviewed-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org> Link: https://lore.kernel.org/r/1617311778-1254-10-git-send-email-bbhatt@codeaurora.org Signed-off-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
2021-04-07bus: mhi: core: Remove pre_init flag used for power purposesBhaumik Bhatt
Some controllers can choose to skip preparation for power up. In that case, device context is initialized based on the pre_init flag not being set during mhi_prepare_for_power_up(). There is no reason MHI host driver should maintain and provide controllers with two separate paths for preparing MHI. Going forward, all controllers will be required to call the mhi_prepare_for_power_up() API followed by their choice of sync or async power up. This allows MHI host driver to get rid of the pre_init flag and sets up a common way for all controllers to use MHI. This also helps controllers fail early on during preparation phase in some failure cases. Signed-off-by: Bhaumik Bhatt <bbhatt@codeaurora.org> Reviewed-by: Hemant Kumar <hemantk@codeaurora.org> Reviewed-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org> Link: https://lore.kernel.org/r/1617313309-24035-1-git-send-email-bbhatt@codeaurora.org Signed-off-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
2021-04-06net/mlx5: Map register values to restore objectsChris Mi
Currently reg_c0 lower 16 bits and reg_b are used to store the chain id that missed in FDB and NIC tables accordingly. However, the registers' values may index a restore object, rather than a single u32 value. Different object types can be used to restore mutually exclusive contexts such as chain id and sample group id. Use the mapping object to associate an index with a restore object as a prestep for supporting additional restore types. Signed-off-by: Chris Mi <cmi@nvidia.com> Reviewed-by: Oz Shlomo <ozsh@nvidia.com> Reviewed-by: Mark Bloch <mbloch@nvidia.com> Signed-off-by: Saeed Mahameed <saeedm@nvidia.com>
2021-04-06net/mlx5: Fix PBMC register mappingAya Levin
Add reserved mapping to cover all the register in order to avoid setting arbitrary values to newer FW which implements the reserved fields. Fixes: 50b4a3c23646 ("net/mlx5: PPTB and PBMC register firmware command support") Signed-off-by: Aya Levin <ayal@nvidia.com> Reviewed-by: Moshe Shemesh <moshe@nvidia.com> Signed-off-by: Saeed Mahameed <saeedm@nvidia.com>
2021-04-06net/mlx5: Fix PPLM register mappingAya Levin
Add reserved mapping to cover all the register in order to avoid setting arbitrary values to newer FW which implements the reserved fields. Fixes: a58837f52d43 ("net/mlx5e: Expose FEC feilds and related capability bit") Signed-off-by: Aya Levin <ayal@nvidia.com> Reviewed-by: Moshe Shemesh <moshe@nvidia.com> Signed-off-by: Saeed Mahameed <saeedm@nvidia.com>
2021-04-06net/mlx5: Fix placement of log_max_flow_counterRaed Salem
The cited commit wrongly placed log_max_flow_counter field of mlx5_ifc_flow_table_prop_layout_bits, align it to the HW spec intended placement. Fixes: 16f1c5bb3ed7 ("net/mlx5: Check device capability for maximum flow counters") Signed-off-by: Raed Salem <raeds@nvidia.com> Reviewed-by: Roi Dayan <roid@nvidia.com> Signed-off-by: Saeed Mahameed <saeedm@nvidia.com>
2021-04-06Merge git://git.kernel.org/pub/scm/linux/kernel/git/pablo/nf-nextDavid S. Miller
Pablo Neira Ayuso says: ==================== Netfilter updates for net-next The following batch contains Netfilter/IPVS updates for your net-next tree: 1) Simplify log infrastructure modularity: Merge ipv4, ipv6, bridge, netdev and ARP families to nf_log_syslog.c. Add module softdeps. This fixes a rare deadlock condition that might occur when log module autoload is required. From Florian Westphal. 2) Moves part of netfilter related pernet data from struct net to net_generic() infrastructure. All of these users can be modules, so if they are not loaded there is no need to waste space. Size reduction is 7 cachelines on x86_64, also from Florian. 2) Update nftables audit support to report events once per table, to get it aligned with iptables. From Richard Guy Briggs. 3) Check for stale routes from the flowtable garbage collector path. This is fixing IPv6 which breaks due missing check for the dst_cookie. 4) Add a nfnl_fill_hdr() function to simplify netlink + nfnetlink headers setup. 5) Remove documentation on several statified functions. 6) Remove printk on netns creation for the FTP IPVS tracker, from Florian Westphal. 7) Remove unnecessary nf_tables_destroy_list_lock spinlock initialization, from Yang Yingliang. 7) Remove a duplicated forward declaration in ipset, from Wan Jiabing. ==================== Signed-off-by: David S. Miller <davem@davemloft.net>
2021-04-06time64.h: Consolidated PSEC_PER_SEC definitionAndy Shevchenko
We have currently three users of the PSEC_PER_SEC each of them defining it individually. Instead, move it to time64.h to be available for everyone. There is a new user coming with the same constant in use. It will also make its life easier. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Acked-by: Heiko Stuebner <heiko@sntech.de> Signed-off-by: David S. Miller <davem@davemloft.net>
generated by cgit (git 2.34.1) at 2025-09-15 13:48:56 +0000