From 8c1dd804734dd1ad73cc3928d0d38010c50c8f9b Mon Sep 17 00:00:00 2001 From: Ryan Wanner Date: Fri, 14 Feb 2025 11:08:14 -0700 Subject: dt-bindings: atmel-sysreg: Add SAMA7D65 Chip ID Add compatible string for SAMA7D65 SoC ChipID dt-bindings. Signed-off-by: Ryan Wanner Acked-by: Rob Herring (Arm) Link: https://lore.kernel.org/r/008e4e49c9fd315cc96a185662b31eca1a64a614.1739555984.git.Ryan.Wanner@microchip.com Signed-off-by: Claudiu Beznea --- Documentation/devicetree/bindings/arm/atmel-sysregs.txt | 1 + 1 file changed, 1 insertion(+) diff --git a/Documentation/devicetree/bindings/arm/atmel-sysregs.txt b/Documentation/devicetree/bindings/arm/atmel-sysregs.txt index 1a173e92bb13..d3821f651e72 100644 --- a/Documentation/devicetree/bindings/arm/atmel-sysregs.txt +++ b/Documentation/devicetree/bindings/arm/atmel-sysregs.txt @@ -2,6 +2,7 @@ Atmel system registers Chipid required properties: - compatible: Should be "atmel,sama5d2-chipid" or "microchip,sama7g5-chipid" + "microchip,sama7d65-chipid" - reg : Should contain registers location and length PIT Timer required properties: -- cgit From 9a913a58b4d5f269e06fe41aea99a5e712982175 Mon Sep 17 00:00:00 2001 From: Ryan Wanner Date: Fri, 14 Feb 2025 11:08:17 -0700 Subject: ARM: at91: Add Support in SoC driver for SAMA7D65 Add support for SAMA7D65 SoC in the SoC driver. Signed-off-by: Ryan Wanner Link: https://lore.kernel.org/r/84b4a7ec0025741bc3ab647671fd4e880b2ed1d5.1739555984.git.Ryan.Wanner@microchip.com [claudiu.beznea: add a space after compatibles to comply with the existing format] Signed-off-by: Claudiu Beznea --- drivers/soc/atmel/soc.c | 5 +++++ drivers/soc/atmel/soc.h | 3 +++ 2 files changed, 8 insertions(+) diff --git a/drivers/soc/atmel/soc.c b/drivers/soc/atmel/soc.c index 298b542dd1c0..09347bccdb1d 100644 --- a/drivers/soc/atmel/soc.c +++ b/drivers/soc/atmel/soc.c @@ -246,6 +246,9 @@ static const struct at91_soc socs[] __initconst = { "samv70q19", "samv7"), #endif #ifdef CONFIG_SOC_SAMA7 + AT91_SOC(SAMA7D65_CIDR_MATCH, AT91_CIDR_MASK_SAMA7G5, + AT91_CIDR_VERSION_MASK_SAMA7G5, SAMA7D65_EXID_MATCH, + "sama7d65", "sama7d6"), AT91_SOC(SAMA7G5_CIDR_MATCH, AT91_CIDR_MATCH_MASK, AT91_CIDR_VERSION_MASK_SAMA7G5, SAMA7G51_EXID_MATCH, "sama7g51", "sama7g5"), @@ -305,6 +308,7 @@ static int __init at91_get_cidr_exid_from_chipid(u32 *cidr, u32 *exid) void __iomem *regs; static const struct of_device_id chipids[] = { { .compatible = "atmel,sama5d2-chipid" }, + { .compatible = "microchip,sama7d65-chipid" }, { .compatible = "microchip,sama7g5-chipid" }, { }, }; @@ -393,6 +397,7 @@ static const struct of_device_id at91_soc_allowed_list[] __initconst = { { .compatible = "atmel,at91sam9", }, { .compatible = "atmel,sama5", }, { .compatible = "atmel,samv7", }, + { .compatible = "microchip,sama7d65", }, { .compatible = "microchip,sama7g5", }, { } }; diff --git a/drivers/soc/atmel/soc.h b/drivers/soc/atmel/soc.h index 2c78e54255f7..66a74017d9a3 100644 --- a/drivers/soc/atmel/soc.h +++ b/drivers/soc/atmel/soc.h @@ -45,6 +45,7 @@ at91_soc_init(const struct at91_soc *socs); #define AT91SAM9N12_CIDR_MATCH 0x019a07a0 #define SAM9X60_CIDR_MATCH 0x019b35a0 #define SAM9X7_CIDR_MATCH 0x09750020 +#define SAMA7D65_CIDR_MATCH 0x00262100 #define SAMA7G5_CIDR_MATCH 0x00162100 #define AT91SAM9M11_EXID_MATCH 0x00000001 @@ -75,6 +76,8 @@ at91_soc_init(const struct at91_soc *socs); #define SAM9X75_D5M_EXID_MATCH 0x00000010 #define SAM9X75_EXID_MATCH 0x00000000 +#define SAMA7D65_EXID_MATCH 0x00000080 + #define SAMA7G51_EXID_MATCH 0x3 #define SAMA7G52_EXID_MATCH 0x2 #define SAMA7G53_EXID_MATCH 0x1 -- cgit From 098ecdef55b7fd738074cc3b5d10ca12f6999db5 Mon Sep 17 00:00:00 2001 From: Wolfram Sang Date: Wed, 26 Feb 2025 09:49:36 +0100 Subject: dt-bindings: ARM: at91: make separate entry for Olimex board The Olimex board exists with only one SoC option. Change the bindings to reflect that. Signed-off-by: Wolfram Sang Acked-by: Rob Herring (Arm) Link: https://lore.kernel.org/r/20250226084938.3436-7-wsa+renesas@sang-engineering.com Signed-off-by: Claudiu Beznea --- Documentation/devicetree/bindings/arm/atmel-at91.yaml | 8 ++++++-- 1 file changed, 6 insertions(+), 2 deletions(-) diff --git a/Documentation/devicetree/bindings/arm/atmel-at91.yaml b/Documentation/devicetree/bindings/arm/atmel-at91.yaml index 0ec29366e6c2..02a8f6aad541 100644 --- a/Documentation/devicetree/bindings/arm/atmel-at91.yaml +++ b/Documentation/devicetree/bindings/arm/atmel-at91.yaml @@ -22,8 +22,6 @@ properties: - items: - const: atmel,at91rm9200 - items: - - enum: - - olimex,sam9-l9260 - enum: - atmel,at91sam9260 - atmel,at91sam9261 @@ -36,6 +34,12 @@ properties: - atmel,at91sam9x60 - const: atmel,at91sam9 + - description: Olimex SAM9-L9260 + items: + - const: olimex,sam9-l9260 + - const: atmel,at91sam9260 + - const: atmel,at91sam9 + - items: - enum: - overkiz,kizboxmini-base # Overkiz kizbox Mini Base Board -- cgit From ebbb3965855e7481395718291fb5b9c79ec5edc4 Mon Sep 17 00:00:00 2001 From: Wolfram Sang Date: Wed, 26 Feb 2025 09:49:37 +0100 Subject: dt-bindings: ARM: at91: add Calao USB boards They have not been added so far. dtbs_check complains loudly. Signed-off-by: Wolfram Sang Acked-by: Rob Herring (Arm) Link: https://lore.kernel.org/r/20250226084938.3436-8-wsa+renesas@sang-engineering.com Signed-off-by: Claudiu Beznea --- .../devicetree/bindings/arm/atmel-at91.yaml | 25 ++++++++++++++++++++++ 1 file changed, 25 insertions(+) diff --git a/Documentation/devicetree/bindings/arm/atmel-at91.yaml b/Documentation/devicetree/bindings/arm/atmel-at91.yaml index 02a8f6aad541..3a34b7a2e8d4 100644 --- a/Documentation/devicetree/bindings/arm/atmel-at91.yaml +++ b/Documentation/devicetree/bindings/arm/atmel-at91.yaml @@ -40,6 +40,31 @@ properties: - const: atmel,at91sam9260 - const: atmel,at91sam9 + - description: Calao USB A9260 + items: + - const: calao,usb-a9260 + - const: atmel,at91sam9260 + - const: atmel,at91sam9 + + - description: Calao USB A9263 + items: + - const: calao,usb-a9263 + - const: atmel,at91sam9263 + - const: atmel,at91sam9 + + - description: Calao USB A9G20 + items: + - const: calao,usb-a9g20 + - const: atmel,at91sam9g20 + - const: atmel,at91sam9 + + - description: Calao USB A9G20-LPW + items: + - const: calao,usb-a9g20-lpw + - const: calao,usb-a9g20 + - const: atmel,at91sam9g20 + - const: atmel,at91sam9 + - items: - enum: - overkiz,kizboxmini-base # Overkiz kizbox Mini Base Board -- cgit From bc4722c3598d0e2c2dbf9609a3d3198993093e2b Mon Sep 17 00:00:00 2001 From: Li Bin Date: Thu, 27 Feb 2025 08:51:56 -0700 Subject: ARM: at91: pm: fix at91_suspend_finish for ZQ calibration For sama7g5 and sama7d65 backup mode, we encountered a "ZQ calibrate error" during recalibrating the impedance in BootStrap. We found that the impedance value saved in at91_suspend_finish() before the DDR entered self-refresh mode did not match the resistor values. The ZDATA field in the DDR3PHY_ZQ0CR0 register uses a modified gray code to select the different impedance setting. But these gray code are incorrect, a workaournd from design team fixed the bug in the calibration logic. The ZDATA contains four independent impedance elements, but the algorithm combined the four elements into one. The elements were fixed using properly shifted offsets. Signed-off-by: Li Bin [nicolas.ferre@microchip.com: fix indentation and combine 2 patches] Signed-off-by: Nicolas Ferre Tested-by: Ryan Wanner Tested-by: Durai Manickam KR Tested-by: Andrei Simion Signed-off-by: Ryan Wanner Link: https://lore.kernel.org/r/28b33f9bcd0ca60ceba032969fe054d38f2b9577.1740671156.git.Ryan.Wanner@microchip.com Signed-off-by: Claudiu Beznea --- arch/arm/mach-at91/pm.c | 21 +++++++++++---------- 1 file changed, 11 insertions(+), 10 deletions(-) diff --git a/arch/arm/mach-at91/pm.c b/arch/arm/mach-at91/pm.c index 05a1547642b6..6c3e6aa22606 100644 --- a/arch/arm/mach-at91/pm.c +++ b/arch/arm/mach-at91/pm.c @@ -545,11 +545,12 @@ extern u32 at91_pm_suspend_in_sram_sz; static int at91_suspend_finish(unsigned long val) { - unsigned char modified_gray_code[] = { - 0x00, 0x01, 0x02, 0x03, 0x06, 0x07, 0x04, 0x05, 0x0c, 0x0d, - 0x0e, 0x0f, 0x0a, 0x0b, 0x08, 0x09, 0x18, 0x19, 0x1a, 0x1b, - 0x1e, 0x1f, 0x1c, 0x1d, 0x14, 0x15, 0x16, 0x17, 0x12, 0x13, - 0x10, 0x11, + /* SYNOPSYS workaround to fix a bug in the calibration logic */ + unsigned char modified_fix_code[] = { + 0x00, 0x01, 0x01, 0x06, 0x07, 0x0c, 0x06, 0x07, 0x0b, 0x18, + 0x0a, 0x0b, 0x0c, 0x0d, 0x0d, 0x0a, 0x13, 0x13, 0x12, 0x13, + 0x14, 0x15, 0x15, 0x12, 0x18, 0x19, 0x19, 0x1e, 0x1f, 0x14, + 0x1e, 0x1f, }; unsigned int tmp, index; int i; @@ -560,25 +561,25 @@ static int at91_suspend_finish(unsigned long val) * restore the ZQ0SR0 with the value saved here. But the * calibration is buggy and restoring some values from ZQ0SR0 * is forbidden and risky thus we need to provide processed - * values for these (modified gray code values). + * values for these. */ tmp = readl(soc_pm.data.ramc_phy + DDR3PHY_ZQ0SR0); /* Store pull-down output impedance select. */ index = (tmp >> DDR3PHY_ZQ0SR0_PDO_OFF) & 0x1f; - soc_pm.bu->ddr_phy_calibration[0] = modified_gray_code[index]; + soc_pm.bu->ddr_phy_calibration[0] = modified_fix_code[index] << DDR3PHY_ZQ0SR0_PDO_OFF; /* Store pull-up output impedance select. */ index = (tmp >> DDR3PHY_ZQ0SR0_PUO_OFF) & 0x1f; - soc_pm.bu->ddr_phy_calibration[0] |= modified_gray_code[index]; + soc_pm.bu->ddr_phy_calibration[0] |= modified_fix_code[index] << DDR3PHY_ZQ0SR0_PUO_OFF; /* Store pull-down on-die termination impedance select. */ index = (tmp >> DDR3PHY_ZQ0SR0_PDODT_OFF) & 0x1f; - soc_pm.bu->ddr_phy_calibration[0] |= modified_gray_code[index]; + soc_pm.bu->ddr_phy_calibration[0] |= modified_fix_code[index] << DDR3PHY_ZQ0SR0_PDODT_OFF; /* Store pull-up on-die termination impedance select. */ index = (tmp >> DDR3PHY_ZQ0SRO_PUODT_OFF) & 0x1f; - soc_pm.bu->ddr_phy_calibration[0] |= modified_gray_code[index]; + soc_pm.bu->ddr_phy_calibration[0] |= modified_fix_code[index] << DDR3PHY_ZQ0SRO_PUODT_OFF; /* * The 1st 8 words of memory might get corrupted in the process -- cgit From 8e96f5080eeef70fccf7007a025de98661a549d8 Mon Sep 17 00:00:00 2001 From: Ryan Wanner Date: Thu, 27 Feb 2025 08:51:57 -0700 Subject: ARM: at91: pm: add DT compatible support for sama7d65 Add support for SAMA7D65 new compatible strings in pm.c file for wakeup source IDs and PMC. This is the first bits of PM for this new SoC. PM depends on other patches. Signed-off-by: Ryan Wanner [nicolas.ferre@microchip.com: split patch and address only the pm.c changes] Signed-off-by: Nicolas Ferre Link: https://lore.kernel.org/r/06b64869f2de4b499835d153411ba30512409168.1740671156.git.Ryan.Wanner@microchip.com [claudiu.beznea: add proper entry in pmc_infos[] for SAMA7D65 instead of using wrong data and fixing it in the next commits] Signed-off-by: Claudiu Beznea --- arch/arm/mach-at91/pm.c | 14 +++++++++++--- 1 file changed, 11 insertions(+), 3 deletions(-) diff --git a/arch/arm/mach-at91/pm.c b/arch/arm/mach-at91/pm.c index 6c3e6aa22606..6c4e168f1844 100644 --- a/arch/arm/mach-at91/pm.c +++ b/arch/arm/mach-at91/pm.c @@ -222,13 +222,16 @@ static const struct of_device_id sam9x60_ws_ids[] = { { /* sentinel */ } }; -static const struct of_device_id sama7g5_ws_ids[] = { +static const struct of_device_id sama7_ws_ids[] = { + { .compatible = "microchip,sama7d65-rtc", .data = &ws_info[1] }, { .compatible = "microchip,sama7g5-rtc", .data = &ws_info[1] }, { .compatible = "microchip,sama7g5-ohci", .data = &ws_info[2] }, { .compatible = "usb-ohci", .data = &ws_info[2] }, { .compatible = "atmel,at91sam9g45-ehci", .data = &ws_info[2] }, { .compatible = "usb-ehci", .data = &ws_info[2] }, + { .compatible = "microchip,sama7d65-sdhci", .data = &ws_info[3] }, { .compatible = "microchip,sama7g5-sdhci", .data = &ws_info[3] }, + { .compatible = "microchip,sama7d65-rtt", .data = &ws_info[4] }, { .compatible = "microchip,sama7g5-rtt", .data = &ws_info[4] }, { /* sentinel */ } }; @@ -1362,7 +1365,11 @@ static const struct pmc_info pmc_infos[] __initconst = { .mckr = 0x28, .version = AT91_PMC_V2, }, - + { + .uhp_udp_mask = AT91SAM926x_PMC_UHP, + .mckr = 0x28, + .version = AT91_PMC_V2, + }, }; static const struct of_device_id atmel_pmc_ids[] __initconst = { @@ -1379,6 +1386,7 @@ static const struct of_device_id atmel_pmc_ids[] __initconst = { { .compatible = "atmel,sama5d2-pmc", .data = &pmc_infos[1] }, { .compatible = "microchip,sam9x60-pmc", .data = &pmc_infos[4] }, { .compatible = "microchip,sam9x7-pmc", .data = &pmc_infos[4] }, + { .compatible = "microchip,sama7d65-pmc", .data = &pmc_infos[6] }, { .compatible = "microchip,sama7g5-pmc", .data = &pmc_infos[5] }, { /* sentinel */ }, }; @@ -1672,7 +1680,7 @@ void __init sama7_pm_init(void) at91_pm_modes_init(iomaps, ARRAY_SIZE(iomaps)); at91_pm_init(NULL); - soc_pm.ws_ids = sama7g5_ws_ids; + soc_pm.ws_ids = sama7_ws_ids; soc_pm.config_pmc_ws = at91_sam9x60_config_pmc_ws; soc_pm.sfrbu_regs.pswbu.key = (0x4BD20C << 8); -- cgit From 23b43c1a821615e04848f85ff90dcc3c3aa96c0c Mon Sep 17 00:00:00 2001 From: Ryan Wanner Date: Thu, 27 Feb 2025 08:51:58 -0700 Subject: ARM: at91: pm: Add Backup mode for SAMA7D65 Add config check that enables Backup mode for SAMA7D65 SoC. Add SHDWC_SR read to clear the status bits once finished exiting backup mode. This is only for SAMA7D65 SoCs. The SHDWC status register needs to be cleared after exiting backup mode to clear the wake up pin status. Signed-off-by: Ryan Wanner Link: https://lore.kernel.org/r/3a1f59af1ac9322b0203694b535d5d13120a31eb.1740671156.git.Ryan.Wanner@microchip.com [claudiu.beznea: dropped extra blank lines, use {} for multi-line statements that includes comments, s/PM/pm in commit title to have the same pattern accross all commits] Signed-off-by: Claudiu Beznea --- arch/arm/mach-at91/pm.c | 8 +++++++- 1 file changed, 7 insertions(+), 1 deletion(-) diff --git a/arch/arm/mach-at91/pm.c b/arch/arm/mach-at91/pm.c index 6c4e168f1844..a2d188b47866 100644 --- a/arch/arm/mach-at91/pm.c +++ b/arch/arm/mach-at91/pm.c @@ -647,6 +647,11 @@ static void at91_pm_suspend(suspend_state_t state) at91_suspend_sram_fn = fncpy(at91_suspend_sram_fn, &at91_pm_suspend_in_sram, at91_pm_suspend_in_sram_sz); + + if (IS_ENABLED(CONFIG_SOC_SAMA7D65)) { + /* SHDWC.SR */ + readl(soc_pm.data.shdwc + 0x08); + } } else { at91_suspend_finish(0); } @@ -1065,7 +1070,8 @@ static int __init at91_pm_backup_init(void) int ret = -ENODEV, located = 0; if (!IS_ENABLED(CONFIG_SOC_SAMA5D2) && - !IS_ENABLED(CONFIG_SOC_SAMA7G5)) + !IS_ENABLED(CONFIG_SOC_SAMA7G5) && + !IS_ENABLED(CONFIG_SOC_SAMA7D65)) return -EPERM; if (!at91_is_pm_mode_active(AT91_PM_BACKUP)) -- cgit From 8bd10f002411c9ea947edc0af18ad81f789e28d5 Mon Sep 17 00:00:00 2001 From: Ryan Wanner Date: Thu, 27 Feb 2025 08:51:59 -0700 Subject: ARM: at91: pm: Enable ULP0/ULP1 for SAMA7D65 New clocks are saved to enable ULP0/ULP1 for SAMA7D65 because this SoC has a total of 9 main clocks that need to be saved for ULP0/ULP1 mode. Add mcks member to at91_pm_data, this will be used to determine how many main clocks need to be saved. In the pm_mcks variable will also make sure that no unnecessary clock settings are written during mck_ps_restore. Signed-off-by: Ryan Wanner Acked-by: Nicolas Ferre Link: https://lore.kernel.org/r/2ac0832f6ede17a5c111ede09b44b8a126e33e36.1740671156.git.Ryan.Wanner@microchip.com [claudiu.beznea: adjusted the entry in pmc_infos[] array] Signed-off-by: Claudiu Beznea --- arch/arm/mach-at91/pm.c | 4 ++ arch/arm/mach-at91/pm.h | 1 + arch/arm/mach-at91/pm_data-offsets.c | 2 + arch/arm/mach-at91/pm_suspend.S | 101 +++++++++++++++++++++++++++++++---- 4 files changed, 99 insertions(+), 9 deletions(-) diff --git a/arch/arm/mach-at91/pm.c b/arch/arm/mach-at91/pm.c index a2d188b47866..3aa20038ad93 100644 --- a/arch/arm/mach-at91/pm.c +++ b/arch/arm/mach-at91/pm.c @@ -1339,6 +1339,7 @@ struct pmc_info { unsigned long uhp_udp_mask; unsigned long mckr; unsigned long version; + unsigned long mcks; }; static const struct pmc_info pmc_infos[] __initconst = { @@ -1370,11 +1371,13 @@ static const struct pmc_info pmc_infos[] __initconst = { { .mckr = 0x28, .version = AT91_PMC_V2, + .mcks = 4, }, { .uhp_udp_mask = AT91SAM926x_PMC_UHP, .mckr = 0x28, .version = AT91_PMC_V2, + .mcks = 9, }, }; @@ -1463,6 +1466,7 @@ static void __init at91_pm_init(void (*pm_idle)(void)) soc_pm.data.uhp_udp_mask = pmc->uhp_udp_mask; soc_pm.data.pmc_mckr_offset = pmc->mckr; soc_pm.data.pmc_version = pmc->version; + soc_pm.data.pmc_mcks = pmc->mcks; if (pm_idle) arm_pm_idle = pm_idle; diff --git a/arch/arm/mach-at91/pm.h b/arch/arm/mach-at91/pm.h index 53bdc9000e44..50c3a425d140 100644 --- a/arch/arm/mach-at91/pm.h +++ b/arch/arm/mach-at91/pm.h @@ -39,6 +39,7 @@ struct at91_pm_data { unsigned int suspend_mode; unsigned int pmc_mckr_offset; unsigned int pmc_version; + unsigned int pmc_mcks; }; #endif diff --git a/arch/arm/mach-at91/pm_data-offsets.c b/arch/arm/mach-at91/pm_data-offsets.c index 40bd4e8fe40a..0ca5da66dc26 100644 --- a/arch/arm/mach-at91/pm_data-offsets.c +++ b/arch/arm/mach-at91/pm_data-offsets.c @@ -18,6 +18,8 @@ int main(void) pmc_mckr_offset)); DEFINE(PM_DATA_PMC_VERSION, offsetof(struct at91_pm_data, pmc_version)); + DEFINE(PM_DATA_PMC_MCKS, offsetof(struct at91_pm_data, + pmc_mcks)); return 0; } diff --git a/arch/arm/mach-at91/pm_suspend.S b/arch/arm/mach-at91/pm_suspend.S index e5869cca5e79..e23b86834096 100644 --- a/arch/arm/mach-at91/pm_suspend.S +++ b/arch/arm/mach-at91/pm_suspend.S @@ -814,18 +814,20 @@ sr_dis_exit: .endm /** - * at91_mckx_ps_enable: save MCK1..4 settings and switch it to main clock + * at91_mckx_ps_enable: save MCK settings and switch it to main clock * - * Side effects: overwrites tmp1, tmp2 + * Side effects: overwrites tmp1, tmp2, tmp3 */ .macro at91_mckx_ps_enable #ifdef CONFIG_SOC_SAMA7 ldr pmc, .pmc_base + ldr tmp3, .mcks - /* There are 4 MCKs we need to handle: MCK1..4 */ + /* Start at MCK1 and go until MCKs */ mov tmp1, #1 -e_loop: cmp tmp1, #5 - beq e_done +e_loop: + cmp tmp1, tmp3 + bgt e_done /* Write MCK ID to retrieve the settings. */ str tmp1, [pmc, #AT91_PMC_MCR_V2] @@ -850,7 +852,37 @@ e_save_mck3: b e_ps e_save_mck4: + cmp tmp1, #4 + bne e_save_mck5 str tmp2, .saved_mck4 + b e_ps + +e_save_mck5: + cmp tmp1, #5 + bne e_save_mck6 + str tmp2, .saved_mck5 + b e_ps + +e_save_mck6: + cmp tmp1, #6 + bne e_save_mck7 + str tmp2, .saved_mck6 + b e_ps + +e_save_mck7: + cmp tmp1, #7 + bne e_save_mck8 + str tmp2, .saved_mck7 + b e_ps + +e_save_mck8: + cmp tmp1, #8 + bne e_save_mck9 + str tmp2, .saved_mck8 + b e_ps + +e_save_mck9: + str tmp2, .saved_mck9 e_ps: /* Use CSS=MAINCK and DIV=1. */ @@ -870,18 +902,20 @@ e_done: .endm /** - * at91_mckx_ps_restore: restore MCK1..4 settings + * at91_mckx_ps_restore: restore MCKx settings * * Side effects: overwrites tmp1, tmp2 */ .macro at91_mckx_ps_restore #ifdef CONFIG_SOC_SAMA7 ldr pmc, .pmc_base + ldr tmp2, .mcks - /* There are 4 MCKs we need to handle: MCK1..4 */ + /* Start from MCK1 and go up to MCKs */ mov tmp1, #1 -r_loop: cmp tmp1, #5 - beq r_done +r_loop: + cmp tmp1, tmp2 + bgt r_done r_save_mck1: cmp tmp1, #1 @@ -902,7 +936,37 @@ r_save_mck3: b r_ps r_save_mck4: + cmp tmp1, #4 + bne r_save_mck5 ldr tmp2, .saved_mck4 + b r_ps + +r_save_mck5: + cmp tmp1, #5 + bne r_save_mck6 + ldr tmp2, .saved_mck5 + b r_ps + +r_save_mck6: + cmp tmp1, #6 + bne r_save_mck7 + ldr tmp2, .saved_mck6 + b r_ps + +r_save_mck7: + cmp tmp1, #7 + bne r_save_mck8 + ldr tmp2, .saved_mck7 + b r_ps + +r_save_mck8: + cmp tmp1, #8 + bne r_save_mck9 + ldr tmp2, .saved_mck8 + b r_ps + +r_save_mck9: + ldr tmp2, .saved_mck9 r_ps: /* Write MCK ID to retrieve the settings. */ @@ -921,6 +985,7 @@ r_ps: wait_mckrdy tmp1 add tmp1, tmp1, #1 + ldr tmp2, .mcks b r_loop r_done: #endif @@ -1045,6 +1110,10 @@ ENTRY(at91_pm_suspend_in_sram) str tmp1, .memtype ldr tmp1, [r0, #PM_DATA_MODE] str tmp1, .pm_mode +#ifdef CONFIG_SOC_SAMA7 + ldr tmp1, [r0, #PM_DATA_PMC_MCKS] + str tmp1, .mcks +#endif /* * ldrne below are here to preload their address in the TLB as access @@ -1132,6 +1201,10 @@ ENDPROC(at91_pm_suspend_in_sram) .word 0 .pmc_version: .word 0 +#ifdef CONFIG_SOC_SAMA7 +.mcks: + .word 0 +#endif .saved_mckr: .word 0 .saved_pllar: @@ -1155,6 +1228,16 @@ ENDPROC(at91_pm_suspend_in_sram) .word 0 .saved_mck4: .word 0 +.saved_mck5: + .word 0 +.saved_mck6: + .word 0 +.saved_mck7: + .word 0 +.saved_mck8: + .word 0 +.saved_mck9: + .word 0 #endif ENTRY(at91_pm_suspend_in_sram_sz) -- cgit