From 9972b45776aba937d0db67f8080ec627a924f56e Mon Sep 17 00:00:00 2001 From: Nishanth Menon Date: Fri, 14 Apr 2023 02:33:19 -0500 Subject: arm64: dts: ti: k3-am64: Add general purpose timers There are 11 general purpose timers on am64 that can be used for things like PWM using pwm-omap-dmtimer driver. There are also additional four timers in the MCU domain that do not have interrupts routable for Linux. We configure the timers with the 25 MHz input clock by default as the 32.768 kHz clock may not be wired on the device. We leave the MCU domain timers clock mux unconfigured, and mark the MCU domain timers reserved. The MCU domain timers are likely reserved by the software for the ESM module. Compared to am65, the timers on am64 do not have a dedicated IO mux for the timers. On am62, the timers have different interrupts, clocks and power domains compared to am65, and the MCU timers are at a different IO address. Compared to AM62, the AM64 times have different clocks and count in main domain are different as well. Signed-off-by: Nishanth Menon Reviewed-by: Roger Quadros Link: https://lore.kernel.org/r/20230414073328.381336-2-nm@ti.com Signed-off-by: Vignesh Raghavendra --- arch/arm64/boot/dts/ti/k3-am64-main.dtsi | 144 +++++++++++++++++++++++++++++++ arch/arm64/boot/dts/ti/k3-am64-mcu.dtsi | 45 ++++++++++ 2 files changed, 189 insertions(+) diff --git a/arch/arm64/boot/dts/ti/k3-am64-main.dtsi b/arch/arm64/boot/dts/ti/k3-am64-main.dtsi index 5e8036f32d79..f5e25d6c3c28 100644 --- a/arch/arm64/boot/dts/ti/k3-am64-main.dtsi +++ b/arch/arm64/boot/dts/ti/k3-am64-main.dtsi @@ -228,6 +228,150 @@ }; }; + main_timer0: timer@2400000 { + compatible = "ti,am654-timer"; + reg = <0x00 0x2400000 0x00 0x400>; + interrupts = ; + clocks = <&k3_clks 36 1>; + clock-names = "fck"; + assigned-clocks = <&k3_clks 36 1>; + assigned-clock-parents = <&k3_clks 36 2>; + power-domains = <&k3_pds 36 TI_SCI_PD_EXCLUSIVE>; + ti,timer-pwm; + }; + + main_timer1: timer@2410000 { + compatible = "ti,am654-timer"; + reg = <0x00 0x2410000 0x00 0x400>; + interrupts = ; + clocks = <&k3_clks 37 1>; + clock-names = "fck"; + assigned-clocks = <&k3_clks 37 1>; + assigned-clock-parents = <&k3_clks 37 2>; + power-domains = <&k3_pds 37 TI_SCI_PD_EXCLUSIVE>; + ti,timer-pwm; + }; + + main_timer2: timer@2420000 { + compatible = "ti,am654-timer"; + reg = <0x00 0x2420000 0x00 0x400>; + interrupts = ; + clocks = <&k3_clks 38 1>; + clock-names = "fck"; + assigned-clocks = <&k3_clks 38 1>; + assigned-clock-parents = <&k3_clks 38 2>; + power-domains = <&k3_pds 38 TI_SCI_PD_EXCLUSIVE>; + ti,timer-pwm; + }; + + main_timer3: timer@2430000 { + compatible = "ti,am654-timer"; + reg = <0x00 0x2430000 0x00 0x400>; + interrupts = ; + clocks = <&k3_clks 39 1>; + clock-names = "fck"; + assigned-clocks = <&k3_clks 39 1>; + assigned-clock-parents = <&k3_clks 39 2>; + power-domains = <&k3_pds 39 TI_SCI_PD_EXCLUSIVE>; + ti,timer-pwm; + }; + + main_timer4: timer@2440000 { + compatible = "ti,am654-timer"; + reg = <0x00 0x2440000 0x00 0x400>; + interrupts = ; + clocks = <&k3_clks 40 1>; + clock-names = "fck"; + assigned-clocks = <&k3_clks 40 1>; + assigned-clock-parents = <&k3_clks 40 2>; + power-domains = <&k3_pds 40 TI_SCI_PD_EXCLUSIVE>; + ti,timer-pwm; + }; + + main_timer5: timer@2450000 { + compatible = "ti,am654-timer"; + reg = <0x00 0x2450000 0x00 0x400>; + interrupts = ; + clocks = <&k3_clks 41 1>; + clock-names = "fck"; + assigned-clocks = <&k3_clks 41 1>; + assigned-clock-parents = <&k3_clks 41 2>; + power-domains = <&k3_pds 41 TI_SCI_PD_EXCLUSIVE>; + ti,timer-pwm; + }; + + main_timer6: timer@2460000 { + compatible = "ti,am654-timer"; + reg = <0x00 0x2460000 0x00 0x400>; + interrupts = ; + clocks = <&k3_clks 42 1>; + clock-names = "fck"; + assigned-clocks = <&k3_clks 42 1>; + assigned-clock-parents = <&k3_clks 42 2>; + power-domains = <&k3_pds 42 TI_SCI_PD_EXCLUSIVE>; + ti,timer-pwm; + }; + + main_timer7: timer@2470000 { + compatible = "ti,am654-timer"; + reg = <0x00 0x2470000 0x00 0x400>; + interrupts = ; + clocks = <&k3_clks 43 1>; + clock-names = "fck"; + assigned-clocks = <&k3_clks 43 1>; + assigned-clock-parents = <&k3_clks 43 2>; + power-domains = <&k3_pds 43 TI_SCI_PD_EXCLUSIVE>; + ti,timer-pwm; + }; + + main_timer8: timer@2480000 { + compatible = "ti,am654-timer"; + reg = <0x00 0x2480000 0x00 0x400>; + interrupts = ; + clocks = <&k3_clks 44 1>; + clock-names = "fck"; + assigned-clocks = <&k3_clks 44 1>; + assigned-clock-parents = <&k3_clks 44 2>; + power-domains = <&k3_pds 44 TI_SCI_PD_EXCLUSIVE>; + ti,timer-pwm; + }; + + main_timer9: timer@2490000 { + compatible = "ti,am654-timer"; + reg = <0x00 0x2490000 0x00 0x400>; + interrupts = ; + clocks = <&k3_clks 45 1>; + clock-names = "fck"; + assigned-clocks = <&k3_clks 45 1>; + assigned-clock-parents = <&k3_clks 45 2>; + power-domains = <&k3_pds 45 TI_SCI_PD_EXCLUSIVE>; + ti,timer-pwm; + }; + + main_timer10: timer@24a0000 { + compatible = "ti,am654-timer"; + reg = <0x00 0x24a0000 0x00 0x400>; + interrupts = ; + clocks = <&k3_clks 46 1>; + clock-names = "fck"; + assigned-clocks = <&k3_clks 46 1>; + assigned-clock-parents = <&k3_clks 46 2>; + power-domains = <&k3_pds 46 TI_SCI_PD_EXCLUSIVE>; + ti,timer-pwm; + }; + + main_timer11: timer@24b0000 { + compatible = "ti,am654-timer"; + reg = <0x00 0x24b0000 0x00 0x400>; + interrupts = ; + clocks = <&k3_clks 47 1>; + clock-names = "fck"; + assigned-clocks = <&k3_clks 47 1>; + assigned-clock-parents = <&k3_clks 47 2>; + power-domains = <&k3_pds 47 TI_SCI_PD_EXCLUSIVE>; + ti,timer-pwm; + }; + main_uart0: serial@2800000 { compatible = "ti,am64-uart", "ti,am654-uart"; reg = <0x00 0x02800000 0x00 0x100>; diff --git a/arch/arm64/boot/dts/ti/k3-am64-mcu.dtsi b/arch/arm64/boot/dts/ti/k3-am64-mcu.dtsi index 38ddf0b3b8a0..31336b0e290e 100644 --- a/arch/arm64/boot/dts/ti/k3-am64-mcu.dtsi +++ b/arch/arm64/boot/dts/ti/k3-am64-mcu.dtsi @@ -6,6 +6,51 @@ */ &cbass_mcu { + /* + * The MCU domain timer interrupts are routed only to the ESM module, + * and not currently available for Linux. The MCU domain timers are + * of limited use without interrupts, and likely reserved by the ESM. + */ + mcu_timer0: timer@4800000 { + compatible = "ti,am654-timer"; + reg = <0x00 0x4800000 0x00 0x400>; + clocks = <&k3_clks 35 1>; + clock-names = "fck"; + power-domains = <&k3_pds 35 TI_SCI_PD_EXCLUSIVE>; + ti,timer-pwm; + status = "reserved"; + }; + + mcu_timer1: timer@4810000 { + compatible = "ti,am654-timer"; + reg = <0x00 0x4810000 0x00 0x400>; + clocks = <&k3_clks 48 1>; + clock-names = "fck"; + power-domains = <&k3_pds 48 TI_SCI_PD_EXCLUSIVE>; + ti,timer-pwm; + status = "reserved"; + }; + + mcu_timer2: timer@4820000 { + compatible = "ti,am654-timer"; + reg = <0x00 0x4820000 0x00 0x400>; + clocks = <&k3_clks 49 1>; + clock-names = "fck"; + power-domains = <&k3_pds 49 TI_SCI_PD_EXCLUSIVE>; + ti,timer-pwm; + status = "reserved"; + }; + + mcu_timer3: timer@4830000 { + compatible = "ti,am654-timer"; + reg = <0x00 0x4830000 0x00 0x400>; + clocks = <&k3_clks 50 1>; + clock-names = "fck"; + power-domains = <&k3_pds 50 TI_SCI_PD_EXCLUSIVE>; + ti,timer-pwm; + status = "reserved"; + }; + mcu_uart0: serial@4a00000 { compatible = "ti,am64-uart", "ti,am654-uart"; reg = <0x00 0x04a00000 0x00 0x100>; -- cgit From 744545ffec14f74f26f57828afa685f6f4eadd9e Mon Sep 17 00:00:00 2001 From: Nishanth Menon Date: Fri, 14 Apr 2023 02:33:20 -0500 Subject: arm64: dts: ti: k3-am642-sk: Fix mmc1 pinmux Fix the pinmux for pulldirection to get stable sdcard behavior. Signed-off-by: Nishanth Menon Reviewed-by: Roger Quadros Link: https://lore.kernel.org/r/20230414073328.381336-3-nm@ti.com Signed-off-by: Vignesh Raghavendra --- arch/arm64/boot/dts/ti/k3-am642-sk.dts | 15 ++++++++------- 1 file changed, 8 insertions(+), 7 deletions(-) diff --git a/arch/arm64/boot/dts/ti/k3-am642-sk.dts b/arch/arm64/boot/dts/ti/k3-am642-sk.dts index 2e2d40da360a..9a65f9b1c9ab 100644 --- a/arch/arm64/boot/dts/ti/k3-am642-sk.dts +++ b/arch/arm64/boot/dts/ti/k3-am642-sk.dts @@ -224,14 +224,15 @@ &main_pmx0 { main_mmc1_pins_default: main-mmc1-pins-default { pinctrl-single,pins = < - AM64X_IOPAD(0x0294, PIN_INPUT, 0) /* (J19) MMC1_CMD */ + AM64X_IOPAD(0x029c, PIN_INPUT_PULLUP, 0) /* (C20) MMC1_SDWP */ + AM64X_IOPAD(0x0298, PIN_INPUT_PULLUP, 0) /* (D19) MMC1_SDCD */ + AM64X_IOPAD(0x0294, PIN_INPUT_PULLUP, 0) /* (J19) MMC1_CMD */ AM64X_IOPAD(0x0290, PIN_INPUT, 0) /* (#N/A) MMC1_CLKLB */ - AM64X_IOPAD(0x028c, PIN_INPUT, 0) /* (L20) MMC1_CLK */ - AM64X_IOPAD(0x0288, PIN_INPUT, 0) /* (K21) MMC1_DAT0 */ - AM64X_IOPAD(0x0284, PIN_INPUT, 0) /* (L21) MMC1_DAT1 */ - AM64X_IOPAD(0x0280, PIN_INPUT, 0) /* (K19) MMC1_DAT2 */ - AM64X_IOPAD(0x027c, PIN_INPUT, 0) /* (K18) MMC1_DAT3 */ - AM64X_IOPAD(0x0298, PIN_INPUT, 0) /* (D19) MMC1_SDCD */ + AM64X_IOPAD(0x028c, PIN_INPUT_PULLDOWN, 0) /* (L20) MMC1_CLK */ + AM64X_IOPAD(0x0288, PIN_INPUT_PULLUP, 0) /* (K21) MMC1_DAT0 */ + AM64X_IOPAD(0x0284, PIN_INPUT_PULLUP, 0) /* (L21) MMC1_DAT1 */ + AM64X_IOPAD(0x0280, PIN_INPUT_PULLUP, 0) /* (K19) MMC1_DAT2 */ + AM64X_IOPAD(0x027c, PIN_INPUT_PULLUP, 0) /* (K18) MMC1_DAT3 */ >; }; -- cgit From 1d79ca01e62096e87686244cdf4864f338ccd200 Mon Sep 17 00:00:00 2001 From: Nishanth Menon Date: Fri, 14 Apr 2023 02:33:21 -0500 Subject: arm64: dts: ti: k3-am642-sk: Enable main_i2c0 and eeprom Enable AT24C512C on the base board. Signed-off-by: Nishanth Menon Reviewed-by: Roger Quadros Link: https://lore.kernel.org/r/20230414073328.381336-4-nm@ti.com Signed-off-by: Vignesh Raghavendra --- arch/arm64/boot/dts/ti/k3-am642-sk.dts | 19 +++++++++++++++++++ 1 file changed, 19 insertions(+) diff --git a/arch/arm64/boot/dts/ti/k3-am642-sk.dts b/arch/arm64/boot/dts/ti/k3-am642-sk.dts index 9a65f9b1c9ab..3e16942c0add 100644 --- a/arch/arm64/boot/dts/ti/k3-am642-sk.dts +++ b/arch/arm64/boot/dts/ti/k3-am642-sk.dts @@ -251,6 +251,13 @@ >; }; + main_i2c0_pins_default: main-i2c0-pins-default { + pinctrl-single,pins = < + AM64X_IOPAD(0x0260, PIN_INPUT_PULLUP, 0) /* (A18) I2C0_SCL */ + AM64X_IOPAD(0x0264, PIN_INPUT_PULLUP, 0) /* (B18) I2C0_SDA */ + >; + }; + main_i2c1_pins_default: main-i2c1-pins-default { pinctrl-single,pins = < AM64X_IOPAD(0x0268, PIN_INPUT_PULLUP, 0) /* (C18) I2C1_SCL */ @@ -350,6 +357,18 @@ status = "reserved"; }; +&main_i2c0 { + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&main_i2c0_pins_default>; + clock-frequency = <400000>; + + eeprom@51 { + compatible = "atmel,24c512"; + reg = <0x51>; + }; +}; + &main_i2c1 { status = "okay"; pinctrl-names = "default"; -- cgit From c8da2f207168d2c93f7fa7bff92f6b395c342e4a Mon Sep 17 00:00:00 2001 From: Nishanth Menon Date: Fri, 14 Apr 2023 02:33:22 -0500 Subject: arm64: dts: ti: k3-am642-sk: Describe main_uart1 pins Describe the main_uart1 pins even though it is a reserved node for hardware complete description. This is used by other users of device tree to help configure the SoC per board requirements. Signed-off-by: Nishanth Menon Reviewed-by: Roger Quadros Link: https://lore.kernel.org/r/20230414073328.381336-5-nm@ti.com Signed-off-by: Vignesh Raghavendra --- arch/arm64/boot/dts/ti/k3-am642-sk.dts | 11 +++++++++++ 1 file changed, 11 insertions(+) diff --git a/arch/arm64/boot/dts/ti/k3-am642-sk.dts b/arch/arm64/boot/dts/ti/k3-am642-sk.dts index 3e16942c0add..da4121b2e2c6 100644 --- a/arch/arm64/boot/dts/ti/k3-am642-sk.dts +++ b/arch/arm64/boot/dts/ti/k3-am642-sk.dts @@ -245,6 +245,15 @@ >; }; + main_uart1_pins_default: main-uart1-pins-default { + pinctrl-single,pins = < + AM64X_IOPAD(0x0248, PIN_INPUT, 0) /* (D16) UART1_CTSn */ + AM64X_IOPAD(0x024c, PIN_OUTPUT, 0) /* (E16) UART1_RTSn */ + AM64X_IOPAD(0x0240, PIN_INPUT, 0) /* (E15) UART1_RXD */ + AM64X_IOPAD(0x0244, PIN_OUTPUT, 0) /* (E14) UART1_TXD */ + >; + }; + main_usb0_pins_default: main-usb0-pins-default { pinctrl-single,pins = < AM64X_IOPAD(0x02a8, PIN_OUTPUT, 0) /* (E19) USB0_DRVVBUS */ @@ -355,6 +364,8 @@ &main_uart1 { /* main_uart1 is reserved for firmware usage */ status = "reserved"; + pinctrl-names = "default"; + pinctrl-0 = <&main_uart1_pins_default>; }; &main_i2c0 { -- cgit From 826b6679bd08694ad7a830eb30608c3e5a780941 Mon Sep 17 00:00:00 2001 From: Nishanth Menon Date: Fri, 14 Apr 2023 02:33:23 -0500 Subject: arm64: dts: ti: k3-am642-sk: Rename regulator node name Rename the regulator node names to the standard regulator-0.. numbers. Signed-off-by: Nishanth Menon Reviewed-by: Roger Quadros Link: https://lore.kernel.org/r/20230414073328.381336-6-nm@ti.com Signed-off-by: Vignesh Raghavendra --- arch/arm64/boot/dts/ti/k3-am642-sk.dts | 10 +++++----- 1 file changed, 5 insertions(+), 5 deletions(-) diff --git a/arch/arm64/boot/dts/ti/k3-am642-sk.dts b/arch/arm64/boot/dts/ti/k3-am642-sk.dts index da4121b2e2c6..5bd69a8e8063 100644 --- a/arch/arm64/boot/dts/ti/k3-am642-sk.dts +++ b/arch/arm64/boot/dts/ti/k3-am642-sk.dts @@ -94,7 +94,7 @@ }; }; - vusb_main: fixed-regulator-vusb-main5v0 { + vusb_main: regulator-0 { /* USB MAIN INPUT 5V DC */ compatible = "regulator-fixed"; regulator-name = "vusb_main5v0"; @@ -104,7 +104,7 @@ regulator-boot-on; }; - vcc_3v3_sys: fixedregulator-vcc-3v3-sys { + vcc_3v3_sys: regulator-1 { /* output of LP8733xx */ compatible = "regulator-fixed"; regulator-name = "vcc_3v3_sys"; @@ -115,7 +115,7 @@ regulator-boot-on; }; - vdd_mmc1: fixed-regulator-sd { + vdd_mmc1: regulator-2 { /* TPS2051BD */ compatible = "regulator-fixed"; regulator-name = "vdd_mmc1"; @@ -127,7 +127,7 @@ gpio = <&exp1 3 GPIO_ACTIVE_HIGH>; }; - com8_ls_en: regulator-1 { + com8_ls_en: regulator-3 { compatible = "regulator-fixed"; regulator-name = "com8_ls_en"; regulator-min-microvolt = <3300000>; @@ -139,7 +139,7 @@ gpio = <&main_gpio0 62 GPIO_ACTIVE_LOW>; }; - wlan_en: regulator-2 { + wlan_en: regulator-4 { /* output of SN74AVC4T245RSVR */ compatible = "regulator-fixed"; regulator-name = "wlan_en"; -- cgit From cf3b25bc3cc0b66cfaae9614620228a5c2246ecb Mon Sep 17 00:00:00 2001 From: Nishanth Menon Date: Fri, 14 Apr 2023 02:33:24 -0500 Subject: arm64: dts: ti: k3-am642-evm: Enable main_i2c0 and eeprom Enable AT24CM01 on the base board using the corresponding compatible. Signed-off-by: Nishanth Menon Reviewed-by: Roger Quadros Link: https://lore.kernel.org/r/20230414073328.381336-7-nm@ti.com Signed-off-by: Vignesh Raghavendra --- arch/arm64/boot/dts/ti/k3-am642-evm.dts | 20 ++++++++++++++++++++ 1 file changed, 20 insertions(+) diff --git a/arch/arm64/boot/dts/ti/k3-am642-evm.dts b/arch/arm64/boot/dts/ti/k3-am642-evm.dts index 39feea78a084..6456cc6d739b 100644 --- a/arch/arm64/boot/dts/ti/k3-am642-evm.dts +++ b/arch/arm64/boot/dts/ti/k3-am642-evm.dts @@ -233,6 +233,13 @@ >; }; + main_i2c0_pins_default: main-i2c0-pins-default { + pinctrl-single,pins = < + AM64X_IOPAD(0x0260, PIN_INPUT_PULLUP, 0) /* (A18) I2C0_SCL */ + AM64X_IOPAD(0x0264, PIN_INPUT_PULLUP, 0) /* (B18) I2C0_SDA */ + >; + }; + main_i2c1_pins_default: main-i2c1-pins-default { pinctrl-single,pins = < AM64X_IOPAD(0x0268, PIN_INPUT_PULLUP, 0) /* (C18) I2C1_SCL */ @@ -335,6 +342,19 @@ status = "reserved"; }; +&main_i2c0 { + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&main_i2c0_pins_default>; + clock-frequency = <400000>; + + eeprom@50 { + /* AT24CM01 */ + compatible = "atmel,24c1024"; + reg = <0x50>; + }; +}; + &main_i2c1 { status = "okay"; pinctrl-names = "default"; -- cgit From e3e1d9ab65ebbd95907b6951637cd6809c69afc7 Mon Sep 17 00:00:00 2001 From: Nishanth Menon Date: Fri, 14 Apr 2023 02:33:25 -0500 Subject: arm64: dts: ti: k3-am642-evm: Describe main_uart1 pins Describe the main_uart1 pins even though it is a reserved node for hardware complete description. This is used by other users of device tree to help configure the SoC per board requirements. Signed-off-by: Nishanth Menon Reviewed-by: Roger Quadros Link: https://lore.kernel.org/r/20230414073328.381336-8-nm@ti.com Signed-off-by: Vignesh Raghavendra --- arch/arm64/boot/dts/ti/k3-am642-evm.dts | 11 +++++++++++ 1 file changed, 11 insertions(+) diff --git a/arch/arm64/boot/dts/ti/k3-am642-evm.dts b/arch/arm64/boot/dts/ti/k3-am642-evm.dts index 6456cc6d739b..a1ed102a69f1 100644 --- a/arch/arm64/boot/dts/ti/k3-am642-evm.dts +++ b/arch/arm64/boot/dts/ti/k3-am642-evm.dts @@ -215,6 +215,15 @@ >; }; + main_uart1_pins_default: main-uart1-pins-default { + pinctrl-single,pins = < + AM64X_IOPAD(0x0248, PIN_INPUT, 0) /* (D16) UART1_CTSn */ + AM64X_IOPAD(0x024c, PIN_OUTPUT, 0) /* (E16) UART1_RTSn */ + AM64X_IOPAD(0x0240, PIN_INPUT, 0) /* (E15) UART1_RXD */ + AM64X_IOPAD(0x0244, PIN_OUTPUT, 0) /* (E14) UART1_TXD */ + >; + }; + main_uart0_pins_default: main-uart0-pins-default { pinctrl-single,pins = < AM64X_IOPAD(0x0238, PIN_INPUT, 0) /* (B16) UART0_CTSn */ @@ -340,6 +349,8 @@ /* main_uart1 is reserved for firmware usage */ &main_uart1 { status = "reserved"; + pinctrl-names = "default"; + pinctrl-0 = <&main_uart1_pins_default>; }; &main_i2c0 { -- cgit From 61ee5572075dfc16b480103763091b603cb06aa1 Mon Sep 17 00:00:00 2001 From: Nishanth Menon Date: Fri, 14 Apr 2023 02:33:26 -0500 Subject: arm64: dts: ti: k3-am642-evm: Rename regulator node name Rename the regulator node names to the standard regulator-0.. numbers. Signed-off-by: Nishanth Menon Reviewed-by: Roger Quadros Link: https://lore.kernel.org/r/20230414073328.381336-9-nm@ti.com Signed-off-by: Vignesh Raghavendra --- arch/arm64/boot/dts/ti/k3-am642-evm.dts | 10 +++++----- 1 file changed, 5 insertions(+), 5 deletions(-) diff --git a/arch/arm64/boot/dts/ti/k3-am642-evm.dts b/arch/arm64/boot/dts/ti/k3-am642-evm.dts index a1ed102a69f1..9cf181d0199f 100644 --- a/arch/arm64/boot/dts/ti/k3-am642-evm.dts +++ b/arch/arm64/boot/dts/ti/k3-am642-evm.dts @@ -94,7 +94,7 @@ }; }; - evm_12v0: fixedregulator-evm12v0 { + evm_12v0: regulator-0 { /* main DC jack */ compatible = "regulator-fixed"; regulator-name = "evm_12v0"; @@ -104,7 +104,7 @@ regulator-boot-on; }; - vsys_5v0: fixedregulator-vsys5v0 { + vsys_5v0: regulator-1 { /* output of LM5140 */ compatible = "regulator-fixed"; regulator-name = "vsys_5v0"; @@ -115,7 +115,7 @@ regulator-boot-on; }; - vsys_3v3: fixedregulator-vsys3v3 { + vsys_3v3: regulator-2 { /* output of LM5140 */ compatible = "regulator-fixed"; regulator-name = "vsys_3v3"; @@ -126,7 +126,7 @@ regulator-boot-on; }; - vdd_mmc1: fixed-regulator-sd { + vdd_mmc1: regulator-3 { /* TPS2051BD */ compatible = "regulator-fixed"; regulator-name = "vdd_mmc1"; @@ -138,7 +138,7 @@ gpio = <&exp1 6 GPIO_ACTIVE_HIGH>; }; - vddb: fixedregulator-vddb { + vddb: regulator-4 { compatible = "regulator-fixed"; regulator-name = "vddb_3v3_display"; regulator-min-microvolt = <3300000>; -- cgit From aca16cefdd25cdcd284212f840b70b07101f2548 Mon Sep 17 00:00:00 2001 From: Nishanth Menon Date: Fri, 14 Apr 2023 02:33:27 -0500 Subject: arm64: dts: ti: k3-am642-evm: Add VTT GPIO regulator for DDR Hold the DDR vtt regulator active for functionality. Signed-off-by: Nishanth Menon Reviewed-by: Roger Quadros Link: https://lore.kernel.org/r/20230414073328.381336-10-nm@ti.com Signed-off-by: Vignesh Raghavendra --- arch/arm64/boot/dts/ti/k3-am642-evm.dts | 20 ++++++++++++++++++++ 1 file changed, 20 insertions(+) diff --git a/arch/arm64/boot/dts/ti/k3-am642-evm.dts b/arch/arm64/boot/dts/ti/k3-am642-evm.dts index 9cf181d0199f..3d0b473d5252 100644 --- a/arch/arm64/boot/dts/ti/k3-am642-evm.dts +++ b/arch/arm64/boot/dts/ti/k3-am642-evm.dts @@ -148,6 +148,20 @@ regulator-boot-on; }; + vtt_supply: regulator-5 { + compatible = "regulator-fixed"; + regulator-name = "vtt"; + pinctrl-names = "default"; + pinctrl-0 = <&ddr_vtt_pins_default>; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + gpio = <&main_gpio0 12 GPIO_ACTIVE_HIGH>; + vin-supply = <&vsys_3v3>; + enable-active-high; + regulator-always-on; + regulator-boot-on; + }; + leds { compatible = "gpio-leds"; @@ -338,6 +352,12 @@ AM64X_IOPAD(0x0258, PIN_OUTPUT, 0) /* (C17) MCAN1_TX */ >; }; + + ddr_vtt_pins_default: ddr-vtt-pins-default { + pinctrl-single,pins = < + AM64X_IOPAD(0x0030, PIN_OUTPUT_PULLUP, 7) /* (L18) OSPI0_CSN1.GPIO0_12 */ + >; + }; }; &main_uart0 { -- cgit From bb3d657872215942cf87dd194904a7543fce3cc4 Mon Sep 17 00:00:00 2001 From: Nishanth Menon Date: Fri, 14 Apr 2023 02:33:28 -0500 Subject: arm64: dts: ti: k3-am642-sk|evm: Drop bootargs, add aliases Drop bootargs and add aliases based on base pinout of SK as per [1] and evm per [2]. Indices chosen attempt to maintain some level of consistency with existing aliases. While at this, drop a extra EoL. While this patch could be split, it seems trivial to add additional cleanup steps. [1] https://www.ti.com/lit/df/sprr432/sprr432.pdf [2] https://www.ti.com/lit/zip/swrr171 Signed-off-by: Nishanth Menon Reviewed-by: Roger Quadros Link: https://lore.kernel.org/r/20230414073328.381336-11-nm@ti.com Signed-off-by: Vignesh Raghavendra --- arch/arm64/boot/dts/ti/k3-am64.dtsi | 16 ---------------- arch/arm64/boot/dts/ti/k3-am642-evm.dts | 15 +++++++++++++-- arch/arm64/boot/dts/ti/k3-am642-sk.dts | 14 ++++++++++++-- 3 files changed, 25 insertions(+), 20 deletions(-) diff --git a/arch/arm64/boot/dts/ti/k3-am64.dtsi b/arch/arm64/boot/dts/ti/k3-am64.dtsi index 60fe95b48312..d6262b5a0a10 100644 --- a/arch/arm64/boot/dts/ti/k3-am64.dtsi +++ b/arch/arm64/boot/dts/ti/k3-am64.dtsi @@ -19,22 +19,6 @@ #address-cells = <2>; #size-cells = <2>; - aliases { - serial0 = &mcu_uart0; - serial1 = &mcu_uart1; - serial2 = &main_uart0; - serial3 = &main_uart1; - serial4 = &main_uart2; - serial5 = &main_uart3; - serial6 = &main_uart4; - serial7 = &main_uart5; - serial8 = &main_uart6; - ethernet0 = &cpsw_port1; - ethernet1 = &cpsw_port2; - mmc0 = &sdhci0; - mmc1 = &sdhci1; - }; - chosen { }; firmware { diff --git a/arch/arm64/boot/dts/ti/k3-am642-evm.dts b/arch/arm64/boot/dts/ti/k3-am642-evm.dts index 3d0b473d5252..3db740f78cd2 100644 --- a/arch/arm64/boot/dts/ti/k3-am642-evm.dts +++ b/arch/arm64/boot/dts/ti/k3-am642-evm.dts @@ -18,14 +18,25 @@ chosen { stdout-path = "serial2:115200n8"; - bootargs = "console=ttyS2,115200n8 earlycon=ns16550a,mmio32,0x02800000"; + }; + + aliases { + serial0 = &mcu_uart0; + serial1 = &main_uart1; + serial2 = &main_uart0; + serial3 = &main_uart3; + i2c0 = &main_i2c0; + i2c1 = &main_i2c1; + mmc0 = &sdhci0; + mmc1 = &sdhci1; + ethernet0 = &cpsw_port1; + ethernet1 = &cpsw_port2; }; memory@80000000 { device_type = "memory"; /* 2G RAM */ reg = <0x00000000 0x80000000 0x00000000 0x80000000>; - }; reserved-memory { diff --git a/arch/arm64/boot/dts/ti/k3-am642-sk.dts b/arch/arm64/boot/dts/ti/k3-am642-sk.dts index 5bd69a8e8063..003cff9a2799 100644 --- a/arch/arm64/boot/dts/ti/k3-am642-sk.dts +++ b/arch/arm64/boot/dts/ti/k3-am642-sk.dts @@ -18,14 +18,24 @@ chosen { stdout-path = "serial2:115200n8"; - bootargs = "console=ttyS2,115200n8 earlycon=ns16550a,mmio32,0x02800000"; + }; + + aliases { + serial0 = &mcu_uart0; + serial1 = &main_uart1; + serial2 = &main_uart0; + i2c0 = &main_i2c0; + i2c1 = &main_i2c1; + mmc0 = &sdhci0; + mmc1 = &sdhci1; + ethernet0 = &cpsw_port1; + ethernet1 = &cpsw_port2; }; memory@80000000 { device_type = "memory"; /* 2G RAM */ reg = <0x00000000 0x80000000 0x00000000 0x80000000>; - }; reserved-memory { -- cgit From d525ef9c7f077bfa8202b4b47ca9242ab936a1dc Mon Sep 17 00:00:00 2001 From: Nishanth Menon Date: Wed, 19 Apr 2023 09:12:18 -0500 Subject: arm64: dts: ti: k3-am62x-sk-common: Drop bootargs Drop bootargs from the dts. The console arguments are already covered in stdout-path property and earlycon is a debug property that should be enabled only when debug is desired and not as default. Link: https://lore.kernel.org/linux-arm-kernel/81134eb9-2b7d-05bc-3035-a47f020861a8@linaro.org/ Suggested-by: Krzysztof Kozlowski Acked-by: Krzysztof Kozlowski Reviewed-by: Roger Quadros Signed-off-by: Nishanth Menon Link: https://lore.kernel.org/r/20230419141222.383567-2-nm@ti.com Signed-off-by: Vignesh Raghavendra --- arch/arm64/boot/dts/ti/k3-am62x-sk-common.dtsi | 1 - 1 file changed, 1 deletion(-) diff --git a/arch/arm64/boot/dts/ti/k3-am62x-sk-common.dtsi b/arch/arm64/boot/dts/ti/k3-am62x-sk-common.dtsi index 976f8303c84f..a61e8648f189 100644 --- a/arch/arm64/boot/dts/ti/k3-am62x-sk-common.dtsi +++ b/arch/arm64/boot/dts/ti/k3-am62x-sk-common.dtsi @@ -25,7 +25,6 @@ chosen { stdout-path = "serial2:115200n8"; - bootargs = "console=ttyS2,115200n8 earlycon=ns16550a,mmio32,0x02800000"; }; memory@80000000 { -- cgit From da4159a776593f802ee211ad4823f3aed31e5375 Mon Sep 17 00:00:00 2001 From: Nishanth Menon Date: Wed, 19 Apr 2023 09:12:19 -0500 Subject: arm64: dts: ti: k3-am65*: Drop bootargs Drop bootargs from the dts. earlycon is a debug property that should be enabled only when debug is desired and not as default - see referenced link on discussion on this topic. Cc: Jan Kiszka Link: https://lore.kernel.org/linux-arm-kernel/81134eb9-2b7d-05bc-3035-a47f020861a8@linaro.org/ Suggested-by: Krzysztof Kozlowski Acked-by: Krzysztof Kozlowski Reviewed-by: Roger Quadros Signed-off-by: Nishanth Menon Acked-by: Jan Kiszka Link: https://lore.kernel.org/r/20230419141222.383567-3-nm@ti.com Signed-off-by: Vignesh Raghavendra --- arch/arm64/boot/dts/ti/k3-am65-iot2050-common.dtsi | 1 - arch/arm64/boot/dts/ti/k3-am654-base-board.dts | 1 - 2 files changed, 2 deletions(-) diff --git a/arch/arm64/boot/dts/ti/k3-am65-iot2050-common.dtsi b/arch/arm64/boot/dts/ti/k3-am65-iot2050-common.dtsi index 96ac2b476b11..7d256a1638ff 100644 --- a/arch/arm64/boot/dts/ti/k3-am65-iot2050-common.dtsi +++ b/arch/arm64/boot/dts/ti/k3-am65-iot2050-common.dtsi @@ -21,7 +21,6 @@ chosen { stdout-path = "serial3:115200n8"; - bootargs = "earlycon=ns16550a,mmio32,0x02810000"; }; reserved-memory { diff --git a/arch/arm64/boot/dts/ti/k3-am654-base-board.dts b/arch/arm64/boot/dts/ti/k3-am654-base-board.dts index 592ab2b54cb3..0d6fc89eba7a 100644 --- a/arch/arm64/boot/dts/ti/k3-am654-base-board.dts +++ b/arch/arm64/boot/dts/ti/k3-am654-base-board.dts @@ -15,7 +15,6 @@ chosen { stdout-path = "serial2:115200n8"; - bootargs = "earlycon=ns16550a,mmio32,0x02800000"; }; memory@80000000 { -- cgit From af2cda7df7769d3353170b6a72d73bc4ea703480 Mon Sep 17 00:00:00 2001 From: Nishanth Menon Date: Wed, 19 Apr 2023 09:12:20 -0500 Subject: arm64: dts: ti: k3-j721e-*: Drop bootargs Drop bootargs from the dts. The console arguments are already covered in stdout-path property and earlycon is a debug property that should be enabled only when debug is desired and not as default. Link: https://lore.kernel.org/linux-arm-kernel/81134eb9-2b7d-05bc-3035-a47f020861a8@linaro.org/ Suggested-by: Krzysztof Kozlowski Acked-by: Krzysztof Kozlowski Reviewed-by: Roger Quadros Signed-off-by: Nishanth Menon Link: https://lore.kernel.org/r/20230419141222.383567-4-nm@ti.com Signed-off-by: Vignesh Raghavendra --- arch/arm64/boot/dts/ti/k3-j721e-common-proc-board.dts | 1 - arch/arm64/boot/dts/ti/k3-j721e-sk.dts | 1 - 2 files changed, 2 deletions(-) diff --git a/arch/arm64/boot/dts/ti/k3-j721e-common-proc-board.dts b/arch/arm64/boot/dts/ti/k3-j721e-common-proc-board.dts index 7db0603125aa..c11c092c1ce0 100644 --- a/arch/arm64/boot/dts/ti/k3-j721e-common-proc-board.dts +++ b/arch/arm64/boot/dts/ti/k3-j721e-common-proc-board.dts @@ -17,7 +17,6 @@ chosen { stdout-path = "serial2:115200n8"; - bootargs = "console=ttyS2,115200n8 earlycon=ns16550a,mmio32,0x02800000"; }; gpio_keys: gpio-keys { diff --git a/arch/arm64/boot/dts/ti/k3-j721e-sk.dts b/arch/arm64/boot/dts/ti/k3-j721e-sk.dts index f650a7fd66b4..ad7b45aeed0a 100644 --- a/arch/arm64/boot/dts/ti/k3-j721e-sk.dts +++ b/arch/arm64/boot/dts/ti/k3-j721e-sk.dts @@ -18,7 +18,6 @@ chosen { stdout-path = "serial2:115200n8"; - bootargs = "console=ttyS2,115200n8 earlycon=ns16550a,mmio32,0x02800000"; }; memory@80000000 { -- cgit From f920c49f1e46a99c410e2aaf486ffb7ce3d12270 Mon Sep 17 00:00:00 2001 From: Nishanth Menon Date: Wed, 19 Apr 2023 09:12:21 -0500 Subject: arm64: dts: ti: k3-j7200-common-proc-board: Drop bootargs Drop bootargs from the dts. The console arguments are already covered in stdout-path property and earlycon is a debug property that should be enabled only when debug is desired and not as default. Link: https://lore.kernel.org/linux-arm-kernel/81134eb9-2b7d-05bc-3035-a47f020861a8@linaro.org/ Suggested-by: Krzysztof Kozlowski Acked-by: Krzysztof Kozlowski Reviewed-by: Roger Quadros Signed-off-by: Nishanth Menon Link: https://lore.kernel.org/r/20230419141222.383567-5-nm@ti.com Signed-off-by: Vignesh Raghavendra --- arch/arm64/boot/dts/ti/k3-j7200-common-proc-board.dts | 1 - 1 file changed, 1 deletion(-) diff --git a/arch/arm64/boot/dts/ti/k3-j7200-common-proc-board.dts b/arch/arm64/boot/dts/ti/k3-j7200-common-proc-board.dts index 0d39d6b8cc0c..5506341aae21 100644 --- a/arch/arm64/boot/dts/ti/k3-j7200-common-proc-board.dts +++ b/arch/arm64/boot/dts/ti/k3-j7200-common-proc-board.dts @@ -17,7 +17,6 @@ chosen { stdout-path = "serial2:115200n8"; - bootargs = "console=ttyS2,115200n8 earlycon=ns16550a,mmio32,0x02800000"; }; evm_12v0: fixedregulator-evm12v0 { -- cgit From cf82a026f54f54c241903add9b9bdbeb2a449db0 Mon Sep 17 00:00:00 2001 From: Nishanth Menon Date: Wed, 19 Apr 2023 09:12:22 -0500 Subject: arm64: dts: ti: k3-j721s2-common-proc-board: Drop bootargs Drop bootargs from the dts. The console arguments are already covered in stdout-path property and earlycon is a debug property that should be enabled only when debug is desired and not as default. Link: https://lore.kernel.org/linux-arm-kernel/81134eb9-2b7d-05bc-3035-a47f020861a8@linaro.org/ Suggested-by: Krzysztof Kozlowski Acked-by: Krzysztof Kozlowski Reviewed-by: Roger Quadros Signed-off-by: Nishanth Menon Link: https://lore.kernel.org/r/20230419141222.383567-6-nm@ti.com Signed-off-by: Vignesh Raghavendra --- arch/arm64/boot/dts/ti/k3-j721s2-common-proc-board.dts | 1 - 1 file changed, 1 deletion(-) diff --git a/arch/arm64/boot/dts/ti/k3-j721s2-common-proc-board.dts b/arch/arm64/boot/dts/ti/k3-j721s2-common-proc-board.dts index b4b9edfe2d12..1299c715f34c 100644 --- a/arch/arm64/boot/dts/ti/k3-j721s2-common-proc-board.dts +++ b/arch/arm64/boot/dts/ti/k3-j721s2-common-proc-board.dts @@ -16,7 +16,6 @@ chosen { stdout-path = "serial2:115200n8"; - bootargs = "console=ttyS2,115200n8 earlycon=ns16550a,mmio32,2880000"; }; aliases { -- cgit From 68dd81a75192248a2c29650d21da495069c74ffa Mon Sep 17 00:00:00 2001 From: Nishanth Menon Date: Mon, 17 Apr 2023 20:27:15 -0500 Subject: arm64: dts: ti: k3-am62a: Add general purpose timers Similar to commit 3308a31c507c ("arm64: dts: ti: k3-am62: Add general purpose timers for am62"), there are 12 general purpose timers on am62a7 split between 8 in main and 4 in mcu domains. The 4 in mcu domain do not have interrupts that are routable to a53. We configure the timers with the 25 MHz input clock by default as the 32.768 kHz clock may not be wired on the device. We leave the MCU domain timers clock mux unconfigured, and mark the MCU domain timers reserved. The MCU domain timers are likely reserved by the software for the ESM module. Signed-off-by: Nishanth Menon Reviewed-by: Tony Lindgren Reviewed-by: Roger Quadros Link: https://lore.kernel.org/r/20230418012717.1230882-2-nm@ti.com Signed-off-by: Vignesh Raghavendra --- arch/arm64/boot/dts/ti/k3-am62a-main.dtsi | 96 +++++++++++++++++++++++++++++++ arch/arm64/boot/dts/ti/k3-am62a-mcu.dtsi | 45 +++++++++++++++ 2 files changed, 141 insertions(+) diff --git a/arch/arm64/boot/dts/ti/k3-am62a-main.dtsi b/arch/arm64/boot/dts/ti/k3-am62a-main.dtsi index 393a1a40b68b..59d1199e43c9 100644 --- a/arch/arm64/boot/dts/ti/k3-am62a-main.dtsi +++ b/arch/arm64/boot/dts/ti/k3-am62a-main.dtsi @@ -177,6 +177,102 @@ pinctrl-single,function-mask = <0xffffffff>; }; + main_timer0: timer@2400000 { + compatible = "ti,am654-timer"; + reg = <0x00 0x2400000 0x00 0x400>; + interrupts = ; + clocks = <&k3_clks 36 2>; + clock-names = "fck"; + assigned-clocks = <&k3_clks 36 2>; + assigned-clock-parents = <&k3_clks 36 3>; + power-domains = <&k3_pds 36 TI_SCI_PD_EXCLUSIVE>; + ti,timer-pwm; + }; + + main_timer1: timer@2410000 { + compatible = "ti,am654-timer"; + reg = <0x00 0x2410000 0x00 0x400>; + interrupts = ; + clocks = <&k3_clks 37 2>; + clock-names = "fck"; + assigned-clocks = <&k3_clks 37 2>; + assigned-clock-parents = <&k3_clks 37 3>; + power-domains = <&k3_pds 37 TI_SCI_PD_EXCLUSIVE>; + ti,timer-pwm; + }; + + main_timer2: timer@2420000 { + compatible = "ti,am654-timer"; + reg = <0x00 0x2420000 0x00 0x400>; + interrupts = ; + clocks = <&k3_clks 38 2>; + clock-names = "fck"; + assigned-clocks = <&k3_clks 38 2>; + assigned-clock-parents = <&k3_clks 38 3>; + power-domains = <&k3_pds 38 TI_SCI_PD_EXCLUSIVE>; + ti,timer-pwm; + }; + + main_timer3: timer@2430000 { + compatible = "ti,am654-timer"; + reg = <0x00 0x2430000 0x00 0x400>; + interrupts = ; + clocks = <&k3_clks 39 2>; + clock-names = "fck"; + assigned-clocks = <&k3_clks 39 2>; + assigned-clock-parents = <&k3_clks 39 3>; + power-domains = <&k3_pds 39 TI_SCI_PD_EXCLUSIVE>; + ti,timer-pwm; + }; + + main_timer4: timer@2440000 { + compatible = "ti,am654-timer"; + reg = <0x00 0x2440000 0x00 0x400>; + interrupts = ; + clocks = <&k3_clks 40 2>; + clock-names = "fck"; + assigned-clocks = <&k3_clks 40 2>; + assigned-clock-parents = <&k3_clks 40 3>; + power-domains = <&k3_pds 40 TI_SCI_PD_EXCLUSIVE>; + ti,timer-pwm; + }; + + main_timer5: timer@2450000 { + compatible = "ti,am654-timer"; + reg = <0x00 0x2450000 0x00 0x400>; + interrupts = ; + clocks = <&k3_clks 41 2>; + clock-names = "fck"; + assigned-clocks = <&k3_clks 41 2>; + assigned-clock-parents = <&k3_clks 41 3>; + power-domains = <&k3_pds 41 TI_SCI_PD_EXCLUSIVE>; + ti,timer-pwm; + }; + + main_timer6: timer@2460000 { + compatible = "ti,am654-timer"; + reg = <0x00 0x2460000 0x00 0x400>; + interrupts = ; + clocks = <&k3_clks 42 2>; + clock-names = "fck"; + assigned-clocks = <&k3_clks 42 2>; + assigned-clock-parents = <&k3_clks 42 3>; + power-domains = <&k3_pds 42 TI_SCI_PD_EXCLUSIVE>; + ti,timer-pwm; + }; + + main_timer7: timer@2470000 { + compatible = "ti,am654-timer"; + reg = <0x00 0x2470000 0x00 0x400>; + interrupts = ; + clocks = <&k3_clks 43 2>; + clock-names = "fck"; + assigned-clocks = <&k3_clks 43 2>; + assigned-clock-parents = <&k3_clks 43 3>; + power-domains = <&k3_pds 43 TI_SCI_PD_EXCLUSIVE>; + ti,timer-pwm; + }; + main_uart0: serial@2800000 { compatible = "ti,am64-uart", "ti,am654-uart"; reg = <0x00 0x02800000 0x00 0x100>; diff --git a/arch/arm64/boot/dts/ti/k3-am62a-mcu.dtsi b/arch/arm64/boot/dts/ti/k3-am62a-mcu.dtsi index 2bb813e784a2..50c94a55fe85 100644 --- a/arch/arm64/boot/dts/ti/k3-am62a-mcu.dtsi +++ b/arch/arm64/boot/dts/ti/k3-am62a-mcu.dtsi @@ -15,6 +15,51 @@ status = "disabled"; }; + /* + * The MCU domain timer interrupts are routed only to the ESM module, + * and not currently available for Linux. The MCU domain timers are + * of limited use without interrupts, and likely reserved by the ESM. + */ + mcu_timer0: timer@4800000 { + compatible = "ti,am654-timer"; + reg = <0x00 0x4800000 0x00 0x400>; + clocks = <&k3_clks 35 2>; + clock-names = "fck"; + power-domains = <&k3_pds 35 TI_SCI_PD_EXCLUSIVE>; + ti,timer-pwm; + status = "reserved"; + }; + + mcu_timer1: timer@4810000 { + compatible = "ti,am654-timer"; + reg = <0x00 0x4810000 0x00 0x400>; + clocks = <&k3_clks 48 2>; + clock-names = "fck"; + power-domains = <&k3_pds 48 TI_SCI_PD_EXCLUSIVE>; + ti,timer-pwm; + status = "reserved"; + }; + + mcu_timer2: timer@4820000 { + compatible = "ti,am654-timer"; + reg = <0x00 0x4820000 0x00 0x400>; + clocks = <&k3_clks 49 2>; + clock-names = "fck"; + power-domains = <&k3_pds 49 TI_SCI_PD_EXCLUSIVE>; + ti,timer-pwm; + status = "reserved"; + }; + + mcu_timer3: timer@4830000 { + compatible = "ti,am654-timer"; + reg = <0x00 0x4830000 0x00 0x400>; + clocks = <&k3_clks 50 2>; + clock-names = "fck"; + power-domains = <&k3_pds 50 TI_SCI_PD_EXCLUSIVE>; + ti,timer-pwm; + status = "reserved"; + }; + mcu_uart0: serial@4a00000 { compatible = "ti,am64-uart", "ti,am654-uart"; reg = <0x00 0x04a00000 0x00 0x100>; -- cgit From 804702e4c2aa5eae4611e9389833631a6b22e913 Mon Sep 17 00:00:00 2001 From: Nishanth Menon Date: Mon, 17 Apr 2023 20:27:16 -0500 Subject: arm64: dts: ti: k3-am62a: Add watchdog nodes Add nodes for watchdogs: - 5 in main domain - 1 in MCU domain - 1 in wakeup domain Signed-off-by: Nishanth Menon Reviewed-by: Tony Lindgren Reviewed-by: Roger Quadros Link: https://lore.kernel.org/r/20230418012717.1230882-3-nm@ti.com Signed-off-by: Vignesh Raghavendra --- arch/arm64/boot/dts/ti/k3-am62a-main.dtsi | 45 +++++++++++++++++++++++++++++ arch/arm64/boot/dts/ti/k3-am62a-mcu.dtsi | 11 +++++++ arch/arm64/boot/dts/ti/k3-am62a-wakeup.dtsi | 11 +++++++ 3 files changed, 67 insertions(+) diff --git a/arch/arm64/boot/dts/ti/k3-am62a-main.dtsi b/arch/arm64/boot/dts/ti/k3-am62a-main.dtsi index 59d1199e43c9..e43e64451bc1 100644 --- a/arch/arm64/boot/dts/ti/k3-am62a-main.dtsi +++ b/arch/arm64/boot/dts/ti/k3-am62a-main.dtsi @@ -697,6 +697,51 @@ status = "disabled"; }; + main_rti0: watchdog@e000000 { + compatible = "ti,j7-rti-wdt"; + reg = <0x00 0x0e000000 0x00 0x100>; + clocks = <&k3_clks 125 0>; + power-domains = <&k3_pds 125 TI_SCI_PD_EXCLUSIVE>; + assigned-clocks = <&k3_clks 125 0>; + assigned-clock-parents = <&k3_clks 125 2>; + }; + + main_rti1: watchdog@e010000 { + compatible = "ti,j7-rti-wdt"; + reg = <0x00 0x0e010000 0x00 0x100>; + clocks = <&k3_clks 126 0>; + power-domains = <&k3_pds 126 TI_SCI_PD_EXCLUSIVE>; + assigned-clocks = <&k3_clks 126 0>; + assigned-clock-parents = <&k3_clks 126 2>; + }; + + main_rti2: watchdog@e020000 { + compatible = "ti,j7-rti-wdt"; + reg = <0x00 0x0e020000 0x00 0x100>; + clocks = <&k3_clks 127 0>; + power-domains = <&k3_pds 127 TI_SCI_PD_EXCLUSIVE>; + assigned-clocks = <&k3_clks 127 0>; + assigned-clock-parents = <&k3_clks 127 2>; + }; + + main_rti3: watchdog@e030000 { + compatible = "ti,j7-rti-wdt"; + reg = <0x00 0x0e030000 0x00 0x100>; + clocks = <&k3_clks 128 0>; + power-domains = <&k3_pds 128 TI_SCI_PD_EXCLUSIVE>; + assigned-clocks = <&k3_clks 128 0>; + assigned-clock-parents = <&k3_clks 128 2>; + }; + + main_rti4: watchdog@e040000 { + compatible = "ti,j7-rti-wdt"; + reg = <0x00 0x0e040000 0x00 0x100>; + clocks = <&k3_clks 205 0>; + power-domains = <&k3_pds 205 TI_SCI_PD_EXCLUSIVE>; + assigned-clocks = <&k3_clks 205 0>; + assigned-clock-parents = <&k3_clks 205 2>; + }; + epwm0: pwm@23000000 { compatible = "ti,am64-epwm", "ti,am3352-ehrpwm"; #pwm-cells = <3>; diff --git a/arch/arm64/boot/dts/ti/k3-am62a-mcu.dtsi b/arch/arm64/boot/dts/ti/k3-am62a-mcu.dtsi index 50c94a55fe85..04599762c2b7 100644 --- a/arch/arm64/boot/dts/ti/k3-am62a-mcu.dtsi +++ b/arch/arm64/boot/dts/ti/k3-am62a-mcu.dtsi @@ -132,4 +132,15 @@ clock-names = "gpio"; status = "disabled"; }; + + mcu_rti0: watchdog@4880000 { + compatible = "ti,j7-rti-wdt"; + reg = <0x00 0x04880000 0x00 0x100>; + clocks = <&k3_clks 131 0>; + power-domains = <&k3_pds 131 TI_SCI_PD_EXCLUSIVE>; + assigned-clocks = <&k3_clks 131 0>; + assigned-clock-parents = <&k3_clks 131 2>; + /* Tightly coupled to M4F */ + status = "reserved"; + }; }; diff --git a/arch/arm64/boot/dts/ti/k3-am62a-wakeup.dtsi b/arch/arm64/boot/dts/ti/k3-am62a-wakeup.dtsi index 81d984414fd4..d848eb24b552 100644 --- a/arch/arm64/boot/dts/ti/k3-am62a-wakeup.dtsi +++ b/arch/arm64/boot/dts/ti/k3-am62a-wakeup.dtsi @@ -51,4 +51,15 @@ wakeup-source; status = "disabled"; }; + + wkup_rti0: watchdog@2b000000 { + compatible = "ti,j7-rti-wdt"; + reg = <0x00 0x2b000000 0x00 0x100>; + clocks = <&k3_clks 132 0>; + power-domains = <&k3_pds 132 TI_SCI_PD_EXCLUSIVE>; + assigned-clocks = <&k3_clks 132 0>; + assigned-clock-parents = <&k3_clks 132 2>; + /* Used by DM firmware */ + status = "reserved"; + }; }; -- cgit From 3ae28642a110485f71091f0a631492e78b396b2b Mon Sep 17 00:00:00 2001 From: Nishanth Menon Date: Wed, 19 Apr 2023 17:59:07 -0500 Subject: arm64: dts: ti: k3-am654-base-board: Add missing pinmux wkup_uart, mcu_uart and mcu_i2c Many of the definitions depend on pinmux done by the bootloader. Be explicit about the pinmux for functionality and completeness. Signed-off-by: Nishanth Menon Reviewed-by: Kamlesh Gurudasani Link: https://lore.kernel.org/r/20230419225913.663448-2-nm@ti.com Signed-off-by: Vignesh Raghavendra --- arch/arm64/boot/dts/ti/k3-am654-base-board.dts | 34 ++++++++++++++++++++++++-- 1 file changed, 32 insertions(+), 2 deletions(-) diff --git a/arch/arm64/boot/dts/ti/k3-am654-base-board.dts b/arch/arm64/boot/dts/ti/k3-am654-base-board.dts index 0d6fc89eba7a..20d1eeadd3f7 100644 --- a/arch/arm64/boot/dts/ti/k3-am654-base-board.dts +++ b/arch/arm64/boot/dts/ti/k3-am654-base-board.dts @@ -119,6 +119,15 @@ }; &wkup_pmx0 { + wkup_uart0_pins_default: wkup-uart0-pins-default { + pinctrl-single,pins = < + AM65X_WKUP_IOPAD(0x00a0, PIN_INPUT, 0) /* (AB1) WKUP_UART0_RXD */ + AM65X_WKUP_IOPAD(0x00a4, PIN_OUTPUT, 0) /* (AB5) WKUP_UART0_TXD */ + AM65X_WKUP_IOPAD(0x00c8, PIN_INPUT, 1) /* (AC2) WKUP_GPIO0_6.WKUP_UART0_CTSn */ + AM65X_WKUP_IOPAD(0x00cc, PIN_OUTPUT, 1) /* (AC1) WKUP_GPIO0_7.WKUP_UART0_RTSn */ + >; + }; + wkup_i2c0_pins_default: wkup-i2c0-pins-default { pinctrl-single,pins = < AM65X_WKUP_IOPAD(0x00e0, PIN_INPUT, 0) /* (AC7) WKUP_I2C0_SCL */ @@ -155,6 +164,15 @@ >; }; + mcu_uart0_pins_default: mcu-uart0-pins-default { + pinctrl-single,pins = < + AM65X_WKUP_IOPAD(0x0044, PIN_INPUT, 4) /* (P4) MCU_OSPI1_D1.MCU_UART0_RXD */ + AM65X_WKUP_IOPAD(0x0048, PIN_OUTPUT, 4) /* (P5) MCU_OSPI1_D2.MCU_UART0_TXD */ + AM65X_WKUP_IOPAD(0x004C, PIN_INPUT, 4) /* (P1) MCU_OSPI1_D3.MCU_UART0_CTSn */ + AM65X_WKUP_IOPAD(0x0054, PIN_OUTPUT, 4) /* (N3) MCU_OSPI1_CSn1.MCU_UART0_RTSn */ + >; + }; + mcu_cpsw_pins_default: mcu-cpsw-pins-default { pinctrl-single,pins = < AM65X_WKUP_IOPAD(0x0058, PIN_OUTPUT, 0) /* (N4) MCU_RGMII1_TX_CTL */ @@ -178,6 +196,13 @@ AM65X_WKUP_IOPAD(0x0088, PIN_INPUT, 0) /* (L4) MCU_MDIO0_MDIO */ >; }; + + mcu_i2c0_pins_default: mcu-i2c0-pins-default { + pinctrl-single,pins = < + AM65X_WKUP_IOPAD(0x00e8, PIN_INPUT, 0) /* (AD8) MCU_I2C0_SCL */ + AM65X_WKUP_IOPAD(0x00ec, PIN_INPUT, 0) /* (AD7) MCU_I2C0_SDA */ + >; + }; }; &main_pmx0 { @@ -268,11 +293,14 @@ &wkup_uart0 { /* Wakeup UART is used by System firmware */ status = "reserved"; + pinctrl-names = "default"; + pinctrl-0 = <&wkup_uart0_pins_default>; }; &mcu_uart0 { status = "okay"; - /* Default pinmux */ + pinctrl-names = "default"; + pinctrl-0 = <&mcu_uart0_pins_default>; }; &main_uart0 { @@ -304,7 +332,9 @@ &mcu_i2c0 { status = "okay"; - /* Default pinmux */ + pinctrl-names = "default"; + pinctrl-0 = <&mcu_i2c0_pins_default>; + clock-frequency = <400000>; }; &main_i2c0 { -- cgit From ec1b54824f022a7e65d858abbe74f5d7effc9817 Mon Sep 17 00:00:00 2001 From: Nishanth Menon Date: Wed, 19 Apr 2023 17:59:08 -0500 Subject: arm64: dts: ti: k3-am654-base-board: Rename regulator node name Rename the regulator node names to the standard regulator-0.. numbers. Signed-off-by: Nishanth Menon Reviewed-by: Kamlesh Gurudasani Link: https://lore.kernel.org/r/20230419225913.663448-3-nm@ti.com Signed-off-by: Vignesh Raghavendra --- arch/arm64/boot/dts/ti/k3-am654-base-board.dts | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/arch/arm64/boot/dts/ti/k3-am654-base-board.dts b/arch/arm64/boot/dts/ti/k3-am654-base-board.dts index 20d1eeadd3f7..01c0f06b599f 100644 --- a/arch/arm64/boot/dts/ti/k3-am654-base-board.dts +++ b/arch/arm64/boot/dts/ti/k3-am654-base-board.dts @@ -85,7 +85,7 @@ }; }; - evm_12v0: fixedregulator-evm12v0 { + evm_12v0: regulator-0 { /* main supply */ compatible = "regulator-fixed"; regulator-name = "evm_12v0"; @@ -95,7 +95,7 @@ regulator-boot-on; }; - vcc3v3_io: fixedregulator-vcc3v3io { + vcc3v3_io: regulator-1 { /* Output of TPS54334 */ compatible = "regulator-fixed"; regulator-name = "vcc3v3_io"; @@ -106,7 +106,7 @@ vin-supply = <&evm_12v0>; }; - vdd_mmc1_sd: fixedregulator-sd { + vdd_mmc1_sd: regulator-2 { compatible = "regulator-fixed"; regulator-name = "vdd_mmc1_sd"; regulator-min-microvolt = <3300000>; -- cgit From 5292f504827c56406975b463eda1270d144cf06f Mon Sep 17 00:00:00 2001 From: Nishanth Menon Date: Wed, 19 Apr 2023 17:59:09 -0500 Subject: arm64: dts: ti: k3-am654-base-board: Add VTT GPIO regulator for DDR Hold the DDR vtt regulator active for functionality. Signed-off-by: Nishanth Menon Reviewed-by: Kamlesh Gurudasani Link: https://lore.kernel.org/r/20230419225913.663448-4-nm@ti.com Signed-off-by: Vignesh Raghavendra --- arch/arm64/boot/dts/ti/k3-am654-base-board.dts | 20 ++++++++++++++++++++ 1 file changed, 20 insertions(+) diff --git a/arch/arm64/boot/dts/ti/k3-am654-base-board.dts b/arch/arm64/boot/dts/ti/k3-am654-base-board.dts index 01c0f06b599f..30bb1c90d425 100644 --- a/arch/arm64/boot/dts/ti/k3-am654-base-board.dts +++ b/arch/arm64/boot/dts/ti/k3-am654-base-board.dts @@ -116,6 +116,20 @@ vin-supply = <&vcc3v3_io>; gpio = <&pca9554 4 GPIO_ACTIVE_HIGH>; }; + + vtt_supply: regulator-3 { + compatible = "regulator-fixed"; + regulator-name = "vtt"; + pinctrl-names = "default"; + pinctrl-0 = <&ddr_vtt_pins_default>; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + enable-active-high; + regulator-always-on; + regulator-boot-on; + vin-supply = <&vcc3v3_io>; + gpio = <&wkup_gpio0 28 GPIO_ACTIVE_HIGH>; + }; }; &wkup_pmx0 { @@ -128,6 +142,12 @@ >; }; + ddr_vtt_pins_default: ddr-vtt-pins-default { + pinctrl-single,pins = < + AM65X_WKUP_IOPAD(0x0040, PIN_OUTPUT_PULLUP, 7) /* WKUP_GPIO0_28 */ + >; + }; + wkup_i2c0_pins_default: wkup-i2c0-pins-default { pinctrl-single,pins = < AM65X_WKUP_IOPAD(0x00e0, PIN_INPUT, 0) /* (AC7) WKUP_I2C0_SCL */ -- cgit From 282621ed6e790ccf7288c4c0aadbb34f1fe25c11 Mon Sep 17 00:00:00 2001 From: Nishanth Menon Date: Wed, 19 Apr 2023 17:59:10 -0500 Subject: arm64: dts: ti: k3-am654-base-board: Add missing PMIC Add the missing vdd_mpu PMIC. Signed-off-by: Nishanth Menon Reviewed-by: Kamlesh Gurudasani Link: https://lore.kernel.org/r/20230419225913.663448-5-nm@ti.com Signed-off-by: Vignesh Raghavendra --- arch/arm64/boot/dts/ti/k3-am654-base-board.dts | 13 +++++++++++++ 1 file changed, 13 insertions(+) diff --git a/arch/arm64/boot/dts/ti/k3-am654-base-board.dts b/arch/arm64/boot/dts/ti/k3-am654-base-board.dts index 30bb1c90d425..91471f015f96 100644 --- a/arch/arm64/boot/dts/ti/k3-am654-base-board.dts +++ b/arch/arm64/boot/dts/ti/k3-am654-base-board.dts @@ -336,6 +336,19 @@ pinctrl-0 = <&wkup_i2c0_pins_default>; clock-frequency = <400000>; + vdd_mpu: regulator@60 { + compatible = "ti,tps62363"; + reg = <0x60>; + regulator-name = "VDD_MPU"; + regulator-min-microvolt = <500000>; + regulator-max-microvolt = <1770000>; + regulator-always-on; + regulator-boot-on; + ti,vsel0-state-high; + ti,vsel1-state-high; + ti,enable-vout-discharge; + }; + pca9554: gpio@39 { compatible = "nxp,pca9554"; reg = <0x39>; -- cgit From 895e2f4f9852e54c0e6d16ddea9882b9b2065eae Mon Sep 17 00:00:00 2001 From: Nishanth Menon Date: Wed, 19 Apr 2023 17:59:11 -0500 Subject: arm64: dts: ti: k3-am654-base-board: Add board detect eeprom Enable AT24CM01 on the base board using the corresponding compatible. Signed-off-by: Nishanth Menon Reviewed-by: Kamlesh Gurudasani Link: https://lore.kernel.org/r/20230419225913.663448-6-nm@ti.com Signed-off-by: Vignesh Raghavendra --- arch/arm64/boot/dts/ti/k3-am654-base-board.dts | 6 ++++++ 1 file changed, 6 insertions(+) diff --git a/arch/arm64/boot/dts/ti/k3-am654-base-board.dts b/arch/arm64/boot/dts/ti/k3-am654-base-board.dts index 91471f015f96..92915870024d 100644 --- a/arch/arm64/boot/dts/ti/k3-am654-base-board.dts +++ b/arch/arm64/boot/dts/ti/k3-am654-base-board.dts @@ -336,6 +336,12 @@ pinctrl-0 = <&wkup_i2c0_pins_default>; clock-frequency = <400000>; + eeprom@50 { + /* AT24CM01 */ + compatible = "atmel,24c1024"; + reg = <0x50>; + }; + vdd_mpu: regulator@60 { compatible = "ti,tps62363"; reg = <0x60>; -- cgit From 692e8888a84357232574caba74f60ceea7364016 Mon Sep 17 00:00:00 2001 From: Nishanth Menon Date: Wed, 19 Apr 2023 17:59:12 -0500 Subject: arm64: dts: ti: k3-am654-base-board: Add aliases Introduce aliases compatible with the base definition, but focussed on the interfaces that have been exposed on the platform. Signed-off-by: Nishanth Menon Reviewed-by: Kamlesh Gurudasani Link: https://lore.kernel.org/r/20230419225913.663448-7-nm@ti.com Signed-off-by: Vignesh Raghavendra --- arch/arm64/boot/dts/ti/k3-am654-base-board.dts | 14 ++++++++++++++ 1 file changed, 14 insertions(+) diff --git a/arch/arm64/boot/dts/ti/k3-am654-base-board.dts b/arch/arm64/boot/dts/ti/k3-am654-base-board.dts index 92915870024d..0a018bcf5735 100644 --- a/arch/arm64/boot/dts/ti/k3-am654-base-board.dts +++ b/arch/arm64/boot/dts/ti/k3-am654-base-board.dts @@ -13,6 +13,20 @@ compatible = "ti,am654-evm", "ti,am654"; model = "Texas Instruments AM654 Base Board"; + aliases { + serial0 = &wkup_uart0; + serial1 = &mcu_uart0; + serial2 = &main_uart0; + i2c0 = &wkup_i2c0; + i2c1 = &mcu_i2c0; + i2c2 = &main_i2c0; + i2c3 = &main_i2c1; + i2c4 = &main_i2c2; + ethernet0 = &cpsw_port1; + mmc0 = &sdhci0; + mmc1 = &sdhci1; + }; + chosen { stdout-path = "serial2:115200n8"; }; -- cgit From ffc449e016e269ce4d19e648bae584f8e5afd59f Mon Sep 17 00:00:00 2001 From: Nishanth Menon Date: Wed, 19 Apr 2023 17:59:13 -0500 Subject: arm64: dts: ti: k3-am65: Drop aliases iot boards have always defined their own aliases and with the base-board defining it's own aliases, there are no pending boards depending on common aliases defined in SoC level. aliases are meant to be defined appropriately based on the exposed interfaces at a board level, drop the aliases defined at SoC level. Signed-off-by: Nishanth Menon Reviewed-by: Kamlesh Gurudasani Link: https://lore.kernel.org/r/20230419225913.663448-8-nm@ti.com Signed-off-by: Vignesh Raghavendra --- arch/arm64/boot/dts/ti/k3-am65.dtsi | 17 ----------------- 1 file changed, 17 deletions(-) diff --git a/arch/arm64/boot/dts/ti/k3-am65.dtsi b/arch/arm64/boot/dts/ti/k3-am65.dtsi index 3093ef6b9b23..4d7b6155a76b 100644 --- a/arch/arm64/boot/dts/ti/k3-am65.dtsi +++ b/arch/arm64/boot/dts/ti/k3-am65.dtsi @@ -19,23 +19,6 @@ #address-cells = <2>; #size-cells = <2>; - aliases { - serial0 = &wkup_uart0; - serial1 = &mcu_uart0; - serial2 = &main_uart0; - serial3 = &main_uart1; - serial4 = &main_uart2; - i2c0 = &wkup_i2c0; - i2c1 = &mcu_i2c0; - i2c2 = &main_i2c0; - i2c3 = &main_i2c1; - i2c4 = &main_i2c2; - i2c5 = &main_i2c3; - ethernet0 = &cpsw_port1; - mmc0 = &sdhci0; - mmc1 = &sdhci1; - }; - chosen { }; firmware { -- cgit From 9b8c6da0b5850bd9645d0f9b4a892e69cb7ec662 Mon Sep 17 00:00:00 2001 From: Krzysztof Kozlowski Date: Sat, 22 Apr 2023 00:31:43 +0200 Subject: arm64: dts: ti: add missing cache properties As all level 2 and level 3 caches are unified, add required cache-unified properties to fix warnings like: k3-am6528-iot2050-basic-pg2.dtb: l3-cache0: 'cache-unified' is a required property Signed-off-by: Krzysztof Kozlowski Acked-by: Nishanth Menon Link: https://lore.kernel.org/r/20230421223143.115099-1-krzysztof.kozlowski@linaro.org Signed-off-by: Vignesh Raghavendra --- arch/arm64/boot/dts/ti/k3-am654.dtsi | 1 + arch/arm64/boot/dts/ti/k3-j7200.dtsi | 1 + arch/arm64/boot/dts/ti/k3-j721e.dtsi | 1 + arch/arm64/boot/dts/ti/k3-j721s2.dtsi | 1 + 4 files changed, 4 insertions(+) diff --git a/arch/arm64/boot/dts/ti/k3-am654.dtsi b/arch/arm64/boot/dts/ti/k3-am654.dtsi index 4cc329b271ac..888567b921f0 100644 --- a/arch/arm64/boot/dts/ti/k3-am654.dtsi +++ b/arch/arm64/boot/dts/ti/k3-am654.dtsi @@ -113,6 +113,7 @@ msmc_l3: l3-cache0 { compatible = "cache"; cache-level = <3>; + cache-unified; }; thermal_zones: thermal-zones { diff --git a/arch/arm64/boot/dts/ti/k3-j7200.dtsi b/arch/arm64/boot/dts/ti/k3-j7200.dtsi index bbe380c72a7e..f1836ec8e934 100644 --- a/arch/arm64/boot/dts/ti/k3-j7200.dtsi +++ b/arch/arm64/boot/dts/ti/k3-j7200.dtsi @@ -95,6 +95,7 @@ msmc_l3: l3-cache0 { compatible = "cache"; cache-level = <3>; + cache-unified; }; firmware { diff --git a/arch/arm64/boot/dts/ti/k3-j721e.dtsi b/arch/arm64/boot/dts/ti/k3-j721e.dtsi index b912143b6a11..c577f3739407 100644 --- a/arch/arm64/boot/dts/ti/k3-j721e.dtsi +++ b/arch/arm64/boot/dts/ti/k3-j721e.dtsi @@ -97,6 +97,7 @@ msmc_l3: l3-cache0 { compatible = "cache"; cache-level = <3>; + cache-unified; }; firmware { diff --git a/arch/arm64/boot/dts/ti/k3-j721s2.dtsi b/arch/arm64/boot/dts/ti/k3-j721s2.dtsi index 376924726f1f..f3db277628cd 100644 --- a/arch/arm64/boot/dts/ti/k3-j721s2.dtsi +++ b/arch/arm64/boot/dts/ti/k3-j721s2.dtsi @@ -81,6 +81,7 @@ msmc_l3: l3-cache0 { compatible = "cache"; cache-level = <3>; + cache-unified; }; firmware { -- cgit From 13fdc081fbe997fbd6addc8eafc240655c2fc7e8 Mon Sep 17 00:00:00 2001 From: Nishanth Menon Date: Mon, 24 Apr 2023 09:49:43 -0500 Subject: arm64: dts: ti: k3-am65-main: Remove "syscon" nodes added for pcieX_ctrl Remove "syscon" nodes added for pcieX_ctrl and have the PCIe node point to the parent with an offset argument. This change is as discussed in [1]. [1] http://lore.kernel.org/r/CAL_JsqKiUcO76bo1GoepWM1TusJWoty_BRy2hFSgtEVMqtrvvQ@mail.gmail.com Signed-off-by: Nishanth Menon Link: https://lore.kernel.org/r/20230424144949.244135-2-nm@ti.com Signed-off-by: Vignesh Raghavendra --- arch/arm64/boot/dts/ti/k3-am65-main.dtsi | 27 ++++++--------------------- 1 file changed, 6 insertions(+), 21 deletions(-) diff --git a/arch/arm64/boot/dts/ti/k3-am65-main.dtsi b/arch/arm64/boot/dts/ti/k3-am65-main.dtsi index 1adba2f2c153..bc63d10bad5a 100644 --- a/arch/arm64/boot/dts/ti/k3-am65-main.dtsi +++ b/arch/arm64/boot/dts/ti/k3-am65-main.dtsi @@ -481,21 +481,6 @@ #size-cells = <1>; ranges = <0x0 0x0 0x00100000 0x1c000>; - pcie0_mode: pcie-mode@4060 { - compatible = "syscon"; - reg = <0x00004060 0x4>; - }; - - pcie1_mode: pcie-mode@4070 { - compatible = "syscon"; - reg = <0x00004070 0x4>; - }; - - pcie_devid: pcie-devid@210 { - compatible = "syscon"; - reg = <0x00000210 0x4>; - }; - serdes0_clk: clock@4080 { compatible = "syscon"; reg = <0x00004080 0x4>; @@ -883,8 +868,8 @@ #size-cells = <2>; ranges = <0x81000000 0 0 0x0 0x10020000 0 0x00010000>, <0x82000000 0 0x10030000 0x0 0x10030000 0 0x07FD0000>; - ti,syscon-pcie-id = <&pcie_devid>; - ti,syscon-pcie-mode = <&pcie0_mode>; + ti,syscon-pcie-id = <&scm_conf 0x210>; + ti,syscon-pcie-mode = <&scm_conf 0x4060>; bus-range = <0x0 0xff>; num-viewport = <16>; max-link-speed = <2>; @@ -900,7 +885,7 @@ reg = <0x0 0x5500000 0x0 0x1000>, <0x0 0x5501000 0x0 0x1000>, <0x0 0x10000000 0x0 0x8000000>, <0x0 0x5506000 0x0 0x1000>; reg-names = "app", "dbics", "addr_space", "atu"; power-domains = <&k3_pds 120 TI_SCI_PD_EXCLUSIVE>; - ti,syscon-pcie-mode = <&pcie0_mode>; + ti,syscon-pcie-mode = <&scm_conf 0x4060>; num-ib-windows = <16>; num-ob-windows = <16>; max-link-speed = <2>; @@ -918,8 +903,8 @@ #size-cells = <2>; ranges = <0x81000000 0 0 0x0 0x18020000 0 0x00010000>, <0x82000000 0 0x18030000 0x0 0x18030000 0 0x07FD0000>; - ti,syscon-pcie-id = <&pcie_devid>; - ti,syscon-pcie-mode = <&pcie1_mode>; + ti,syscon-pcie-id = <&scm_conf 0x210>; + ti,syscon-pcie-mode = <&scm_conf 0x4070>; bus-range = <0x0 0xff>; num-viewport = <16>; max-link-speed = <2>; @@ -935,7 +920,7 @@ reg = <0x0 0x5600000 0x0 0x1000>, <0x0 0x5601000 0x0 0x1000>, <0x0 0x18000000 0x0 0x4000000>, <0x0 0x5606000 0x0 0x1000>; reg-names = "app", "dbics", "addr_space", "atu"; power-domains = <&k3_pds 121 TI_SCI_PD_EXCLUSIVE>; - ti,syscon-pcie-mode = <&pcie1_mode>; + ti,syscon-pcie-mode = <&scm_conf 0x4070>; num-ib-windows = <16>; num-ob-windows = <16>; max-link-speed = <2>; -- cgit From cf39ff15cc01adea0ec46d1571d5ae849bb02d43 Mon Sep 17 00:00:00 2001 From: Nishanth Menon Date: Tue, 25 Apr 2023 17:17:08 -0500 Subject: arm64: dts: ti: k3-am62a7-sk: Describe main_uart1 and wkup_uart wkup_uart and main_uart1 on this platform is used by tifs and DM firmwares. Describe them for completeness including the pinmux. Signed-off-by: Nishanth Menon [bb@ti.com: updated pinmux and commit subject] Signed-off-by: Bryan Brattlof Link: https://lore.kernel.org/r/20230425221708.549675-1-bb@ti.com Signed-off-by: Vignesh Raghavendra --- arch/arm64/boot/dts/ti/k3-am62a7-sk.dts | 40 +++++++++++++++++++++++++++++++-- 1 file changed, 38 insertions(+), 2 deletions(-) diff --git a/arch/arm64/boot/dts/ti/k3-am62a7-sk.dts b/arch/arm64/boot/dts/ti/k3-am62a7-sk.dts index f6a67f072dca..65caa5611d6d 100644 --- a/arch/arm64/boot/dts/ti/k3-am62a7-sk.dts +++ b/arch/arm64/boot/dts/ti/k3-am62a7-sk.dts @@ -17,7 +17,9 @@ model = "Texas Instruments AM62A7 SK"; aliases { + serial0 = &wkup_uart0; serial2 = &main_uart0; + serial3 = &main_uart1; mmc1 = &sdhci1; }; @@ -114,11 +116,38 @@ }; }; +&mcu_pmx0 { + wkup_uart0_pins_default: wkup-uart0-pins-default { + pinctrl-single,pins = < + AM62AX_MCU_IOPAD(0x0024, PIN_INPUT, 0) /* (C9) WKUP_UART0_RXD */ + AM62AX_MCU_IOPAD(0x0028, PIN_OUTPUT, 0) /* (E9) WKUP_UART0_TXD */ + AM62AX_MCU_IOPAD(0x002c, PIN_INPUT, 0) /* (C10) WKUP_UART0_CTSn */ + AM62AX_MCU_IOPAD(0x0030, PIN_OUTPUT, 0) /* (C8) WKUP_UART0_RTSn */ + >; + }; +}; + +/* WKUP UART0 is used for DM firmware logs */ +&wkup_uart0 { + pinctrl-names = "default"; + pinctrl-0 = <&wkup_uart0_pins_default>; + status = "reserved"; +}; + &main_pmx0 { main_uart0_pins_default: main-uart0-pins-default { pinctrl-single,pins = < - AM62AX_IOPAD(0x1c8, PIN_INPUT, 0) /* (D14) UART0_RXD */ - AM62AX_IOPAD(0x1cc, PIN_OUTPUT, 0) /* (E14) UART0_TXD */ + AM62AX_IOPAD(0x1c8, PIN_INPUT, 0) /* (E14) UART0_RXD */ + AM62AX_IOPAD(0x1cc, PIN_OUTPUT, 0) /* (D15) UART0_TXD */ + >; + }; + + main_uart1_pins_default: main-uart1-pins-default { + pinctrl-single,pins = < + AM62AX_IOPAD(0x01e8, PIN_INPUT, 1) /* (C17) I2C1_SCL.UART1_RXD */ + AM62AX_IOPAD(0x01ec, PIN_OUTPUT, 1) /* (E17) I2C1_SDA.UART1_TXD */ + AM62AX_IOPAD(0x0194, PIN_INPUT, 2) /* (C19) MCASP0_AXR3.UART1_CTSn */ + AM62AX_IOPAD(0x0198, PIN_OUTPUT, 2) /* (B19) MCASP0_AXR2.UART1_RTSn */ >; }; @@ -254,6 +283,13 @@ pinctrl-0 = <&main_uart0_pins_default>; }; +/* Main UART1 is used for TIFS firmware logs */ +&main_uart1 { + pinctrl-names = "default"; + pinctrl-0 = <&main_uart1_pins_default>; + status = "reserved"; +}; + &usbss1 { status = "okay"; }; -- cgit From 3d011933000ed9054c649952d83162d24f020a93 Mon Sep 17 00:00:00 2001 From: Keerthy Date: Wed, 19 Apr 2023 09:30:06 +0530 Subject: arm64: dts: ti: k3-j7200: Fix physical address of pin wkup_pmx splits into multiple regions. Like wkup_pmx0 -> 13 pins (WKUP_PADCONFIG 0 - 12) wkup_pmx1 -> 2 pins (WKUP_PADCONFIG 14 - 15) wkup_pmx2 -> 59 pins (WKUP_PADCONFIG 26 - 84) wkup_pmx3 -> 8 pins (WKUP_PADCONFIG 93 - 100) With this split, pin offset needs to be adjusted to match with new pmx for all pins above wkup_pmx0. Example a pin under wkup_pmx1 should start from 0 instead of old offset(0x38 WKUP_PADCONFIG 14 offset) J7200 Datasheet (Table 6-106, Section 6.4 Pin Multiplexing) : https://www.ti.com/lit/ds/symlink/dra821u.pdf Fixes: 9ae21ac445e9 ("arm64: dts: ti: k3-j7200: Fix wakeup pinmux range") Signed-off-by: Keerthy Signed-off-by: Udit Kumar Link: https://lore.kernel.org/r/20230419040007.3022780-2-u-kumar1@ti.com Signed-off-by: Vignesh Raghavendra --- .../boot/dts/ti/k3-j7200-common-proc-board.dts | 28 +++++++++++----------- 1 file changed, 14 insertions(+), 14 deletions(-) diff --git a/arch/arm64/boot/dts/ti/k3-j7200-common-proc-board.dts b/arch/arm64/boot/dts/ti/k3-j7200-common-proc-board.dts index 5506341aae21..0cc0e1dc40c5 100644 --- a/arch/arm64/boot/dts/ti/k3-j7200-common-proc-board.dts +++ b/arch/arm64/boot/dts/ti/k3-j7200-common-proc-board.dts @@ -82,25 +82,25 @@ &wkup_pmx2 { mcu_cpsw_pins_default: mcu-cpsw-pins-default { pinctrl-single,pins = < - J721E_WKUP_IOPAD(0x0068, PIN_OUTPUT, 0) /* MCU_RGMII1_TX_CTL */ - J721E_WKUP_IOPAD(0x006c, PIN_INPUT, 0) /* MCU_RGMII1_RX_CTL */ - J721E_WKUP_IOPAD(0x0070, PIN_OUTPUT, 0) /* MCU_RGMII1_TD3 */ - J721E_WKUP_IOPAD(0x0074, PIN_OUTPUT, 0) /* MCU_RGMII1_TD2 */ - J721E_WKUP_IOPAD(0x0078, PIN_OUTPUT, 0) /* MCU_RGMII1_TD1 */ - J721E_WKUP_IOPAD(0x007c, PIN_OUTPUT, 0) /* MCU_RGMII1_TD0 */ - J721E_WKUP_IOPAD(0x0088, PIN_INPUT, 0) /* MCU_RGMII1_RD3 */ - J721E_WKUP_IOPAD(0x008c, PIN_INPUT, 0) /* MCU_RGMII1_RD2 */ - J721E_WKUP_IOPAD(0x0090, PIN_INPUT, 0) /* MCU_RGMII1_RD1 */ - J721E_WKUP_IOPAD(0x0094, PIN_INPUT, 0) /* MCU_RGMII1_RD0 */ - J721E_WKUP_IOPAD(0x0080, PIN_OUTPUT, 0) /* MCU_RGMII1_TXC */ - J721E_WKUP_IOPAD(0x0084, PIN_INPUT, 0) /* MCU_RGMII1_RXC */ + J721E_WKUP_IOPAD(0x0000, PIN_OUTPUT, 0) /* MCU_RGMII1_TX_CTL */ + J721E_WKUP_IOPAD(0x0004, PIN_INPUT, 0) /* MCU_RGMII1_RX_CTL */ + J721E_WKUP_IOPAD(0x0008, PIN_OUTPUT, 0) /* MCU_RGMII1_TD3 */ + J721E_WKUP_IOPAD(0x000c, PIN_OUTPUT, 0) /* MCU_RGMII1_TD2 */ + J721E_WKUP_IOPAD(0x0010, PIN_OUTPUT, 0) /* MCU_RGMII1_TD1 */ + J721E_WKUP_IOPAD(0x0014, PIN_OUTPUT, 0) /* MCU_RGMII1_TD0 */ + J721E_WKUP_IOPAD(0x0020, PIN_INPUT, 0) /* MCU_RGMII1_RD3 */ + J721E_WKUP_IOPAD(0x0024, PIN_INPUT, 0) /* MCU_RGMII1_RD2 */ + J721E_WKUP_IOPAD(0x0028, PIN_INPUT, 0) /* MCU_RGMII1_RD1 */ + J721E_WKUP_IOPAD(0x002c, PIN_INPUT, 0) /* MCU_RGMII1_RD0 */ + J721E_WKUP_IOPAD(0x0018, PIN_OUTPUT, 0) /* MCU_RGMII1_TXC */ + J721E_WKUP_IOPAD(0x001c, PIN_INPUT, 0) /* MCU_RGMII1_RXC */ >; }; mcu_mdio_pins_default: mcu-mdio1-pins-default { pinctrl-single,pins = < - J721E_WKUP_IOPAD(0x009c, PIN_OUTPUT, 0) /* (L1) MCU_MDIO0_MDC */ - J721E_WKUP_IOPAD(0x0098, PIN_INPUT, 0) /* (L4) MCU_MDIO0_MDIO */ + J721E_WKUP_IOPAD(0x0034, PIN_OUTPUT, 0) /* (L1) MCU_MDIO0_MDC */ + J721E_WKUP_IOPAD(0x0030, PIN_INPUT, 0) /* (L4) MCU_MDIO0_MDIO */ >; }; }; -- cgit From 2f932d4151599bc647607ae841cf57273279168c Mon Sep 17 00:00:00 2001 From: Udit Kumar Date: Wed, 19 Apr 2023 09:30:07 +0530 Subject: arm64: dts: ti: k3-j7200-som: Enable I2C This patch enables wkup_i2c0 node in board dts file along with pin mux and speed. Also enables underneath eeprom CAV24C256WE. J7200 Datasheet (Table 6-106, Section 6.4 Pin Multiplexing) : https://www.ti.com/lit/ds/symlink/dra821u.pdf J7200 User Guide (Section 4.3, Table 4-2) : https://www.ti.com/lit/ug/spruiw7a/spruiw7a.pdf Signed-off-by: Udit Kumar Link: https://lore.kernel.org/r/20230419040007.3022780-3-u-kumar1@ti.com Signed-off-by: Vignesh Raghavendra --- arch/arm64/boot/dts/ti/k3-j7200-som-p0.dtsi | 21 +++++++++++++++++++++ 1 file changed, 21 insertions(+) diff --git a/arch/arm64/boot/dts/ti/k3-j7200-som-p0.dtsi b/arch/arm64/boot/dts/ti/k3-j7200-som-p0.dtsi index fa44ed4c17d5..269424154771 100644 --- a/arch/arm64/boot/dts/ti/k3-j7200-som-p0.dtsi +++ b/arch/arm64/boot/dts/ti/k3-j7200-som-p0.dtsi @@ -118,6 +118,15 @@ }; }; +&wkup_pmx2 { + wkup_i2c0_pins_default: wkup-i2c0-pins-default { + pinctrl-single,pins = < + J721E_WKUP_IOPAD(0x98, PIN_INPUT_PULLUP, 0) /* (F20) WKUP_I2C0_SCL */ + J721E_WKUP_IOPAD(0x9c, PIN_INPUT_PULLUP, 0) /* (H21) WKUP_I2C0_SDA */ + >; + }; +}; + &main_pmx0 { main_i2c0_pins_default: main-i2c0-pins-default { pinctrl-single,pins = < @@ -214,6 +223,18 @@ }; }; +&wkup_i2c0 { + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&wkup_i2c0_pins_default>; + clock-frequency = <400000>; + + eeprom@50 { + compatible = "atmel,24c256"; + reg = <0x50>; + }; +}; + &ospi0 { pinctrl-names = "default"; pinctrl-0 = <&mcu_fss0_ospi0_pins_default>; -- cgit From 7e5fd896c3d1ecf7b806f5fd42245c1135fe878d Mon Sep 17 00:00:00 2001 From: Hari Nagalla Date: Tue, 2 May 2023 18:15:25 -0500 Subject: arm64: dts: ti: k3-j784s4-main: Add R5F cluster nodes The J784S4 SoCs have 4 dual-core Arm Cortex-R5F processor (R5FSS) subsystems/clusters. One R5F cluster (MCU_R5FSS0) is present within the MCU domain, and the remaining three clusters are present in the MAIN domain (MAIN_R5FSS0, MAIN_R5FSS1 & MAIN_R5FSS2). The functionality of the R5FSS is same as the R5FSS functionality on earlier K3 platform device J721S2. Each of the R5FSS can be configured at boot time to be either run in a LockStep mode or in an Asymmetric Multi Processing (AMP) fashion in Split-mode. These subsystems have 64 KB each Tightly-Coupled Memory (TCM) internal memories for each core split between two banks - ATCM and BTCM (further interleaved into two banks). There are some IP integration differences from standard Arm R5 clusters such as the absence of an ACP port, presence of an additional TI-specific Region Address Translater (RAT) module for translating 32-bit CPU addresses into larger system bus addresses etc. Add the DT nodes for the R5F cluster/subsystems, the two R5F cores are each added as child nodes to the corresponding cluster node. The clusters are configured to run in LockStep mode by default, with the ATCMs enabled to allow the R5 cores to execute code from DDR with boot-strapping code from ATCM. The inter-processor communication between the main A72 cores and these processors is achieved through shared memory and Mailboxes. The following firmware names are used by default for these cores, and can be overridden in a board dts file if needed: MAIN R5FSS0 Core0: j784s4-main-r5f0_0-fw (both in LockStep and Split modes) MAIN R5FSS0 Core1: j784s4-main-r5f0_1-fw (needed only in Split mode) MAIN R5FSS1 Core0: j784s4-main-r5f1_0-fw (both in LockStep and Split modes) MAIN R5FSS1 Core1: j784s4-main-r5f1_1-fw (needed only in Split mode) MAIN R5FSS2 Core0: j784s4-main-r5f2_0-fw (both in LockStep and Split modes) MAIN R5FSS2 Core1: j784s4-main-r5f2_1-fw (needed only in Split mode) MCU R5FSS0 Core0: j784s4-mcu-r5f0_0-fw (needed only in Split mode) MCU R5FSS0 Core1: j784s4-mcu-r5f0_1-fw (needed only in Split mode) Signed-off-by: Hari Nagalla Link: https://lore.kernel.org/r/20230502231527.25879-2-hnagalla@ti.com Signed-off-by: Vignesh Raghavendra --- arch/arm64/boot/dts/ti/k3-j784s4-main.dtsi | 120 +++++++++++++++++++++++ arch/arm64/boot/dts/ti/k3-j784s4-mcu-wakeup.dtsi | 40 ++++++++ 2 files changed, 160 insertions(+) diff --git a/arch/arm64/boot/dts/ti/k3-j784s4-main.dtsi b/arch/arm64/boot/dts/ti/k3-j784s4-main.dtsi index e9169eb358c1..3c785cef4f20 100644 --- a/arch/arm64/boot/dts/ti/k3-j784s4-main.dtsi +++ b/arch/arm64/boot/dts/ti/k3-j784s4-main.dtsi @@ -1112,4 +1112,124 @@ clocks = <&k3_clks 383 1>; status = "disabled"; }; + + main_r5fss0: r5fss@5c00000 { + compatible = "ti,j721s2-r5fss"; + ti,cluster-mode = <1>; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x5c00000 0x00 0x5c00000 0x20000>, + <0x5d00000 0x00 0x5d00000 0x20000>; + power-domains = <&k3_pds 336 TI_SCI_PD_EXCLUSIVE>; + + main_r5fss0_core0: r5f@5c00000 { + compatible = "ti,j721s2-r5f"; + reg = <0x5c00000 0x00010000>, + <0x5c10000 0x00010000>; + reg-names = "atcm", "btcm"; + ti,sci = <&sms>; + ti,sci-dev-id = <339>; + ti,sci-proc-ids = <0x06 0xff>; + resets = <&k3_reset 339 1>; + firmware-name = "j784s4-main-r5f0_0-fw"; + ti,atcm-enable = <1>; + ti,btcm-enable = <1>; + ti,loczrama = <1>; + }; + + main_r5fss0_core1: r5f@5d00000 { + compatible = "ti,j721s2-r5f"; + reg = <0x5d00000 0x00010000>, + <0x5d10000 0x00010000>; + reg-names = "atcm", "btcm"; + ti,sci = <&sms>; + ti,sci-dev-id = <340>; + ti,sci-proc-ids = <0x07 0xff>; + resets = <&k3_reset 340 1>; + firmware-name = "j784s4-main-r5f0_1-fw"; + ti,atcm-enable = <1>; + ti,btcm-enable = <1>; + ti,loczrama = <1>; + }; + }; + + main_r5fss1: r5fss@5e00000 { + compatible = "ti,j721s2-r5fss"; + ti,cluster-mode = <1>; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x5e00000 0x00 0x5e00000 0x20000>, + <0x5f00000 0x00 0x5f00000 0x20000>; + power-domains = <&k3_pds 337 TI_SCI_PD_EXCLUSIVE>; + + main_r5fss1_core0: r5f@5e00000 { + compatible = "ti,j721s2-r5f"; + reg = <0x5e00000 0x00010000>, + <0x5e10000 0x00010000>; + reg-names = "atcm", "btcm"; + ti,sci = <&sms>; + ti,sci-dev-id = <341>; + ti,sci-proc-ids = <0x08 0xff>; + resets = <&k3_reset 341 1>; + firmware-name = "j784s4-main-r5f1_0-fw"; + ti,atcm-enable = <1>; + ti,btcm-enable = <1>; + ti,loczrama = <1>; + }; + + main_r5fss1_core1: r5f@5f00000 { + compatible = "ti,j721s2-r5f"; + reg = <0x5f00000 0x00010000>, + <0x5f10000 0x00010000>; + reg-names = "atcm", "btcm"; + ti,sci = <&sms>; + ti,sci-dev-id = <342>; + ti,sci-proc-ids = <0x09 0xff>; + resets = <&k3_reset 342 1>; + firmware-name = "j784s4-main-r5f1_1-fw"; + ti,atcm-enable = <1>; + ti,btcm-enable = <1>; + ti,loczrama = <1>; + }; + }; + + main_r5fss2: r5fss@5900000 { + compatible = "ti,j721s2-r5fss"; + ti,cluster-mode = <1>; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x5900000 0x00 0x5900000 0x20000>, + <0x5a00000 0x00 0x5a00000 0x20000>; + power-domains = <&k3_pds 338 TI_SCI_PD_EXCLUSIVE>; + + main_r5fss2_core0: r5f@5900000 { + compatible = "ti,j721s2-r5f"; + reg = <0x5900000 0x00010000>, + <0x5910000 0x00010000>; + reg-names = "atcm", "btcm"; + ti,sci = <&sms>; + ti,sci-dev-id = <343>; + ti,sci-proc-ids = <0x0a 0xff>; + resets = <&k3_reset 343 1>; + firmware-name = "j784s4-main-r5f2_0-fw"; + ti,atcm-enable = <1>; + ti,btcm-enable = <1>; + ti,loczrama = <1>; + }; + + main_r5fss2_core1: r5f@5a00000 { + compatible = "ti,j721s2-r5f"; + reg = <0x5a00000 0x00010000>, + <0x5a10000 0x00010000>; + reg-names = "atcm", "btcm"; + ti,sci = <&sms>; + ti,sci-dev-id = <344>; + ti,sci-proc-ids = <0x0b 0xff>; + resets = <&k3_reset 344 1>; + firmware-name = "j784s4-main-r5f2_1-fw"; + ti,atcm-enable = <1>; + ti,btcm-enable = <1>; + ti,loczrama = <1>; + }; + }; }; diff --git a/arch/arm64/boot/dts/ti/k3-j784s4-mcu-wakeup.dtsi b/arch/arm64/boot/dts/ti/k3-j784s4-mcu-wakeup.dtsi index f04fcb614cbe..e517043d3eb2 100644 --- a/arch/arm64/boot/dts/ti/k3-j784s4-mcu-wakeup.dtsi +++ b/arch/arm64/boot/dts/ti/k3-j784s4-mcu-wakeup.dtsi @@ -342,4 +342,44 @@ ti,cpts-periodic-outputs = <2>; }; }; + + mcu_r5fss0: r5fss@41000000 { + compatible = "ti,j721s2-r5fss"; + ti,cluster-mode = <1>; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x41000000 0x00 0x41000000 0x20000>, + <0x41400000 0x00 0x41400000 0x20000>; + power-domains = <&k3_pds 345 TI_SCI_PD_EXCLUSIVE>; + + mcu_r5fss0_core0: r5f@41000000 { + compatible = "ti,j721s2-r5f"; + reg = <0x41000000 0x00010000>, + <0x41010000 0x00010000>; + reg-names = "atcm", "btcm"; + ti,sci = <&sms>; + ti,sci-dev-id = <346>; + ti,sci-proc-ids = <0x01 0xff>; + resets = <&k3_reset 346 1>; + firmware-name = "j784s4-mcu-r5f0_0-fw"; + ti,atcm-enable = <1>; + ti,btcm-enable = <1>; + ti,loczrama = <1>; + }; + + mcu_r5fss0_core1: r5f@41400000 { + compatible = "ti,j721s2-r5f"; + reg = <0x41400000 0x00010000>, + <0x41410000 0x00010000>; + reg-names = "atcm", "btcm"; + ti,sci = <&sms>; + ti,sci-dev-id = <347>; + ti,sci-proc-ids = <0x02 0xff>; + resets = <&k3_reset 347 1>; + firmware-name = "j784s4-mcu-r5f0_1-fw"; + ti,atcm-enable = <1>; + ti,btcm-enable = <1>; + ti,loczrama = <1>; + }; + }; }; -- cgit From 257d206b6d117d8e40742dc17ae02406747753ad Mon Sep 17 00:00:00 2001 From: Hari Nagalla Date: Tue, 2 May 2023 18:15:26 -0500 Subject: arm64: dts: ti: k3-j784s4-main: Add C71x DSP nodes The J784S4 SoCs have four TMS320C71x DSP subsystems in the MAIN voltage domain. The functionality of these DSP subsystems is similar to the C71x DSP subsystems on earlier k3 device J721S2. Each subsystem has a 48 KB of L1D configurable SRAM/Cache and 512 KB of L2 SRAM/Cache. This subsystem has a CMMU but is not currently used. The inter-processor communication between the main A72 cores and the C71x DSPs is achieved through shared memory and mailboxes. Add the DT nodes for these DSP processor sub-systems. Signed-off-by: Hari Nagalla Link: https://lore.kernel.org/r/20230502231527.25879-3-hnagalla@ti.com Signed-off-by: Vignesh Raghavendra --- arch/arm64/boot/dts/ti/k3-j784s4-main.dtsi | 48 ++++++++++++++++++++++++++++++ 1 file changed, 48 insertions(+) diff --git a/arch/arm64/boot/dts/ti/k3-j784s4-main.dtsi b/arch/arm64/boot/dts/ti/k3-j784s4-main.dtsi index 3c785cef4f20..7277bf6eda09 100644 --- a/arch/arm64/boot/dts/ti/k3-j784s4-main.dtsi +++ b/arch/arm64/boot/dts/ti/k3-j784s4-main.dtsi @@ -1232,4 +1232,52 @@ ti,loczrama = <1>; }; }; + + c71_0: dsp@64800000 { + compatible = "ti,j721s2-c71-dsp"; + reg = <0x00 0x64800000 0x00 0x00080000>, + <0x00 0x64e00000 0x00 0x0000c000>; + reg-names = "l2sram", "l1dram"; + ti,sci = <&sms>; + ti,sci-dev-id = <30>; + ti,sci-proc-ids = <0x30 0xff>; + resets = <&k3_reset 30 1>; + firmware-name = "j784s4-c71_0-fw"; + }; + + c71_1: dsp@65800000 { + compatible = "ti,j721s2-c71-dsp"; + reg = <0x00 0x65800000 0x00 0x00080000>, + <0x00 0x65e00000 0x00 0x0000c000>; + reg-names = "l2sram", "l1dram"; + ti,sci = <&sms>; + ti,sci-dev-id = <33>; + ti,sci-proc-ids = <0x31 0xff>; + resets = <&k3_reset 33 1>; + firmware-name = "j784s4-c71_1-fw"; + }; + + c71_2: dsp@66800000 { + compatible = "ti,j721s2-c71-dsp"; + reg = <0x00 0x66800000 0x00 0x00080000>, + <0x00 0x66e00000 0x00 0x0000c000>; + reg-names = "l2sram", "l1dram"; + ti,sci = <&sms>; + ti,sci-dev-id = <37>; + ti,sci-proc-ids = <0x32 0xff>; + resets = <&k3_reset 37 1>; + firmware-name = "j784s4-c71_2-fw"; + }; + + c71_3: dsp@67800000 { + compatible = "ti,j721s2-c71-dsp"; + reg = <0x00 0x67800000 0x00 0x00080000>, + <0x00 0x67e00000 0x00 0x0000c000>; + reg-names = "l2sram", "l1dram"; + ti,sci = <&sms>; + ti,sci-dev-id = <40>; + ti,sci-proc-ids = <0x33 0xff>; + resets = <&k3_reset 40 1>; + firmware-name = "j784s4-c71_3-fw"; + }; }; -- cgit From ba12d4dde708de01d3cae5ae368a930ec5f5fd07 Mon Sep 17 00:00:00 2001 From: Hari Nagalla Date: Tue, 2 May 2023 18:15:27 -0500 Subject: arm64: dts: ti: k3-j784s4-evm: Reserve memory for remote proc IPC Reserve memory for remote processors. Two memory regions are reserved for each remote processor. The first 1Mb region is used for virtio Vring buffers for IPC and the second region is used for holding resource table, trace buffer and as external memory to the remote processor. The mailboxes are also assigned for each remote processor. Signed-off-by: Hari Nagalla Link: https://lore.kernel.org/r/20230502231527.25879-4-hnagalla@ti.com Signed-off-by: Vignesh Raghavendra --- arch/arm64/boot/dts/ti/k3-j784s4-evm.dts | 318 +++++++++++++++++++++++++++++++ 1 file changed, 318 insertions(+) diff --git a/arch/arm64/boot/dts/ti/k3-j784s4-evm.dts b/arch/arm64/boot/dts/ti/k3-j784s4-evm.dts index f33815953e77..1200cc677eb6 100644 --- a/arch/arm64/boot/dts/ti/k3-j784s4-evm.dts +++ b/arch/arm64/boot/dts/ti/k3-j784s4-evm.dts @@ -42,6 +42,150 @@ reg = <0x00 0x9e800000 0x00 0x01800000>; no-map; }; + + mcu_r5fss0_core0_dma_memory_region: r5f-dma-memory@a0000000 { + compatible = "shared-dma-pool"; + reg = <0x00 0xa0000000 0x00 0x100000>; + no-map; + }; + + mcu_r5fss0_core0_memory_region: r5f-memory@a0100000 { + compatible = "shared-dma-pool"; + reg = <0x00 0xa0100000 0x00 0xf00000>; + no-map; + }; + + mcu_r5fss0_core1_dma_memory_region: r5f-dma-memory@a1000000 { + compatible = "shared-dma-pool"; + reg = <0x00 0xa1000000 0x00 0x100000>; + no-map; + }; + + mcu_r5fss0_core1_memory_region: r5f-memory@a1100000 { + compatible = "shared-dma-pool"; + reg = <0x00 0xa1100000 0x00 0xf00000>; + no-map; + }; + + main_r5fss0_core0_dma_memory_region: r5f-dma-memory@a2000000 { + compatible = "shared-dma-pool"; + reg = <0x00 0xa2000000 0x00 0x100000>; + no-map; + }; + + main_r5fss0_core0_memory_region: r5f-memory@a2100000 { + compatible = "shared-dma-pool"; + reg = <0x00 0xa2100000 0x00 0xf00000>; + no-map; + }; + + main_r5fss0_core1_dma_memory_region: r5f-dma-memory@a3000000 { + compatible = "shared-dma-pool"; + reg = <0x00 0xa3000000 0x00 0x100000>; + no-map; + }; + + main_r5fss0_core1_memory_region: r5f-memory@a3100000 { + compatible = "shared-dma-pool"; + reg = <0x00 0xa3100000 0x00 0xf00000>; + no-map; + }; + + main_r5fss1_core0_dma_memory_region: r5f-dma-memory@a4000000 { + compatible = "shared-dma-pool"; + reg = <0x00 0xa4000000 0x00 0x100000>; + no-map; + }; + + main_r5fss1_core0_memory_region: r5f-memory@a4100000 { + compatible = "shared-dma-pool"; + reg = <0x00 0xa4100000 0x00 0xf00000>; + no-map; + }; + + main_r5fss1_core1_dma_memory_region: r5f-dma-memory@a5000000 { + compatible = "shared-dma-pool"; + reg = <0x00 0xa5000000 0x00 0x100000>; + no-map; + }; + + main_r5fss1_core1_memory_region: r5f-memory@a5100000 { + compatible = "shared-dma-pool"; + reg = <0x00 0xa5100000 0x00 0xf00000>; + no-map; + }; + + main_r5fss2_core0_dma_memory_region: r5f-dma-memory@a6000000 { + compatible = "shared-dma-pool"; + reg = <0x00 0xa6000000 0x00 0x100000>; + no-map; + }; + + main_r5fss2_core0_memory_region: r5f-memory@a6100000 { + compatible = "shared-dma-pool"; + reg = <0x00 0xa6100000 0x00 0xf00000>; + no-map; + }; + + main_r5fss2_core1_dma_memory_region: r5f-dma-memory@a7000000 { + compatible = "shared-dma-pool"; + reg = <0x00 0xa7000000 0x00 0x100000>; + no-map; + }; + + main_r5fss2_core1_memory_region: r5f-memory@a7100000 { + compatible = "shared-dma-pool"; + reg = <0x00 0xa7100000 0x00 0xf00000>; + no-map; + }; + + c71_0_dma_memory_region: c71-dma-memory@a8000000 { + compatible = "shared-dma-pool"; + reg = <0x00 0xa8000000 0x00 0x100000>; + no-map; + }; + + c71_0_memory_region: c71-memory@a8100000 { + compatible = "shared-dma-pool"; + reg = <0x00 0xa8100000 0x00 0xf00000>; + no-map; + }; + + c71_1_dma_memory_region: c71-dma-memory@a9000000 { + compatible = "shared-dma-pool"; + reg = <0x00 0xa9000000 0x00 0x100000>; + no-map; + }; + + c71_1_memory_region: c71-memory@a9100000 { + compatible = "shared-dma-pool"; + reg = <0x00 0xa9100000 0x00 0xf00000>; + no-map; + }; + + c71_2_dma_memory_region: c71-dma-memory@aa000000 { + compatible = "shared-dma-pool"; + reg = <0x00 0xaa000000 0x00 0x100000>; + no-map; + }; + + c71_2_memory_region: c71-memory@aa100000 { + compatible = "shared-dma-pool"; + reg = <0x00 0xaa100000 0x00 0xf00000>; + no-map; + }; + + c71_3_dma_memory_region: c71-dma-memory@ab000000 { + compatible = "shared-dma-pool"; + reg = <0x00 0xab000000 0x00 0x100000>; + no-map; + }; + + c71_3_memory_region: c71-memory@ab100000 { + compatible = "shared-dma-pool"; + reg = <0x00 0xab100000 0x00 0xf00000>; + no-map; + }; }; evm_12v0: regulator-evm12v0 { @@ -253,3 +397,177 @@ phy-mode = "rgmii-rxid"; phy-handle = <&mcu_phy0>; }; + +&mailbox0_cluster0 { + status = "okay"; + interrupts = <436>; + + mbox_mcu_r5fss0_core0: mbox-mcu-r5fss0-core0 { + ti,mbox-rx = <0 0 0>; + ti,mbox-tx = <1 0 0>; + }; + + mbox_mcu_r5fss0_core1: mbox-mcu-r5fss0-core1 { + ti,mbox-rx = <2 0 0>; + ti,mbox-tx = <3 0 0>; + }; +}; + +&mailbox0_cluster1 { + status = "okay"; + interrupts = <432>; + + mbox_main_r5fss0_core0: mbox-main-r5fss0-core0 { + ti,mbox-rx = <0 0 0>; + ti,mbox-tx = <1 0 0>; + }; + + mbox_main_r5fss0_core1: mbox-main-r5fss0-core1 { + ti,mbox-rx = <2 0 0>; + ti,mbox-tx = <3 0 0>; + }; +}; + +&mailbox0_cluster2 { + status = "okay"; + interrupts = <428>; + + mbox_main_r5fss1_core0: mbox-main-r5fss1-core0 { + ti,mbox-rx = <0 0 0>; + ti,mbox-tx = <1 0 0>; + }; + + mbox_main_r5fss1_core1: mbox-main-r5fss1-core1 { + ti,mbox-rx = <2 0 0>; + ti,mbox-tx = <3 0 0>; + }; +}; + +&mailbox0_cluster3 { + status = "okay"; + interrupts = <424>; + + mbox_main_r5fss2_core0: mbox-main-r5fss2-core0 { + ti,mbox-rx = <0 0 0>; + ti,mbox-tx = <1 0 0>; + }; + + mbox_main_r5fss2_core1: mbox-main-r5fss2-core1 { + ti,mbox-rx = <2 0 0>; + ti,mbox-tx = <3 0 0>; + }; +}; + +&mailbox0_cluster4 { + status = "okay"; + interrupts = <420>; + + mbox_c71_0: mbox-c71-0 { + ti,mbox-rx = <0 0 0>; + ti,mbox-tx = <1 0 0>; + }; + + mbox_c71_1: mbox-c71-1 { + ti,mbox-rx = <2 0 0>; + ti,mbox-tx = <3 0 0>; + }; +}; + +&mailbox0_cluster5 { + status = "okay"; + interrupts = <416>; + + mbox_c71_2: mbox-c71-2 { + ti,mbox-rx = <0 0 0>; + ti,mbox-tx = <1 0 0>; + }; + + mbox_c71_3: mbox-c71-3 { + ti,mbox-rx = <2 0 0>; + ti,mbox-tx = <3 0 0>; + }; +}; + +&mcu_r5fss0_core0 { + status = "okay"; + mboxes = <&mailbox0_cluster0 &mbox_mcu_r5fss0_core0>; + memory-region = <&mcu_r5fss0_core0_dma_memory_region>, + <&mcu_r5fss0_core0_memory_region>; +}; + +&mcu_r5fss0_core1 { + status = "okay"; + mboxes = <&mailbox0_cluster0 &mbox_mcu_r5fss0_core1>; + memory-region = <&mcu_r5fss0_core1_dma_memory_region>, + <&mcu_r5fss0_core1_memory_region>; +}; + +&main_r5fss0_core0 { + status = "okay"; + mboxes = <&mailbox0_cluster1 &mbox_main_r5fss0_core0>; + memory-region = <&main_r5fss0_core0_dma_memory_region>, + <&main_r5fss0_core0_memory_region>; +}; + +&main_r5fss0_core1 { + status = "okay"; + mboxes = <&mailbox0_cluster1 &mbox_main_r5fss0_core1>; + memory-region = <&main_r5fss0_core1_dma_memory_region>, + <&main_r5fss0_core1_memory_region>; +}; + +&main_r5fss1_core0 { + status = "okay"; + mboxes = <&mailbox0_cluster2 &mbox_main_r5fss1_core0>; + memory-region = <&main_r5fss1_core0_dma_memory_region>, + <&main_r5fss1_core0_memory_region>; +}; + +&main_r5fss1_core1 { + status = "okay"; + mboxes = <&mailbox0_cluster2 &mbox_main_r5fss1_core1>; + memory-region = <&main_r5fss1_core1_dma_memory_region>, + <&main_r5fss1_core1_memory_region>; +}; + +&main_r5fss2_core0 { + status = "okay"; + mboxes = <&mailbox0_cluster3 &mbox_main_r5fss2_core0>; + memory-region = <&main_r5fss2_core0_dma_memory_region>, + <&main_r5fss2_core0_memory_region>; +}; + +&main_r5fss2_core1 { + status = "okay"; + mboxes = <&mailbox0_cluster3 &mbox_main_r5fss2_core1>; + memory-region = <&main_r5fss2_core1_dma_memory_region>, + <&main_r5fss2_core1_memory_region>; +}; + +&c71_0 { + status = "okay"; + mboxes = <&mailbox0_cluster4 &mbox_c71_0>; + memory-region = <&c71_0_dma_memory_region>, + <&c71_0_memory_region>; +}; + +&c71_1 { + status = "okay"; + mboxes = <&mailbox0_cluster4 &mbox_c71_1>; + memory-region = <&c71_1_dma_memory_region>, + <&c71_1_memory_region>; +}; + +&c71_2 { + status = "okay"; + mboxes = <&mailbox0_cluster5 &mbox_c71_2>; + memory-region = <&c71_2_dma_memory_region>, + <&c71_2_memory_region>; +}; + +&c71_3 { + status = "okay"; + mboxes = <&mailbox0_cluster5 &mbox_c71_3>; + memory-region = <&c71_3_dma_memory_region>, + <&c71_3_memory_region>; +}; -- cgit From 2c213d19515caf880e6c8266fbeda4145894c10e Mon Sep 17 00:00:00 2001 From: Roger Quadros Date: Thu, 30 Mar 2023 11:49:53 +0300 Subject: arm64: dts: ti: k3-am625: Enable Type-C port for USB0 USB0 is a Type-C port with dual data role and power sink. Signed-off-by: Roger Quadros Link: https://lore.kernel.org/r/20230330084954.49763-3-rogerq@kernel.org Signed-off-by: Vignesh Raghavendra --- arch/arm64/boot/dts/ti/k3-am625-sk.dts | 2 +- arch/arm64/boot/dts/ti/k3-am62x-sk-common.dtsi | 35 +++++++++++++++++++++++++- 2 files changed, 35 insertions(+), 2 deletions(-) diff --git a/arch/arm64/boot/dts/ti/k3-am625-sk.dts b/arch/arm64/boot/dts/ti/k3-am625-sk.dts index 2a1adda9bff6..729f95e19042 100644 --- a/arch/arm64/boot/dts/ti/k3-am625-sk.dts +++ b/arch/arm64/boot/dts/ti/k3-am625-sk.dts @@ -161,7 +161,7 @@ "UART1_FET_BUF_EN", "WL_LT_EN", "GPIO_HDMI_RSTn", "CSI_GPIO1", "CSI_GPIO2", "PRU_3V3_EN", - "HDMI_INTn", "TEST_GPIO2", + "HDMI_INTn", "PD_I2C_IRQ", "MCASP1_FET_EN", "MCASP1_BUF_BT_EN", "MCASP1_FET_SEL", "UART1_FET_SEL", "TSINT#", "IO_EXP_TEST_LED"; diff --git a/arch/arm64/boot/dts/ti/k3-am62x-sk-common.dtsi b/arch/arm64/boot/dts/ti/k3-am62x-sk-common.dtsi index a61e8648f189..4345b9fdd2a0 100644 --- a/arch/arm64/boot/dts/ti/k3-am62x-sk-common.dtsi +++ b/arch/arm64/boot/dts/ti/k3-am62x-sk-common.dtsi @@ -241,6 +241,30 @@ pinctrl-names = "default"; pinctrl-0 = <&main_i2c0_pins_default>; clock-frequency = <400000>; + + typec_pd0: tps6598x@3f { + compatible = "ti,tps6598x"; + reg = <0x3f>; + + connector { + compatible = "usb-c-connector"; + label = "USB-C"; + self-powered; + data-role = "dual"; + power-role = "sink"; + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + usb_con_hs: endpoint { + remote-endpoint = <&usb0_hs_ep>; + }; + }; + }; + }; + }; }; &main_i2c1 { @@ -320,7 +344,16 @@ }; &usb0 { - dr_mode = "peripheral"; + #address-cells = <1>; + #size-cells = <0>; + usb-role-switch; + + port@0 { + reg = <0>; + usb0_hs_ep: endpoint { + remote-endpoint = <&usb_con_hs>; + }; + }; }; &usb1 { -- cgit From 20fcf9d691ff6cde865f8486288b7babe1826b49 Mon Sep 17 00:00:00 2001 From: Aswath Govindraju Date: Fri, 31 Mar 2023 14:30:21 +0530 Subject: arm64: dts: ti: k3-j721s2-main: Add support for USB Add support for single instance of USB 3.0 controller in J721S2 SoC. Signed-off-by: Aswath Govindraju Signed-off-by: Matt Ranostay Signed-off-by: Ravi Gunasekaran Reviewed-by: Roger Quadros Link: https://lore.kernel.org/r/20230331090028.8373-2-r-gunasekaran@ti.com Signed-off-by: Vignesh Raghavendra --- arch/arm64/boot/dts/ti/k3-j721s2-main.dtsi | 45 ++++++++++++++++++++++++++++++ 1 file changed, 45 insertions(+) diff --git a/arch/arm64/boot/dts/ti/k3-j721s2-main.dtsi b/arch/arm64/boot/dts/ti/k3-j721s2-main.dtsi index 2dd7865f7654..8d7b64728f88 100644 --- a/arch/arm64/boot/dts/ti/k3-j721s2-main.dtsi +++ b/arch/arm64/boot/dts/ti/k3-j721s2-main.dtsi @@ -26,6 +26,21 @@ }; }; + scm_conf: syscon@104000 { + compatible = "ti,j721e-system-controller", "syscon", "simple-mfd"; + reg = <0x00 0x00104000 0x00 0x18000>; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x00 0x00 0x00104000 0x18000>; + + usb_serdes_mux: mux-controller@0 { + compatible = "mmio-mux"; + reg = <0x0 0x4>; + #mux-control-cells = <1>; + mux-reg-masks = <0x0 0x8000000>; /* USB0 to SERDES0 lane 1/3 mux */ + }; + }; + gic500: interrupt-controller@1800000 { compatible = "arm,gic-v3"; #address-cells = <2>; @@ -745,6 +760,36 @@ }; }; + usbss0: cdns-usb@4104000 { + compatible = "ti,j721e-usb"; + reg = <0x00 0x04104000 0x00 0x100>; + clocks = <&k3_clks 360 16>, <&k3_clks 360 15>; + clock-names = "ref", "lpm"; + assigned-clocks = <&k3_clks 360 16>; /* USB2_REFCLK */ + assigned-clock-parents = <&k3_clks 360 17>; + power-domains = <&k3_pds 360 TI_SCI_PD_EXCLUSIVE>; + #address-cells = <2>; + #size-cells = <2>; + ranges; + dma-coherent; + + status = "disabled"; /* Needs pinmux */ + + usb0: usb@6000000 { + compatible = "cdns,usb3"; + reg = <0x00 0x06000000 0x00 0x10000>, + <0x00 0x06010000 0x00 0x10000>, + <0x00 0x06020000 0x00 0x10000>; + reg-names = "otg", "xhci", "dev"; + interrupts = , + , + ; + interrupt-names = "host", "peripheral", "otg"; + maximum-speed = "super-speed"; + dr_mode = "otg"; + }; + }; + main_mcan0: can@2701000 { compatible = "bosch,m_can"; reg = <0x00 0x02701000 0x00 0x200>, -- cgit From 393eee04065d26d53e9167e3721ad9a0ff89d40f Mon Sep 17 00:00:00 2001 From: Matt Ranostay Date: Fri, 31 Mar 2023 14:30:22 +0530 Subject: arm64: dts: ti: k3-j721s2-main: Add SERDES and WIZ device tree node Add dt node for the single instance of WIZ (SERDES wrapper) and SERDES module shared by PCIe, eDP and USB. Signed-off-by: Matt Ranostay Signed-off-by: Ravi Gunasekaran Reviewed-by: Roger Quadros Link: https://lore.kernel.org/r/20230331090028.8373-3-r-gunasekaran@ti.com Signed-off-by: Vignesh Raghavendra --- arch/arm64/boot/dts/ti/k3-j721s2-main.dtsi | 57 ++++++++++++++++++++++++++++++ 1 file changed, 57 insertions(+) diff --git a/arch/arm64/boot/dts/ti/k3-j721s2-main.dtsi b/arch/arm64/boot/dts/ti/k3-j721s2-main.dtsi index 8d7b64728f88..931263919086 100644 --- a/arch/arm64/boot/dts/ti/k3-j721s2-main.dtsi +++ b/arch/arm64/boot/dts/ti/k3-j721s2-main.dtsi @@ -5,6 +5,17 @@ * Copyright (C) 2021 Texas Instruments Incorporated - https://www.ti.com/ */ +#include +#include + +/ { + serdes_refclk: clock-cmnrefclk { + #clock-cells = <0>; + compatible = "fixed-clock"; + clock-frequency = <0>; + }; +}; + &cbass_main { msmc_ram: sram@70000000 { compatible = "mmio-sram"; @@ -39,6 +50,14 @@ #mux-control-cells = <1>; mux-reg-masks = <0x0 0x8000000>; /* USB0 to SERDES0 lane 1/3 mux */ }; + + serdes_ln_ctrl: mux-controller@80 { + compatible = "mmio-mux"; + reg = <0x80 0x10>; + #mux-control-cells = <1>; + mux-reg-masks = <0x80 0x3>, <0x84 0x3>, /* SERDES0 lane0/1 select */ + <0x88 0x3>, <0x8c 0x3>; /* SERDES0 lane2/3 select */ + }; }; gic500: interrupt-controller@1800000 { @@ -790,6 +809,44 @@ }; }; + serdes_wiz0: wiz@5060000 { + compatible = "ti,j721s2-wiz-10g"; + #address-cells = <1>; + #size-cells = <1>; + power-domains = <&k3_pds 365 TI_SCI_PD_EXCLUSIVE>; + clocks = <&k3_clks 365 0>, <&k3_clks 365 3>, <&serdes_refclk>; + clock-names = "fck", "core_ref_clk", "ext_ref_clk"; + num-lanes = <4>; + #reset-cells = <1>; + #clock-cells = <1>; + ranges = <0x5060000 0x0 0x5060000 0x10000>; + + assigned-clocks = <&k3_clks 365 3>; + assigned-clock-parents = <&k3_clks 365 7>; + + serdes0: serdes@5060000 { + compatible = "ti,j721e-serdes-10g"; + reg = <0x05060000 0x00010000>; + reg-names = "torrent_phy"; + resets = <&serdes_wiz0 0>; + reset-names = "torrent_reset"; + clocks = <&serdes_wiz0 TI_WIZ_PLL0_REFCLK>, + <&serdes_wiz0 TI_WIZ_PHY_EN_REFCLK>; + clock-names = "refclk", "phy_en_refclk"; + assigned-clocks = <&serdes_wiz0 TI_WIZ_PLL0_REFCLK>, + <&serdes_wiz0 TI_WIZ_PLL1_REFCLK>, + <&serdes_wiz0 TI_WIZ_REFCLK_DIG>; + assigned-clock-parents = <&k3_clks 365 3>, + <&k3_clks 365 3>, + <&k3_clks 365 3>; + #address-cells = <1>; + #size-cells = <0>; + #clock-cells = <1>; + + status = "disabled"; /* Needs lane config */ + }; + }; + main_mcan0: can@2701000 { compatible = "bosch,m_can"; reg = <0x00 0x02701000 0x00 0x200>, -- cgit From 80cfbf2f4ac735ab8e72a3c70188c433f06810c1 Mon Sep 17 00:00:00 2001 From: Aswath Govindraju Date: Fri, 31 Mar 2023 14:30:23 +0530 Subject: arm64: dts: ti: k3-j721s2-mcu-wakeup: Add support of OSPI Add support for two instance of OSPI in J721S2 SoC. Reviewed-by: Vaishnav Achath Signed-off-by: Aswath Govindraju Signed-off-by: Matt Ranostay Signed-off-by: Ravi Gunasekaran Reviewed-by: Roger Quadros Link: https://lore.kernel.org/r/20230331090028.8373-4-r-gunasekaran@ti.com Signed-off-by: Vignesh Raghavendra --- arch/arm64/boot/dts/ti/k3-j721s2-mcu-wakeup.dtsi | 44 ++++++++++++++++++++++++ 1 file changed, 44 insertions(+) diff --git a/arch/arm64/boot/dts/ti/k3-j721s2-mcu-wakeup.dtsi b/arch/arm64/boot/dts/ti/k3-j721s2-mcu-wakeup.dtsi index a353705a7463..6e981fe4727e 100644 --- a/arch/arm64/boot/dts/ti/k3-j721s2-mcu-wakeup.dtsi +++ b/arch/arm64/boot/dts/ti/k3-j721s2-mcu-wakeup.dtsi @@ -379,4 +379,48 @@ compatible = "ti,am3359-adc"; }; }; + + fss: bus@47000000 { + compatible = "simple-bus"; + #address-cells = <2>; + #size-cells = <2>; + ranges = <0x00 0x47000000 0x00 0x47000000 0x00 0x00068400>, + <0x05 0x00000000 0x05 0x00000000 0x01 0x00000000>, + <0x07 0x00000000 0x07 0x00000000 0x01 0x00000000>; + + ospi0: spi@47040000 { + compatible = "ti,am654-ospi", "cdns,qspi-nor"; + reg = <0x00 0x47040000 0x00 0x100>, + <0x05 0x00000000 0x01 0x00000000>; + interrupts = ; + cdns,fifo-depth = <256>; + cdns,fifo-width = <4>; + cdns,trigger-address = <0x0>; + clocks = <&k3_clks 109 5>; + assigned-clocks = <&k3_clks 109 5>; + assigned-clock-parents = <&k3_clks 109 7>; + assigned-clock-rates = <166666666>; + power-domains = <&k3_pds 109 TI_SCI_PD_EXCLUSIVE>; + #address-cells = <1>; + #size-cells = <0>; + + status = "disabled"; /* Needs pinmux */ + }; + + ospi1: spi@47050000 { + compatible = "ti,am654-ospi", "cdns,qspi-nor"; + reg = <0x00 0x47050000 0x00 0x100>, + <0x07 0x00000000 0x01 0x00000000>; + interrupts = ; + cdns,fifo-depth = <256>; + cdns,fifo-width = <4>; + cdns,trigger-address = <0x0>; + clocks = <&k3_clks 110 5>; + power-domains = <&k3_pds 110 TI_SCI_PD_EXCLUSIVE>; + #address-cells = <1>; + #size-cells = <0>; + + status = "disabled"; /* Needs pinmux */ + }; + }; }; -- cgit From da61731dc7f5d7a676acd81124229b57e6fbe0ef Mon Sep 17 00:00:00 2001 From: Aswath Govindraju Date: Fri, 31 Mar 2023 14:30:24 +0530 Subject: arm64: dts: ti: k3-j721s2-common-proc-board: Enable SERDES0 Configure first lane to PCIe, the second lane to USB and the last two lanes to eDP. Also, add sub-nodes to SERDES0 DT node to represent SERDES0 is connected to PCIe. Signed-off-by: Aswath Govindraju Signed-off-by: Matt Ranostay Signed-off-by: Ravi Gunasekaran Reviewed-by: Roger Quadros Link: https://lore.kernel.org/r/20230331090028.8373-5-r-gunasekaran@ti.com Signed-off-by: Vignesh Raghavendra --- .../boot/dts/ti/k3-j721s2-common-proc-board.dts | 23 ++++++++++++++++++++++ 1 file changed, 23 insertions(+) diff --git a/arch/arm64/boot/dts/ti/k3-j721s2-common-proc-board.dts b/arch/arm64/boot/dts/ti/k3-j721s2-common-proc-board.dts index 1299c715f34c..30a566fef195 100644 --- a/arch/arm64/boot/dts/ti/k3-j721s2-common-proc-board.dts +++ b/arch/arm64/boot/dts/ti/k3-j721s2-common-proc-board.dts @@ -9,6 +9,9 @@ #include "k3-j721s2-som-p0.dtsi" #include +#include +#include +#include / { compatible = "ti,j721s2-evm", "ti,j721s2"; @@ -321,6 +324,26 @@ phy-handle = <&phy0>; }; +&serdes_ln_ctrl { + idle-states = , , + , ; +}; + +&serdes_refclk { + clock-frequency = <100000000>; +}; + +&serdes0 { + status = "okay"; + serdes0_pcie_link: phy@0 { + reg = <0>; + cdns,num-lanes = <1>; + #phy-cells = <0>; + cdns,phy-type = ; + resets = <&serdes_wiz0 1>; + }; +}; + &mcu_mcan0 { status = "okay"; pinctrl-names = "default"; -- cgit From 7743a9d7517a6a1f3b21d32db3bc1d00d6b16983 Mon Sep 17 00:00:00 2001 From: Aswath Govindraju Date: Fri, 31 Mar 2023 14:30:25 +0530 Subject: arm64: dts: ti: k3-j721s2-common-proc-board: Add USB support The board uses lane 1 of SERDES for USB. Set the mux accordingly. The USB controller and EVM supports super-speed for USB0 on the Type-C port. However, the SERDES has a limitation that up to 2 protocols can be used at a time. The SERDES is wired for PCIe, eDP and USB super-speed. It has been chosen to use PCIe and eDP as default. So restrict USB0 to high-speed mode. Signed-off-by: Aswath Govindraju Signed-off-by: Matt Ranostay Signed-off-by: Ravi Gunasekaran Reviewed-by: Roger Quadros Link: https://lore.kernel.org/r/20230331090028.8373-6-r-gunasekaran@ti.com Signed-off-by: Vignesh Raghavendra --- .../boot/dts/ti/k3-j721s2-common-proc-board.dts | 23 ++++++++++++++++++++++ 1 file changed, 23 insertions(+) diff --git a/arch/arm64/boot/dts/ti/k3-j721s2-common-proc-board.dts b/arch/arm64/boot/dts/ti/k3-j721s2-common-proc-board.dts index 30a566fef195..f81a40bbdac0 100644 --- a/arch/arm64/boot/dts/ti/k3-j721s2-common-proc-board.dts +++ b/arch/arm64/boot/dts/ti/k3-j721s2-common-proc-board.dts @@ -146,6 +146,12 @@ J721S2_IOPAD(0x020, PIN_INPUT, 7) /* (AA23) MCAN15_RX.GPIO0_8 */ >; }; + + main_usbss0_pins_default: main-usbss0-pins-default { + pinctrl-single,pins = < + J721S2_IOPAD(0x0ec, PIN_OUTPUT, 6) /* (AG25) TIMER_IO1.USB0_DRVVBUS */ + >; + }; }; &wkup_pmx0 { @@ -344,6 +350,23 @@ }; }; +&usb_serdes_mux { + idle-states = <1>; /* USB0 to SERDES lane 1 */ +}; + +&usbss0 { + status = "okay"; + pinctrl-0 = <&main_usbss0_pins_default>; + pinctrl-names = "default"; + ti,vbus-divider; + ti,usb2-only; +}; + +&usb0 { + dr_mode = "otg"; + maximum-speed = "high-speed"; +}; + &mcu_mcan0 { status = "okay"; pinctrl-names = "default"; -- cgit From bbabba4ece74c51b98e7c8dbd8fa4725d0ae9baf Mon Sep 17 00:00:00 2001 From: Aswath Govindraju Date: Fri, 31 Mar 2023 14:30:26 +0530 Subject: arm64: dts: ti: k3-j721s2: Add support for OSPI Flashes J721S2 has an OSPI NOR flash on its SOM connected the OSPI0 instance and a QSPI NOR flash on the common processor board connected to the OSPI1 instance. Add support for the same Reviewed-by: Vaishnav Achath Signed-off-by: Aswath Govindraju Signed-off-by: Matt Ranostay Signed-off-by: Ravi Gunasekaran Reviewed-by: Roger Quadros Link: https://lore.kernel.org/r/20230331090028.8373-7-r-gunasekaran@ti.com Signed-off-by: Vignesh Raghavendra --- .../boot/dts/ti/k3-j721s2-common-proc-board.dts | 33 +++++++++++++++++ arch/arm64/boot/dts/ti/k3-j721s2-som-p0.dtsi | 41 ++++++++++++++++++++++ 2 files changed, 74 insertions(+) diff --git a/arch/arm64/boot/dts/ti/k3-j721s2-common-proc-board.dts b/arch/arm64/boot/dts/ti/k3-j721s2-common-proc-board.dts index f81a40bbdac0..9066d8bc34be 100644 --- a/arch/arm64/boot/dts/ti/k3-j721s2-common-proc-board.dts +++ b/arch/arm64/boot/dts/ti/k3-j721s2-common-proc-board.dts @@ -231,6 +231,20 @@ J721S2_WKUP_IOPAD(0x170, PIN_INPUT, 0) /* (N27) MCU_ADC1_AIN7 */ >; }; + + mcu_fss0_ospi1_pins_default: mcu-fss0-ospi1-pins-default { + pinctrl-single,pins = < + J721S2_WKUP_IOPAD(0x040, PIN_OUTPUT, 0) /* (A19) MCU_OSPI1_CLK */ + J721S2_WKUP_IOPAD(0x05c, PIN_OUTPUT, 0) /* (D20) MCU_OSPI1_CSn0 */ + J721S2_WKUP_IOPAD(0x060, PIN_OUTPUT, 0) /* (C21) MCU_OSPI1_CSn1 */ + J721S2_WKUP_IOPAD(0x04c, PIN_INPUT, 0) /* (D21) MCU_OSPI1_D0 */ + J721S2_WKUP_IOPAD(0x050, PIN_INPUT, 0) /* (G20) MCU_OSPI1_D1 */ + J721S2_WKUP_IOPAD(0x054, PIN_INPUT, 0) /* (C20) MCU_OSPI1_D2 */ + J721S2_WKUP_IOPAD(0x058, PIN_INPUT, 0) /* (A20) MCU_OSPI1_D3 */ + J721S2_WKUP_IOPAD(0x048, PIN_INPUT, 0) /* (B19) MCU_OSPI1_DQS */ + J721S2_WKUP_IOPAD(0x044, PIN_INPUT, 0) /* (B20) MCU_OSPI1_LBCLKO */ + >; + }; }; &main_gpio2 { @@ -367,6 +381,25 @@ maximum-speed = "high-speed"; }; +&ospi1 { + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&mcu_fss0_ospi1_pins_default>; + + flash@0{ + compatible = "jedec,spi-nor"; + reg = <0x0>; + spi-tx-bus-width = <1>; + spi-rx-bus-width = <4>; + spi-max-frequency = <40000000>; + cdns,tshsl-ns = <60>; + cdns,tsd2d-ns = <60>; + cdns,tchsh-ns = <60>; + cdns,tslch-ns = <60>; + cdns,read-delay = <2>; + }; +}; + &mcu_mcan0 { status = "okay"; pinctrl-names = "default"; diff --git a/arch/arm64/boot/dts/ti/k3-j721s2-som-p0.dtsi b/arch/arm64/boot/dts/ti/k3-j721s2-som-p0.dtsi index 6930efff8a5a..d473d79c2757 100644 --- a/arch/arm64/boot/dts/ti/k3-j721s2-som-p0.dtsi +++ b/arch/arm64/boot/dts/ti/k3-j721s2-som-p0.dtsi @@ -39,6 +39,28 @@ }; }; +&wkup_pmx0 { + mcu_fss0_ospi0_pins_default: mcu-fss0-ospi0-pins-default { + pinctrl-single,pins = < + J721S2_WKUP_IOPAD(0x000, PIN_OUTPUT, 0) /* (D19) MCU_OSPI0_CLK */ + J721S2_WKUP_IOPAD(0x02c, PIN_OUTPUT, 0) /* (F15) MCU_OSPI0_CSn0 */ + J721S2_WKUP_IOPAD(0x030, PIN_OUTPUT, 0) /* (G17) MCU_OSPI0_CSn1 */ + J721S2_WKUP_IOPAD(0x038, PIN_OUTPUT, 0) /* (F14) MCU_OSPI0_CSn2 */ + J721S2_WKUP_IOPAD(0x03c, PIN_OUTPUT, 0) /* (F17) MCU_OSPI0_CSn3 */ + J721S2_WKUP_IOPAD(0x00c, PIN_INPUT, 0) /* (C19) MCU_OSPI0_D0 */ + J721S2_WKUP_IOPAD(0x010, PIN_INPUT, 0) /* (F16) MCU_OSPI0_D1 */ + J721S2_WKUP_IOPAD(0x014, PIN_INPUT, 0) /* (G15) MCU_OSPI0_D2 */ + J721S2_WKUP_IOPAD(0x018, PIN_INPUT, 0) /* (F18) MCU_OSPI0_D3 */ + J721S2_WKUP_IOPAD(0x01c, PIN_INPUT, 0) /* (E19) MCU_OSPI0_D4 */ + J721S2_WKUP_IOPAD(0x020, PIN_INPUT, 0) /* (G19) MCU_OSPI0_D5 */ + J721S2_WKUP_IOPAD(0x024, PIN_INPUT, 0) /* (F19) MCU_OSPI0_D6 */ + J721S2_WKUP_IOPAD(0x028, PIN_INPUT, 0) /* (F20) MCU_OSPI0_D7 */ + J721S2_WKUP_IOPAD(0x008, PIN_INPUT, 0) /* (E18) MCU_OSPI0_DQS */ + J721S2_WKUP_IOPAD(0x004, PIN_INPUT, 0) /* (E20) MCU_OSPI0_LBCLKO */ + >; + }; +}; + &main_pmx0 { main_i2c0_pins_default: main-i2c0-pins-default { pinctrl-single,pins = < @@ -79,3 +101,22 @@ pinctrl-names = "default"; phys = <&transceiver0>; }; + +&ospi0 { + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&mcu_fss0_ospi0_pins_default>; + + flash@0 { + compatible = "jedec,spi-nor"; + reg = <0x0>; + spi-tx-bus-width = <8>; + spi-rx-bus-width = <8>; + spi-max-frequency = <25000000>; + cdns,tshsl-ns = <60>; + cdns,tsd2d-ns = <60>; + cdns,tchsh-ns = <60>; + cdns,tslch-ns = <60>; + cdns,read-delay = <4>; + }; +}; -- cgit From b6f18aa80f4eee59f9292f0007c021cb7e7dbbec Mon Sep 17 00:00:00 2001 From: Aswath Govindraju Date: Fri, 31 Mar 2023 14:30:27 +0530 Subject: arm64: dts: ti: k3-j721s2-main: Add PCIe device tree node Add PCIe1 RC device tree node for the single PCIe instance present on the J721S2. Reviewed-by: Siddharth Vadapalli Signed-off-by: Aswath Govindraju Signed-off-by: Matt Ranostay Signed-off-by: Ravi Gunasekaran Reviewed-by: Roger Quadros Link: https://lore.kernel.org/r/20230331090028.8373-8-r-gunasekaran@ti.com Signed-off-by: Vignesh Raghavendra --- arch/arm64/boot/dts/ti/k3-j721s2-main.dtsi | 43 ++++++++++++++++++++++++++++++ 1 file changed, 43 insertions(+) diff --git a/arch/arm64/boot/dts/ti/k3-j721s2-main.dtsi b/arch/arm64/boot/dts/ti/k3-j721s2-main.dtsi index 931263919086..6629b2989180 100644 --- a/arch/arm64/boot/dts/ti/k3-j721s2-main.dtsi +++ b/arch/arm64/boot/dts/ti/k3-j721s2-main.dtsi @@ -847,6 +847,49 @@ }; }; + pcie1_rc: pcie@2910000 { + compatible = "ti,j7200-pcie-host", "ti,j721e-pcie-host"; + reg = <0x00 0x02910000 0x00 0x1000>, + <0x00 0x02917000 0x00 0x400>, + <0x00 0x0d800000 0x00 0x800000>, + <0x00 0x18000000 0x00 0x1000>; + reg-names = "intd_cfg", "user_cfg", "reg", "cfg"; + interrupt-names = "link_state"; + interrupts = ; + device_type = "pci"; + ti,syscon-pcie-ctrl = <&scm_conf 0x074>; + max-link-speed = <3>; + num-lanes = <4>; + power-domains = <&k3_pds 276 TI_SCI_PD_EXCLUSIVE>; + clocks = <&k3_clks 276 41>; + clock-names = "fck"; + #address-cells = <3>; + #size-cells = <2>; + bus-range = <0x0 0xff>; + vendor-id = <0x104c>; + device-id = <0xb013>; + msi-map = <0x0 &gic_its 0x0 0x10000>; + dma-coherent; + ranges = <0x01000000 0x0 0x18001000 0x00 0x18001000 0x0 0x0010000>, + <0x02000000 0x0 0x18011000 0x00 0x18011000 0x0 0x7fef000>; + dma-ranges = <0x02000000 0x0 0x0 0x0 0x0 0x10000 0x0>; + #interrupt-cells = <1>; + interrupt-map-mask = <0 0 0 7>; + interrupt-map = <0 0 0 1 &pcie1_intc 0>, /* INT A */ + <0 0 0 2 &pcie1_intc 0>, /* INT B */ + <0 0 0 3 &pcie1_intc 0>, /* INT C */ + <0 0 0 4 &pcie1_intc 0>; /* INT D */ + + status = "disabled"; /* Needs gpio and serdes info */ + + pcie1_intc: interrupt-controller { + interrupt-controller; + #interrupt-cells = <1>; + interrupt-parent = <&gic500>; + interrupts = ; + }; + }; + main_mcan0: can@2701000 { compatible = "bosch,m_can"; reg = <0x00 0x02701000 0x00 0x200>, -- cgit From 715084ecc25adafe7f724721807b64fcc3a13e4a Mon Sep 17 00:00:00 2001 From: Aswath Govindraju Date: Fri, 31 Mar 2023 14:30:28 +0530 Subject: arm64: dts: ti: k3-j721s2-common-proc-board: Enable PCIe x1 lane PCIe slot in the common processor board is enabled and connected to J721S2 SOM. Add PCIe DT node in common processor board to reflect the same. Reviewed-by: Siddharth Vadapalli Signed-off-by: Aswath Govindraju Signed-off-by: Matt Ranostay Signed-off-by: Ravi Gunasekaran Reviewed-by: Roger Quadros Link: https://lore.kernel.org/r/20230331090028.8373-9-r-gunasekaran@ti.com Signed-off-by: Vignesh Raghavendra --- arch/arm64/boot/dts/ti/k3-j721s2-common-proc-board.dts | 8 ++++++++ 1 file changed, 8 insertions(+) diff --git a/arch/arm64/boot/dts/ti/k3-j721s2-common-proc-board.dts b/arch/arm64/boot/dts/ti/k3-j721s2-common-proc-board.dts index 9066d8bc34be..924e0dc4ac1e 100644 --- a/arch/arm64/boot/dts/ti/k3-j721s2-common-proc-board.dts +++ b/arch/arm64/boot/dts/ti/k3-j721s2-common-proc-board.dts @@ -400,6 +400,14 @@ }; }; +&pcie1_rc { + status = "okay"; + reset-gpios = <&exp1 2 GPIO_ACTIVE_HIGH>; + phys = <&serdes0_pcie_link>; + phy-names = "pcie-phy"; + num-lanes = <1>; +}; + &mcu_mcan0 { status = "okay"; pinctrl-names = "default"; -- cgit From 96135297a76003faae68e3aa86e2e19851510eb9 Mon Sep 17 00:00:00 2001 From: Bryan Brattlof Date: Wed, 5 Apr 2023 16:53:22 -0500 Subject: arm64: dts: ti: k3-am64-main: add VTM node The am64x supports a single VTM module which is located in the main domain with two associated temperature monitors located at different hot spots on the die. Tested-by: Christian Gmeiner Signed-off-by: Bryan Brattlof Link: https://lore.kernel.org/r/20230405215328.3755561-2-bb@ti.com Signed-off-by: Vignesh Raghavendra --- arch/arm64/boot/dts/ti/k3-am64-main.dtsi | 8 +++++++ arch/arm64/boot/dts/ti/k3-am64-thermal.dtsi | 33 +++++++++++++++++++++++++++++ arch/arm64/boot/dts/ti/k3-am64.dtsi | 3 +++ 3 files changed, 44 insertions(+) create mode 100644 arch/arm64/boot/dts/ti/k3-am64-thermal.dtsi diff --git a/arch/arm64/boot/dts/ti/k3-am64-main.dtsi b/arch/arm64/boot/dts/ti/k3-am64-main.dtsi index f5e25d6c3c28..9dea128893db 100644 --- a/arch/arm64/boot/dts/ti/k3-am64-main.dtsi +++ b/arch/arm64/boot/dts/ti/k3-am64-main.dtsi @@ -1536,4 +1536,12 @@ clock-names = "fck"; status = "disabled"; }; + + main_vtm0: temperature-sensor@b00000 { + compatible = "ti,j7200-vtm"; + reg = <0x00 0xb00000 0x00 0x400>, + <0x00 0xb01000 0x00 0x400>; + power-domains = <&k3_pds 95 TI_SCI_PD_EXCLUSIVE>; + #thermal-sensor-cells = <1>; + }; }; diff --git a/arch/arm64/boot/dts/ti/k3-am64-thermal.dtsi b/arch/arm64/boot/dts/ti/k3-am64-thermal.dtsi new file mode 100644 index 000000000000..036db56ba797 --- /dev/null +++ b/arch/arm64/boot/dts/ti/k3-am64-thermal.dtsi @@ -0,0 +1,33 @@ +// SPDX-License-Identifier: GPL-2.0 + +#include + +thermal_zones: thermal-zones { + main0_thermal: main0-thermal { + polling-delay-passive = <250>; /* milliSeconds */ + polling-delay = <500>; /* milliSeconds */ + thermal-sensors = <&main_vtm0 0>; + + trips { + main0_crit: main0-crit { + temperature = <105000>; /* milliCelsius */ + hysteresis = <2000>; /* milliCelsius */ + type = "critical"; + }; + }; + }; + + main1_thermal: main1-thermal { + polling-delay-passive = <250>; /* milliSeconds */ + polling-delay = <500>; /* milliSeconds */ + thermal-sensors = <&main_vtm0 1>; + + trips { + main1_crit: main1-crit { + temperature = <105000>; /* milliCelsius */ + hysteresis = <2000>; /* milliCelsius */ + type = "critical"; + }; + }; + }; +}; diff --git a/arch/arm64/boot/dts/ti/k3-am64.dtsi b/arch/arm64/boot/dts/ti/k3-am64.dtsi index d6262b5a0a10..8e9c2bc70f4d 100644 --- a/arch/arm64/boot/dts/ti/k3-am64.dtsi +++ b/arch/arm64/boot/dts/ti/k3-am64.dtsi @@ -54,6 +54,7 @@ <0x00 0x00420000 0x00 0x00420000 0x00 0x00001000>, /* ESM0 */ <0x00 0x00600000 0x00 0x00600000 0x00 0x00001100>, /* GPIO */ <0x00 0x00a40000 0x00 0x00a40000 0x00 0x00000800>, /* Timesync router */ + <0x00 0x00b00000 0x00 0x00b00000 0x00 0x00002400>, /* VTM */ <0x00 0x01000000 0x00 0x01000000 0x00 0x02330400>, /* First peripheral window */ <0x00 0x08000000 0x00 0x08000000 0x00 0x00200000>, /* Main CPSW */ <0x00 0x0d000000 0x00 0x0d000000 0x00 0x00800000>, /* PCIE_CORE */ @@ -90,6 +91,8 @@ ranges = <0x00 0x04000000 0x00 0x04000000 0x00 0x01ff1400>; /* Peripheral window */ }; }; + + #include "k3-am64-thermal.dtsi" }; /* Now include the peripherals for each bus segments */ -- cgit From bbb6dc62505acf6fcb80573f7e7a59875c33be0d Mon Sep 17 00:00:00 2001 From: Bryan Brattlof Date: Wed, 5 Apr 2023 16:53:23 -0500 Subject: arm64: dts: ti: k3-am62-wakeup: add VTM node The am62x supports a single Voltage and Thermal Management (VTM) module located in the wakeup domain with two associated temperature monitors located in hot spots of the die. Signed-off-by: Bryan Brattlof Link: https://lore.kernel.org/r/20230405215328.3755561-3-bb@ti.com Signed-off-by: Vignesh Raghavendra --- arch/arm64/boot/dts/ti/k3-am62-thermal.dtsi | 33 +++++++++++++++++++++++++++++ arch/arm64/boot/dts/ti/k3-am62-wakeup.dtsi | 8 +++++++ arch/arm64/boot/dts/ti/k3-am62.dtsi | 8 +++++-- 3 files changed, 47 insertions(+), 2 deletions(-) create mode 100644 arch/arm64/boot/dts/ti/k3-am62-thermal.dtsi diff --git a/arch/arm64/boot/dts/ti/k3-am62-thermal.dtsi b/arch/arm64/boot/dts/ti/k3-am62-thermal.dtsi new file mode 100644 index 000000000000..a358757e26f0 --- /dev/null +++ b/arch/arm64/boot/dts/ti/k3-am62-thermal.dtsi @@ -0,0 +1,33 @@ +// SPDX-License-Identifier: GPL-2.0 + +#include + +thermal_zones: thermal-zones { + main0_thermal: main0-thermal { + polling-delay-passive = <250>; /* milliSeconds */ + polling-delay = <500>; /* milliSeconds */ + thermal-sensors = <&wkup_vtm0 0>; + + trips { + main0_crit: main0-crit { + temperature = <105000>; /* milliCelsius */ + hysteresis = <2000>; /* milliCelsius */ + type = "critical"; + }; + }; + }; + + main1_thermal: main1-thermal { + polling-delay-passive = <250>; /* milliSeconds */ + polling-delay = <500>; /* milliSeconds */ + thermal-sensors = <&wkup_vtm0 1>; + + trips { + main1_crit: main1-crit { + temperature = <105000>; /* milliCelsius */ + hysteresis = <2000>; /* milliCelsius */ + type = "critical"; + }; + }; + }; +}; diff --git a/arch/arm64/boot/dts/ti/k3-am62-wakeup.dtsi b/arch/arm64/boot/dts/ti/k3-am62-wakeup.dtsi index 7726ebae2539..eae052887186 100644 --- a/arch/arm64/boot/dts/ti/k3-am62-wakeup.dtsi +++ b/arch/arm64/boot/dts/ti/k3-am62-wakeup.dtsi @@ -61,4 +61,12 @@ /* Used by DM firmware */ status = "reserved"; }; + + wkup_vtm0: temperature-sensor@b00000 { + compatible = "ti,j7200-vtm"; + reg = <0x00 0xb00000 0x00 0x400>, + <0x00 0xb01000 0x00 0x400>; + power-domains = <&k3_pds 95 TI_SCI_PD_EXCLUSIVE>; + #thermal-sensor-cells = <1>; + }; }; diff --git a/arch/arm64/boot/dts/ti/k3-am62.dtsi b/arch/arm64/boot/dts/ti/k3-am62.dtsi index a401f5225243..5e72c445f37a 100644 --- a/arch/arm64/boot/dts/ti/k3-am62.dtsi +++ b/arch/arm64/boot/dts/ti/k3-am62.dtsi @@ -81,6 +81,7 @@ <0x00 0x04000000 0x00 0x04000000 0x00 0x01ff1400>, /* Wakeup Domain Range */ + <0x00 0x00b00000 0x00 0x00b00000 0x00 0x00002400>, /* VTM */ <0x00 0x2b000000 0x00 0x2b000000 0x00 0x00300400>, <0x00 0x43000000 0x00 0x43000000 0x00 0x00020000>; @@ -91,14 +92,17 @@ ranges = <0x00 0x04000000 0x00 0x04000000 0x00 0x01ff1400>; /* Peripheral window */ }; - cbass_wakeup: bus@2b000000 { + cbass_wakeup: bus@b00000 { compatible = "simple-bus"; #address-cells = <2>; #size-cells = <2>; - ranges = <0x00 0x2b000000 0x00 0x2b000000 0x00 0x00300400>, /* Peripheral Window */ + ranges = <0x00 0x00b00000 0x00 0x00b00000 0x00 0x00002400>, /* VTM */ + <0x00 0x2b000000 0x00 0x2b000000 0x00 0x00300400>, /* Peripheral Window */ <0x00 0x43000000 0x00 0x43000000 0x00 0x00020000>; }; }; + + #include "k3-am62-thermal.dtsi" }; /* Now include the peripherals for each bus segments */ -- cgit From 225312fbaf37bb283dbc92a0a1d4dfe58629ab64 Mon Sep 17 00:00:00 2001 From: Bryan Brattlof Date: Wed, 5 Apr 2023 16:53:24 -0500 Subject: arm64: dts: ti: k3-am62a-wakeup: add VTM node The am62ax supports a single Voltage and Thermal Management (VTM) device located in the wakeup domain with three associated temperature monitors located in various hot spots of the die. Signed-off-by: Bryan Brattlof Link: https://lore.kernel.org/r/20230405215328.3755561-4-bb@ti.com Signed-off-by: Vignesh Raghavendra --- arch/arm64/boot/dts/ti/k3-am62a-thermal.dtsi | 47 ++++++++++++++++++++++++++++ arch/arm64/boot/dts/ti/k3-am62a-wakeup.dtsi | 8 +++++ arch/arm64/boot/dts/ti/k3-am62a.dtsi | 2 ++ 3 files changed, 57 insertions(+) create mode 100644 arch/arm64/boot/dts/ti/k3-am62a-thermal.dtsi diff --git a/arch/arm64/boot/dts/ti/k3-am62a-thermal.dtsi b/arch/arm64/boot/dts/ti/k3-am62a-thermal.dtsi new file mode 100644 index 000000000000..85ce545633ea --- /dev/null +++ b/arch/arm64/boot/dts/ti/k3-am62a-thermal.dtsi @@ -0,0 +1,47 @@ +// SPDX-License-Identifier: GPL-2.0 + +#include + +thermal_zones: thermal-zones { + main0_thermal: main0-thermal { + polling-delay-passive = <250>; /* milliSeconds */ + polling-delay = <500>; /* milliSeconds */ + thermal-sensors = <&wkup_vtm0 0>; + + trips { + main0_crit: main0-crit { + temperature = <125000>; /* milliCelsius */ + hysteresis = <2000>; /* milliCelsius */ + type = "critical"; + }; + }; + }; + + main1_thermal: main1-thermal { + polling-delay-passive = <250>; /* milliSeconds */ + polling-delay = <500>; /* milliSeconds */ + thermal-sensors = <&wkup_vtm0 1>; + + trips { + main1_crit: main1-crit { + temperature = <125000>; /* milliCelsius */ + hysteresis = <2000>; /* milliCelsius */ + type = "critical"; + }; + }; + }; + + main2_thermal: main2-thermal { + polling-delay-passive = <250>; /* milliSeconds */ + polling-delay = <500>; /* milliSeconds */ + thermal-sensors = <&wkup_vtm0 2>; + + trips { + main2_crit: main2-crit { + temperature = <125000>; /* milliCelsius */ + hysteresis = <2000>; /* milliCelsius */ + type = "critical"; + }; + }; + }; +}; diff --git a/arch/arm64/boot/dts/ti/k3-am62a-wakeup.dtsi b/arch/arm64/boot/dts/ti/k3-am62a-wakeup.dtsi index d848eb24b552..4e8279fa01e1 100644 --- a/arch/arm64/boot/dts/ti/k3-am62a-wakeup.dtsi +++ b/arch/arm64/boot/dts/ti/k3-am62a-wakeup.dtsi @@ -62,4 +62,12 @@ /* Used by DM firmware */ status = "reserved"; }; + + wkup_vtm0: temperature-sensor@b00000 { + compatible = "ti,j7200-vtm"; + reg = <0x00 0xb00000 0x00 0x400>, + <0x00 0xb01000 0x00 0x400>; + power-domains = <&k3_pds 95 TI_SCI_PD_EXCLUSIVE>; + #thermal-sensor-cells = <1>; + }; }; diff --git a/arch/arm64/boot/dts/ti/k3-am62a.dtsi b/arch/arm64/boot/dts/ti/k3-am62a.dtsi index fe60c9ce21e3..61a210ecd5ff 100644 --- a/arch/arm64/boot/dts/ti/k3-am62a.dtsi +++ b/arch/arm64/boot/dts/ti/k3-am62a.dtsi @@ -115,6 +115,8 @@ <0x00 0x78100000 0x00 0x78100000 0x00 0x00008000>; /* DM R5 BTCM*/ }; }; + + #include "k3-am62a-thermal.dtsi" }; /* Now include the peripherals for each bus segments */ -- cgit From 64821fbf67382951c5eae4e088df93f236c1ead6 Mon Sep 17 00:00:00 2001 From: Keerthy Date: Wed, 5 Apr 2023 16:53:25 -0500 Subject: arm64: dts: ti: j784s4: Add VTM node VTM stands for Voltage Thermal Management. Add the thermal zones. Seven sensors mapping to seven thermal zones. Main0, Main1, Main2, Main3, Main4, WKUP1 & WKUP2 domains respectively. Signed-off-by: Keerthy [bb@ti.com: rebased on v6.3-rc1] Signed-off-by: Bryan Brattlof Link: https://lore.kernel.org/r/20230405215328.3755561-5-bb@ti.com Signed-off-by: Vignesh Raghavendra --- arch/arm64/boot/dts/ti/k3-j784s4-mcu-wakeup.dtsi | 8 ++ arch/arm64/boot/dts/ti/k3-j784s4-thermal.dtsi | 101 +++++++++++++++++++++++ arch/arm64/boot/dts/ti/k3-j784s4.dtsi | 4 + 3 files changed, 113 insertions(+) create mode 100644 arch/arm64/boot/dts/ti/k3-j784s4-thermal.dtsi diff --git a/arch/arm64/boot/dts/ti/k3-j784s4-mcu-wakeup.dtsi b/arch/arm64/boot/dts/ti/k3-j784s4-mcu-wakeup.dtsi index e517043d3eb2..32ba27680c6d 100644 --- a/arch/arm64/boot/dts/ti/k3-j784s4-mcu-wakeup.dtsi +++ b/arch/arm64/boot/dts/ti/k3-j784s4-mcu-wakeup.dtsi @@ -382,4 +382,12 @@ ti,loczrama = <1>; }; }; + + wkup_vtm0: temperature-sensor@42040000 { + compatible = "ti,j7200-vtm"; + reg = <0x00 0x42040000 0x00 0x350>, + <0x00 0x42050000 0x00 0x350>; + power-domains = <&k3_pds 154 TI_SCI_PD_SHARED>; + #thermal-sensor-cells = <1>; + }; }; diff --git a/arch/arm64/boot/dts/ti/k3-j784s4-thermal.dtsi b/arch/arm64/boot/dts/ti/k3-j784s4-thermal.dtsi new file mode 100644 index 000000000000..f7b1a15b8fa0 --- /dev/null +++ b/arch/arm64/boot/dts/ti/k3-j784s4-thermal.dtsi @@ -0,0 +1,101 @@ +// SPDX-License-Identifier: GPL-2.0 + +#include + +wkup0_thermal: wkup0-thermal { + polling-delay-passive = <250>; /* milliseconds */ + polling-delay = <500>; /* milliseconds */ + thermal-sensors = <&wkup_vtm0 0>; + + trips { + wkup0_crit: wkup0-crit { + temperature = <125000>; /* milliCelsius */ + hysteresis = <2000>; /* milliCelsius */ + type = "critical"; + }; + }; +}; + +wkup1_thermal: wkup1-thermal { + polling-delay-passive = <250>; /* milliseconds */ + polling-delay = <500>; /* milliseconds */ + thermal-sensors = <&wkup_vtm0 1>; + + trips { + wkup1_crit: wkup1-crit { + temperature = <125000>; /* milliCelsius */ + hysteresis = <2000>; /* milliCelsius */ + type = "critical"; + }; + }; +}; + +main0_thermal: main0-thermal { + polling-delay-passive = <250>; /* milliseconds */ + polling-delay = <500>; /* milliseconds */ + thermal-sensors = <&wkup_vtm0 2>; + + trips { + main0_crit: main0-crit { + temperature = <125000>; /* milliCelsius */ + hysteresis = <2000>; /* milliCelsius */ + type = "critical"; + }; + }; +}; + +main1_thermal: main1-thermal { + polling-delay-passive = <250>; /* milliseconds */ + polling-delay = <500>; /* milliseconds */ + thermal-sensors = <&wkup_vtm0 3>; + + trips { + main1_crit: main1-crit { + temperature = <125000>; /* milliCelsius */ + hysteresis = <2000>; /* milliCelsius */ + type = "critical"; + }; + }; +}; + +main2_thermal: main2-thermal { + polling-delay-passive = <250>; /* milliseconds */ + polling-delay = <500>; /* milliseconds */ + thermal-sensors = <&wkup_vtm0 4>; + + trips { + main2_crit: main2-crit { + temperature = <125000>; /* milliCelsius */ + hysteresis = <2000>; /* milliCelsius */ + type = "critical"; + }; + }; +}; + +main3_thermal: main3-thermal { + polling-delay-passive = <250>; /* milliseconds */ + polling-delay = <500>; /* milliseconds */ + thermal-sensors = <&wkup_vtm0 5>; + + trips { + main3_crit: main3-crit { + temperature = <125000>; /* milliCelsius */ + hysteresis = <2000>; /* milliCelsius */ + type = "critical"; + }; + }; +}; + +main4_thermal: main4-thermal { + polling-delay-passive = <250>; /* milliseconds */ + polling-delay = <500>; /* milliseconds */ + thermal-sensors = <&wkup_vtm0 6>; + + trips { + main4_crit: main4-crit { + temperature = <125000>; /* milliCelsius */ + hysteresis = <2000>; /* milliCelsius */ + type = "critical"; + }; + }; +}; diff --git a/arch/arm64/boot/dts/ti/k3-j784s4.dtsi b/arch/arm64/boot/dts/ti/k3-j784s4.dtsi index 2e03d84da7d2..cd403c3d2be8 100644 --- a/arch/arm64/boot/dts/ti/k3-j784s4.dtsi +++ b/arch/arm64/boot/dts/ti/k3-j784s4.dtsi @@ -281,6 +281,10 @@ <0x07 0x00000000 0x07 0x00000000 0x01 0x00000000>; /* FSS OSPI1 data region 3*/ }; }; + + thermal_zones: thermal-zones { + #include "k3-j784s4-thermal.dtsi" + }; }; /* Now include peripherals from each bus segment */ -- cgit From 8fb4e87c55979c1f6691346205b884d1863ca6db Mon Sep 17 00:00:00 2001 From: Keerthy Date: Wed, 5 Apr 2023 16:53:26 -0500 Subject: arm64: dts: ti: j721e: Add VTM node VTM stands for Voltage Thermal Management. Add the thermal zones. Five sensors mapping ton 5 thermal zones. WKUP, MPU, C7x, GPU & R5F respectively. Signed-off-by: Keerthy [bb@ti.com: rebased on v6.3-rc1] Signed-off-by: Bryan Brattlof Link: https://lore.kernel.org/r/20230405215328.3755561-6-bb@ti.com Signed-off-by: Vignesh Raghavendra --- arch/arm64/boot/dts/ti/k3-j721e-mcu-wakeup.dtsi | 9 +++ arch/arm64/boot/dts/ti/k3-j721e-thermal.dtsi | 75 +++++++++++++++++++++++++ arch/arm64/boot/dts/ti/k3-j721e.dtsi | 2 + 3 files changed, 86 insertions(+) create mode 100644 arch/arm64/boot/dts/ti/k3-j721e-thermal.dtsi diff --git a/arch/arm64/boot/dts/ti/k3-j721e-mcu-wakeup.dtsi b/arch/arm64/boot/dts/ti/k3-j721e-mcu-wakeup.dtsi index 24e8125db8c4..8d86f23b2123 100644 --- a/arch/arm64/boot/dts/ti/k3-j721e-mcu-wakeup.dtsi +++ b/arch/arm64/boot/dts/ti/k3-j721e-mcu-wakeup.dtsi @@ -458,4 +458,13 @@ clocks = <&k3_clks 276 0>; status = "disabled"; }; + + wkup_vtm0: temperature-sensor@42040000 { + compatible = "ti,j721e-vtm"; + reg = <0x00 0x42040000 0x00 0x350>, + <0x00 0x42050000 0x00 0x350>, + <0x00 0x43000300 0x00 0x10>; + power-domains = <&k3_pds 154 TI_SCI_PD_EXCLUSIVE>; + #thermal-sensor-cells = <1>; + }; }; diff --git a/arch/arm64/boot/dts/ti/k3-j721e-thermal.dtsi b/arch/arm64/boot/dts/ti/k3-j721e-thermal.dtsi new file mode 100644 index 000000000000..c2523279001b --- /dev/null +++ b/arch/arm64/boot/dts/ti/k3-j721e-thermal.dtsi @@ -0,0 +1,75 @@ +// SPDX-License-Identifier: GPL-2.0 + +#include + +thermal_zones: thermal-zones { + wkup_thermal: wkup-thermal { + polling-delay-passive = <250>; /* milliseconds */ + polling-delay = <500>; /* milliseconds */ + thermal-sensors = <&wkup_vtm0 0>; + + trips { + wkup_crit: wkup-crit { + temperature = <125000>; /* milliCelsius */ + hysteresis = <2000>; /* milliCelsius */ + type = "critical"; + }; + }; + }; + + mpu_thermal: mpu-thermal { + polling-delay-passive = <250>; /* milliseconds */ + polling-delay = <500>; /* milliseconds */ + thermal-sensors = <&wkup_vtm0 1>; + + trips { + mpu_crit: mpu-crit { + temperature = <125000>; /* milliCelsius */ + hysteresis = <2000>; /* milliCelsius */ + type = "critical"; + }; + }; + }; + + c7x_thermal: c7x-thermal { + polling-delay-passive = <250>; /* milliseconds */ + polling-delay = <500>; /* milliseconds */ + thermal-sensors = <&wkup_vtm0 2>; + + trips { + c7x_crit: c7x-crit { + temperature = <125000>; /* milliCelsius */ + hysteresis = <2000>; /* milliCelsius */ + type = "critical"; + }; + }; + }; + + gpu_thermal: gpu-thermal { + polling-delay-passive = <250>; /* milliseconds */ + polling-delay = <500>; /* milliseconds */ + thermal-sensors = <&wkup_vtm0 3>; + + trips { + gpu_crit: gpu-crit { + temperature = <125000>; /* milliCelsius */ + hysteresis = <2000>; /* milliCelsius */ + type = "critical"; + }; + }; + }; + + r5f_thermal: r5f-thermal { + polling-delay-passive = <250>; /* milliseconds */ + polling-delay = <500>; /* milliseconds */ + thermal-sensors = <&wkup_vtm0 4>; + + trips { + r5f_crit: r5f-crit { + temperature = <125000>; /* milliCelsius */ + hysteresis = <2000>; /* milliCelsius */ + type = "critical"; + }; + }; + }; +}; diff --git a/arch/arm64/boot/dts/ti/k3-j721e.dtsi b/arch/arm64/boot/dts/ti/k3-j721e.dtsi index c577f3739407..99436105ada1 100644 --- a/arch/arm64/boot/dts/ti/k3-j721e.dtsi +++ b/arch/arm64/boot/dts/ti/k3-j721e.dtsi @@ -185,6 +185,8 @@ <0x07 0x00000000 0x07 0x00000000 0x01 0x00000000>; /* FSS OSPI1 data region 3*/ }; }; + + #include "k3-j721e-thermal.dtsi" }; /* Now include the peripherals for each bus segments */ -- cgit From 4aa6586a9720849527379c415d0977f0d5bcfcac Mon Sep 17 00:00:00 2001 From: Keerthy Date: Wed, 5 Apr 2023 16:53:27 -0500 Subject: arm64: dts: ti: j7200: Add VTM node VTM stands for Voltage Thermal Management. Add the thermal zones. Three sensors mapping to 3 thermal zones. MCU, MPU & Main domains respectively. Signed-off-by: Keerthy [bb@ti.com: rebased on v6.3-rc1] Signed-off-by: Bryan Brattlof Link: https://lore.kernel.org/r/20230405215328.3755561-7-bb@ti.com Signed-off-by: Vignesh Raghavendra --- arch/arm64/boot/dts/ti/k3-j7200-mcu-wakeup.dtsi | 8 +++++ arch/arm64/boot/dts/ti/k3-j7200-thermal.dtsi | 47 +++++++++++++++++++++++++ arch/arm64/boot/dts/ti/k3-j7200.dtsi | 2 ++ 3 files changed, 57 insertions(+) create mode 100644 arch/arm64/boot/dts/ti/k3-j7200-thermal.dtsi diff --git a/arch/arm64/boot/dts/ti/k3-j7200-mcu-wakeup.dtsi b/arch/arm64/boot/dts/ti/k3-j7200-mcu-wakeup.dtsi index 331b4e482e41..6a26758af7be 100644 --- a/arch/arm64/boot/dts/ti/k3-j7200-mcu-wakeup.dtsi +++ b/arch/arm64/boot/dts/ti/k3-j7200-mcu-wakeup.dtsi @@ -459,4 +459,12 @@ status = "disabled"; /* Used by OP-TEE */ }; }; + + wkup_vtm0: temperature-sensor@42040000 { + compatible = "ti,j7200-vtm"; + reg = <0x00 0x42040000 0x00 0x350>, + <0x00 0x42050000 0x00 0x350>; + power-domains = <&k3_pds 154 TI_SCI_PD_EXCLUSIVE>; + #thermal-sensor-cells = <1>; + }; }; diff --git a/arch/arm64/boot/dts/ti/k3-j7200-thermal.dtsi b/arch/arm64/boot/dts/ti/k3-j7200-thermal.dtsi new file mode 100644 index 000000000000..e7e3a643a6f0 --- /dev/null +++ b/arch/arm64/boot/dts/ti/k3-j7200-thermal.dtsi @@ -0,0 +1,47 @@ +// SPDX-License-Identifier: GPL-2.0 + +#include + +thermal_zones: thermal-zones { + mcu_thermal: mcu-thermal { + polling-delay-passive = <250>; /* milliseconds */ + polling-delay = <500>; /* milliseconds */ + thermal-sensors = <&wkup_vtm0 0>; + + trips { + wkup_crit: wkup-crit { + temperature = <125000>; /* milliCelsius */ + hysteresis = <2000>; /* milliCelsius */ + type = "critical"; + }; + }; + }; + + mpu_thermal: mpu-thermal { + polling-delay-passive = <250>; /* milliseconds */ + polling-delay = <500>; /* milliseconds */ + thermal-sensors = <&wkup_vtm0 1>; + + trips { + mpu_crit: mpu-crit { + temperature = <125000>; /* milliCelsius */ + hysteresis = <2000>; /* milliCelsius */ + type = "critical"; + }; + }; + }; + + main_thermal: main-thermal { + polling-delay-passive = <250>; /* milliseconds */ + polling-delay = <500>; /* milliseconds */ + thermal-sensors = <&wkup_vtm0 2>; + + trips { + c7x_crit: c7x-crit { + temperature = <125000>; /* milliCelsius */ + hysteresis = <2000>; /* milliCelsius */ + type = "critical"; + }; + }; + }; +}; diff --git a/arch/arm64/boot/dts/ti/k3-j7200.dtsi b/arch/arm64/boot/dts/ti/k3-j7200.dtsi index f1836ec8e934..6c96759e8752 100644 --- a/arch/arm64/boot/dts/ti/k3-j7200.dtsi +++ b/arch/arm64/boot/dts/ti/k3-j7200.dtsi @@ -171,6 +171,8 @@ <0x07 0x00000000 0x07 0x00000000 0x01 0x00000000>; /* FSS OSPI1 data region 3 */ }; }; + + #include "k3-j7200-thermal.dtsi" }; /* Now include the peripherals for each bus segments */ -- cgit From d148e3fe52c855b1709ed031eff6e63e87ad0372 Mon Sep 17 00:00:00 2001 From: Keerthy Date: Wed, 5 Apr 2023 16:53:28 -0500 Subject: arm64: dts: ti: j721s2: Add VTM node VTM stands for Voltage Thermal Management. Add the thermal zones. Six sensors mapping to six thermal zones. Main0, Main1, Main2, Main3, WKUP1 & WKUP2 domains respectively. Signed-off-by: Keerthy [bb@ti.com: rebased on v6.3-rc1] Signed-off-by: Bryan Brattlof Link: https://lore.kernel.org/r/20230405215328.3755561-8-bb@ti.com Signed-off-by: Vignesh Raghavendra --- arch/arm64/boot/dts/ti/k3-j721s2-mcu-wakeup.dtsi | 8 ++ arch/arm64/boot/dts/ti/k3-j721s2-thermal.dtsi | 101 +++++++++++++++++++++++ arch/arm64/boot/dts/ti/k3-j721s2.dtsi | 4 + 3 files changed, 113 insertions(+) create mode 100644 arch/arm64/boot/dts/ti/k3-j721s2-thermal.dtsi diff --git a/arch/arm64/boot/dts/ti/k3-j721s2-mcu-wakeup.dtsi b/arch/arm64/boot/dts/ti/k3-j721s2-mcu-wakeup.dtsi index 6e981fe4727e..9c6bb6db59f8 100644 --- a/arch/arm64/boot/dts/ti/k3-j721s2-mcu-wakeup.dtsi +++ b/arch/arm64/boot/dts/ti/k3-j721s2-mcu-wakeup.dtsi @@ -423,4 +423,12 @@ status = "disabled"; /* Needs pinmux */ }; }; + + wkup_vtm0: temperature-sensor@42040000 { + compatible = "ti,j7200-vtm"; + reg = <0x00 0x42040000 0x0 0x350>, + <0x00 0x42050000 0x0 0x350>; + power-domains = <&k3_pds 154 TI_SCI_PD_SHARED>; + #thermal-sensor-cells = <1>; + }; }; diff --git a/arch/arm64/boot/dts/ti/k3-j721s2-thermal.dtsi b/arch/arm64/boot/dts/ti/k3-j721s2-thermal.dtsi new file mode 100644 index 000000000000..f7b1a15b8fa0 --- /dev/null +++ b/arch/arm64/boot/dts/ti/k3-j721s2-thermal.dtsi @@ -0,0 +1,101 @@ +// SPDX-License-Identifier: GPL-2.0 + +#include + +wkup0_thermal: wkup0-thermal { + polling-delay-passive = <250>; /* milliseconds */ + polling-delay = <500>; /* milliseconds */ + thermal-sensors = <&wkup_vtm0 0>; + + trips { + wkup0_crit: wkup0-crit { + temperature = <125000>; /* milliCelsius */ + hysteresis = <2000>; /* milliCelsius */ + type = "critical"; + }; + }; +}; + +wkup1_thermal: wkup1-thermal { + polling-delay-passive = <250>; /* milliseconds */ + polling-delay = <500>; /* milliseconds */ + thermal-sensors = <&wkup_vtm0 1>; + + trips { + wkup1_crit: wkup1-crit { + temperature = <125000>; /* milliCelsius */ + hysteresis = <2000>; /* milliCelsius */ + type = "critical"; + }; + }; +}; + +main0_thermal: main0-thermal { + polling-delay-passive = <250>; /* milliseconds */ + polling-delay = <500>; /* milliseconds */ + thermal-sensors = <&wkup_vtm0 2>; + + trips { + main0_crit: main0-crit { + temperature = <125000>; /* milliCelsius */ + hysteresis = <2000>; /* milliCelsius */ + type = "critical"; + }; + }; +}; + +main1_thermal: main1-thermal { + polling-delay-passive = <250>; /* milliseconds */ + polling-delay = <500>; /* milliseconds */ + thermal-sensors = <&wkup_vtm0 3>; + + trips { + main1_crit: main1-crit { + temperature = <125000>; /* milliCelsius */ + hysteresis = <2000>; /* milliCelsius */ + type = "critical"; + }; + }; +}; + +main2_thermal: main2-thermal { + polling-delay-passive = <250>; /* milliseconds */ + polling-delay = <500>; /* milliseconds */ + thermal-sensors = <&wkup_vtm0 4>; + + trips { + main2_crit: main2-crit { + temperature = <125000>; /* milliCelsius */ + hysteresis = <2000>; /* milliCelsius */ + type = "critical"; + }; + }; +}; + +main3_thermal: main3-thermal { + polling-delay-passive = <250>; /* milliseconds */ + polling-delay = <500>; /* milliseconds */ + thermal-sensors = <&wkup_vtm0 5>; + + trips { + main3_crit: main3-crit { + temperature = <125000>; /* milliCelsius */ + hysteresis = <2000>; /* milliCelsius */ + type = "critical"; + }; + }; +}; + +main4_thermal: main4-thermal { + polling-delay-passive = <250>; /* milliseconds */ + polling-delay = <500>; /* milliseconds */ + thermal-sensors = <&wkup_vtm0 6>; + + trips { + main4_crit: main4-crit { + temperature = <125000>; /* milliCelsius */ + hysteresis = <2000>; /* milliCelsius */ + type = "critical"; + }; + }; +}; diff --git a/arch/arm64/boot/dts/ti/k3-j721s2.dtsi b/arch/arm64/boot/dts/ti/k3-j721s2.dtsi index f3db277628cd..2abeb857fde7 100644 --- a/arch/arm64/boot/dts/ti/k3-j721s2.dtsi +++ b/arch/arm64/boot/dts/ti/k3-j721s2.dtsi @@ -164,6 +164,10 @@ }; }; + + thermal_zones: thermal-zones { + #include "k3-j721s2-thermal.dtsi" + }; }; /* Now include peripherals from each bus segment */ -- cgit From 5e880618936229b85a185cef736c573b81ef0c9d Mon Sep 17 00:00:00 2001 From: Nishanth Menon Date: Mon, 17 Apr 2023 17:54:50 -0500 Subject: arm64: dts: ti: k3: j721s2/j784s4: Switch to https links Looks like a couple of http:// links crept in. Use https instead. While at it, drop unicode encoded character. Signed-off-by: Nishanth Menon Link: https://lore.kernel.org/r/20230417225450.1182047-1-nm@ti.com Signed-off-by: Vignesh Raghavendra --- arch/arm64/boot/dts/ti/k3-j721s2.dtsi | 2 +- arch/arm64/boot/dts/ti/k3-j784s4.dtsi | 2 +- 2 files changed, 2 insertions(+), 2 deletions(-) diff --git a/arch/arm64/boot/dts/ti/k3-j721s2.dtsi b/arch/arm64/boot/dts/ti/k3-j721s2.dtsi index 2abeb857fde7..1f636acd4eee 100644 --- a/arch/arm64/boot/dts/ti/k3-j721s2.dtsi +++ b/arch/arm64/boot/dts/ti/k3-j721s2.dtsi @@ -2,7 +2,7 @@ /* * Device Tree Source for J721S2 SoC Family * - * TRM (SPRUJ28 – NOVEMBER 2021) : http://www.ti.com/lit/pdf/spruj28 + * TRM (SPRUJ28 NOVEMBER 2021): https://www.ti.com/lit/pdf/spruj28 * * Copyright (C) 2021 Texas Instruments Incorporated - https://www.ti.com/ * diff --git a/arch/arm64/boot/dts/ti/k3-j784s4.dtsi b/arch/arm64/boot/dts/ti/k3-j784s4.dtsi index cd403c3d2be8..8b5974d92e33 100644 --- a/arch/arm64/boot/dts/ti/k3-j784s4.dtsi +++ b/arch/arm64/boot/dts/ti/k3-j784s4.dtsi @@ -2,7 +2,7 @@ /* * Device Tree Source for J784S4 SoC Family * - * TRM (SPRUJ43 JULY 2022) : http://www.ti.com/lit/zip/spruj52 + * TRM (SPRUJ43 JULY 2022): https://www.ti.com/lit/zip/spruj52 * * Copyright (C) 2022 Texas Instruments Incorporated - https://www.ti.com/ * -- cgit From 477d43f6d8546597e007a3a2ebd19f6e4e090fee Mon Sep 17 00:00:00 2001 From: Nishanth Menon Date: Tue, 18 Apr 2023 16:37:37 -0500 Subject: arm64: dts: ti: k3-am62x-sk-common: Drop extra EoL Drop an extra EoL Signed-off-by: Nishanth Menon Link: https://lore.kernel.org/r/20230418213740.153519-2-nm@ti.com Signed-off-by: Vignesh Raghavendra --- arch/arm64/boot/dts/ti/k3-am62x-sk-common.dtsi | 1 - 1 file changed, 1 deletion(-) diff --git a/arch/arm64/boot/dts/ti/k3-am62x-sk-common.dtsi b/arch/arm64/boot/dts/ti/k3-am62x-sk-common.dtsi index 4345b9fdd2a0..29a43db97b3d 100644 --- a/arch/arm64/boot/dts/ti/k3-am62x-sk-common.dtsi +++ b/arch/arm64/boot/dts/ti/k3-am62x-sk-common.dtsi @@ -31,7 +31,6 @@ device_type = "memory"; /* 2G RAM */ reg = <0x00000000 0x80000000 0x00000000 0x80000000>; - }; reserved-memory { -- cgit From 76194aba0c30b1ee25067b34235141443bd078fb Mon Sep 17 00:00:00 2001 From: Nishanth Menon Date: Tue, 18 Apr 2023 16:37:38 -0500 Subject: arm64: dts: ti: k3-am62x-sk-common: Describe main_uart1 and wkup_uart wkup_uart and main_uart1 on this platform is used by tifs and DM firmwares. Describe them for completeness including the pinmux. Signed-off-by: Nishanth Menon Link: https://lore.kernel.org/r/20230418213740.153519-3-nm@ti.com Signed-off-by: Vignesh Raghavendra --- arch/arm64/boot/dts/ti/k3-am62x-sk-common.dtsi | 24 ++++++++++++++++++++++++ 1 file changed, 24 insertions(+) diff --git a/arch/arm64/boot/dts/ti/k3-am62x-sk-common.dtsi b/arch/arm64/boot/dts/ti/k3-am62x-sk-common.dtsi index 29a43db97b3d..3e6ae4c4f8ee 100644 --- a/arch/arm64/boot/dts/ti/k3-am62x-sk-common.dtsi +++ b/arch/arm64/boot/dts/ti/k3-am62x-sk-common.dtsi @@ -125,6 +125,15 @@ >; }; + main_uart1_pins_default: main-uart1-pins-default { + pinctrl-single,pins = < + AM62X_IOPAD(0x194, PIN_INPUT, 2) /* (B19/B18) MCASP0_AXR3.UART1_CTSn */ + AM62X_IOPAD(0x198, PIN_OUTPUT, 2) /* (A19/B17) MCASP0_AXR2.UART1_RTSn */ + AM62X_IOPAD(0x1ac, PIN_INPUT, 2) /* (E19/D15) MCASP0_AFSR.UART1_RXD */ + AM62X_IOPAD(0x1b0, PIN_OUTPUT, 2) /* (A20/D16) MCASP0_ACLKR.UART1_TXD */ + >; + }; + main_i2c0_pins_default: main-i2c0-pins-default { pinctrl-single,pins = < AM62X_IOPAD(0x1e0, PIN_INPUT_PULLUP, 0) /* (B16/E12) I2C0_SCL */ @@ -219,9 +228,22 @@ }; }; +&mcu_pmx0 { + wkup_uart0_pins_default: wkup-uart0-pins-default { + pinctrl-single,pins = < + AM62X_MCU_IOPAD(0x02c, PIN_INPUT, 0) /* (C6/A7) WKUP_UART0_CTSn */ + AM62X_MCU_IOPAD(0x030, PIN_OUTPUT, 0) /* (A4/B4) WKUP_UART0_RTSn */ + AM62X_MCU_IOPAD(0x024, PIN_INPUT, 0) /* (B4/B5) WKUP_UART0_RXD */ + AM62X_MCU_IOPAD(0x028, PIN_OUTPUT, 0) /* (C5/C6) WKUP_UART0_TXD */ + >; + }; +}; + &wkup_uart0 { /* WKUP UART0 is used by DM firmware */ status = "reserved"; + pinctrl-names = "default"; + pinctrl-0 = <&wkup_uart0_pins_default>; }; &main_uart0 { @@ -233,6 +255,8 @@ &main_uart1 { /* Main UART1 is used by TIFS firmware */ status = "reserved"; + pinctrl-names = "default"; + pinctrl-0 = <&main_uart1_pins_default>; }; &main_i2c0 { -- cgit From f40ed3b39b486ed8fbca7aa4a319c8d1d14ac97d Mon Sep 17 00:00:00 2001 From: Nishanth Menon Date: Tue, 18 Apr 2023 16:37:39 -0500 Subject: arm64: dts: ti: k3-am62x-sk-common: Add eeprom Add board EEPROM support to device tree Signed-off-by: Nishanth Menon Link: https://lore.kernel.org/r/20230418213740.153519-4-nm@ti.com Signed-off-by: Vignesh Raghavendra --- arch/arm64/boot/dts/ti/k3-am62x-sk-common.dtsi | 6 ++++++ 1 file changed, 6 insertions(+) diff --git a/arch/arm64/boot/dts/ti/k3-am62x-sk-common.dtsi b/arch/arm64/boot/dts/ti/k3-am62x-sk-common.dtsi index 3e6ae4c4f8ee..4f06d25f0b92 100644 --- a/arch/arm64/boot/dts/ti/k3-am62x-sk-common.dtsi +++ b/arch/arm64/boot/dts/ti/k3-am62x-sk-common.dtsi @@ -265,6 +265,12 @@ pinctrl-0 = <&main_i2c0_pins_default>; clock-frequency = <400000>; + eeprom@51 { + /* AT24C512C-MAHM-T or M24512-DFMC6TG */ + compatible = "atmel,24c512"; + reg = <0x51>; + }; + typec_pd0: tps6598x@3f { compatible = "ti,tps6598x"; reg = <0x3f>; -- cgit From 5cab8abaee22470523a5293994a52784360a7926 Mon Sep 17 00:00:00 2001 From: Nishanth Menon Date: Tue, 18 Apr 2023 16:37:40 -0500 Subject: arm64: dts: ti: k3-am62x-sk-common: Improve documentation of mcasp1_pins Include documentation of the AMC package pin name as well to keep it consistent with the rest of the pinctrl documentation. Signed-off-by: Nishanth Menon Link: https://lore.kernel.org/r/20230418213740.153519-5-nm@ti.com Signed-off-by: Vignesh Raghavendra --- arch/arm64/boot/dts/ti/k3-am62x-sk-common.dtsi | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) diff --git a/arch/arm64/boot/dts/ti/k3-am62x-sk-common.dtsi b/arch/arm64/boot/dts/ti/k3-am62x-sk-common.dtsi index 4f06d25f0b92..d39cfc533583 100644 --- a/arch/arm64/boot/dts/ti/k3-am62x-sk-common.dtsi +++ b/arch/arm64/boot/dts/ti/k3-am62x-sk-common.dtsi @@ -220,10 +220,10 @@ main_mcasp1_pins_default: main-mcasp1-pins-default { pinctrl-single,pins = < - AM62X_IOPAD(0x090, PIN_INPUT, 2) /* (M24) GPMC0_BE0N_CLE.MCASP1_ACLKX */ - AM62X_IOPAD(0x098, PIN_INPUT, 2) /* (U23) GPMC0_WAIT0.MCASP1_AFSX */ - AM62X_IOPAD(0x08c, PIN_OUTPUT, 2) /* (L25) GPMC0_WEN.MCASP1_AXR0 */ - AM62X_IOPAD(0x084, PIN_INPUT, 2) /* (L23) GPMC0_ADVN_ALE.MCASP1_AXR2 */ + AM62X_IOPAD(0x090, PIN_INPUT, 2) /* (M24/K17) GPMC0_BE0N_CLE.MCASP1_ACLKX */ + AM62X_IOPAD(0x098, PIN_INPUT, 2) /* (U23/P21) GPMC0_WAIT0.MCASP1_AFSX */ + AM62X_IOPAD(0x08c, PIN_OUTPUT, 2) /* (L25/J17) GPMC0_WEN.MCASP1_AXR0 */ + AM62X_IOPAD(0x084, PIN_INPUT, 2) /* (L23/K20) GPMC0_ADVN_ALE.MCASP1_AXR2 */ >; }; }; -- cgit From af398252d68edbeef3b1f8cbdf3867b70d2dbbe8 Mon Sep 17 00:00:00 2001 From: Bhavya Kapoor Date: Mon, 24 Apr 2023 15:08:27 +0530 Subject: arm64: dts: ti: k3-j721e-main: Update delay select values for MMC subsystems MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Update the delay values for various speed modes supported, based on the revised august 2021 J721E Datasheet. [1] - Table 7-77. MMC0 DLL Delay Mapping for All Timing Modes and Table 7-86. MMC1/2 DLL Delay Mapping for All Timing Modes, in https://www.ti.com/lit/ds/symlink/tda4vm.pdf, (SPRSP36J – FEBRUARY 2019 – REVISED AUGUST 2021) Signed-off-by: Bhavya Kapoor Link: https://lore.kernel.org/r/20230424093827.1378602-1-b-kapoor@ti.com Signed-off-by: Vignesh Raghavendra --- arch/arm64/boot/dts/ti/k3-j721e-main.dtsi | 10 ++++++---- 1 file changed, 6 insertions(+), 4 deletions(-) diff --git a/arch/arm64/boot/dts/ti/k3-j721e-main.dtsi b/arch/arm64/boot/dts/ti/k3-j721e-main.dtsi index 10c8a5fb4ee2..c249cc3d1fba 100644 --- a/arch/arm64/boot/dts/ti/k3-j721e-main.dtsi +++ b/arch/arm64/boot/dts/ti/k3-j721e-main.dtsi @@ -1287,8 +1287,8 @@ bus-width = <8>; mmc-hs200-1_8v; mmc-ddr-1_8v; - ti,otap-del-sel-legacy = <0xf>; - ti,otap-del-sel-mmc-hs = <0xf>; + ti,otap-del-sel-legacy = <0x0>; + ti,otap-del-sel-mmc-hs = <0x0>; ti,otap-del-sel-ddr52 = <0x5>; ti,otap-del-sel-hs200 = <0x6>; ti,otap-del-sel-hs400 = <0x0>; @@ -1309,11 +1309,12 @@ assigned-clocks = <&k3_clks 92 0>; assigned-clock-parents = <&k3_clks 92 1>; ti,otap-del-sel-legacy = <0x0>; - ti,otap-del-sel-sd-hs = <0xf>; + ti,otap-del-sel-sd-hs = <0x0>; ti,otap-del-sel-sdr12 = <0xf>; ti,otap-del-sel-sdr25 = <0xf>; ti,otap-del-sel-sdr50 = <0xc>; ti,otap-del-sel-ddr50 = <0xc>; + ti,otap-del-sel-sdr104 = <0x5>; ti,itap-del-sel-legacy = <0x0>; ti,itap-del-sel-sd-hs = <0x0>; ti,itap-del-sel-sdr12 = <0x0>; @@ -1335,11 +1336,12 @@ assigned-clocks = <&k3_clks 93 0>; assigned-clock-parents = <&k3_clks 93 1>; ti,otap-del-sel-legacy = <0x0>; - ti,otap-del-sel-sd-hs = <0xf>; + ti,otap-del-sel-sd-hs = <0x0>; ti,otap-del-sel-sdr12 = <0xf>; ti,otap-del-sel-sdr25 = <0xf>; ti,otap-del-sel-sdr50 = <0xc>; ti,otap-del-sel-ddr50 = <0xc>; + ti,otap-del-sel-sdr104 = <0x5>; ti,itap-del-sel-legacy = <0x0>; ti,itap-del-sel-sd-hs = <0x0>; ti,itap-del-sel-sdr12 = <0x0>; -- cgit From b8690ed3d1d16153be76f24de3a13797c9fd29b3 Mon Sep 17 00:00:00 2001 From: Jyri Sarha Date: Tue, 9 May 2023 15:53:53 +0530 Subject: arm64: dts: ti: am65x: Add Rocktech OLDI panel DT overlay The OLDI-LCD1EVM add on board has Rocktech RK101II01D-CT panel[1] with integrated touch screen. The integrated touch screen is Goodix GT928. This panel connects with AM65 GP-EVM[2]. Add DT nodes for these and connect the endpoint nodes with DSS. [1]: Panel link https://www.digimax.it/en/tft-lcd/20881-RK101II01D-CT [2]: AM654 LCD EVM: https://www.ti.com/tool/TMDSLCD1EVM Signed-off-by: Jyri Sarha Signed-off-by: Nikhil Devshatwar [abhatia1@ti.com: Make cosmetic and 6.4 kernel DTSO syntax changes] Signed-off-by: Aradhya Bhatia Reviewed-by: Tomi Valkeinen Reviewed-by: Andrew Davis Link: https://lore.kernel.org/r/20230509102354.10116-2-a-bhatia1@ti.com Signed-off-by: Vignesh Raghavendra --- arch/arm64/boot/dts/ti/Makefile | 2 + .../k3-am654-base-board-rocktech-rk101-panel.dtso | 71 ++++++++++++++++++++++ 2 files changed, 73 insertions(+) create mode 100644 arch/arm64/boot/dts/ti/k3-am654-base-board-rocktech-rk101-panel.dtso diff --git a/arch/arm64/boot/dts/ti/Makefile b/arch/arm64/boot/dts/ti/Makefile index c83c9d772b81..47b0d257b508 100644 --- a/arch/arm64/boot/dts/ti/Makefile +++ b/arch/arm64/boot/dts/ti/Makefile @@ -22,12 +22,14 @@ dtb-$(CONFIG_ARCH_K3) += k3-am642-phyboard-electra-rdk.dtb dtb-$(CONFIG_ARCH_K3) += k3-am642-sk.dtb # Boards with AM65x SoC +k3-am654-gp-evm-dtbs := k3-am654-base-board.dtb k3-am654-base-board-rocktech-rk101-panel.dtbo dtb-$(CONFIG_ARCH_K3) += k3-am6528-iot2050-basic.dtb dtb-$(CONFIG_ARCH_K3) += k3-am6528-iot2050-basic-pg2.dtb dtb-$(CONFIG_ARCH_K3) += k3-am6548-iot2050-advanced.dtb dtb-$(CONFIG_ARCH_K3) += k3-am6548-iot2050-advanced-m2.dtb dtb-$(CONFIG_ARCH_K3) += k3-am6548-iot2050-advanced-pg2.dtb dtb-$(CONFIG_ARCH_K3) += k3-am654-base-board.dtb +dtb-$(CONFIG_ARCH_K3) += k3-am654-gp-evm.dtb # Boards with J7200 SoC k3-j7200-evm-dtbs := k3-j7200-common-proc-board.dtb k3-j7200-evm-quad-port-eth-exp.dtbo diff --git a/arch/arm64/boot/dts/ti/k3-am654-base-board-rocktech-rk101-panel.dtso b/arch/arm64/boot/dts/ti/k3-am654-base-board-rocktech-rk101-panel.dtso new file mode 100644 index 000000000000..3be92c39ecba --- /dev/null +++ b/arch/arm64/boot/dts/ti/k3-am654-base-board-rocktech-rk101-panel.dtso @@ -0,0 +1,71 @@ +// SPDX-License-Identifier: GPL-2.0 +/** + * OLDI-LCD1EVM Rocktech integrated panel and touch DT overlay for AM654-EVM. + * Panel Link: https://www.digimax.it/en/tft-lcd/20881-RK101II01D-CT + * AM654 LCD EVM: https://www.ti.com/tool/TMDSLCD1EVM + * + * Copyright (C) 2023 Texas Instruments Incorporated - http://www.ti.com/ + */ + +/dts-v1/; +/plugin/; + +#include +#include +#include + +&{/} { + display0 { + compatible = "rocktech,rk101ii01d-ct"; + backlight = <&lcd_bl>; + enable-gpios = <&pca9555 8 GPIO_ACTIVE_HIGH>; + port { + lcd_in0: endpoint { + remote-endpoint = <&oldi_out0>; + }; + }; + }; + + lcd_bl: backlight { + compatible = "pwm-backlight"; + pwms = <&ecap0 0 50000 PWM_POLARITY_INVERTED>; + brightness-levels = + <0 32 64 96 128 160 192 224 255>; + default-brightness-level = <8>; + }; +}; + +&dss { + status = "okay"; +}; + +&dss_ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + + oldi_out0: endpoint { + remote-endpoint = <&lcd_in0>; + }; + }; +}; + +&main_i2c1 { + #address-cells = <1>; + #size-cells = <0>; + + touchscreen@14 { + compatible = "goodix,gt928"; + reg = <0x14>; + + interrupt-parent = <&pca9554>; + interrupts = <3 IRQ_TYPE_EDGE_FALLING>; + touchscreen-size-x = <1280>; + touchscreen-size-y = <800>; + + reset-gpios = <&pca9555 9 GPIO_ACTIVE_HIGH>; + irq-gpios = <&pca9554 3 GPIO_ACTIVE_HIGH>; + }; +}; -- cgit From ad5f7c514442a5eb29a415f75b3ea2744933e274 Mon Sep 17 00:00:00 2001 From: Bhavya Kapoor Date: Tue, 2 May 2023 13:41:16 +0530 Subject: arm64: dts: ti: k3-j784s4-mcu-wakeup: Add support for ADC nodes J784S4 has two instances of 8 channel ADCs in MCU domain. Add support for both ADC nodes. Signed-off-by: Bhavya Kapoor Link: https://lore.kernel.org/r/20230502081117.21431-2-b-kapoor@ti.com Signed-off-by: Vignesh Raghavendra --- arch/arm64/boot/dts/ti/k3-j784s4-mcu-wakeup.dtsi | 40 ++++++++++++++++++++++++ 1 file changed, 40 insertions(+) diff --git a/arch/arm64/boot/dts/ti/k3-j784s4-mcu-wakeup.dtsi b/arch/arm64/boot/dts/ti/k3-j784s4-mcu-wakeup.dtsi index 32ba27680c6d..d640e31a8335 100644 --- a/arch/arm64/boot/dts/ti/k3-j784s4-mcu-wakeup.dtsi +++ b/arch/arm64/boot/dts/ti/k3-j784s4-mcu-wakeup.dtsi @@ -390,4 +390,44 @@ power-domains = <&k3_pds 154 TI_SCI_PD_SHARED>; #thermal-sensor-cells = <1>; }; + + tscadc0: tscadc@40200000 { + compatible = "ti,am3359-tscadc"; + reg = <0x00 0x40200000 0x00 0x1000>; + interrupts = ; + power-domains = <&k3_pds 0 TI_SCI_PD_EXCLUSIVE>; + clocks = <&k3_clks 0 0>; + assigned-clocks = <&k3_clks 0 2>; + assigned-clock-rates = <60000000>; + clock-names = "fck"; + dmas = <&main_udmap 0x7400>, + <&main_udmap 0x7401>; + dma-names = "fifo0", "fifo1"; + status = "disabled"; + + adc { + #io-channel-cells = <1>; + compatible = "ti,am3359-adc"; + }; + }; + + tscadc1: tscadc@40210000 { + compatible = "ti,am3359-tscadc"; + reg = <0x00 0x40210000 0x00 0x1000>; + interrupts = ; + power-domains = <&k3_pds 1 TI_SCI_PD_EXCLUSIVE>; + clocks = <&k3_clks 1 0>; + assigned-clocks = <&k3_clks 1 2>; + assigned-clock-rates = <60000000>; + clock-names = "fck"; + dmas = <&main_udmap 0x7402>, + <&main_udmap 0x7403>; + dma-names = "fifo0", "fifo1"; + status = "disabled"; + + adc { + #io-channel-cells = <1>; + compatible = "ti,am3359-adc"; + }; + }; }; -- cgit From e99913ad58af3172343e3b22fa7a2a794d78b8c1 Mon Sep 17 00:00:00 2001 From: Bhavya Kapoor Date: Tue, 2 May 2023 13:41:17 +0530 Subject: arm64: dts: ti: k3-j784s4-evm: Add pinmux information for ADC J784S4 has two instances of 8 channel ADCs in MCU domain. Add pinmux information for both ADC nodes. Signed-off-by: Bhavya Kapoor Link: https://lore.kernel.org/r/20230502081117.21431-3-b-kapoor@ti.com Signed-off-by: Vignesh Raghavendra --- arch/arm64/boot/dts/ti/k3-j784s4-evm.dts | 44 ++++++++++++++++++++++++++++++++ 1 file changed, 44 insertions(+) diff --git a/arch/arm64/boot/dts/ti/k3-j784s4-evm.dts b/arch/arm64/boot/dts/ti/k3-j784s4-evm.dts index 1200cc677eb6..64b58e0d2e5d 100644 --- a/arch/arm64/boot/dts/ti/k3-j784s4-evm.dts +++ b/arch/arm64/boot/dts/ti/k3-j784s4-evm.dts @@ -309,6 +309,32 @@ J784S4_WKUP_IOPAD(0x098, PIN_INPUT, 0) /* (B35) MCU_MDIO0_MDIO */ >; }; + + mcu_adc0_pins_default: mcu-adc0-pins-default { + pinctrl-single,pins = < + J784S4_WKUP_IOPAD(0x134, PIN_INPUT, 0) /* (P36) MCU_ADC0_AIN0 */ + J784S4_WKUP_IOPAD(0x138, PIN_INPUT, 0) /* (V36) MCU_ADC0_AIN1 */ + J784S4_WKUP_IOPAD(0x13c, PIN_INPUT, 0) /* (T34) MCU_ADC0_AIN2 */ + J784S4_WKUP_IOPAD(0x140, PIN_INPUT, 0) /* (T36) MCU_ADC0_AIN3 */ + J784S4_WKUP_IOPAD(0x144, PIN_INPUT, 0) /* (P34) MCU_ADC0_AIN4 */ + J784S4_WKUP_IOPAD(0x148, PIN_INPUT, 0) /* (R37) MCU_ADC0_AIN5 */ + J784S4_WKUP_IOPAD(0x14c, PIN_INPUT, 0) /* (R33) MCU_ADC0_AIN6 */ + J784S4_WKUP_IOPAD(0x150, PIN_INPUT, 0) /* (V38) MCU_ADC0_AIN7 */ + >; + }; + + mcu_adc1_pins_default: mcu-adc1-pins-default { + pinctrl-single,pins = < + J784S4_WKUP_IOPAD(0x154, PIN_INPUT, 0) /* (Y38) MCU_ADC1_AIN0 */ + J784S4_WKUP_IOPAD(0x158, PIN_INPUT, 0) /* (Y34) MCU_ADC1_AIN1 */ + J784S4_WKUP_IOPAD(0x15c, PIN_INPUT, 0) /* (V34) MCU_ADC1_AIN2 */ + J784S4_WKUP_IOPAD(0x160, PIN_INPUT, 0) /* (W37) MCU_ADC1_AIN3 */ + J784S4_WKUP_IOPAD(0x164, PIN_INPUT, 0) /* (AA37) MCU_ADC1_AIN4 */ + J784S4_WKUP_IOPAD(0x168, PIN_INPUT, 0) /* (W33) MCU_ADC1_AIN5 */ + J784S4_WKUP_IOPAD(0x16c, PIN_INPUT, 0) /* (U33) MCU_ADC1_AIN6 */ + J784S4_WKUP_IOPAD(0x170, PIN_INPUT, 0) /* (Y36) MCU_ADC1_AIN7 */ + >; + }; }; &main_uart8 { @@ -571,3 +597,21 @@ memory-region = <&c71_3_dma_memory_region>, <&c71_3_memory_region>; }; + +&tscadc0 { + pinctrl-0 = <&mcu_adc0_pins_default>; + pinctrl-names = "default"; + status = "okay"; + adc { + ti,adc-channels = <0 1 2 3 4 5 6 7>; + }; +}; + +&tscadc1 { + pinctrl-0 = <&mcu_adc1_pins_default>; + pinctrl-names = "default"; + status = "okay"; + adc { + ti,adc-channels = <0 1 2 3 4 5 6 7>; + }; +}; -- cgit From 426e720259c9e4066cafac9d4592cfbca4031b1d Mon Sep 17 00:00:00 2001 From: Bhavya Kapoor Date: Tue, 2 May 2023 14:38:14 +0530 Subject: arm64: dts: ti: k3-j784s4-main: Enable support for high speed modes eMMC tuning was incomplete earlier, so support for high speed modes was kept disabled. Remove no-1-8-v property to enable support for high speed modes for eMMC in J784S4 SoC. Signed-off-by: Bhavya Kapoor Link: https://lore.kernel.org/r/20230502090814.144791-1-b-kapoor@ti.com Signed-off-by: Vignesh Raghavendra --- arch/arm64/boot/dts/ti/k3-j784s4-main.dtsi | 1 - 1 file changed, 1 deletion(-) diff --git a/arch/arm64/boot/dts/ti/k3-j784s4-main.dtsi b/arch/arm64/boot/dts/ti/k3-j784s4-main.dtsi index 7277bf6eda09..742bab1c5103 100644 --- a/arch/arm64/boot/dts/ti/k3-j784s4-main.dtsi +++ b/arch/arm64/boot/dts/ti/k3-j784s4-main.dtsi @@ -378,7 +378,6 @@ mmc-hs200-1_8v; mmc-hs400-1_8v; dma-coherent; - no-1-8-v; status = "disabled"; }; -- cgit From 155e7635ed1f3814d94d12556a3a0fed41d05b76 Mon Sep 17 00:00:00 2001 From: Andrew Davis Date: Mon, 15 May 2023 12:21:33 -0500 Subject: arm64: dts: ti: k3-j721e-beagleboneai64: Fix mailbox node status Mailbox nodes are now disabled by default. The BeagleBoard AI64 DT addition went in at around the same time and must have missed that change so the mailboxes are not re-enabled. Do that here. Fixes: fae14a1cb8dd ("arm64: dts: ti: Add k3-j721e-beagleboneai64") Signed-off-by: Andrew Davis Reviewed-by: Nishanth Menon Link: https://lore.kernel.org/r/20230515172137.474626-1-afd@ti.com Signed-off-by: Vignesh Raghavendra --- arch/arm64/boot/dts/ti/k3-j721e-beagleboneai64.dts | 5 +++++ 1 file changed, 5 insertions(+) diff --git a/arch/arm64/boot/dts/ti/k3-j721e-beagleboneai64.dts b/arch/arm64/boot/dts/ti/k3-j721e-beagleboneai64.dts index 37c24b077b6a..8a62ac263b89 100644 --- a/arch/arm64/boot/dts/ti/k3-j721e-beagleboneai64.dts +++ b/arch/arm64/boot/dts/ti/k3-j721e-beagleboneai64.dts @@ -936,6 +936,7 @@ }; &mailbox0_cluster0 { + status = "okay"; interrupts = <436>; mbox_mcu_r5fss0_core0: mbox-mcu-r5fss0-core0 { @@ -950,6 +951,7 @@ }; &mailbox0_cluster1 { + status = "okay"; interrupts = <432>; mbox_main_r5fss0_core0: mbox-main-r5fss0-core0 { @@ -964,6 +966,7 @@ }; &mailbox0_cluster2 { + status = "okay"; interrupts = <428>; mbox_main_r5fss1_core0: mbox-main-r5fss1-core0 { @@ -978,6 +981,7 @@ }; &mailbox0_cluster3 { + status = "okay"; interrupts = <424>; mbox_c66_0: mbox-c66-0 { @@ -992,6 +996,7 @@ }; &mailbox0_cluster4 { + status = "okay"; interrupts = <420>; mbox_c71_0: mbox-c71-0 { -- cgit From a0cfd88d4a8a1106e9de5c3b03e68efe9e6249ec Mon Sep 17 00:00:00 2001 From: Andrew Davis Date: Mon, 15 May 2023 12:21:34 -0500 Subject: arm64: dts: ti: k3-j721e: Remove PCIe endpoint nodes These nodes are example nodes for the PCIe controller in "endpoint" mode. By default the controller is in "root complex" mode and there is already a DT node for the same. Examples should go in the bindings or other documentation. Remove this node. Signed-off-by: Andrew Davis Link: https://lore.kernel.org/r/20230515172137.474626-2-afd@ti.com Signed-off-by: Vignesh Raghavendra --- arch/arm64/boot/dts/ti/k3-j721e-beagleboneai64.dts | 24 ------- .../boot/dts/ti/k3-j721e-common-proc-board.dts | 25 ------- arch/arm64/boot/dts/ti/k3-j721e-main.dtsi | 82 ---------------------- arch/arm64/boot/dts/ti/k3-j721e-sk.dts | 24 ------- 4 files changed, 155 deletions(-) diff --git a/arch/arm64/boot/dts/ti/k3-j721e-beagleboneai64.dts b/arch/arm64/boot/dts/ti/k3-j721e-beagleboneai64.dts index 8a62ac263b89..d77eeff0d81d 100644 --- a/arch/arm64/boot/dts/ti/k3-j721e-beagleboneai64.dts +++ b/arch/arm64/boot/dts/ti/k3-j721e-beagleboneai64.dts @@ -892,35 +892,11 @@ status = "disabled"; }; -&pcie0_ep { - status = "disabled"; - phys = <&serdes0_pcie_link>; - phy-names = "pcie-phy"; - num-lanes = <1>; -}; - -&pcie1_ep { - status = "disabled"; - phys = <&serdes1_pcie_link>; - phy-names = "pcie-phy"; - num-lanes = <2>; -}; - -&pcie2_ep { - /* Unused */ - status = "disabled"; -}; - &pcie3_rc { /* Unused */ status = "disabled"; }; -&pcie3_ep { - /* Unused */ - status = "disabled"; -}; - &icssg0_mdio { /* Unused */ status = "disabled"; diff --git a/arch/arm64/boot/dts/ti/k3-j721e-common-proc-board.dts b/arch/arm64/boot/dts/ti/k3-j721e-common-proc-board.dts index c11c092c1ce0..7957d09bf04b 100644 --- a/arch/arm64/boot/dts/ti/k3-j721e-common-proc-board.dts +++ b/arch/arm64/boot/dts/ti/k3-j721e-common-proc-board.dts @@ -839,35 +839,10 @@ num-lanes = <2>; }; -&pcie0_ep { - phys = <&serdes0_pcie_link>; - phy-names = "pcie-phy"; - num-lanes = <1>; - status = "disabled"; -}; - -&pcie1_ep { - phys = <&serdes1_pcie_link>; - phy-names = "pcie-phy"; - num-lanes = <2>; - status = "disabled"; -}; - -&pcie2_ep { - phys = <&serdes2_pcie_link>; - phy-names = "pcie-phy"; - num-lanes = <2>; - status = "disabled"; -}; - &pcie3_rc { status = "disabled"; }; -&pcie3_ep { - status = "disabled"; -}; - &icssg0_mdio { status = "disabled"; }; diff --git a/arch/arm64/boot/dts/ti/k3-j721e-main.dtsi b/arch/arm64/boot/dts/ti/k3-j721e-main.dtsi index c249cc3d1fba..5ca0ddd82bfc 100644 --- a/arch/arm64/boot/dts/ti/k3-j721e-main.dtsi +++ b/arch/arm64/boot/dts/ti/k3-j721e-main.dtsi @@ -816,26 +816,6 @@ dma-ranges = <0x02000000 0x0 0x0 0x0 0x0 0x10000 0x0>; }; - pcie0_ep: pcie-ep@2900000 { - compatible = "ti,j721e-pcie-ep"; - reg = <0x00 0x02900000 0x00 0x1000>, - <0x00 0x02907000 0x00 0x400>, - <0x00 0x0d000000 0x00 0x00800000>, - <0x00 0x10000000 0x00 0x08000000>; - reg-names = "intd_cfg", "user_cfg", "reg", "mem"; - interrupt-names = "link_state"; - interrupts = ; - ti,syscon-pcie-ctrl = <&scm_conf 0x4070>; - max-link-speed = <3>; - num-lanes = <2>; - power-domains = <&k3_pds 239 TI_SCI_PD_EXCLUSIVE>; - clocks = <&k3_clks 239 1>; - clock-names = "fck"; - max-functions = /bits/ 8 <6>; - max-virtual-functions = /bits/ 8 <4 4 4 4 0 0>; - dma-coherent; - }; - pcie1_rc: pcie@2910000 { compatible = "ti,j721e-pcie-host"; reg = <0x00 0x02910000 0x00 0x1000>, @@ -864,26 +844,6 @@ dma-ranges = <0x02000000 0x0 0x0 0x0 0x0 0x10000 0x0>; }; - pcie1_ep: pcie-ep@2910000 { - compatible = "ti,j721e-pcie-ep"; - reg = <0x00 0x02910000 0x00 0x1000>, - <0x00 0x02917000 0x00 0x400>, - <0x00 0x0d800000 0x00 0x00800000>, - <0x00 0x18000000 0x00 0x08000000>; - reg-names = "intd_cfg", "user_cfg", "reg", "mem"; - interrupt-names = "link_state"; - interrupts = ; - ti,syscon-pcie-ctrl = <&scm_conf 0x4074>; - max-link-speed = <3>; - num-lanes = <2>; - power-domains = <&k3_pds 240 TI_SCI_PD_EXCLUSIVE>; - clocks = <&k3_clks 240 1>; - clock-names = "fck"; - max-functions = /bits/ 8 <6>; - max-virtual-functions = /bits/ 8 <4 4 4 4 0 0>; - dma-coherent; - }; - pcie2_rc: pcie@2920000 { compatible = "ti,j721e-pcie-host"; reg = <0x00 0x02920000 0x00 0x1000>, @@ -912,26 +872,6 @@ dma-ranges = <0x02000000 0x0 0x0 0x0 0x0 0x10000 0x0>; }; - pcie2_ep: pcie-ep@2920000 { - compatible = "ti,j721e-pcie-ep"; - reg = <0x00 0x02920000 0x00 0x1000>, - <0x00 0x02927000 0x00 0x400>, - <0x00 0x0e000000 0x00 0x00800000>, - <0x44 0x00000000 0x00 0x08000000>; - reg-names = "intd_cfg", "user_cfg", "reg", "mem"; - interrupt-names = "link_state"; - interrupts = ; - ti,syscon-pcie-ctrl = <&scm_conf 0x4078>; - max-link-speed = <3>; - num-lanes = <2>; - power-domains = <&k3_pds 241 TI_SCI_PD_EXCLUSIVE>; - clocks = <&k3_clks 241 1>; - clock-names = "fck"; - max-functions = /bits/ 8 <6>; - max-virtual-functions = /bits/ 8 <4 4 4 4 0 0>; - dma-coherent; - }; - pcie3_rc: pcie@2930000 { compatible = "ti,j721e-pcie-host"; reg = <0x00 0x02930000 0x00 0x1000>, @@ -960,28 +900,6 @@ dma-ranges = <0x02000000 0x0 0x0 0x0 0x0 0x10000 0x0>; }; - pcie3_ep: pcie-ep@2930000 { - compatible = "ti,j721e-pcie-ep"; - reg = <0x00 0x02930000 0x00 0x1000>, - <0x00 0x02937000 0x00 0x400>, - <0x00 0x0e800000 0x00 0x00800000>, - <0x44 0x10000000 0x00 0x08000000>; - reg-names = "intd_cfg", "user_cfg", "reg", "mem"; - interrupt-names = "link_state"; - interrupts = ; - ti,syscon-pcie-ctrl = <&scm_conf 0x407c>; - max-link-speed = <3>; - num-lanes = <2>; - power-domains = <&k3_pds 242 TI_SCI_PD_EXCLUSIVE>; - clocks = <&k3_clks 242 1>; - clock-names = "fck"; - max-functions = /bits/ 8 <6>; - max-virtual-functions = /bits/ 8 <4 4 4 4 0 0>; - dma-coherent; - #address-cells = <2>; - #size-cells = <2>; - }; - serdes_wiz4: wiz@5050000 { compatible = "ti,am64-wiz-10g"; #address-cells = <1>; diff --git a/arch/arm64/boot/dts/ti/k3-j721e-sk.dts b/arch/arm64/boot/dts/ti/k3-j721e-sk.dts index ad7b45aeed0a..3fb24b68fe8e 100644 --- a/arch/arm64/boot/dts/ti/k3-j721e-sk.dts +++ b/arch/arm64/boot/dts/ti/k3-j721e-sk.dts @@ -895,35 +895,11 @@ status = "disabled"; }; -&pcie0_ep { - status = "disabled"; - phys = <&serdes0_pcie_link>; - phy-names = "pcie-phy"; - num-lanes = <1>; -}; - -&pcie1_ep { - status = "disabled"; - phys = <&serdes1_pcie_link>; - phy-names = "pcie-phy"; - num-lanes = <2>; -}; - -&pcie2_ep { - /* Unused */ - status = "disabled"; -}; - &pcie3_rc { /* Unused */ status = "disabled"; }; -&pcie3_ep { - /* Unused */ - status = "disabled"; -}; - &icssg0_mdio { status = "disabled"; }; -- cgit From 731c6deda85ffcac3629bea757a806306e335618 Mon Sep 17 00:00:00 2001 From: Andrew Davis Date: Mon, 15 May 2023 12:21:35 -0500 Subject: arm64: dts: ti: k3-j721e: Enable PCIe nodes at the board level PCIe nodes defined in the top-level J721e SoC dtsi files are incomplete and will not be functional unless they are extended with a SerDes PHY. And usually only one of the two modes can be used at a time as they share a SerDes link. As the PHY and mode is only known at the board integration level, these nodes should only be enabled when provided with this information. Disable the PCIe nodes in the dtsi files and only enable the ones that are actually pinned out on a given board. Signed-off-by: Andrew Davis Link: https://lore.kernel.org/r/20230515172137.474626-3-afd@ti.com Signed-off-by: Vignesh Raghavendra --- arch/arm64/boot/dts/ti/k3-j721e-beagleboneai64.dts | 16 +--------------- arch/arm64/boot/dts/ti/k3-j721e-common-proc-board.dts | 7 +++---- arch/arm64/boot/dts/ti/k3-j721e-main.dtsi | 4 ++++ arch/arm64/boot/dts/ti/k3-j721e-sk.dts | 12 ++---------- 4 files changed, 10 insertions(+), 29 deletions(-) diff --git a/arch/arm64/boot/dts/ti/k3-j721e-beagleboneai64.dts b/arch/arm64/boot/dts/ti/k3-j721e-beagleboneai64.dts index d77eeff0d81d..be0c5431119e 100644 --- a/arch/arm64/boot/dts/ti/k3-j721e-beagleboneai64.dts +++ b/arch/arm64/boot/dts/ti/k3-j721e-beagleboneai64.dts @@ -872,12 +872,8 @@ }; }; -&pcie0_rc { - /* Unused */ - status = "disabled"; -}; - &pcie1_rc { + status = "okay"; pinctrl-names = "default"; pinctrl-0 = <&pcie1_rst_pins_default>; phys = <&serdes1_pcie_link>; @@ -887,16 +883,6 @@ reset-gpios = <&main_gpio0 22 GPIO_ACTIVE_HIGH>; }; -&pcie2_rc { - /* Unused */ - status = "disabled"; -}; - -&pcie3_rc { - /* Unused */ - status = "disabled"; -}; - &icssg0_mdio { /* Unused */ status = "disabled"; diff --git a/arch/arm64/boot/dts/ti/k3-j721e-common-proc-board.dts b/arch/arm64/boot/dts/ti/k3-j721e-common-proc-board.dts index 7957d09bf04b..42579564c3bd 100644 --- a/arch/arm64/boot/dts/ti/k3-j721e-common-proc-board.dts +++ b/arch/arm64/boot/dts/ti/k3-j721e-common-proc-board.dts @@ -819,6 +819,7 @@ }; &pcie0_rc { + status = "okay"; reset-gpios = <&exp1 6 GPIO_ACTIVE_HIGH>; phys = <&serdes0_pcie_link>; phy-names = "pcie-phy"; @@ -826,6 +827,7 @@ }; &pcie1_rc { + status = "okay"; reset-gpios = <&exp1 2 GPIO_ACTIVE_HIGH>; phys = <&serdes1_pcie_link>; phy-names = "pcie-phy"; @@ -833,16 +835,13 @@ }; &pcie2_rc { + status = "okay"; reset-gpios = <&exp2 20 GPIO_ACTIVE_HIGH>; phys = <&serdes2_pcie_link>; phy-names = "pcie-phy"; num-lanes = <2>; }; -&pcie3_rc { - status = "disabled"; -}; - &icssg0_mdio { status = "disabled"; }; diff --git a/arch/arm64/boot/dts/ti/k3-j721e-main.dtsi b/arch/arm64/boot/dts/ti/k3-j721e-main.dtsi index 5ca0ddd82bfc..af5bc2d284ca 100644 --- a/arch/arm64/boot/dts/ti/k3-j721e-main.dtsi +++ b/arch/arm64/boot/dts/ti/k3-j721e-main.dtsi @@ -814,6 +814,7 @@ ranges = <0x01000000 0x0 0x10001000 0x0 0x10001000 0x0 0x0010000>, <0x02000000 0x0 0x10011000 0x0 0x10011000 0x0 0x7fef000>; dma-ranges = <0x02000000 0x0 0x0 0x0 0x0 0x10000 0x0>; + status = "disabled"; }; pcie1_rc: pcie@2910000 { @@ -842,6 +843,7 @@ ranges = <0x01000000 0x0 0x18001000 0x0 0x18001000 0x0 0x0010000>, <0x02000000 0x0 0x18011000 0x0 0x18011000 0x0 0x7fef000>; dma-ranges = <0x02000000 0x0 0x0 0x0 0x0 0x10000 0x0>; + status = "disabled"; }; pcie2_rc: pcie@2920000 { @@ -870,6 +872,7 @@ ranges = <0x01000000 0x0 0x00001000 0x44 0x00001000 0x0 0x0010000>, <0x02000000 0x0 0x00011000 0x44 0x00011000 0x0 0x7fef000>; dma-ranges = <0x02000000 0x0 0x0 0x0 0x0 0x10000 0x0>; + status = "disabled"; }; pcie3_rc: pcie@2930000 { @@ -898,6 +901,7 @@ ranges = <0x01000000 0x0 0x00001000 0x44 0x10001000 0x0 0x0010000>, <0x02000000 0x0 0x00011000 0x44 0x10011000 0x0 0x7fef000>; dma-ranges = <0x02000000 0x0 0x0 0x0 0x0 0x10000 0x0>; + status = "disabled"; }; serdes_wiz4: wiz@5050000 { diff --git a/arch/arm64/boot/dts/ti/k3-j721e-sk.dts b/arch/arm64/boot/dts/ti/k3-j721e-sk.dts index 3fb24b68fe8e..50364c05415e 100644 --- a/arch/arm64/boot/dts/ti/k3-j721e-sk.dts +++ b/arch/arm64/boot/dts/ti/k3-j721e-sk.dts @@ -871,6 +871,7 @@ }; &pcie0_rc { + status = "okay"; pinctrl-names = "default"; pinctrl-0 = <&ekey_reset_pins_default>; reset-gpios = <&main_gpio0 72 GPIO_ACTIVE_HIGH>; @@ -881,6 +882,7 @@ }; &pcie1_rc { + status = "okay"; pinctrl-names = "default"; pinctrl-0 = <&mkey_reset_pins_default>; reset-gpios = <&wkup_gpio0 11 GPIO_ACTIVE_HIGH>; @@ -890,16 +892,6 @@ num-lanes = <2>; }; -&pcie2_rc { - /* Unused */ - status = "disabled"; -}; - -&pcie3_rc { - /* Unused */ - status = "disabled"; -}; - &icssg0_mdio { status = "disabled"; }; -- cgit From 91f983ff7039fa2ff8ef153e118eec6d60f55e45 Mon Sep 17 00:00:00 2001 From: Andrew Davis Date: Mon, 15 May 2023 12:21:36 -0500 Subject: arm64: dts: ti: k3-am64: Enable Mailbox nodes at the board level Mailbox nodes defined in the top-level AM64x SoC dtsi files are incomplete and may not be functional unless they are extended with a chosen interrupt and connection to a remote processor. As the remote processors depend on memory nodes which are only known at the board integration level, these nodes should only be enabled when provided with the above information. Disable the Mailbox nodes in the dtsi files and only enable the ones that are actually used on a given board. Signed-off-by: Andrew Davis Link: https://lore.kernel.org/r/20230515172137.474626-4-afd@ti.com Signed-off-by: Vignesh Raghavendra --- arch/arm64/boot/dts/ti/k3-am64-main.dtsi | 6 ++++++ arch/arm64/boot/dts/ti/k3-am64-phycore-som.dtsi | 24 ------------------------ arch/arm64/boot/dts/ti/k3-am642-evm.dts | 18 ++++++------------ arch/arm64/boot/dts/ti/k3-am642-sk.dts | 18 ++++++------------ 4 files changed, 18 insertions(+), 48 deletions(-) diff --git a/arch/arm64/boot/dts/ti/k3-am64-main.dtsi b/arch/arm64/boot/dts/ti/k3-am64-main.dtsi index 9dea128893db..3c387d479b36 100644 --- a/arch/arm64/boot/dts/ti/k3-am64-main.dtsi +++ b/arch/arm64/boot/dts/ti/k3-am64-main.dtsi @@ -820,6 +820,7 @@ #mbox-cells = <1>; ti,mbox-num-users = <4>; ti,mbox-num-fifos = <16>; + status = "disabled"; }; mailbox0_cluster3: mailbox@29030000 { @@ -830,6 +831,7 @@ #mbox-cells = <1>; ti,mbox-num-users = <4>; ti,mbox-num-fifos = <16>; + status = "disabled"; }; mailbox0_cluster4: mailbox@29040000 { @@ -840,6 +842,7 @@ #mbox-cells = <1>; ti,mbox-num-users = <4>; ti,mbox-num-fifos = <16>; + status = "disabled"; }; mailbox0_cluster5: mailbox@29050000 { @@ -850,6 +853,7 @@ #mbox-cells = <1>; ti,mbox-num-users = <4>; ti,mbox-num-fifos = <16>; + status = "disabled"; }; mailbox0_cluster6: mailbox@29060000 { @@ -859,6 +863,7 @@ #mbox-cells = <1>; ti,mbox-num-users = <4>; ti,mbox-num-fifos = <16>; + status = "disabled"; }; mailbox0_cluster7: mailbox@29070000 { @@ -868,6 +873,7 @@ #mbox-cells = <1>; ti,mbox-num-users = <4>; ti,mbox-num-fifos = <16>; + status = "disabled"; }; main_r5fss0: r5fss@78000000 { diff --git a/arch/arm64/boot/dts/ti/k3-am64-phycore-som.dtsi b/arch/arm64/boot/dts/ti/k3-am64-phycore-som.dtsi index 8dfb6301b17d..7c2e26ef726c 100644 --- a/arch/arm64/boot/dts/ti/k3-am64-phycore-som.dtsi +++ b/arch/arm64/boot/dts/ti/k3-am64-phycore-som.dtsi @@ -160,30 +160,6 @@ status = "disabled"; }; -&mailbox0_cluster2 { - status = "disabled"; -}; - -&mailbox0_cluster3 { - status = "disabled"; -}; - -&mailbox0_cluster4 { - status = "disabled"; -}; - -&mailbox0_cluster5 { - status = "disabled"; -}; - -&mailbox0_cluster6 { - status = "disabled"; -}; - -&mailbox0_cluster7 { - status = "disabled"; -}; - &main_i2c0 { status = "okay"; pinctrl-names = "default"; diff --git a/arch/arm64/boot/dts/ti/k3-am642-evm.dts b/arch/arm64/boot/dts/ti/k3-am642-evm.dts index 3db740f78cd2..7c90e284e2bf 100644 --- a/arch/arm64/boot/dts/ti/k3-am642-evm.dts +++ b/arch/arm64/boot/dts/ti/k3-am642-evm.dts @@ -537,6 +537,8 @@ }; &mailbox0_cluster2 { + status = "okay"; + mbox_main_r5fss0_core0: mbox-main-r5fss0-core0 { ti,mbox-rx = <0 0 2>; ti,mbox-tx = <1 0 2>; @@ -548,11 +550,9 @@ }; }; -&mailbox0_cluster3 { - status = "disabled"; -}; - &mailbox0_cluster4 { + status = "okay"; + mbox_main_r5fss1_core0: mbox-main-r5fss1-core0 { ti,mbox-rx = <0 0 2>; ti,mbox-tx = <1 0 2>; @@ -564,21 +564,15 @@ }; }; -&mailbox0_cluster5 { - status = "disabled"; -}; - &mailbox0_cluster6 { + status = "okay"; + mbox_m4_0: mbox-m4-0 { ti,mbox-rx = <0 0 2>; ti,mbox-tx = <1 0 2>; }; }; -&mailbox0_cluster7 { - status = "disabled"; -}; - &main_r5fss0_core0 { mboxes = <&mailbox0_cluster2 &mbox_main_r5fss0_core0>; memory-region = <&main_r5fss0_core0_dma_memory_region>, diff --git a/arch/arm64/boot/dts/ti/k3-am642-sk.dts b/arch/arm64/boot/dts/ti/k3-am642-sk.dts index 003cff9a2799..f9ed22c5a472 100644 --- a/arch/arm64/boot/dts/ti/k3-am642-sk.dts +++ b/arch/arm64/boot/dts/ti/k3-am642-sk.dts @@ -535,6 +535,8 @@ }; &mailbox0_cluster2 { + status = "okay"; + mbox_main_r5fss0_core0: mbox-main-r5fss0-core0 { ti,mbox-rx = <0 0 2>; ti,mbox-tx = <1 0 2>; @@ -546,11 +548,9 @@ }; }; -&mailbox0_cluster3 { - status = "disabled"; -}; - &mailbox0_cluster4 { + status = "okay"; + mbox_main_r5fss1_core0: mbox-main-r5fss1-core0 { ti,mbox-rx = <0 0 2>; ti,mbox-tx = <1 0 2>; @@ -562,21 +562,15 @@ }; }; -&mailbox0_cluster5 { - status = "disabled"; -}; - &mailbox0_cluster6 { + status = "okay"; + mbox_m4_0: mbox-m4-0 { ti,mbox-rx = <0 0 2>; ti,mbox-tx = <1 0 2>; }; }; -&mailbox0_cluster7 { - status = "disabled"; -}; - &main_r5fss0_core0 { mboxes = <&mailbox0_cluster2 &mbox_main_r5fss0_core0>; memory-region = <&main_r5fss0_core0_dma_memory_region>, -- cgit From b0efb45d126ee914bafca37a582ae6574560dd25 Mon Sep 17 00:00:00 2001 From: Andrew Davis Date: Mon, 15 May 2023 12:21:37 -0500 Subject: arm64: dts: ti: k3-j721e: Enable MDIO nodes at the board level MDIO nodes defined in the top-level J721e SoC dtsi files are incomplete and will not be functional unless they are extended with a pinmux. As the attached PHY is only known about at the board integration level, these nodes should only be enabled when provided with this information. Disable the MDIO nodes in the dtsi files and only enable the ones that are actually pinned out on a given board. Signed-off-by: Andrew Davis Link: https://lore.kernel.org/r/20230515172137.474626-5-afd@ti.com Signed-off-by: Vignesh Raghavendra --- arch/arm64/boot/dts/ti/k3-j721e-beagleboneai64.dts | 10 ---------- arch/arm64/boot/dts/ti/k3-j721e-common-proc-board.dts | 8 -------- arch/arm64/boot/dts/ti/k3-j721e-main.dtsi | 2 ++ arch/arm64/boot/dts/ti/k3-j721e-sk.dts | 8 -------- 4 files changed, 2 insertions(+), 26 deletions(-) diff --git a/arch/arm64/boot/dts/ti/k3-j721e-beagleboneai64.dts b/arch/arm64/boot/dts/ti/k3-j721e-beagleboneai64.dts index be0c5431119e..a7b686cab3e6 100644 --- a/arch/arm64/boot/dts/ti/k3-j721e-beagleboneai64.dts +++ b/arch/arm64/boot/dts/ti/k3-j721e-beagleboneai64.dts @@ -883,16 +883,6 @@ reset-gpios = <&main_gpio0 22 GPIO_ACTIVE_HIGH>; }; -&icssg0_mdio { - /* Unused */ - status = "disabled"; -}; - -&icssg1_mdio { - /* Unused */ - status = "disabled"; -}; - &ufs_wrapper { status = "disabled"; }; diff --git a/arch/arm64/boot/dts/ti/k3-j721e-common-proc-board.dts b/arch/arm64/boot/dts/ti/k3-j721e-common-proc-board.dts index 42579564c3bd..7f9bd6bb004e 100644 --- a/arch/arm64/boot/dts/ti/k3-j721e-common-proc-board.dts +++ b/arch/arm64/boot/dts/ti/k3-j721e-common-proc-board.dts @@ -842,14 +842,6 @@ num-lanes = <2>; }; -&icssg0_mdio { - status = "disabled"; -}; - -&icssg1_mdio { - status = "disabled"; -}; - &mcu_mcan0 { status = "okay"; pinctrl-names = "default"; diff --git a/arch/arm64/boot/dts/ti/k3-j721e-main.dtsi b/arch/arm64/boot/dts/ti/k3-j721e-main.dtsi index af5bc2d284ca..5f35f823a8fa 100644 --- a/arch/arm64/boot/dts/ti/k3-j721e-main.dtsi +++ b/arch/arm64/boot/dts/ti/k3-j721e-main.dtsi @@ -2015,6 +2015,7 @@ #address-cells = <1>; #size-cells = <0>; bus_freq = <1000000>; + status = "disabled"; }; }; @@ -2156,6 +2157,7 @@ #address-cells = <1>; #size-cells = <0>; bus_freq = <1000000>; + status = "disabled"; }; }; diff --git a/arch/arm64/boot/dts/ti/k3-j721e-sk.dts b/arch/arm64/boot/dts/ti/k3-j721e-sk.dts index 50364c05415e..72804a03c10d 100644 --- a/arch/arm64/boot/dts/ti/k3-j721e-sk.dts +++ b/arch/arm64/boot/dts/ti/k3-j721e-sk.dts @@ -892,14 +892,6 @@ num-lanes = <2>; }; -&icssg0_mdio { - status = "disabled"; -}; - -&icssg1_mdio { - status = "disabled"; -}; - &ufs_wrapper { status = "disabled"; }; -- cgit From d93036b47f354b7acb95aad5c91e9becbe4e9f61 Mon Sep 17 00:00:00 2001 From: Vaishnav Achath Date: Sat, 13 May 2023 18:03:10 +0530 Subject: arm64: dts: ti: k3-j721e-mcu-wakeup: Add HyperBus node J721E has a Flash SubSystem that has one OSPI and one HyperBus with muxed datapath and another independent OSPI. Add DT nodes for HyperBus controller and keep it disabled and model the data path selection mux as a reg-mux. Signed-off-by: Vaishnav Achath Link: https://lore.kernel.org/r/20230513123313.11462-2-vaishnav.a@ti.com Signed-off-by: Vignesh Raghavendra --- arch/arm64/boot/dts/ti/k3-j721e-mcu-wakeup.dtsi | 21 +++++++++++++++++++++ 1 file changed, 21 insertions(+) diff --git a/arch/arm64/boot/dts/ti/k3-j721e-mcu-wakeup.dtsi b/arch/arm64/boot/dts/ti/k3-j721e-mcu-wakeup.dtsi index 8d86f23b2123..bfe3907b4b55 100644 --- a/arch/arm64/boot/dts/ti/k3-j721e-mcu-wakeup.dtsi +++ b/arch/arm64/boot/dts/ti/k3-j721e-mcu-wakeup.dtsi @@ -181,6 +181,27 @@ #size-cells = <2>; ranges; + hbmc_mux: mux-controller@47000004 { + compatible = "reg-mux"; + reg = <0x00 0x47000004 0x00 0x2>; + #mux-control-cells = <1>; + mux-reg-masks = <0x4 0x2>; /* HBMC select */ + }; + + hbmc: hyperbus@47034000 { + compatible = "ti,am654-hbmc"; + reg = <0x00 0x47034000 0x00 0x100>, + <0x05 0x00000000 0x01 0x0000000>; + power-domains = <&k3_pds 102 TI_SCI_PD_EXCLUSIVE>; + clocks = <&k3_clks 102 0>; + assigned-clocks = <&k3_clks 102 5>; + assigned-clock-rates = <333333333>; + #address-cells = <2>; + #size-cells = <1>; + mux-controls = <&hbmc_mux 0>; + status = "disabled"; + }; + ospi0: spi@47040000 { compatible = "ti,am654-ospi", "cdns,qspi-nor"; reg = <0x0 0x47040000 0x0 0x100>, -- cgit From 0979c0069cb669528d13818410de9f0dd41585f3 Mon Sep 17 00:00:00 2001 From: Vaishnav Achath Date: Sat, 13 May 2023 18:03:11 +0530 Subject: arm64: dts: ti: k3-j721e-som-p0: Add HyperFlash node J721E SoM has a HyperFlash and HyperRam connected to HyperBus memory controller, add corresponding node, pinmux and partitions for the same. HyperBus is muxed with OSPI and only one controller can be active at a time, therefore keep HyperBus node disabled. Bootloader will detect the external mux state through a wkup gpio and enable the node as required. Signed-off-by: Vaishnav Achath Link: https://lore.kernel.org/r/20230513123313.11462-3-vaishnav.a@ti.com Signed-off-by: Vignesh Raghavendra --- arch/arm64/boot/dts/ti/k3-j721e-som-p0.dtsi | 71 +++++++++++++++++++++++++++++ 1 file changed, 71 insertions(+) diff --git a/arch/arm64/boot/dts/ti/k3-j721e-som-p0.dtsi b/arch/arm64/boot/dts/ti/k3-j721e-som-p0.dtsi index e289d5b44356..b96e5fdddb4b 100644 --- a/arch/arm64/boot/dts/ti/k3-j721e-som-p0.dtsi +++ b/arch/arm64/boot/dts/ti/k3-j721e-som-p0.dtsi @@ -165,6 +165,25 @@ J721E_WKUP_IOPAD(0x002c, PIN_OUTPUT, 0) /* MCU_OSPI0_CSn0 */ >; }; + + mcu_fss0_hpb0_pins_default: mcu-fss0-hpb0-pins-default { + pinctrl-single,pins = < + J721E_WKUP_IOPAD(0x0, PIN_OUTPUT, 1) /* MCU_HYPERBUS0_CK */ + J721E_WKUP_IOPAD(0x4, PIN_OUTPUT, 1) /* MCU_HYPERBUS0_CKn */ + J721E_WKUP_IOPAD(0x2c, PIN_OUTPUT, 1) /* MCU_HYPERBUS0_CSn0 */ + J721E_WKUP_IOPAD(0x54, PIN_OUTPUT, 3) /* MCU_HYPERBUS0_CSn1 */ + J721E_WKUP_IOPAD(0x30, PIN_OUTPUT, 1) /* MCU_HYPERBUS0_RESETn */ + J721E_WKUP_IOPAD(0x8, PIN_INPUT, 1) /* MCU_HYPERBUS0_RWDS */ + J721E_WKUP_IOPAD(0xc, PIN_INPUT, 1) /* MCU_HYPERBUS0_DQ0 */ + J721E_WKUP_IOPAD(0x10, PIN_INPUT, 1) /* MCU_HYPERBUS0_DQ1 */ + J721E_WKUP_IOPAD(0x14, PIN_INPUT, 1) /* MCU_HYPERBUS0_DQ2 */ + J721E_WKUP_IOPAD(0x18, PIN_INPUT, 1) /* MCU_HYPERBUS0_DQ3 */ + J721E_WKUP_IOPAD(0x1c, PIN_INPUT, 1) /* MCU_HYPERBUS0_DQ4 */ + J721E_WKUP_IOPAD(0x20, PIN_INPUT, 1) /* MCU_HYPERBUS0_DQ5 */ + J721E_WKUP_IOPAD(0x24, PIN_INPUT, 1) /* MCU_HYPERBUS0_DQ6 */ + J721E_WKUP_IOPAD(0x28, PIN_INPUT, 1) /* MCU_HYPERBUS0_DQ7 */ + >; + }; }; &ospi0 { @@ -185,6 +204,58 @@ }; }; +&hbmc { + /* OSPI and HBMC are muxed inside FSS, Bootloader will enable + * appropriate node based on board detection + */ + status = "disabled"; + pinctrl-names = "default"; + pinctrl-0 = <&mcu_fss0_hpb0_pins_default>; + ranges = <0x00 0x00 0x05 0x00000000 0x4000000>, /* 64MB Flash on CS0 */ + <0x01 0x00 0x05 0x04000000 0x800000>; /* 8MB RAM on CS1 */ + + flash@0,0 { + compatible = "cypress,hyperflash", "cfi-flash"; + reg = <0x00 0x00 0x4000000>; + + partitions { + compatible = "fixed-partitions"; + #address-cells = <1>; + #size-cells = <1>; + + partition@0 { + label = "hbmc.tiboot3"; + reg = <0x0 0x80000>; + }; + + partition@80000 { + label = "hbmc.tispl"; + reg = <0x80000 0x200000>; + }; + + partition@280000 { + label = "hbmc.u-boot"; + reg = <0x280000 0x400000>; + }; + + partition@680000 { + label = "hbmc.env"; + reg = <0x680000 0x40000>; + }; + + partition@6c0000 { + label = "hbmc.sysfw"; + reg = <0x6c0000 0x100000>; + }; + + partition@800000 { + label = "hbmc.rootfs"; + reg = <0x800000 0x3800000>; + }; + }; + }; +}; + &mailbox0_cluster0 { status = "okay"; interrupts = <436>; -- cgit From be8be0d036b2fed1f705931ac3901077039b7496 Mon Sep 17 00:00:00 2001 From: Vaishnav Achath Date: Sat, 13 May 2023 18:03:12 +0530 Subject: arm64: dts: ti: k3-j7200-common-proc-board: Add OSPI/Hyperflash select pinmux J7200 common processor board has an onboard mux for selecting whether the OSPI signals are externally routed to OSPI flash or Hyperflash. The mux state signal input is tied to WKUP_GPIO0_6 and is used by bootloader for enabling the corresponding node accordingly. Add pinmux for the same. Signed-off-by: Vaishnav Achath Link: https://lore.kernel.org/r/20230513123313.11462-4-vaishnav.a@ti.com Signed-off-by: Vignesh Raghavendra --- arch/arm64/boot/dts/ti/k3-j7200-common-proc-board.dts | 11 +++++++++++ 1 file changed, 11 insertions(+) diff --git a/arch/arm64/boot/dts/ti/k3-j7200-common-proc-board.dts b/arch/arm64/boot/dts/ti/k3-j7200-common-proc-board.dts index 0cc0e1dc40c5..e1017027d649 100644 --- a/arch/arm64/boot/dts/ti/k3-j7200-common-proc-board.dts +++ b/arch/arm64/boot/dts/ti/k3-j7200-common-proc-board.dts @@ -97,6 +97,12 @@ >; }; + wkup_gpio_pins_default: wkup-gpio-pins-default { + pinctrl-single,pins = < + J721E_WKUP_IOPAD(0x70, PIN_INPUT, 7) /* (C14) WKUP_GPIO0_6 */ + >; + }; + mcu_mdio_pins_default: mcu-mdio1-pins-default { pinctrl-single,pins = < J721E_WKUP_IOPAD(0x0034, PIN_OUTPUT, 0) /* (L1) MCU_MDIO0_MDC */ @@ -186,6 +192,11 @@ status = "disabled"; }; +&wkup_gpio0 { + pinctrl-names = "default"; + pinctrl-0 = <&wkup_gpio_pins_default>; +}; + &wkup_gpio1 { status = "disabled"; }; -- cgit From 58cd171af4d7e27525b1924b72100cba98d88d2a Mon Sep 17 00:00:00 2001 From: Vaishnav Achath Date: Sat, 13 May 2023 18:03:13 +0530 Subject: arm64: dts: ti: k3-j721e-common-proc-board: Add OSPI/Hyperflash select pinmux J721E common processor board has an onboard mux for selecting whether the OSPI signals are externally routed to OSPI flash or Hyperflash. The mux state signal input is tied to WKUP_GPIO0_8 and is used by bootloader for enabling the corresponding node accordingly. Add pinmux for the same. Signed-off-by: Vaishnav Achath Link: https://lore.kernel.org/r/20230513123313.11462-5-vaishnav.a@ti.com Signed-off-by: Vignesh Raghavendra --- arch/arm64/boot/dts/ti/k3-j721e-common-proc-board.dts | 11 +++++++++++ 1 file changed, 11 insertions(+) diff --git a/arch/arm64/boot/dts/ti/k3-j721e-common-proc-board.dts b/arch/arm64/boot/dts/ti/k3-j721e-common-proc-board.dts index 7f9bd6bb004e..dea451e10f2a 100644 --- a/arch/arm64/boot/dts/ti/k3-j721e-common-proc-board.dts +++ b/arch/arm64/boot/dts/ti/k3-j721e-common-proc-board.dts @@ -362,6 +362,12 @@ J721E_WKUP_IOPAD(0xb8, PIN_INPUT, 7) /* (F28) WKUP_GPIO0_2 */ >; }; + + wkup_gpio_pins_default: wkup-gpio-pins-default { + pinctrl-single,pins = < + J721E_WKUP_IOPAD(0xd0, PIN_INPUT, 7) /* (C14) WKUP_GPIO0_8 */ + >; + }; }; &wkup_uart0 { @@ -419,6 +425,11 @@ status = "disabled"; }; +&wkup_gpio0 { + pinctrl-names = "default"; + pinctrl-0 = <&wkup_gpio_pins_default>; +}; + &wkup_gpio1 { status = "disabled"; }; -- cgit From 2dc39c564982f2ca77a9589a3d9906ecaf5a42e4 Mon Sep 17 00:00:00 2001 From: Wadim Egorov Date: Fri, 5 May 2023 15:10:12 +0200 Subject: arm64: dts: ti: Add LED controller to phyBOARD-Electra With commit 9f6ffd0da650 ("dt-bindings: leds: Convert PCA9532 to dtschema"), we can now add the LED controller without introducing new dtbs_check warnings. Add missing I2C LED controller. Signed-off-by: Wadim Egorov Link: https://lore.kernel.org/r/20230505131012.2027309-1-w.egorov@phytec.de Signed-off-by: Vignesh Raghavendra --- .../boot/dts/ti/k3-am642-phyboard-electra-rdk.dts | 21 +++++++++++++++++++++ 1 file changed, 21 insertions(+) diff --git a/arch/arm64/boot/dts/ti/k3-am642-phyboard-electra-rdk.dts b/arch/arm64/boot/dts/ti/k3-am642-phyboard-electra-rdk.dts index 8d3114d14a8b..8199ac06c09a 100644 --- a/arch/arm64/boot/dts/ti/k3-am642-phyboard-electra-rdk.dts +++ b/arch/arm64/boot/dts/ti/k3-am642-phyboard-electra-rdk.dts @@ -15,6 +15,7 @@ #include #include #include +#include #include #include #include "k3-am642.dtsi" @@ -210,6 +211,26 @@ pagesize = <16>; reg = <0x51>; }; + + led-controller@62 { + compatible = "nxp,pca9533"; + reg = <0x62>; + + led-3 { + label = "red:user"; + type = ; + }; + + led-4 { + label = "green:user"; + type = ; + }; + + led-5 { + label = "blue:user"; + type = ; + }; + }; }; &main_mcan0 { -- cgit From 8758109d135401c8afea0d0e3c51e7a52c843b7b Mon Sep 17 00:00:00 2001 From: Apurva Nandan Date: Thu, 4 May 2023 13:33:04 +0530 Subject: arm64: dts: ti: k3-j784s4-mcu-wakeup: Add FSS OSPI0 and FSS OSPI1 TI K3 J784S4 has the Cadence OSPI controllers OSPI0 and OSPI1 on FSS bus for interfacing with OSPI flashes. Add the nodes to allow using SPI flashes. Signed-off-by: Apurva Nandan Link: https://lore.kernel.org/r/20230504080305.38986-2-a-nandan@ti.com Signed-off-by: Vignesh Raghavendra --- arch/arm64/boot/dts/ti/k3-j784s4-mcu-wakeup.dtsi | 41 ++++++++++++++++++++++++ 1 file changed, 41 insertions(+) diff --git a/arch/arm64/boot/dts/ti/k3-j784s4-mcu-wakeup.dtsi b/arch/arm64/boot/dts/ti/k3-j784s4-mcu-wakeup.dtsi index d640e31a8335..ae9a8856bc40 100644 --- a/arch/arm64/boot/dts/ti/k3-j784s4-mcu-wakeup.dtsi +++ b/arch/arm64/boot/dts/ti/k3-j784s4-mcu-wakeup.dtsi @@ -430,4 +430,45 @@ compatible = "ti,am3359-adc"; }; }; + + fss: bus@47000000 { + compatible = "simple-bus"; + reg = <0x00 0x47000000 0x00 0x100>; + #address-cells = <2>; + #size-cells = <2>; + ranges; + + ospi0: spi@47040000 { + compatible = "ti,am654-ospi", "cdns,qspi-nor"; + reg = <0x00 0x47040000 0x00 0x100>, + <0x05 0x0000000 0x01 0x0000000>; + interrupts = ; + cdns,fifo-depth = <256>; + cdns,fifo-width = <4>; + cdns,trigger-address = <0x0>; + clocks = <&k3_clks 161 7>; + assigned-clocks = <&k3_clks 161 7>; + assigned-clock-parents = <&k3_clks 161 9>; + assigned-clock-rates = <166666666>; + power-domains = <&k3_pds 161 TI_SCI_PD_EXCLUSIVE>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + ospi1: spi@47050000 { + compatible = "ti,am654-ospi", "cdns,qspi-nor"; + reg = <0x00 0x47050000 0x00 0x100>, + <0x07 0x0000000 0x01 0x0000000>; + interrupts = ; + cdns,fifo-depth = <256>; + cdns,fifo-width = <4>; + cdns,trigger-address = <0x0>; + clocks = <&k3_clks 162 7>; + power-domains = <&k3_pds 162 TI_SCI_PD_EXCLUSIVE>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + }; }; -- cgit From 150ce1b10740c10f87e90e485bc279c205e3f731 Mon Sep 17 00:00:00 2001 From: Apurva Nandan Date: Thu, 4 May 2023 13:33:05 +0530 Subject: arm64: dts: ti: k3-j784s4-evm: Add support for OSPI and QSPI flashes J784S4 has S28HS512T OSPI flash connected to OSPI0 and MT25QU512A QSPI flash connected to OSPI1, enable support for the same. Also describe the partition information according to the offsets in the bootloader. Co-developed-by: Vaishnav Achath Signed-off-by: Vaishnav Achath Signed-off-by: Apurva Nandan Link: https://lore.kernel.org/r/20230504080305.38986-3-a-nandan@ti.com Signed-off-by: Vignesh Raghavendra --- arch/arm64/boot/dts/ti/k3-j784s4-evm.dts | 158 +++++++++++++++++++++++++++++++ 1 file changed, 158 insertions(+) diff --git a/arch/arm64/boot/dts/ti/k3-j784s4-evm.dts b/arch/arm64/boot/dts/ti/k3-j784s4-evm.dts index 64b58e0d2e5d..8271ac16b319 100644 --- a/arch/arm64/boot/dts/ti/k3-j784s4-evm.dts +++ b/arch/arm64/boot/dts/ti/k3-j784s4-evm.dts @@ -337,12 +337,170 @@ }; }; +&wkup_pmx0 { + mcu_fss0_ospi0_pins_default: mcu-fss0-ospi0-pins-default { + pinctrl-single,pins = < + J784S4_WKUP_IOPAD(0x000, PIN_OUTPUT, 0) /* (E32) MCU_OSPI0_CLK */ + J784S4_WKUP_IOPAD(0x02c, PIN_OUTPUT, 0) /* (A32) MCU_OSPI0_CSn0 */ + J784S4_WKUP_IOPAD(0x00c, PIN_INPUT, 0) /* (B33) MCU_OSPI0_D0 */ + J784S4_WKUP_IOPAD(0x010, PIN_INPUT, 0) /* (B32) MCU_OSPI0_D1 */ + J784S4_WKUP_IOPAD(0x014, PIN_INPUT, 0) /* (C33) MCU_OSPI0_D2 */ + J784S4_WKUP_IOPAD(0x018, PIN_INPUT, 0) /* (C35) MCU_OSPI0_D3 */ + J784S4_WKUP_IOPAD(0x01c, PIN_INPUT, 0) /* (D33) MCU_OSPI0_D4 */ + J784S4_WKUP_IOPAD(0x020, PIN_INPUT, 0) /* (D34) MCU_OSPI0_D5 */ + J784S4_WKUP_IOPAD(0x024, PIN_INPUT, 0) /* (E34) MCU_OSPI0_D6 */ + J784S4_WKUP_IOPAD(0x028, PIN_INPUT, 0) /* (E33) MCU_OSPI0_D7 */ + J784S4_WKUP_IOPAD(0x008, PIN_INPUT, 0) /* (C34) MCU_OSPI0_DQS */ + J784S4_WKUP_IOPAD(0x03c, PIN_OUTPUT, 6) /* (C32) MCU_OSPI0_CSn3.MCU_OSPI0_ECC_FAIL */ + J784S4_WKUP_IOPAD(0x038, PIN_OUTPUT, 6) /* (B34) MCU_OSPI0_CSn2.MCU_OSPI0_RESET_OUT0 */ + >; + }; + + mcu_fss0_ospi1_pins_default: mcu-fss0-ospi1-pins-default { + pinctrl-single,pins = < + J784S4_WKUP_IOPAD(0x040, PIN_OUTPUT, 0) /* (F32) MCU_OSPI1_CLK */ + J784S4_WKUP_IOPAD(0x05c, PIN_OUTPUT, 0) /* (G32) MCU_OSPI1_CSn0 */ + J784S4_WKUP_IOPAD(0x04c, PIN_INPUT, 0) /* (E35) MCU_OSPI1_D0 */ + J784S4_WKUP_IOPAD(0x050, PIN_INPUT, 0) /* (D31) MCU_OSPI1_D1 */ + J784S4_WKUP_IOPAD(0x054, PIN_INPUT, 0) /* (G31) MCU_OSPI1_D2 */ + J784S4_WKUP_IOPAD(0x058, PIN_INPUT, 0) /* (F33) MCU_OSPI1_D3 */ + J784S4_WKUP_IOPAD(0x048, PIN_INPUT, 0) /* (F31) MCU_OSPI1_DQS */ + J784S4_WKUP_IOPAD(0x044, PIN_INPUT, 0) /* (C31) MCU_OSPI1_LBCLKO */ + >; + }; +}; + &main_uart8 { status = "okay"; pinctrl-names = "default"; pinctrl-0 = <&main_uart8_pins_default>; }; +&fss { + status = "okay"; +}; + +&ospi0 { + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&mcu_fss0_ospi0_pins_default>; + + flash@0 { + compatible = "jedec,spi-nor"; + reg = <0x0>; + spi-tx-bus-width = <8>; + spi-rx-bus-width = <8>; + spi-max-frequency = <25000000>; + cdns,tshsl-ns = <60>; + cdns,tsd2d-ns = <60>; + cdns,tchsh-ns = <60>; + cdns,tslch-ns = <60>; + cdns,read-delay = <4>; + + partitions { + compatible = "fixed-partitions"; + #address-cells = <1>; + #size-cells = <1>; + + partition@0 { + label = "ospi.tiboot3"; + reg = <0x0 0x80000>; + }; + + partition@80000 { + label = "ospi.tispl"; + reg = <0x80000 0x200000>; + }; + + partition@280000 { + label = "ospi.u-boot"; + reg = <0x280000 0x400000>; + }; + + partition@680000 { + label = "ospi.env"; + reg = <0x680000 0x40000>; + }; + + partition@6c0000 { + label = "ospi.env.backup"; + reg = <0x6c0000 0x40000>; + }; + + partition@800000 { + label = "ospi.rootfs"; + reg = <0x800000 0x37c0000>; + }; + + partition@3fc0000 { + label = "ospi.phypattern"; + reg = <0x3fc0000 0x40000>; + }; + }; + }; +}; + +&ospi1 { + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&mcu_fss0_ospi1_pins_default>; + + flash@0{ + compatible = "jedec,spi-nor"; + reg = <0x0>; + spi-tx-bus-width = <1>; + spi-rx-bus-width = <4>; + spi-max-frequency = <40000000>; + cdns,tshsl-ns = <60>; + cdns,tsd2d-ns = <60>; + cdns,tchsh-ns = <60>; + cdns,tslch-ns = <60>; + cdns,read-delay = <2>; + + partitions { + compatible = "fixed-partitions"; + #address-cells = <1>; + #size-cells = <1>; + + partition@0 { + label = "qspi.tiboot3"; + reg = <0x0 0x80000>; + }; + + partition@80000 { + label = "qspi.tispl"; + reg = <0x80000 0x200000>; + }; + + partition@280000 { + label = "qspi.u-boot"; + reg = <0x280000 0x400000>; + }; + + partition@680000 { + label = "qspi.env"; + reg = <0x680000 0x40000>; + }; + + partition@6c0000 { + label = "qspi.env.backup"; + reg = <0x6c0000 0x40000>; + }; + + partition@800000 { + label = "qspi.rootfs"; + reg = <0x800000 0x37c0000>; + }; + + partition@3fc0000 { + label = "qspi.phypattern"; + reg = <0x3fc0000 0x40000>; + }; + }; + + }; +}; + &main_i2c0 { status = "okay"; pinctrl-names = "default"; -- cgit From e96b5e98482354be3ef666704964f8c2ed6b6e8d Mon Sep 17 00:00:00 2001 From: Vaishnav Achath Date: Sat, 13 May 2023 19:47:07 +0530 Subject: arm64: dts: ti: k3-j721e: Describe OSPI and QSPI flash partition info Describe OSPI and QSPI flash partition information through device tree, this helps to remove passing partition information through the mtdparts commandline parameter which requires maintaining the partition information in a string format. J721E SoM has a MT35 64 MiB OSPI flash and MT25 64 MiB QSPI flash both with sector size of 128 KiB thus the size of the smallest partition is chosen as 128KiB, the partition names and offsets are chosen according to the corresponding name and offsets in bootloader. Signed-off-by: Vaishnav Achath Link: https://lore.kernel.org/r/20230513141712.27346-2-vaishnav.a@ti.com Signed-off-by: Vignesh Raghavendra --- .../boot/dts/ti/k3-j721e-common-proc-board.dts | 46 ++++++++++++++++++++++ arch/arm64/boot/dts/ti/k3-j721e-som-p0.dtsi | 46 ++++++++++++++++++++++ 2 files changed, 92 insertions(+) diff --git a/arch/arm64/boot/dts/ti/k3-j721e-common-proc-board.dts b/arch/arm64/boot/dts/ti/k3-j721e-common-proc-board.dts index dea451e10f2a..fa6ac3475290 100644 --- a/arch/arm64/boot/dts/ti/k3-j721e-common-proc-board.dts +++ b/arch/arm64/boot/dts/ti/k3-j721e-common-proc-board.dts @@ -523,6 +523,52 @@ cdns,tchsh-ns = <60>; cdns,tslch-ns = <60>; cdns,read-delay = <2>; + + partitions { + compatible = "fixed-partitions"; + #address-cells = <1>; + #size-cells = <1>; + + partition@0 { + label = "qspi.tiboot3"; + reg = <0x0 0x80000>; + }; + + partition@80000 { + label = "qspi.tispl"; + reg = <0x80000 0x200000>; + }; + + partition@280000 { + label = "qspi.u-boot"; + reg = <0x280000 0x400000>; + }; + + partition@680000 { + label = "qspi.env"; + reg = <0x680000 0x20000>; + }; + + partition@6a0000 { + label = "qspi.env.backup"; + reg = <0x6a0000 0x20000>; + }; + + partition@6c0000 { + label = "qspi.sysfw"; + reg = <0x6c0000 0x100000>; + }; + + partition@800000 { + label = "qspi.rootfs"; + reg = <0x800000 0x37c0000>; + }; + + partition@3fe0000 { + label = "qspi.phypattern"; + reg = <0x3fe0000 0x20000>; + }; + }; }; }; diff --git a/arch/arm64/boot/dts/ti/k3-j721e-som-p0.dtsi b/arch/arm64/boot/dts/ti/k3-j721e-som-p0.dtsi index b96e5fdddb4b..67e52ee3a8bd 100644 --- a/arch/arm64/boot/dts/ti/k3-j721e-som-p0.dtsi +++ b/arch/arm64/boot/dts/ti/k3-j721e-som-p0.dtsi @@ -201,6 +201,52 @@ cdns,tchsh-ns = <60>; cdns,tslch-ns = <60>; cdns,read-delay = <0>; + + partitions { + compatible = "fixed-partitions"; + #address-cells = <1>; + #size-cells = <1>; + + partition@0 { + label = "ospi.tiboot3"; + reg = <0x0 0x80000>; + }; + + partition@80000 { + label = "ospi.tispl"; + reg = <0x80000 0x200000>; + }; + + partition@280000 { + label = "ospi.u-boot"; + reg = <0x280000 0x400000>; + }; + + partition@680000 { + label = "ospi.env"; + reg = <0x680000 0x20000>; + }; + + partition@6a0000 { + label = "ospi.env.backup"; + reg = <0x6a0000 0x20000>; + }; + + partition@6c0000 { + label = "ospi.sysfw"; + reg = <0x6c0000 0x100000>; + }; + + partition@800000 { + label = "ospi.rootfs"; + reg = <0x800000 0x37c0000>; + }; + + partition@3fe0000 { + label = "ospi.phypattern"; + reg = <0x3fe0000 0x20000>; + }; + }; }; }; -- cgit From 2f1023d5f050e4b83b5e71fb9ad5a81e95e4123d Mon Sep 17 00:00:00 2001 From: Vaishnav Achath Date: Sat, 13 May 2023 19:47:08 +0530 Subject: arm64: dts: ti: k3-j721e-sk: Describe OSPI flash partition info Describe OSPI flash partition information through device tree, this helps to remove passing partition information through the mtdparts commandline parameter which requires maintaining the partition information in a string format. J721E SK has a S28 64 MiB OSPI flash with sector size of 256 KiB thus the size of the smallest partition is chosen as 256 KiB, the partition names and offsets are chosen according to the corresponding name and offsets in bootloader. Signed-off-by: Vaishnav Achath Link: https://lore.kernel.org/r/20230513141712.27346-3-vaishnav.a@ti.com Signed-off-by: Vignesh Raghavendra --- arch/arm64/boot/dts/ti/k3-j721e-sk.dts | 46 ++++++++++++++++++++++++++++++++++ 1 file changed, 46 insertions(+) diff --git a/arch/arm64/boot/dts/ti/k3-j721e-sk.dts b/arch/arm64/boot/dts/ti/k3-j721e-sk.dts index 72804a03c10d..ffb9820cb61f 100644 --- a/arch/arm64/boot/dts/ti/k3-j721e-sk.dts +++ b/arch/arm64/boot/dts/ti/k3-j721e-sk.dts @@ -568,6 +568,52 @@ cdns,tchsh-ns = <60>; cdns,tslch-ns = <60>; cdns,read-delay = <4>; + + partitions { + compatible = "fixed-partitions"; + #address-cells = <1>; + #size-cells = <1>; + + partition@0 { + label = "ospi.tiboot3"; + reg = <0x0 0x80000>; + }; + + partition@80000 { + label = "ospi.tispl"; + reg = <0x80000 0x200000>; + }; + + partition@280000 { + label = "ospi.u-boot"; + reg = <0x280000 0x400000>; + }; + + partition@680000 { + label = "ospi.env"; + reg = <0x680000 0x40000>; + }; + + partition@6c0000 { + label = "ospi.sysfw"; + reg = <0x6c0000 0x100000>; + }; + + partition@7c0000 { + label = "ospi.env.backup"; + reg = <0x7c0000 0x40000>; + }; + + partition@800000 { + label = "ospi.rootfs"; + reg = <0x800000 0x37c0000>; + }; + + partition@3fc0000 { + label = "ospi.phypattern"; + reg = <0x3fc0000 0x40000>; + }; + }; }; }; -- cgit From 7f80deb0c6c779ee19996918962c8cad058efd10 Mon Sep 17 00:00:00 2001 From: Vaishnav Achath Date: Sat, 13 May 2023 19:47:09 +0530 Subject: arm64: dts: ti: k3-j7200-som: Describe OSPI and Hyperflash partition info Describe OSPI and Hyperflash partition information through device tree, this helps to remove passing partition information through the mtdparts commandline parameter which requires maintaining the partition information in a string format. J7200 SoM has a S28 64 MiB OSPI flash with sector size of 256 KiB thus the size of the smallest partition is chosen as 256 KiB, the SoM also has a 64 MiB Hyperflash present on it, the partition names and offsets are chosen according to the corresponding name and offsets in bootloader. Signed-off-by: Vaishnav Achath Link: https://lore.kernel.org/r/20230513141712.27346-4-vaishnav.a@ti.com Signed-off-by: Vignesh Raghavendra --- arch/arm64/boot/dts/ti/k3-j7200-som-p0.dtsi | 72 +++++++++++++++++++++++++++++ 1 file changed, 72 insertions(+) diff --git a/arch/arm64/boot/dts/ti/k3-j7200-som-p0.dtsi b/arch/arm64/boot/dts/ti/k3-j7200-som-p0.dtsi index 269424154771..2a743b895074 100644 --- a/arch/arm64/boot/dts/ti/k3-j7200-som-p0.dtsi +++ b/arch/arm64/boot/dts/ti/k3-j7200-som-p0.dtsi @@ -149,6 +149,37 @@ flash@0,0 { compatible = "cypress,hyperflash", "cfi-flash"; reg = <0x00 0x00 0x4000000>; + + partitions { + compatible = "fixed-partitions"; + #address-cells = <1>; + #size-cells = <1>; + + partition@0 { + label = "hbmc.tiboot3"; + reg = <0x0 0x100000>; + }; + + partition@100000 { + label = "hbmc.tispl"; + reg = <0x100000 0x200000>; + }; + + partition@300000 { + label = "hbmc.u-boot"; + reg = <0x300000 0x400000>; + }; + + partition@700000 { + label = "hbmc.env"; + reg = <0x700000 0x40000>; + }; + + partition@800000 { + label = "hbmc.rootfs"; + reg = <0x800000 0x3800000>; + }; + }; }; }; @@ -250,5 +281,46 @@ cdns,tchsh-ns = <60>; cdns,tslch-ns = <60>; cdns,read-delay = <4>; + + partitions { + compatible = "fixed-partitions"; + #address-cells = <1>; + #size-cells = <1>; + + partition@0 { + label = "ospi.tiboot3"; + reg = <0x0 0x100000>; + }; + + partition@100000 { + label = "ospi.tispl"; + reg = <0x100000 0x200000>; + }; + + partition@300000 { + label = "ospi.u-boot"; + reg = <0x300000 0x400000>; + }; + + partition@700000 { + label = "ospi.env"; + reg = <0x700000 0x40000>; + }; + + partition@740000 { + label = "ospi.env.backup"; + reg = <0x740000 0x40000>; + }; + + partition@800000 { + label = "ospi.rootfs"; + reg = <0x800000 0x37c0000>; + }; + + partition@3fc0000 { + label = "ospi.phypattern"; + reg = <0x3fc0000 0x40000>; + }; + }; }; }; -- cgit From c08cb9cef76abc6216347af8fd8452037b9795de Mon Sep 17 00:00:00 2001 From: Vaishnav Achath Date: Sat, 13 May 2023 19:47:10 +0530 Subject: arm64: dts: ti: k3-am654-baseboard: Describe OSPI flash partition info Describe OSPI flash partition information through device tree, this helps to remove passing partition information through the mtdparts commandline parameter which requires maintaining the partition information in a string format. AM654 baseboard has a MT35XU512ABA 64 MiB OSPI flash with sector size of 128 KiB thus the size of the smallest partition is chosen as 128 KiB, the partition names and offsets are chosen according to the corresponding name and offsets in bootloader. Signed-off-by: Vaishnav Achath Link: https://lore.kernel.org/r/20230513141712.27346-5-vaishnav.a@ti.com Signed-off-by: Vignesh Raghavendra --- arch/arm64/boot/dts/ti/k3-am654-base-board.dts | 46 ++++++++++++++++++++++++++ 1 file changed, 46 insertions(+) diff --git a/arch/arm64/boot/dts/ti/k3-am654-base-board.dts b/arch/arm64/boot/dts/ti/k3-am654-base-board.dts index 0a018bcf5735..73dd50586c64 100644 --- a/arch/arm64/boot/dts/ti/k3-am654-base-board.dts +++ b/arch/arm64/boot/dts/ti/k3-am654-base-board.dts @@ -544,6 +544,52 @@ cdns,tchsh-ns = <60>; cdns,tslch-ns = <60>; cdns,read-delay = <0>; + + partitions { + compatible = "fixed-partitions"; + #address-cells = <1>; + #size-cells = <1>; + + partition@0 { + label = "ospi.tiboot3"; + reg = <0x0 0x80000>; + }; + + partition@80000 { + label = "ospi.tispl"; + reg = <0x80000 0x200000>; + }; + + partition@280000 { + label = "ospi.u-boot"; + reg = <0x280000 0x400000>; + }; + + partition@680000 { + label = "ospi.env"; + reg = <0x680000 0x20000>; + }; + + partition@6a0000 { + label = "ospi.env.backup"; + reg = <0x6a0000 0x20000>; + }; + + partition@6c0000 { + label = "ospi.sysfw"; + reg = <0x6c0000 0x100000>; + }; + + partition@800000 { + label = "ospi.rootfs"; + reg = <0x800000 0x37c0000>; + }; + + partition@3fe0000 { + label = "ospi.phypattern"; + reg = <0x3fe0000 0x20000>; + }; + }; }; }; -- cgit From 9227c49a09b0cfb152a7824b69db46940db81ff3 Mon Sep 17 00:00:00 2001 From: Vaishnav Achath Date: Sat, 13 May 2023 19:47:11 +0530 Subject: arm64: dts: ti: k3-am642-sk/evm: Describe OSPI flash partition info Describe OSPI flash partition information through device tree, this helps to remove passing partition information through the mtdparts commandline parameter which requires maintaining the partition information in a string format. AM64 SK and EVM has a S28 64 MiB OSPI flash with sector size of 256 KiB thus the size of the smallest partition is chosen as 256 KiB, the partition names and offsets are chosen according to the corresponding name and offsets in bootloader. Signed-off-by: Vaishnav Achath Link: https://lore.kernel.org/r/20230513141712.27346-6-vaishnav.a@ti.com Signed-off-by: Vignesh Raghavendra --- arch/arm64/boot/dts/ti/k3-am642-evm.dts | 41 +++++++++++++++++++++++++++++++++ arch/arm64/boot/dts/ti/k3-am642-sk.dts | 41 +++++++++++++++++++++++++++++++++ 2 files changed, 82 insertions(+) diff --git a/arch/arm64/boot/dts/ti/k3-am642-evm.dts b/arch/arm64/boot/dts/ti/k3-am642-evm.dts index 7c90e284e2bf..309500e4c237 100644 --- a/arch/arm64/boot/dts/ti/k3-am642-evm.dts +++ b/arch/arm64/boot/dts/ti/k3-am642-evm.dts @@ -533,6 +533,47 @@ cdns,tchsh-ns = <60>; cdns,tslch-ns = <60>; cdns,read-delay = <4>; + + partitions { + compatible = "fixed-partitions"; + #address-cells = <1>; + #size-cells = <1>; + + partition@0 { + label = "ospi.tiboot3"; + reg = <0x0 0x100000>; + }; + + partition@100000 { + label = "ospi.tispl"; + reg = <0x100000 0x200000>; + }; + + partition@300000 { + label = "ospi.u-boot"; + reg = <0x300000 0x400000>; + }; + + partition@700000 { + label = "ospi.env"; + reg = <0x700000 0x40000>; + }; + + partition@740000 { + label = "ospi.env.backup"; + reg = <0x740000 0x40000>; + }; + + partition@800000 { + label = "ospi.rootfs"; + reg = <0x800000 0x37c0000>; + }; + + partition@3fc0000 { + label = "ospi.phypattern"; + reg = <0x3fc0000 0x40000>; + }; + }; }; }; diff --git a/arch/arm64/boot/dts/ti/k3-am642-sk.dts b/arch/arm64/boot/dts/ti/k3-am642-sk.dts index f9ed22c5a472..9ea012b883e8 100644 --- a/arch/arm64/boot/dts/ti/k3-am642-sk.dts +++ b/arch/arm64/boot/dts/ti/k3-am642-sk.dts @@ -531,6 +531,47 @@ cdns,tchsh-ns = <60>; cdns,tslch-ns = <60>; cdns,read-delay = <4>; + + partitions { + compatible = "fixed-partitions"; + #address-cells = <1>; + #size-cells = <1>; + + partition@0 { + label = "ospi.tiboot3"; + reg = <0x0 0x100000>; + }; + + partition@100000 { + label = "ospi.tispl"; + reg = <0x100000 0x200000>; + }; + + partition@300000 { + label = "ospi.u-boot"; + reg = <0x300000 0x400000>; + }; + + partition@700000 { + label = "ospi.env"; + reg = <0x700000 0x40000>; + }; + + partition@740000 { + label = "ospi.env.backup"; + reg = <0x740000 0x40000>; + }; + + partition@800000 { + label = "ospi.rootfs"; + reg = <0x800000 0x37c0000>; + }; + + partition@3fc0000 { + label = "ospi.phypattern"; + reg = <0x3fc0000 0x40000>; + }; + }; }; }; -- cgit From 498f7b0f9da9be6f6c099b4c8ffb502174623565 Mon Sep 17 00:00:00 2001 From: Nishanth Menon Date: Wed, 7 Jun 2023 08:20:41 -0500 Subject: arm64: dts: ti: k3-am65-main: Fix mcan node name s/mcan/can to stay in sync with bindings conventions. Signed-off-by: Nishanth Menon Link: https://lore.kernel.org/r/20230607132043.3932726-2-nm@ti.com Signed-off-by: Vignesh Raghavendra --- arch/arm64/boot/dts/ti/k3-am65-mcu.dtsi | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/arch/arm64/boot/dts/ti/k3-am65-mcu.dtsi b/arch/arm64/boot/dts/ti/k3-am65-mcu.dtsi index 5dfa31840e9c..c2519d4607a5 100644 --- a/arch/arm64/boot/dts/ti/k3-am65-mcu.dtsi +++ b/arch/arm64/boot/dts/ti/k3-am65-mcu.dtsi @@ -227,7 +227,7 @@ }; }; - m_can0: mcan@40528000 { + m_can0: can@40528000 { compatible = "bosch,m_can"; reg = <0x0 0x40528000 0x0 0x400>, <0x0 0x40500000 0x0 0x4400>; @@ -243,7 +243,7 @@ status = "disabled"; }; - m_can1: mcan@40568000 { + m_can1: can@40568000 { compatible = "bosch,m_can"; reg = <0x0 0x40568000 0x0 0x400>, <0x0 0x40540000 0x0 0x4400>; -- cgit From 2b9bb988742d1794e78d4297a99658f38477eedd Mon Sep 17 00:00:00 2001 From: Nishanth Menon Date: Wed, 7 Jun 2023 08:20:42 -0500 Subject: arm64: dts: ti: k3-am65-main: Drop deprecated ti,otap-del-sel property ti,otap-del-sel has been deprecated in favor of ti,otap-del-sel-legacy. Drop the duplicate and misleading ti,otap-del-sel property. Signed-off-by: Nishanth Menon Link: https://lore.kernel.org/r/20230607132043.3932726-3-nm@ti.com Signed-off-by: Vignesh Raghavendra --- arch/arm64/boot/dts/ti/k3-am65-main.dtsi | 1 - 1 file changed, 1 deletion(-) diff --git a/arch/arm64/boot/dts/ti/k3-am65-main.dtsi b/arch/arm64/boot/dts/ti/k3-am65-main.dtsi index bc63d10bad5a..3f8ff2589842 100644 --- a/arch/arm64/boot/dts/ti/k3-am65-main.dtsi +++ b/arch/arm64/boot/dts/ti/k3-am65-main.dtsi @@ -469,7 +469,6 @@ ti,otap-del-sel-ddr52 = <0x4>; ti,otap-del-sel-hs200 = <0x7>; ti,clkbuf-sel = <0x7>; - ti,otap-del-sel = <0x2>; ti,trm-icp = <0x8>; dma-coherent; }; -- cgit From 400f4953d53ccc07bb26bb6c9d425934ecab4aa8 Mon Sep 17 00:00:00 2001 From: Nishanth Menon Date: Wed, 7 Jun 2023 08:20:43 -0500 Subject: arm64: dts: ti: k3-am65-iot2050-common: Rename rtc8564 nodename Just use "rtc" as the nodename to better match with the bindings. Signed-off-by: Nishanth Menon Link: https://lore.kernel.org/r/20230607132043.3932726-4-nm@ti.com Signed-off-by: Vignesh Raghavendra --- arch/arm64/boot/dts/ti/k3-am65-iot2050-common.dtsi | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm64/boot/dts/ti/k3-am65-iot2050-common.dtsi b/arch/arm64/boot/dts/ti/k3-am65-iot2050-common.dtsi index 7d256a1638ff..6b052a0ecfa1 100644 --- a/arch/arm64/boot/dts/ti/k3-am65-iot2050-common.dtsi +++ b/arch/arm64/boot/dts/ti/k3-am65-iot2050-common.dtsi @@ -482,7 +482,7 @@ pinctrl-0 = <&main_i2c0_pins_default>; clock-frequency = <400000>; - rtc: rtc8564@51 { + rtc: rtc@51 { compatible = "nxp,pcf8563"; reg = <0x51>; }; -- cgit From 7450aa5153af55a0c63785a6917e35a989a4fdf5 Mon Sep 17 00:00:00 2001 From: Nitin Yadav Date: Tue, 30 May 2023 11:58:54 -0500 Subject: arm64: dts: ti: k3-am62-main: Add sa3_secproxy Security Management Subsystem(SMS) has it's own unique secure proxy as part of Security Accelerator (SA3) module. This is used for communicating with ROM and for special usecases such as HSM operations. This is in addition to the one in the main domain DMSS subsystem that is used for general purpose communication. Describe the node for use with bootloaders and firmware that require this communication path which uses interrupts to corresponding micro controller interrupt controller. Mark the node as disabled since this instance does not have interrupts routed to the main processor by default for a complete description of the node. Signed-off-by: Nitin Yadav [nm@ti.com: Update commit message, minor updates] Signed-off-by: Nishanth Menon Link: https://lore.kernel.org/r/20230530165900.47502-2-nm@ti.com Signed-off-by: Vignesh Raghavendra --- arch/arm64/boot/dts/ti/k3-am62-main.dtsi | 15 +++++++++++++++ 1 file changed, 15 insertions(+) diff --git a/arch/arm64/boot/dts/ti/k3-am62-main.dtsi b/arch/arm64/boot/dts/ti/k3-am62-main.dtsi index b3e4857bbbe4..bf3e054c72ce 100644 --- a/arch/arm64/boot/dts/ti/k3-am62-main.dtsi +++ b/arch/arm64/boot/dts/ti/k3-am62-main.dtsi @@ -184,6 +184,21 @@ dma-names = "tx", "rx1", "rx2"; }; + secure_proxy_sa3: mailbox@43600000 { + compatible = "ti,am654-secure-proxy"; + #mbox-cells = <1>; + reg-names = "target_data", "rt", "scfg"; + reg = <0x00 0x43600000 0x00 0x10000>, + <0x00 0x44880000 0x00 0x20000>, + <0x00 0x44860000 0x00 0x20000>; + /* + * Marked Disabled: + * Node is incomplete as it is meant for bootloaders and + * firmware on non-MPU processors + */ + status = "disabled"; + }; + main_pmx0: pinctrl@f4000 { compatible = "pinctrl-single"; reg = <0x00 0xf4000 0x00 0x2ac>; -- cgit From f7d3b11cacd1fc9596444e89209b80800d20ea22 Mon Sep 17 00:00:00 2001 From: Nishanth Menon Date: Tue, 30 May 2023 11:58:55 -0500 Subject: arm64: dts: ti: k3-am62a-main: Add sa3_secproxy Security Management Subsystem(SMS) has it's own unique secure proxy as part of Security Accelerator (SA3) module. This is used for communicating with ROM and for special usecases such as HSM operations. This is in addition to the one in the main domain DMSS subsystem that is used for general purpose communication. Describe the node for use with bootloaders and firmware that require this communication path which uses interrupts to corresponding micro controller interrupt controller. Mark the node as disabled since this instance does not have interrupts routed to the main processor by default for a complete description of the node. Signed-off-by: Nishanth Menon Link: https://lore.kernel.org/r/20230530165900.47502-3-nm@ti.com Signed-off-by: Vignesh Raghavendra --- arch/arm64/boot/dts/ti/k3-am62a-main.dtsi | 15 +++++++++++++++ 1 file changed, 15 insertions(+) diff --git a/arch/arm64/boot/dts/ti/k3-am62a-main.dtsi b/arch/arm64/boot/dts/ti/k3-am62a-main.dtsi index e43e64451bc1..8b315cc61550 100644 --- a/arch/arm64/boot/dts/ti/k3-am62a-main.dtsi +++ b/arch/arm64/boot/dts/ti/k3-am62a-main.dtsi @@ -169,6 +169,21 @@ }; }; + secure_proxy_sa3: mailbox@43600000 { + compatible = "ti,am654-secure-proxy"; + #mbox-cells = <1>; + reg-names = "target_data", "rt", "scfg"; + reg = <0x00 0x43600000 0x00 0x10000>, + <0x00 0x44880000 0x00 0x20000>, + <0x00 0x44860000 0x00 0x20000>; + /* + * Marked Disabled: + * Node is incomplete as it is meant for bootloaders and + * firmware on non-MPU processors + */ + status = "disabled"; + }; + main_pmx0: pinctrl@f4000 { compatible = "pinctrl-single"; reg = <0x00 0xf4000 0x00 0x2ac>; -- cgit From 84debc33b529cae428f29b1eb21ccc05c8b47a16 Mon Sep 17 00:00:00 2001 From: Nishanth Menon Date: Tue, 30 May 2023 11:58:56 -0500 Subject: arm64: dts: ti: k3-am65-mcu: Add mcu_secproxy MCU domain has it's own secure proxy for communicating with ROM and for R5 micro controller firmware operations. This is in addition to the one in the main domain NAVSS subsystem that is used for general purpose communication. Describe the node for use with bootloaders and firmware that require this communication path which uses interrupts to corresponding micro controller interrupt controller. Mark the node as disabled since this instance does not have interrupts routed to the main processor by default for a complete description of the node. Signed-off-by: Nishanth Menon Link: https://lore.kernel.org/r/20230530165900.47502-4-nm@ti.com Signed-off-by: Vignesh Raghavendra --- arch/arm64/boot/dts/ti/k3-am65-mcu.dtsi | 15 +++++++++++++++ 1 file changed, 15 insertions(+) diff --git a/arch/arm64/boot/dts/ti/k3-am65-mcu.dtsi b/arch/arm64/boot/dts/ti/k3-am65-mcu.dtsi index c2519d4607a5..b7a4b5a89aaf 100644 --- a/arch/arm64/boot/dts/ti/k3-am65-mcu.dtsi +++ b/arch/arm64/boot/dts/ti/k3-am65-mcu.dtsi @@ -227,6 +227,21 @@ }; }; + secure_proxy_mcu: mailbox@2a480000 { + compatible = "ti,am654-secure-proxy"; + #mbox-cells = <1>; + reg-names = "target_data", "rt", "scfg"; + reg = <0x0 0x2a480000 0x0 0x80000>, + <0x0 0x2a380000 0x0 0x80000>, + <0x0 0x2a400000 0x0 0x80000>; + /* + * Marked Disabled: + * Node is incomplete as it is meant for bootloaders and + * firmware on non-MPU processors + */ + status = "disabled"; + }; + m_can0: can@40528000 { compatible = "bosch,m_can"; reg = <0x0 0x40528000 0x0 0x400>, -- cgit From c4e43f5aef9731c480789dcb044d261f894a102e Mon Sep 17 00:00:00 2001 From: Nishanth Menon Date: Tue, 30 May 2023 11:58:57 -0500 Subject: arm64: dts: ti: k3-j7200-mcu: Add mcu_secproxy MCU domain has it's own secure proxy for communicating with ROM and for R5 micro controller firmware operations. This is in addition to the one in the main domain NAVSS subsystem that is used for general purpose communication. Describe the node for use with bootloaders and firmware that require this communication path which uses interrupts to corresponding micro controller interrupt controller. Mark the node as disabled since this instance does not have interrupts routed to the main processor by default for a complete description of the node. Signed-off-by: Nishanth Menon Reviewed-by: Udit Kumar Link: https://lore.kernel.org/r/20230530165900.47502-5-nm@ti.com Signed-off-by: Vignesh Raghavendra --- arch/arm64/boot/dts/ti/k3-j7200-mcu-wakeup.dtsi | 15 +++++++++++++++ 1 file changed, 15 insertions(+) diff --git a/arch/arm64/boot/dts/ti/k3-j7200-mcu-wakeup.dtsi b/arch/arm64/boot/dts/ti/k3-j7200-mcu-wakeup.dtsi index 6a26758af7be..22084bdf6d26 100644 --- a/arch/arm64/boot/dts/ti/k3-j7200-mcu-wakeup.dtsi +++ b/arch/arm64/boot/dts/ti/k3-j7200-mcu-wakeup.dtsi @@ -209,6 +209,21 @@ }; }; + secure_proxy_mcu: mailbox@2a480000 { + compatible = "ti,am654-secure-proxy"; + #mbox-cells = <1>; + reg-names = "target_data", "rt", "scfg"; + reg = <0x0 0x2a480000 0x0 0x80000>, + <0x0 0x2a380000 0x0 0x80000>, + <0x0 0x2a400000 0x0 0x80000>; + /* + * Marked Disabled: + * Node is incomplete as it is meant for bootloaders and + * firmware on non-MPU processors + */ + status = "disabled"; + }; + mcu_cpsw: ethernet@46000000 { compatible = "ti,j721e-cpsw-nuss"; #address-cells = <2>; -- cgit From 753904da7072646666fa17a5030ef2be871a385a Mon Sep 17 00:00:00 2001 From: Nishanth Menon Date: Tue, 30 May 2023 11:58:58 -0500 Subject: arm64: dts: ti: k3-j721e-mcu: Add mcu_secproxy MCU domain has it's own secure proxy for communicating with ROM and for R5 micro controller firmware operations. This is in addition to the one in the main domain NAVSS subsystem that is used for general purpose communication. Describe the node for use with bootloaders and firmware that require this communication path which uses interrupts to corresponding micro controller interrupt controller. Mark the node as disabled since this instance does not have interrupts routed to the main processor by default for a complete description of the node. Signed-off-by: Nishanth Menon Link: https://lore.kernel.org/r/20230530165900.47502-6-nm@ti.com Signed-off-by: Vignesh Raghavendra --- arch/arm64/boot/dts/ti/k3-j721e-mcu-wakeup.dtsi | 15 +++++++++++++++ 1 file changed, 15 insertions(+) diff --git a/arch/arm64/boot/dts/ti/k3-j721e-mcu-wakeup.dtsi b/arch/arm64/boot/dts/ti/k3-j721e-mcu-wakeup.dtsi index bfe3907b4b55..230d14fe11b4 100644 --- a/arch/arm64/boot/dts/ti/k3-j721e-mcu-wakeup.dtsi +++ b/arch/arm64/boot/dts/ti/k3-j721e-mcu-wakeup.dtsi @@ -317,6 +317,21 @@ }; }; + secure_proxy_mcu: mailbox@2a480000 { + compatible = "ti,am654-secure-proxy"; + #mbox-cells = <1>; + reg-names = "target_data", "rt", "scfg"; + reg = <0x0 0x2a480000 0x0 0x80000>, + <0x0 0x2a380000 0x0 0x80000>, + <0x0 0x2a400000 0x0 0x80000>; + /* + * Marked Disabled: + * Node is incomplete as it is meant for bootloaders and + * firmware on non-MPU processors + */ + status = "disabled"; + }; + mcu_cpsw: ethernet@46000000 { compatible = "ti,j721e-cpsw-nuss"; #address-cells = <2>; -- cgit From 77f622cb8633c020a78cfb8b7d3d73ba3eaf0a44 Mon Sep 17 00:00:00 2001 From: Nishanth Menon Date: Tue, 30 May 2023 11:58:59 -0500 Subject: arm64: dts: ti: k3-j721s2-mcu-wakeup: Add sa3_secproxy and mcu_sec_proxy Security Management Subsystem(SMS) has it's own unique secure proxy as part of Security Accelerator (SA3) module. This is used for communicating with ROM and for special usecases such as HSM operations. In addition MCU island has it's own secure proxy for usecases involving the MCU micro controllers. These are in addition to the one in the main domain DMSS subsystem that is used for general purpose communication. Describe the nodes for use with bootloaders and firmware that require these communication paths which uses interrupts to corresponding micro controller interrupt controller. Mark the node as disabled since these instances do not have interrupts routed to the main processor by default for a complete description of the node. Signed-off-by: Nishanth Menon Link: https://lore.kernel.org/r/20230530165900.47502-7-nm@ti.com Signed-off-by: Vignesh Raghavendra --- arch/arm64/boot/dts/ti/k3-j721s2-mcu-wakeup.dtsi | 30 ++++++++++++++++++++++++ 1 file changed, 30 insertions(+) diff --git a/arch/arm64/boot/dts/ti/k3-j721s2-mcu-wakeup.dtsi b/arch/arm64/boot/dts/ti/k3-j721s2-mcu-wakeup.dtsi index 9c6bb6db59f8..4013f036d371 100644 --- a/arch/arm64/boot/dts/ti/k3-j721s2-mcu-wakeup.dtsi +++ b/arch/arm64/boot/dts/ti/k3-j721s2-mcu-wakeup.dtsi @@ -39,6 +39,21 @@ reg = <0x00 0x43000014 0x00 0x4>; }; + secure_proxy_sa3: mailbox@43600000 { + compatible = "ti,am654-secure-proxy"; + #mbox-cells = <1>; + reg-names = "target_data", "rt", "scfg"; + reg = <0x00 0x43600000 0x00 0x10000>, + <0x00 0x44880000 0x00 0x20000>, + <0x00 0x44860000 0x00 0x20000>; + /* + * Marked Disabled: + * Node is incomplete as it is meant for bootloaders and + * firmware on non-MPU processors + */ + status = "disabled"; + }; + mcu_ram: sram@41c00000 { compatible = "mmio-sram"; reg = <0x00 0x41c00000 0x00 0x100000>; @@ -280,6 +295,21 @@ }; }; + secure_proxy_mcu: mailbox@2a480000 { + compatible = "ti,am654-secure-proxy"; + #mbox-cells = <1>; + reg-names = "target_data", "rt", "scfg"; + reg = <0x00 0x2a480000 0x00 0x80000>, + <0x00 0x2a380000 0x00 0x80000>, + <0x00 0x2a400000 0x00 0x80000>; + /* + * Marked Disabled: + * Node is incomplete as it is meant for bootloaders and + * firmware on non-MPU processors + */ + status = "disabled"; + }; + mcu_cpsw: ethernet@46000000 { compatible = "ti,j721e-cpsw-nuss"; #address-cells = <2>; -- cgit From 389ad7111ddd99a05c75bc7d4f480a0526761d06 Mon Sep 17 00:00:00 2001 From: Nishanth Menon Date: Tue, 30 May 2023 11:59:00 -0500 Subject: arm64: dts: ti: k3-j784s4-mcu-wakeup: Add sa3_secproxy and mcu_sec_proxy Security Management Subsystem(SMS) has it's own unique secure proxy as part of Security Accelerator (SA3) module. This is used for communicating with ROM and for special usecases such as HSM operations. In addition MCU island has it's own secure proxy for usecases involving the MCU micro controllers. These are in addition to the one in the main domain DMSS subsystem that is used for general purpose communication. Describe the nodes for use with bootloaders and firmware that require these communication paths which uses interrupts to corresponding micro controller interrupt controller. Mark the node as disabled since these instances do not have interrupts routed to the main processor by default for a complete description of the node. Signed-off-by: Nishanth Menon Link: https://lore.kernel.org/r/20230530165900.47502-8-nm@ti.com Signed-off-by: Vignesh Raghavendra --- arch/arm64/boot/dts/ti/k3-j784s4-mcu-wakeup.dtsi | 30 ++++++++++++++++++++++++ 1 file changed, 30 insertions(+) diff --git a/arch/arm64/boot/dts/ti/k3-j784s4-mcu-wakeup.dtsi b/arch/arm64/boot/dts/ti/k3-j784s4-mcu-wakeup.dtsi index ae9a8856bc40..b356845412bf 100644 --- a/arch/arm64/boot/dts/ti/k3-j784s4-mcu-wakeup.dtsi +++ b/arch/arm64/boot/dts/ti/k3-j784s4-mcu-wakeup.dtsi @@ -39,6 +39,21 @@ reg = <0x00 0x43000014 0x00 0x4>; }; + secure_proxy_sa3: mailbox@43600000 { + compatible = "ti,am654-secure-proxy"; + #mbox-cells = <1>; + reg-names = "target_data", "rt", "scfg"; + reg = <0x00 0x43600000 0x00 0x10000>, + <0x00 0x44880000 0x00 0x20000>, + <0x00 0x44860000 0x00 0x20000>; + /* + * Marked Disabled: + * Node is incomplete as it is meant for bootloaders and + * firmware on non-MPU processors + */ + status = "disabled"; + }; + mcu_ram: sram@41c00000 { compatible = "mmio-sram"; reg = <0x00 0x41c00000 0x00 0x100000>; @@ -280,6 +295,21 @@ }; }; + secure_proxy_mcu: mailbox@2a480000 { + compatible = "ti,am654-secure-proxy"; + #mbox-cells = <1>; + reg-names = "target_data", "rt", "scfg"; + reg = <0x00 0x2a480000 0x00 0x80000>, + <0x00 0x2a380000 0x00 0x80000>, + <0x00 0x2a400000 0x00 0x80000>; + /* + * Marked Disabled: + * Node is incomplete as it is meant for bootloaders and + * firmware on non-MPU processors + */ + status = "disabled"; + }; + mcu_cpsw: ethernet@46000000 { compatible = "ti,j721e-cpsw-nuss"; #address-cells = <2>; -- cgit From 7f209dd1267ce2a4a5f6a9e4571858fa2d2e588c Mon Sep 17 00:00:00 2001 From: Nishanth Menon Date: Wed, 31 May 2023 16:32:10 -0500 Subject: arm64: dts: ti: k3-j721e: Add general purpose timers There are 20 general purpose timers on j721e that can be used for things like PWM using pwm-omap-dmtimer driver. There are also additional ten timers in the MCU domain which are meant for MCU firmware usage and hence marked reserved by default. The odd numbered timers have the option of being cascaded to even timers to create a 64 bit non-atomic counter which is racy in simple usage, hence the clock muxes are explicitly setup to individual 32 bit counters driven off system crystal (HFOSC) as default. These instantiation differs from J7200 and other SoCs with the device IDs and clocks involved for muxing. Signed-off-by: Nishanth Menon Reviewed-by: Tony Lindgren Link: https://lore.kernel.org/r/20230531213215.602395-2-nm@ti.com Signed-off-by: Vignesh Raghavendra --- arch/arm64/boot/dts/ti/k3-j721e-main.dtsi | 240 ++++++++++++++++++++++++ arch/arm64/boot/dts/ti/k3-j721e-mcu-wakeup.dtsi | 139 ++++++++++++++ 2 files changed, 379 insertions(+) diff --git a/arch/arm64/boot/dts/ti/k3-j721e-main.dtsi b/arch/arm64/boot/dts/ti/k3-j721e-main.dtsi index 5f35f823a8fa..784cce413a11 100644 --- a/arch/arm64/boot/dts/ti/k3-j721e-main.dtsi +++ b/arch/arm64/boot/dts/ti/k3-j721e-main.dtsi @@ -945,6 +945,246 @@ }; }; + main_timer0: timer@2400000 { + compatible = "ti,am654-timer"; + reg = <0x00 0x2400000 0x00 0x400>; + interrupts = ; + clocks = <&k3_clks 49 1>; + clock-names = "fck"; + assigned-clocks = <&k3_clks 49 1>; + assigned-clock-parents = <&k3_clks 49 2>; + power-domains = <&k3_pds 49 TI_SCI_PD_EXCLUSIVE>; + ti,timer-pwm; + }; + + main_timer1: timer@2410000 { + compatible = "ti,am654-timer"; + reg = <0x00 0x2410000 0x00 0x400>; + interrupts = ; + clocks = <&k3_clks 50 1>; + clock-names = "fck"; + assigned-clocks = <&k3_clks 50 1>, <&k3_clks 327 0>; + assigned-clock-parents = <&k3_clks 50 2>, <&k3_clks 327 1>; + power-domains = <&k3_pds 50 TI_SCI_PD_EXCLUSIVE>; + ti,timer-pwm; + }; + + main_timer2: timer@2420000 { + compatible = "ti,am654-timer"; + reg = <0x00 0x2420000 0x00 0x400>; + interrupts = ; + clocks = <&k3_clks 51 1>; + clock-names = "fck"; + assigned-clocks = <&k3_clks 51 1>; + assigned-clock-parents = <&k3_clks 51 2>; + power-domains = <&k3_pds 51 TI_SCI_PD_EXCLUSIVE>; + ti,timer-pwm; + }; + + main_timer3: timer@2430000 { + compatible = "ti,am654-timer"; + reg = <0x00 0x2430000 0x00 0x400>; + interrupts = ; + clocks = <&k3_clks 52 1>; + clock-names = "fck"; + assigned-clocks = <&k3_clks 52 1>, <&k3_clks 328 0>; + assigned-clock-parents = <&k3_clks 52 2>, <&k3_clks 328 1>; + power-domains = <&k3_pds 52 TI_SCI_PD_EXCLUSIVE>; + ti,timer-pwm; + }; + + main_timer4: timer@2440000 { + compatible = "ti,am654-timer"; + reg = <0x00 0x2440000 0x00 0x400>; + interrupts = ; + clocks = <&k3_clks 53 1>; + clock-names = "fck"; + assigned-clocks = <&k3_clks 53 1>; + assigned-clock-parents = <&k3_clks 53 2>; + power-domains = <&k3_pds 53 TI_SCI_PD_EXCLUSIVE>; + ti,timer-pwm; + }; + + main_timer5: timer@2450000 { + compatible = "ti,am654-timer"; + reg = <0x00 0x2450000 0x00 0x400>; + interrupts = ; + clocks = <&k3_clks 54 1>; + clock-names = "fck"; + assigned-clocks = <&k3_clks 54 1>, <&k3_clks 329 0>; + assigned-clock-parents = <&k3_clks 54 2>, <&k3_clks 329 1>; + power-domains = <&k3_pds 54 TI_SCI_PD_EXCLUSIVE>; + ti,timer-pwm; + }; + + main_timer6: timer@2460000 { + compatible = "ti,am654-timer"; + reg = <0x00 0x2460000 0x00 0x400>; + interrupts = ; + clocks = <&k3_clks 55 1>; + clock-names = "fck"; + assigned-clocks = <&k3_clks 55 1>; + assigned-clock-parents = <&k3_clks 55 2>; + power-domains = <&k3_pds 55 TI_SCI_PD_EXCLUSIVE>; + ti,timer-pwm; + }; + + main_timer7: timer@2470000 { + compatible = "ti,am654-timer"; + reg = <0x00 0x2470000 0x00 0x400>; + interrupts = ; + clocks = <&k3_clks 57 1>; + clock-names = "fck"; + assigned-clocks = <&k3_clks 57 1>, <&k3_clks 330 0>; + assigned-clock-parents = <&k3_clks 57 2>, <&k3_clks 330 1>; + power-domains = <&k3_pds 57 TI_SCI_PD_EXCLUSIVE>; + ti,timer-pwm; + }; + + main_timer8: timer@2480000 { + compatible = "ti,am654-timer"; + reg = <0x00 0x2480000 0x00 0x400>; + interrupts = ; + clocks = <&k3_clks 58 1>; + clock-names = "fck"; + assigned-clocks = <&k3_clks 58 1>; + assigned-clock-parents = <&k3_clks 58 2>; + power-domains = <&k3_pds 58 TI_SCI_PD_EXCLUSIVE>; + ti,timer-pwm; + }; + + main_timer9: timer@2490000 { + compatible = "ti,am654-timer"; + reg = <0x00 0x2490000 0x00 0x400>; + interrupts = ; + clocks = <&k3_clks 59 1>; + clock-names = "fck"; + assigned-clocks = <&k3_clks 59 1>, <&k3_clks 331 0>; + assigned-clock-parents = <&k3_clks 59 2>, <&k3_clks 331 1>; + power-domains = <&k3_pds 59 TI_SCI_PD_EXCLUSIVE>; + ti,timer-pwm; + }; + + main_timer10: timer@24a0000 { + compatible = "ti,am654-timer"; + reg = <0x00 0x24a0000 0x00 0x400>; + interrupts = ; + clocks = <&k3_clks 60 1>; + clock-names = "fck"; + assigned-clocks = <&k3_clks 60 1>; + assigned-clock-parents = <&k3_clks 60 2>; + power-domains = <&k3_pds 60 TI_SCI_PD_EXCLUSIVE>; + ti,timer-pwm; + }; + + main_timer11: timer@24b0000 { + compatible = "ti,am654-timer"; + reg = <0x00 0x24b0000 0x00 0x400>; + interrupts = ; + clocks = <&k3_clks 62 1>; + clock-names = "fck"; + assigned-clocks = <&k3_clks 62 1>, <&k3_clks 332 0>; + assigned-clock-parents = <&k3_clks 62 2>, <&k3_clks 332 1>; + power-domains = <&k3_pds 62 TI_SCI_PD_EXCLUSIVE>; + ti,timer-pwm; + }; + + main_timer12: timer@24c0000 { + compatible = "ti,am654-timer"; + reg = <0x00 0x24c0000 0x00 0x400>; + interrupts = ; + clocks = <&k3_clks 63 1>; + clock-names = "fck"; + assigned-clocks = <&k3_clks 63 1>; + assigned-clock-parents = <&k3_clks 63 2>; + power-domains = <&k3_pds 63 TI_SCI_PD_EXCLUSIVE>; + ti,timer-pwm; + }; + + main_timer13: timer@24d0000 { + compatible = "ti,am654-timer"; + reg = <0x00 0x24d0000 0x00 0x400>; + interrupts = ; + clocks = <&k3_clks 64 1>; + clock-names = "fck"; + assigned-clocks = <&k3_clks 64 1>, <&k3_clks 333 0>; + assigned-clock-parents = <&k3_clks 64 2>, <&k3_clks 333 1>; + power-domains = <&k3_pds 64 TI_SCI_PD_EXCLUSIVE>; + ti,timer-pwm; + }; + + main_timer14: timer@24e0000 { + compatible = "ti,am654-timer"; + reg = <0x00 0x24e0000 0x00 0x400>; + interrupts = ; + clocks = <&k3_clks 65 1>; + clock-names = "fck"; + assigned-clocks = <&k3_clks 65 1>; + assigned-clock-parents = <&k3_clks 65 2>; + power-domains = <&k3_pds 65 TI_SCI_PD_EXCLUSIVE>; + ti,timer-pwm; + }; + + main_timer15: timer@24f0000 { + compatible = "ti,am654-timer"; + reg = <0x00 0x24f0000 0x00 0x400>; + interrupts = ; + clocks = <&k3_clks 66 1>; + clock-names = "fck"; + assigned-clocks = <&k3_clks 66 1>, <&k3_clks 334 0>; + assigned-clock-parents = <&k3_clks 66 2>, <&k3_clks 334 1>; + power-domains = <&k3_pds 66 TI_SCI_PD_EXCLUSIVE>; + ti,timer-pwm; + }; + + main_timer16: timer@2500000 { + compatible = "ti,am654-timer"; + reg = <0x00 0x2500000 0x00 0x400>; + interrupts = ; + clocks = <&k3_clks 67 1>; + clock-names = "fck"; + assigned-clocks = <&k3_clks 67 1>; + assigned-clock-parents = <&k3_clks 67 2>; + power-domains = <&k3_pds 67 TI_SCI_PD_EXCLUSIVE>; + ti,timer-pwm; + }; + + main_timer17: timer@2510000 { + compatible = "ti,am654-timer"; + reg = <0x00 0x2510000 0x00 0x400>; + interrupts = ; + clocks = <&k3_clks 68 1>; + clock-names = "fck"; + assigned-clocks = <&k3_clks 68 1>, <&k3_clks 335 0>; + assigned-clock-parents = <&k3_clks 68 2>, <&k3_clks 335 1>; + power-domains = <&k3_pds 68 TI_SCI_PD_EXCLUSIVE>; + ti,timer-pwm; + }; + + main_timer18: timer@2520000 { + compatible = "ti,am654-timer"; + reg = <0x00 0x2520000 0x00 0x400>; + interrupts = ; + clocks = <&k3_clks 69 1>; + clock-names = "fck"; + assigned-clocks = <&k3_clks 69 1>; + assigned-clock-parents = <&k3_clks 69 2>; + power-domains = <&k3_pds 69 TI_SCI_PD_EXCLUSIVE>; + ti,timer-pwm; + }; + + main_timer19: timer@2530000 { + compatible = "ti,am654-timer"; + reg = <0x00 0x2530000 0x00 0x400>; + interrupts = ; + clocks = <&k3_clks 70 1>; + clock-names = "fck"; + assigned-clocks = <&k3_clks 70 1>, <&k3_clks 336 0>; + assigned-clock-parents = <&k3_clks 70 2>, <&k3_clks 336 1>; + power-domains = <&k3_pds 70 TI_SCI_PD_EXCLUSIVE>; + ti,timer-pwm; + }; + main_uart0: serial@2800000 { compatible = "ti,j721e-uart", "ti,am654-uart"; reg = <0x00 0x02800000 0x00 0x100>; diff --git a/arch/arm64/boot/dts/ti/k3-j721e-mcu-wakeup.dtsi b/arch/arm64/boot/dts/ti/k3-j721e-mcu-wakeup.dtsi index 230d14fe11b4..edad335de0c2 100644 --- a/arch/arm64/boot/dts/ti/k3-j721e-mcu-wakeup.dtsi +++ b/arch/arm64/boot/dts/ti/k3-j721e-mcu-wakeup.dtsi @@ -70,6 +70,145 @@ #size-cells = <1>; }; + mcu_timer0: timer@40400000 { + compatible = "ti,am654-timer"; + reg = <0x00 0x40400000 0x00 0x400>; + interrupts = ; + clocks = <&k3_clks 35 1>; + clock-names = "fck"; + assigned-clocks = <&k3_clks 35 1>; + assigned-clock-parents = <&k3_clks 35 2>; + power-domains = <&k3_pds 35 TI_SCI_PD_EXCLUSIVE>; + ti,timer-pwm; + /* Non-MPU Firmware usage */ + status = "reserved"; + }; + + mcu_timer1: timer@40410000 { + compatible = "ti,am654-timer"; + reg = <0x00 0x40410000 0x00 0x400>; + interrupts = ; + clocks = <&k3_clks 71 1>; + clock-names = "fck"; + assigned-clocks = <&k3_clks 71 1>, <&k3_clks 322 0>; + assigned-clock-parents = <&k3_clks 71 2>, <&k3_clks 322 1>; + power-domains = <&k3_pds 71 TI_SCI_PD_EXCLUSIVE>; + ti,timer-pwm; + /* Non-MPU Firmware usage */ + status = "reserved"; + }; + + mcu_timer2: timer@40420000 { + compatible = "ti,am654-timer"; + reg = <0x00 0x40420000 0x00 0x400>; + interrupts = ; + clocks = <&k3_clks 72 1>; + clock-names = "fck"; + assigned-clocks = <&k3_clks 72 1>; + assigned-clock-parents = <&k3_clks 72 2>; + power-domains = <&k3_pds 72 TI_SCI_PD_EXCLUSIVE>; + ti,timer-pwm; + /* Non-MPU Firmware usage */ + status = "reserved"; + }; + + mcu_timer3: timer@40430000 { + compatible = "ti,am654-timer"; + reg = <0x00 0x40430000 0x00 0x400>; + interrupts = ; + clocks = <&k3_clks 73 1>; + clock-names = "fck"; + assigned-clocks = <&k3_clks 73 1>, <&k3_clks 323 0>; + assigned-clock-parents = <&k3_clks 73 2>, <&k3_clks 323 1>; + power-domains = <&k3_pds 73 TI_SCI_PD_EXCLUSIVE>; + ti,timer-pwm; + /* Non-MPU Firmware usage */ + status = "reserved"; + }; + + mcu_timer4: timer@40440000 { + compatible = "ti,am654-timer"; + reg = <0x00 0x40440000 0x00 0x400>; + interrupts = ; + clocks = <&k3_clks 74 1>; + clock-names = "fck"; + assigned-clocks = <&k3_clks 74 1>; + assigned-clock-parents = <&k3_clks 74 2>; + power-domains = <&k3_pds 74 TI_SCI_PD_EXCLUSIVE>; + ti,timer-pwm; + /* Non-MPU Firmware usage */ + status = "reserved"; + }; + + mcu_timer5: timer@40450000 { + compatible = "ti,am654-timer"; + reg = <0x00 0x40450000 0x00 0x400>; + interrupts = ; + clocks = <&k3_clks 75 1>; + clock-names = "fck"; + assigned-clocks = <&k3_clks 75 1>, <&k3_clks 324 0>; + assigned-clock-parents = <&k3_clks 75 2>, <&k3_clks 324 1>; + power-domains = <&k3_pds 75 TI_SCI_PD_EXCLUSIVE>; + ti,timer-pwm; + /* Non-MPU Firmware usage */ + status = "reserved"; + }; + + mcu_timer6: timer@40460000 { + compatible = "ti,am654-timer"; + reg = <0x00 0x40460000 0x00 0x400>; + interrupts = ; + clocks = <&k3_clks 76 1>; + clock-names = "fck"; + assigned-clocks = <&k3_clks 76 1>; + assigned-clock-parents = <&k3_clks 76 2>; + power-domains = <&k3_pds 76 TI_SCI_PD_EXCLUSIVE>; + ti,timer-pwm; + /* Non-MPU Firmware usage */ + status = "reserved"; + }; + + mcu_timer7: timer@40470000 { + compatible = "ti,am654-timer"; + reg = <0x00 0x40470000 0x00 0x400>; + interrupts = ; + clocks = <&k3_clks 77 1>; + clock-names = "fck"; + assigned-clocks = <&k3_clks 77 1>, <&k3_clks 325 0>; + assigned-clock-parents = <&k3_clks 77 2>, <&k3_clks 325 1>; + power-domains = <&k3_pds 77 TI_SCI_PD_EXCLUSIVE>; + ti,timer-pwm; + /* Non-MPU Firmware usage */ + status = "reserved"; + }; + + mcu_timer8: timer@40480000 { + compatible = "ti,am654-timer"; + reg = <0x00 0x40480000 0x00 0x400>; + interrupts = ; + clocks = <&k3_clks 78 1>; + clock-names = "fck"; + assigned-clocks = <&k3_clks 78 1>; + assigned-clock-parents = <&k3_clks 78 2>; + power-domains = <&k3_pds 78 TI_SCI_PD_EXCLUSIVE>; + ti,timer-pwm; + /* Non-MPU Firmware usage */ + status = "reserved"; + }; + + mcu_timer9: timer@40490000 { + compatible = "ti,am654-timer"; + reg = <0x00 0x40490000 0x00 0x400>; + interrupts = ; + clocks = <&k3_clks 79 1>; + clock-names = "fck"; + assigned-clocks = <&k3_clks 79 1>, <&k3_clks 326 0>; + assigned-clock-parents = <&k3_clks 79 2>, <&k3_clks 326 1>; + power-domains = <&k3_pds 79 TI_SCI_PD_EXCLUSIVE>; + ti,timer-pwm; + /* Non-MPU Firmware usage */ + status = "reserved"; + }; wkup_uart0: serial@42300000 { compatible = "ti,j721e-uart", "ti,am654-uart"; reg = <0x00 0x42300000 0x00 0x100>; -- cgit From 72a44d1c473486582d1d6177404e2fa7adf531ac Mon Sep 17 00:00:00 2001 From: Nishanth Menon Date: Wed, 31 May 2023 16:32:11 -0500 Subject: arm64: dts: ti: k3-j721e: Configure pinctrl for timer IO There are timer IO pads in the MCU domain, and in the MAIN domain. These pads can be muxed for the related timers. There are timer IO control registers for input and output. The registers for CTRLMMR_TIMER*_CTRL and CTRLMMR_MCU_TIMER*_CTRL are used to control the input. The registers for CTCTRLMMR_TIMERIO*_CTRL and CTRLMMR_MCU_TIMERIO*_CTRL the output. The multiplexing is documented in Technical Reference Manual[1] under "Timer IO Muxing Control Registers" and "Timer IO Muxing Control Registers", and the "Timers Overview" chapters. We do not expose the cascade_en bit due to the racy usage of independent 32 bit registers in-line with the timer instantiation in the device tree. The MCU timer controls are also marked as reserved for usage by the MCU firmware. [1] http://www.ti.com/lit/pdf/spruil1 Signed-off-by: Nishanth Menon Reviewed-by: Tony Lindgren Link: https://lore.kernel.org/r/20230531213215.602395-3-nm@ti.com Signed-off-by: Vignesh Raghavendra --- arch/arm64/boot/dts/ti/k3-j721e-main.dtsi | 18 ++++++++++++++++++ arch/arm64/boot/dts/ti/k3-j721e-mcu-wakeup.dtsi | 22 ++++++++++++++++++++++ 2 files changed, 40 insertions(+) diff --git a/arch/arm64/boot/dts/ti/k3-j721e-main.dtsi b/arch/arm64/boot/dts/ti/k3-j721e-main.dtsi index 784cce413a11..a40d34f43abc 100644 --- a/arch/arm64/boot/dts/ti/k3-j721e-main.dtsi +++ b/arch/arm64/boot/dts/ti/k3-j721e-main.dtsi @@ -548,6 +548,24 @@ pinctrl-single,function-mask = <0xffffffff>; }; + /* TIMERIO pad input CTRLMMR_TIMER*_CTRL registers */ + main_timerio_input: pinctrl@104200 { + compatible = "pinctrl-single"; + reg = <0x00 0x104200 0x00 0x50>; + #pinctrl-cells = <1>; + pinctrl-single,register-width = <32>; + pinctrl-single,function-mask = <0x00000007>; + }; + + /* TIMERIO pad output CTCTRLMMR_TIMERIO*_CTRL registers */ + main_timerio_output: pinctrl@104280 { + compatible = "pinctrl-single"; + reg = <0x00 0x104280 0x00 0x20>; + #pinctrl-cells = <1>; + pinctrl-single,register-width = <32>; + pinctrl-single,function-mask = <0x0000001f>; + }; + serdes_wiz0: wiz@5000000 { compatible = "ti,j721e-wiz-16g"; #address-cells = <1>; diff --git a/arch/arm64/boot/dts/ti/k3-j721e-mcu-wakeup.dtsi b/arch/arm64/boot/dts/ti/k3-j721e-mcu-wakeup.dtsi index edad335de0c2..ea5b9e104491 100644 --- a/arch/arm64/boot/dts/ti/k3-j721e-mcu-wakeup.dtsi +++ b/arch/arm64/boot/dts/ti/k3-j721e-mcu-wakeup.dtsi @@ -62,6 +62,28 @@ pinctrl-single,function-mask = <0xffffffff>; }; + /* MCU_TIMERIO pad input CTRLMMR_MCU_TIMER*_CTRL registers */ + mcu_timerio_input: pinctrl@40f04200 { + compatible = "pinctrl-single"; + reg = <0x00 0x40f04200 0x00 0x28>; + #pinctrl-cells = <1>; + pinctrl-single,register-width = <32>; + pinctrl-single,function-mask = <0x0000000f>; + /* Non-MPU Firmware usage */ + status = "reserved"; + }; + + /* MCU_TIMERIO pad output CTRLMMR_MCU_TIMERIO*_CTRL registers */ + mcu_timerio_output: pinctrl@40f04280 { + compatible = "pinctrl-single"; + reg = <0x00 0x40f04280 0x00 0x28>; + #pinctrl-cells = <1>; + pinctrl-single,register-width = <32>; + pinctrl-single,function-mask = <0x0000000f>; + /* Non-MPU Firmware usage */ + status = "reserved"; + }; + mcu_ram: sram@41c00000 { compatible = "mmio-sram"; reg = <0x00 0x41c00000 0x00 0x100000>; -- cgit From 835d04422f9d4c232c060150e696075cd34e081a Mon Sep 17 00:00:00 2001 From: Nishanth Menon Date: Wed, 31 May 2023 16:32:12 -0500 Subject: arm64: dts: ti: k3-j721s2: Add general purpose timers There are 20 general purpose timers on j721s2 that can be used for things like PWM using pwm-omap-dmtimer driver. There are also additional ten timers in the MCU domain which are meant for MCU firmware usage and hence marked reserved by default. Though the count is similar to J721e/J7200, the device IDs and clocks used in j721s2 are different with the option of certain clocks having options of additional clock muxes. Since there is very minimal reuse, it is cleaner to integrate as part of SoC files itself. The defaults are configured for clocking the timers from system clock(HFOSC0). Signed-off-by: Nishanth Menon Reviewed-by: Tony Lindgren Link: https://lore.kernel.org/r/20230531213215.602395-4-nm@ti.com Signed-off-by: Vignesh Raghavendra --- arch/arm64/boot/dts/ti/k3-j721s2-main.dtsi | 240 +++++++++++++++++++++++ arch/arm64/boot/dts/ti/k3-j721s2-mcu-wakeup.dtsi | 140 +++++++++++++ 2 files changed, 380 insertions(+) diff --git a/arch/arm64/boot/dts/ti/k3-j721s2-main.dtsi b/arch/arm64/boot/dts/ti/k3-j721s2-main.dtsi index 6629b2989180..eeb20353599b 100644 --- a/arch/arm64/boot/dts/ti/k3-j721s2-main.dtsi +++ b/arch/arm64/boot/dts/ti/k3-j721s2-main.dtsi @@ -125,6 +125,246 @@ }; }; + main_timer0: timer@2400000 { + compatible = "ti,am654-timer"; + reg = <0x00 0x2400000 0x00 0x400>; + interrupts = ; + clocks = <&k3_clks 63 1>; + clock-names = "fck"; + assigned-clocks = <&k3_clks 63 1>; + assigned-clock-parents = <&k3_clks 63 2>; + power-domains = <&k3_pds 63 TI_SCI_PD_EXCLUSIVE>; + ti,timer-pwm; + }; + + main_timer1: timer@2410000 { + compatible = "ti,am654-timer"; + reg = <0x00 0x2410000 0x00 0x400>; + interrupts = ; + clocks = <&k3_clks 64 1>; + clock-names = "fck"; + assigned-clocks = <&k3_clks 64 1>; + assigned-clock-parents = <&k3_clks 64 2>; + power-domains = <&k3_pds 64 TI_SCI_PD_EXCLUSIVE>; + ti,timer-pwm; + }; + + main_timer2: timer@2420000 { + compatible = "ti,am654-timer"; + reg = <0x00 0x2420000 0x00 0x400>; + interrupts = ; + clocks = <&k3_clks 65 1>; + clock-names = "fck"; + assigned-clocks = <&k3_clks 65 1>; + assigned-clock-parents = <&k3_clks 65 2>; + power-domains = <&k3_pds 65 TI_SCI_PD_EXCLUSIVE>; + ti,timer-pwm; + }; + + main_timer3: timer@2430000 { + compatible = "ti,am654-timer"; + reg = <0x00 0x2430000 0x00 0x400>; + interrupts = ; + clocks = <&k3_clks 66 1>; + clock-names = "fck"; + assigned-clocks = <&k3_clks 66 1>; + assigned-clock-parents = <&k3_clks 66 2>; + power-domains = <&k3_pds 66 TI_SCI_PD_EXCLUSIVE>; + ti,timer-pwm; + }; + + main_timer4: timer@2440000 { + compatible = "ti,am654-timer"; + reg = <0x00 0x2440000 0x00 0x400>; + interrupts = ; + clocks = <&k3_clks 67 1>; + clock-names = "fck"; + assigned-clocks = <&k3_clks 67 1>; + assigned-clock-parents = <&k3_clks 67 2>; + power-domains = <&k3_pds 67 TI_SCI_PD_EXCLUSIVE>; + ti,timer-pwm; + }; + + main_timer5: timer@2450000 { + compatible = "ti,am654-timer"; + reg = <0x00 0x2450000 0x00 0x400>; + interrupts = ; + clocks = <&k3_clks 68 1>; + clock-names = "fck"; + assigned-clocks = <&k3_clks 68 1>; + assigned-clock-parents = <&k3_clks 68 2>; + power-domains = <&k3_pds 68 TI_SCI_PD_EXCLUSIVE>; + ti,timer-pwm; + }; + + main_timer6: timer@2460000 { + compatible = "ti,am654-timer"; + reg = <0x00 0x2460000 0x00 0x400>; + interrupts = ; + clocks = <&k3_clks 69 1>; + clock-names = "fck"; + assigned-clocks = <&k3_clks 69 1>; + assigned-clock-parents = <&k3_clks 69 2>; + power-domains = <&k3_pds 69 TI_SCI_PD_EXCLUSIVE>; + ti,timer-pwm; + }; + + main_timer7: timer@2470000 { + compatible = "ti,am654-timer"; + reg = <0x00 0x2470000 0x00 0x400>; + interrupts = ; + clocks = <&k3_clks 70 1>; + clock-names = "fck"; + assigned-clocks = <&k3_clks 70 1>; + assigned-clock-parents = <&k3_clks 70 2>; + power-domains = <&k3_pds 70 TI_SCI_PD_EXCLUSIVE>; + ti,timer-pwm; + }; + + main_timer8: timer@2480000 { + compatible = "ti,am654-timer"; + reg = <0x00 0x2480000 0x00 0x400>; + interrupts = ; + clocks = <&k3_clks 71 1>; + clock-names = "fck"; + assigned-clocks = <&k3_clks 71 1>; + assigned-clock-parents = <&k3_clks 71 2>; + power-domains = <&k3_pds 71 TI_SCI_PD_EXCLUSIVE>; + ti,timer-pwm; + }; + + main_timer9: timer@2490000 { + compatible = "ti,am654-timer"; + reg = <0x00 0x2490000 0x00 0x400>; + interrupts = ; + clocks = <&k3_clks 72 1>; + clock-names = "fck"; + assigned-clocks = <&k3_clks 72 1>; + assigned-clock-parents = <&k3_clks 72 2>; + power-domains = <&k3_pds 72 TI_SCI_PD_EXCLUSIVE>; + ti,timer-pwm; + }; + + main_timer10: timer@24a0000 { + compatible = "ti,am654-timer"; + reg = <0x00 0x24a0000 0x00 0x400>; + interrupts = ; + clocks = <&k3_clks 73 1>; + clock-names = "fck"; + assigned-clocks = <&k3_clks 73 1>; + assigned-clock-parents = <&k3_clks 73 2>; + power-domains = <&k3_pds 73 TI_SCI_PD_EXCLUSIVE>; + ti,timer-pwm; + }; + + main_timer11: timer@24b0000 { + compatible = "ti,am654-timer"; + reg = <0x00 0x24b0000 0x00 0x400>; + interrupts = ; + clocks = <&k3_clks 74 1>; + clock-names = "fck"; + assigned-clocks = <&k3_clks 74 1>; + assigned-clock-parents = <&k3_clks 74 2>; + power-domains = <&k3_pds 74 TI_SCI_PD_EXCLUSIVE>; + ti,timer-pwm; + }; + + main_timer12: timer@24c0000 { + compatible = "ti,am654-timer"; + reg = <0x00 0x24c0000 0x00 0x400>; + interrupts = ; + clocks = <&k3_clks 75 1>; + clock-names = "fck"; + assigned-clocks = <&k3_clks 75 1>; + assigned-clock-parents = <&k3_clks 75 2>; + power-domains = <&k3_pds 75 TI_SCI_PD_EXCLUSIVE>; + ti,timer-pwm; + }; + + main_timer13: timer@24d0000 { + compatible = "ti,am654-timer"; + reg = <0x00 0x24d0000 0x00 0x400>; + interrupts = ; + clocks = <&k3_clks 76 1>; + clock-names = "fck"; + assigned-clocks = <&k3_clks 76 1>; + assigned-clock-parents = <&k3_clks 76 2>; + power-domains = <&k3_pds 76 TI_SCI_PD_EXCLUSIVE>; + ti,timer-pwm; + }; + + main_timer14: timer@24e0000 { + compatible = "ti,am654-timer"; + reg = <0x00 0x24e0000 0x00 0x400>; + interrupts = ; + clocks = <&k3_clks 77 1>; + clock-names = "fck"; + assigned-clocks = <&k3_clks 77 1>; + assigned-clock-parents = <&k3_clks 77 2>; + power-domains = <&k3_pds 77 TI_SCI_PD_EXCLUSIVE>; + ti,timer-pwm; + }; + + main_timer15: timer@24f0000 { + compatible = "ti,am654-timer"; + reg = <0x00 0x24f0000 0x00 0x400>; + interrupts = ; + clocks = <&k3_clks 78 1>; + clock-names = "fck"; + assigned-clocks = <&k3_clks 78 1>; + assigned-clock-parents = <&k3_clks 78 2>; + power-domains = <&k3_pds 78 TI_SCI_PD_EXCLUSIVE>; + ti,timer-pwm; + }; + + main_timer16: timer@2500000 { + compatible = "ti,am654-timer"; + reg = <0x00 0x2500000 0x00 0x400>; + interrupts = ; + clocks = <&k3_clks 79 1>; + clock-names = "fck"; + assigned-clocks = <&k3_clks 79 1>; + assigned-clock-parents = <&k3_clks 79 2>; + power-domains = <&k3_pds 79 TI_SCI_PD_EXCLUSIVE>; + ti,timer-pwm; + }; + + main_timer17: timer@2510000 { + compatible = "ti,am654-timer"; + reg = <0x00 0x2510000 0x00 0x400>; + interrupts = ; + clocks = <&k3_clks 80 1>; + clock-names = "fck"; + assigned-clocks = <&k3_clks 80 1>; + assigned-clock-parents = <&k3_clks 80 2>; + power-domains = <&k3_pds 80 TI_SCI_PD_EXCLUSIVE>; + ti,timer-pwm; + }; + + main_timer18: timer@2520000 { + compatible = "ti,am654-timer"; + reg = <0x00 0x2520000 0x00 0x400>; + interrupts = ; + clocks = <&k3_clks 81 1>; + clock-names = "fck"; + assigned-clocks = <&k3_clks 81 1>; + assigned-clock-parents = <&k3_clks 81 2>; + power-domains = <&k3_pds 81 TI_SCI_PD_EXCLUSIVE>; + ti,timer-pwm; + }; + + main_timer19: timer@2530000 { + compatible = "ti,am654-timer"; + reg = <0x00 0x2530000 0x00 0x400>; + interrupts = ; + clocks = <&k3_clks 82 1>; + clock-names = "fck"; + assigned-clocks = <&k3_clks 82 1>; + assigned-clock-parents = <&k3_clks 82 2>; + power-domains = <&k3_pds 82 TI_SCI_PD_EXCLUSIVE>; + ti,timer-pwm; + }; + main_uart0: serial@2800000 { compatible = "ti,j721e-uart", "ti,am654-uart"; reg = <0x00 0x02800000 0x00 0x200>; diff --git a/arch/arm64/boot/dts/ti/k3-j721s2-mcu-wakeup.dtsi b/arch/arm64/boot/dts/ti/k3-j721s2-mcu-wakeup.dtsi index 4013f036d371..4b05399c1536 100644 --- a/arch/arm64/boot/dts/ti/k3-j721s2-mcu-wakeup.dtsi +++ b/arch/arm64/boot/dts/ti/k3-j721s2-mcu-wakeup.dtsi @@ -98,6 +98,146 @@ }; + mcu_timer0: timer@40400000 { + compatible = "ti,am654-timer"; + reg = <0x00 0x40400000 0x00 0x400>; + interrupts = ; + clocks = <&k3_clks 35 1>; + clock-names = "fck"; + assigned-clocks = <&k3_clks 35 1>; + assigned-clock-parents = <&k3_clks 35 2>; + power-domains = <&k3_pds 35 TI_SCI_PD_EXCLUSIVE>; + ti,timer-pwm; + /* Non-MPU Firmware usage */ + status = "reserved"; + }; + + mcu_timer1: timer@40410000 { + compatible = "ti,am654-timer"; + reg = <0x00 0x40410000 0x00 0x400>; + interrupts = ; + clocks = <&k3_clks 83 1>; + clock-names = "fck"; + assigned-clocks = <&k3_clks 83 1>; + assigned-clock-parents = <&k3_clks 83 2>; + power-domains = <&k3_pds 83 TI_SCI_PD_EXCLUSIVE>; + ti,timer-pwm; + /* Non-MPU Firmware usage */ + status = "reserved"; + }; + + mcu_timer2: timer@40420000 { + compatible = "ti,am654-timer"; + reg = <0x00 0x40420000 0x00 0x400>; + interrupts = ; + clocks = <&k3_clks 84 1>; + clock-names = "fck"; + assigned-clocks = <&k3_clks 84 1>; + assigned-clock-parents = <&k3_clks 84 2>; + power-domains = <&k3_pds 84 TI_SCI_PD_EXCLUSIVE>; + ti,timer-pwm; + /* Non-MPU Firmware usage */ + status = "reserved"; + }; + + mcu_timer3: timer@40430000 { + compatible = "ti,am654-timer"; + reg = <0x00 0x40430000 0x00 0x400>; + interrupts = ; + clocks = <&k3_clks 85 1>; + clock-names = "fck"; + assigned-clocks = <&k3_clks 85 1>; + assigned-clock-parents = <&k3_clks 85 2>; + power-domains = <&k3_pds 85 TI_SCI_PD_EXCLUSIVE>; + ti,timer-pwm; + /* Non-MPU Firmware usage */ + status = "reserved"; + }; + + mcu_timer4: timer@40440000 { + compatible = "ti,am654-timer"; + reg = <0x00 0x40440000 0x00 0x400>; + interrupts = ; + clocks = <&k3_clks 86 1>; + clock-names = "fck"; + assigned-clocks = <&k3_clks 86 1>; + assigned-clock-parents = <&k3_clks 86 2>; + power-domains = <&k3_pds 86 TI_SCI_PD_EXCLUSIVE>; + ti,timer-pwm; + /* Non-MPU Firmware usage */ + status = "reserved"; + }; + + mcu_timer5: timer@40450000 { + compatible = "ti,am654-timer"; + reg = <0x00 0x40450000 0x00 0x400>; + interrupts = ; + clocks = <&k3_clks 87 1>; + clock-names = "fck"; + assigned-clocks = <&k3_clks 87 1>; + assigned-clock-parents = <&k3_clks 87 2>; + power-domains = <&k3_pds 87 TI_SCI_PD_EXCLUSIVE>; + ti,timer-pwm; + /* Non-MPU Firmware usage */ + status = "reserved"; + }; + + mcu_timer6: timer@40460000 { + compatible = "ti,am654-timer"; + reg = <0x00 0x40460000 0x00 0x400>; + interrupts = ; + clocks = <&k3_clks 88 1>; + clock-names = "fck"; + assigned-clocks = <&k3_clks 88 1>; + assigned-clock-parents = <&k3_clks 88 2>; + power-domains = <&k3_pds 88 TI_SCI_PD_EXCLUSIVE>; + ti,timer-pwm; + /* Non-MPU Firmware usage */ + status = "reserved"; + }; + + mcu_timer7: timer@40470000 { + compatible = "ti,am654-timer"; + reg = <0x00 0x40470000 0x00 0x400>; + interrupts = ; + clocks = <&k3_clks 89 1>; + clock-names = "fck"; + assigned-clocks = <&k3_clks 89 1>; + assigned-clock-parents = <&k3_clks 89 2>; + power-domains = <&k3_pds 89 TI_SCI_PD_EXCLUSIVE>; + ti,timer-pwm; + /* Non-MPU Firmware usage */ + status = "reserved"; + }; + + mcu_timer8: timer@40480000 { + compatible = "ti,am654-timer"; + reg = <0x00 0x40480000 0x00 0x400>; + interrupts = ; + clocks = <&k3_clks 90 1>; + clock-names = "fck"; + assigned-clocks = <&k3_clks 90 1>; + assigned-clock-parents = <&k3_clks 90 2>; + power-domains = <&k3_pds 90 TI_SCI_PD_EXCLUSIVE>; + ti,timer-pwm; + /* Non-MPU Firmware usage */ + status = "reserved"; + }; + + mcu_timer9: timer@40490000 { + compatible = "ti,am654-timer"; + reg = <0x00 0x40490000 0x00 0x400>; + interrupts = ; + clocks = <&k3_clks 91 1>; + clock-names = "fck"; + assigned-clocks = <&k3_clks 91 1>; + assigned-clock-parents = <&k3_clks 91 2>; + power-domains = <&k3_pds 91 TI_SCI_PD_EXCLUSIVE>; + ti,timer-pwm; + /* Non-MPU Firmware usage */ + status = "reserved"; + }; + wkup_uart0: serial@42300000 { compatible = "ti,j721e-uart", "ti,am654-uart"; reg = <0x00 0x42300000 0x00 0x200>; -- cgit From 1ecc75be7bc522941261b5eb0c315b09098a47f4 Mon Sep 17 00:00:00 2001 From: Nishanth Menon Date: Wed, 31 May 2023 16:32:13 -0500 Subject: arm64: dts: ti: k3-j721s2: Configure pinctrl for timer IO There are timer IO pads in the MCU domain, and in the MAIN domain. These pads can be muxed for the related timers. The details of the multiplexing can be found in the register documentation and Technical Reference Manual[1]. These are similar to J721e/J7200, but have different mux capabilities. [1] https://www.ti.com/lit/zip/spruj28 Signed-off-by: Nishanth Menon Reviewed-by: Tony Lindgren Link: https://lore.kernel.org/r/20230531213215.602395-5-nm@ti.com Signed-off-by: Vignesh Raghavendra --- arch/arm64/boot/dts/ti/k3-j721s2-main.dtsi | 18 ++++++++++++++++++ arch/arm64/boot/dts/ti/k3-j721s2-mcu-wakeup.dtsi | 22 ++++++++++++++++++++++ 2 files changed, 40 insertions(+) diff --git a/arch/arm64/boot/dts/ti/k3-j721s2-main.dtsi b/arch/arm64/boot/dts/ti/k3-j721s2-main.dtsi index eeb20353599b..12a5b7008aca 100644 --- a/arch/arm64/boot/dts/ti/k3-j721s2-main.dtsi +++ b/arch/arm64/boot/dts/ti/k3-j721s2-main.dtsi @@ -106,6 +106,24 @@ pinctrl-single,function-mask = <0xffffffff>; }; + /* TIMERIO pad input CTRLMMR_TIMER*_CTRL registers */ + main_timerio_input: pinctrl@104200 { + compatible = "pinctrl-single"; + reg = <0x00 0x104200 0x00 0x50>; + #pinctrl-cells = <1>; + pinctrl-single,register-width = <32>; + pinctrl-single,function-mask = <0x00000007>; + }; + + /* TIMERIO pad output CTCTRLMMR_TIMERIO*_CTRL registers */ + main_timerio_output: pinctrl@104280 { + compatible = "pinctrl-single"; + reg = <0x00 0x104280 0x00 0x20>; + #pinctrl-cells = <1>; + pinctrl-single,register-width = <32>; + pinctrl-single,function-mask = <0x0000001f>; + }; + main_crypto: crypto@4e00000 { compatible = "ti,j721e-sa2ul"; reg = <0x00 0x04e00000 0x00 0x1200>; diff --git a/arch/arm64/boot/dts/ti/k3-j721s2-mcu-wakeup.dtsi b/arch/arm64/boot/dts/ti/k3-j721s2-mcu-wakeup.dtsi index 4b05399c1536..939cd037a814 100644 --- a/arch/arm64/boot/dts/ti/k3-j721s2-mcu-wakeup.dtsi +++ b/arch/arm64/boot/dts/ti/k3-j721s2-mcu-wakeup.dtsi @@ -71,6 +71,28 @@ pinctrl-single,function-mask = <0xffffffff>; }; + /* MCU_TIMERIO pad input CTRLMMR_MCU_TIMER*_CTRL registers */ + mcu_timerio_input: pinctrl@40f04200 { + compatible = "pinctrl-single"; + reg = <0x00 0x40f04200 0x00 0x28>; + #pinctrl-cells = <1>; + pinctrl-single,register-width = <32>; + pinctrl-single,function-mask = <0x0000000f>; + /* Non-MPU Firmware usage */ + status = "reserved"; + }; + + /* MCU_TIMERIO pad output CTRLMMR_MCU_TIMERIO*_CTRL registers */ + mcu_timerio_output: pinctrl@40f04280 { + compatible = "pinctrl-single"; + reg = <0x00 0x40f04280 0x00 0x28>; + #pinctrl-cells = <1>; + pinctrl-single,register-width = <32>; + pinctrl-single,function-mask = <0x0000000f>; + /* Non-MPU Firmware usage */ + status = "reserved"; + }; + wkup_gpio_intr: interrupt-controller@42200000 { compatible = "ti,sci-intr"; reg = <0x00 0x42200000 0x00 0x400>; -- cgit From 833377cf858b24d45e658454bcb683dd9076b576 Mon Sep 17 00:00:00 2001 From: Nishanth Menon Date: Wed, 31 May 2023 16:32:14 -0500 Subject: arm64: dts: ti: k3-j784s4: Add general purpose timers There are 20 general purpose timers on j784s4 that can be used for things like PWM using pwm-omap-dmtimer driver. There are also additional ten timers in the MCU domain which are meant for MCU firmware usage and hence marked reserved by default. Though the count is similar to J721e/J7200/j721s2, the device IDs and clocks used in j784s4 are different with the option of certain clocks having options of additional clock muxes. Since there is very minimal reuse, it is cleaner to integrate as part of SoC files itself. The defaults are configured for clocking the timers from system clock(HFOSC0). Signed-off-by: Nishanth Menon Reviewed-by: Tony Lindgren Link: https://lore.kernel.org/r/20230531213215.602395-6-nm@ti.com Signed-off-by: Vignesh Raghavendra --- arch/arm64/boot/dts/ti/k3-j784s4-main.dtsi | 240 +++++++++++++++++++++++ arch/arm64/boot/dts/ti/k3-j784s4-mcu-wakeup.dtsi | 140 +++++++++++++ 2 files changed, 380 insertions(+) diff --git a/arch/arm64/boot/dts/ti/k3-j784s4-main.dtsi b/arch/arm64/boot/dts/ti/k3-j784s4-main.dtsi index 742bab1c5103..446350f099f3 100644 --- a/arch/arm64/boot/dts/ti/k3-j784s4-main.dtsi +++ b/arch/arm64/boot/dts/ti/k3-j784s4-main.dtsi @@ -91,6 +91,246 @@ }; }; + main_timer0: timer@2400000 { + compatible = "ti,am654-timer"; + reg = <0x00 0x2400000 0x00 0x400>; + interrupts = ; + clocks = <&k3_clks 97 2>; + clock-names = "fck"; + assigned-clocks = <&k3_clks 97 2>; + assigned-clock-parents = <&k3_clks 97 3>; + power-domains = <&k3_pds 97 TI_SCI_PD_EXCLUSIVE>; + ti,timer-pwm; + }; + + main_timer1: timer@2410000 { + compatible = "ti,am654-timer"; + reg = <0x00 0x2410000 0x00 0x400>; + interrupts = ; + clocks = <&k3_clks 98 2>; + clock-names = "fck"; + assigned-clocks = <&k3_clks 98 2>; + assigned-clock-parents = <&k3_clks 98 3>; + power-domains = <&k3_pds 98 TI_SCI_PD_EXCLUSIVE>; + ti,timer-pwm; + }; + + main_timer2: timer@2420000 { + compatible = "ti,am654-timer"; + reg = <0x00 0x2420000 0x00 0x400>; + interrupts = ; + clocks = <&k3_clks 99 2>; + clock-names = "fck"; + assigned-clocks = <&k3_clks 99 2>; + assigned-clock-parents = <&k3_clks 99 3>; + power-domains = <&k3_pds 99 TI_SCI_PD_EXCLUSIVE>; + ti,timer-pwm; + }; + + main_timer3: timer@2430000 { + compatible = "ti,am654-timer"; + reg = <0x00 0x2430000 0x00 0x400>; + interrupts = ; + clocks = <&k3_clks 100 2>; + clock-names = "fck"; + assigned-clocks = <&k3_clks 100 2>; + assigned-clock-parents = <&k3_clks 100 3>; + power-domains = <&k3_pds 100 TI_SCI_PD_EXCLUSIVE>; + ti,timer-pwm; + }; + + main_timer4: timer@2440000 { + compatible = "ti,am654-timer"; + reg = <0x00 0x2440000 0x00 0x400>; + interrupts = ; + clocks = <&k3_clks 101 2>; + clock-names = "fck"; + assigned-clocks = <&k3_clks 101 2>; + assigned-clock-parents = <&k3_clks 101 3>; + power-domains = <&k3_pds 101 TI_SCI_PD_EXCLUSIVE>; + ti,timer-pwm; + }; + + main_timer5: timer@2450000 { + compatible = "ti,am654-timer"; + reg = <0x00 0x2450000 0x00 0x400>; + interrupts = ; + clocks = <&k3_clks 102 2>; + clock-names = "fck"; + assigned-clocks = <&k3_clks 102 2>; + assigned-clock-parents = <&k3_clks 102 3>; + power-domains = <&k3_pds 102 TI_SCI_PD_EXCLUSIVE>; + ti,timer-pwm; + }; + + main_timer6: timer@2460000 { + compatible = "ti,am654-timer"; + reg = <0x00 0x2460000 0x00 0x400>; + interrupts = ; + clocks = <&k3_clks 103 2>; + clock-names = "fck"; + assigned-clocks = <&k3_clks 103 2>; + assigned-clock-parents = <&k3_clks 103 3>; + power-domains = <&k3_pds 103 TI_SCI_PD_EXCLUSIVE>; + ti,timer-pwm; + }; + + main_timer7: timer@2470000 { + compatible = "ti,am654-timer"; + reg = <0x00 0x2470000 0x00 0x400>; + interrupts = ; + clocks = <&k3_clks 104 2>; + clock-names = "fck"; + assigned-clocks = <&k3_clks 104 2>; + assigned-clock-parents = <&k3_clks 104 3>; + power-domains = <&k3_pds 104 TI_SCI_PD_EXCLUSIVE>; + ti,timer-pwm; + }; + + main_timer8: timer@2480000 { + compatible = "ti,am654-timer"; + reg = <0x00 0x2480000 0x00 0x400>; + interrupts = ; + clocks = <&k3_clks 105 2>; + clock-names = "fck"; + assigned-clocks = <&k3_clks 105 2>; + assigned-clock-parents = <&k3_clks 105 3>; + power-domains = <&k3_pds 105 TI_SCI_PD_EXCLUSIVE>; + ti,timer-pwm; + }; + + main_timer9: timer@2490000 { + compatible = "ti,am654-timer"; + reg = <0x00 0x2490000 0x00 0x400>; + interrupts = ; + clocks = <&k3_clks 106 2>; + clock-names = "fck"; + assigned-clocks = <&k3_clks 106 2>; + assigned-clock-parents = <&k3_clks 106 3>; + power-domains = <&k3_pds 106 TI_SCI_PD_EXCLUSIVE>; + ti,timer-pwm; + }; + + main_timer10: timer@24a0000 { + compatible = "ti,am654-timer"; + reg = <0x00 0x24a0000 0x00 0x400>; + interrupts = ; + clocks = <&k3_clks 107 2>; + clock-names = "fck"; + assigned-clocks = <&k3_clks 107 2>; + assigned-clock-parents = <&k3_clks 107 3>; + power-domains = <&k3_pds 107 TI_SCI_PD_EXCLUSIVE>; + ti,timer-pwm; + }; + + main_timer11: timer@24b0000 { + compatible = "ti,am654-timer"; + reg = <0x00 0x24b0000 0x00 0x400>; + interrupts = ; + clocks = <&k3_clks 108 2>; + clock-names = "fck"; + assigned-clocks = <&k3_clks 108 2>; + assigned-clock-parents = <&k3_clks 108 3>; + power-domains = <&k3_pds 108 TI_SCI_PD_EXCLUSIVE>; + ti,timer-pwm; + }; + + main_timer12: timer@24c0000 { + compatible = "ti,am654-timer"; + reg = <0x00 0x24c0000 0x00 0x400>; + interrupts = ; + clocks = <&k3_clks 109 2>; + clock-names = "fck"; + assigned-clocks = <&k3_clks 109 2>; + assigned-clock-parents = <&k3_clks 109 3>; + power-domains = <&k3_pds 109 TI_SCI_PD_EXCLUSIVE>; + ti,timer-pwm; + }; + + main_timer13: timer@24d0000 { + compatible = "ti,am654-timer"; + reg = <0x00 0x24d0000 0x00 0x400>; + interrupts = ; + clocks = <&k3_clks 110 2>; + clock-names = "fck"; + assigned-clocks = <&k3_clks 110 2>; + assigned-clock-parents = <&k3_clks 110 3>; + power-domains = <&k3_pds 110 TI_SCI_PD_EXCLUSIVE>; + ti,timer-pwm; + }; + + main_timer14: timer@24e0000 { + compatible = "ti,am654-timer"; + reg = <0x00 0x24e0000 0x00 0x400>; + interrupts = ; + clocks = <&k3_clks 111 2>; + clock-names = "fck"; + assigned-clocks = <&k3_clks 111 2>; + assigned-clock-parents = <&k3_clks 111 3>; + power-domains = <&k3_pds 111 TI_SCI_PD_EXCLUSIVE>; + ti,timer-pwm; + }; + + main_timer15: timer@24f0000 { + compatible = "ti,am654-timer"; + reg = <0x00 0x24f0000 0x00 0x400>; + interrupts = ; + clocks = <&k3_clks 112 2>; + clock-names = "fck"; + assigned-clocks = <&k3_clks 112 2>; + assigned-clock-parents = <&k3_clks 112 3>; + power-domains = <&k3_pds 112 TI_SCI_PD_EXCLUSIVE>; + ti,timer-pwm; + }; + + main_timer16: timer@2500000 { + compatible = "ti,am654-timer"; + reg = <0x00 0x2500000 0x00 0x400>; + interrupts = ; + clocks = <&k3_clks 113 2>; + clock-names = "fck"; + assigned-clocks = <&k3_clks 113 2>; + assigned-clock-parents = <&k3_clks 113 3>; + power-domains = <&k3_pds 113 TI_SCI_PD_EXCLUSIVE>; + ti,timer-pwm; + }; + + main_timer17: timer@2510000 { + compatible = "ti,am654-timer"; + reg = <0x00 0x2510000 0x00 0x400>; + interrupts = ; + clocks = <&k3_clks 114 2>; + clock-names = "fck"; + assigned-clocks = <&k3_clks 114 2>; + assigned-clock-parents = <&k3_clks 114 3>; + power-domains = <&k3_pds 114 TI_SCI_PD_EXCLUSIVE>; + ti,timer-pwm; + }; + + main_timer18: timer@2520000 { + compatible = "ti,am654-timer"; + reg = <0x00 0x2520000 0x00 0x400>; + interrupts = ; + clocks = <&k3_clks 115 2>; + clock-names = "fck"; + assigned-clocks = <&k3_clks 115 2>; + assigned-clock-parents = <&k3_clks 115 3>; + power-domains = <&k3_pds 115 TI_SCI_PD_EXCLUSIVE>; + ti,timer-pwm; + }; + + main_timer19: timer@2530000 { + compatible = "ti,am654-timer"; + reg = <0x00 0x2530000 0x00 0x400>; + interrupts = ; + clocks = <&k3_clks 116 2>; + clock-names = "fck"; + assigned-clocks = <&k3_clks 116 2>; + assigned-clock-parents = <&k3_clks 116 3>; + power-domains = <&k3_pds 116 TI_SCI_PD_EXCLUSIVE>; + ti,timer-pwm; + }; + main_uart0: serial@2800000 { compatible = "ti,j721e-uart", "ti,am654-uart"; reg = <0x00 0x02800000 0x00 0x200>; diff --git a/arch/arm64/boot/dts/ti/k3-j784s4-mcu-wakeup.dtsi b/arch/arm64/boot/dts/ti/k3-j784s4-mcu-wakeup.dtsi index b356845412bf..591fce5ad56e 100644 --- a/arch/arm64/boot/dts/ti/k3-j784s4-mcu-wakeup.dtsi +++ b/arch/arm64/boot/dts/ti/k3-j784s4-mcu-wakeup.dtsi @@ -97,6 +97,146 @@ }; }; + mcu_timer0: timer@40400000 { + compatible = "ti,am654-timer"; + reg = <0x00 0x40400000 0x00 0x400>; + interrupts = ; + clocks = <&k3_clks 35 2>; + clock-names = "fck"; + assigned-clocks = <&k3_clks 35 2>; + assigned-clock-parents = <&k3_clks 35 3>; + power-domains = <&k3_pds 35 TI_SCI_PD_EXCLUSIVE>; + ti,timer-pwm; + /* Non-MPU Firmware usage */ + status = "reserved"; + }; + + mcu_timer1: timer@40410000 { + compatible = "ti,am654-timer"; + reg = <0x00 0x40410000 0x00 0x400>; + interrupts = ; + clocks = <&k3_clks 117 2>; + clock-names = "fck"; + assigned-clocks = <&k3_clks 117 2>; + assigned-clock-parents = <&k3_clks 117 3>; + power-domains = <&k3_pds 117 TI_SCI_PD_EXCLUSIVE>; + ti,timer-pwm; + /* Non-MPU Firmware usage */ + status = "reserved"; + }; + + mcu_timer2: timer@40420000 { + compatible = "ti,am654-timer"; + reg = <0x00 0x40420000 0x00 0x400>; + interrupts = ; + clocks = <&k3_clks 118 2>; + clock-names = "fck"; + assigned-clocks = <&k3_clks 118 2>; + assigned-clock-parents = <&k3_clks 118 3>; + power-domains = <&k3_pds 118 TI_SCI_PD_EXCLUSIVE>; + ti,timer-pwm; + /* Non-MPU Firmware usage */ + status = "reserved"; + }; + + mcu_timer3: timer@40430000 { + compatible = "ti,am654-timer"; + reg = <0x00 0x40430000 0x00 0x400>; + interrupts = ; + clocks = <&k3_clks 119 2>; + clock-names = "fck"; + assigned-clocks = <&k3_clks 119 2>; + assigned-clock-parents = <&k3_clks 119 3>; + power-domains = <&k3_pds 119 TI_SCI_PD_EXCLUSIVE>; + ti,timer-pwm; + /* Non-MPU Firmware usage */ + status = "reserved"; + }; + + mcu_timer4: timer@40440000 { + compatible = "ti,am654-timer"; + reg = <0x00 0x40440000 0x00 0x400>; + interrupts = ; + clocks = <&k3_clks 120 2>; + clock-names = "fck"; + assigned-clocks = <&k3_clks 120 2>; + assigned-clock-parents = <&k3_clks 120 3>; + power-domains = <&k3_pds 120 TI_SCI_PD_EXCLUSIVE>; + ti,timer-pwm; + /* Non-MPU Firmware usage */ + status = "reserved"; + }; + + mcu_timer5: timer@40450000 { + compatible = "ti,am654-timer"; + reg = <0x00 0x40450000 0x00 0x400>; + interrupts = ; + clocks = <&k3_clks 121 2>; + clock-names = "fck"; + assigned-clocks = <&k3_clks 121 2>; + assigned-clock-parents = <&k3_clks 121 3>; + power-domains = <&k3_pds 121 TI_SCI_PD_EXCLUSIVE>; + ti,timer-pwm; + /* Non-MPU Firmware usage */ + status = "reserved"; + }; + + mcu_timer6: timer@40460000 { + compatible = "ti,am654-timer"; + reg = <0x00 0x40460000 0x00 0x400>; + interrupts = ; + clocks = <&k3_clks 122 2>; + clock-names = "fck"; + assigned-clocks = <&k3_clks 122 2>; + assigned-clock-parents = <&k3_clks 122 3>; + power-domains = <&k3_pds 122 TI_SCI_PD_EXCLUSIVE>; + ti,timer-pwm; + /* Non-MPU Firmware usage */ + status = "reserved"; + }; + + mcu_timer7: timer@40470000 { + compatible = "ti,am654-timer"; + reg = <0x00 0x40470000 0x00 0x400>; + interrupts = ; + clocks = <&k3_clks 123 2>; + clock-names = "fck"; + assigned-clocks = <&k3_clks 123 2>; + assigned-clock-parents = <&k3_clks 123 3>; + power-domains = <&k3_pds 123 TI_SCI_PD_EXCLUSIVE>; + ti,timer-pwm; + /* Non-MPU Firmware usage */ + status = "reserved"; + }; + + mcu_timer8: timer@40480000 { + compatible = "ti,am654-timer"; + reg = <0x00 0x40480000 0x00 0x400>; + interrupts = ; + clocks = <&k3_clks 124 2>; + clock-names = "fck"; + assigned-clocks = <&k3_clks 124 2>; + assigned-clock-parents = <&k3_clks 124 3>; + power-domains = <&k3_pds 124 TI_SCI_PD_EXCLUSIVE>; + ti,timer-pwm; + /* Non-MPU Firmware usage */ + status = "reserved"; + }; + + mcu_timer9: timer@40490000 { + compatible = "ti,am654-timer"; + reg = <0x00 0x40490000 0x00 0x400>; + interrupts = ; + clocks = <&k3_clks 125 2>; + clock-names = "fck"; + assigned-clocks = <&k3_clks 125 2>; + assigned-clock-parents = <&k3_clks 125 3>; + power-domains = <&k3_pds 125 TI_SCI_PD_EXCLUSIVE>; + ti,timer-pwm; + /* Non-MPU Firmware usage */ + status = "reserved"; + }; + wkup_uart0: serial@42300000 { compatible = "ti,j721e-uart", "ti,am654-uart"; reg = <0x00 0x42300000 0x00 0x200>; -- cgit From 5a41bcff08f9c0705f4e6c576d168051a7b323be Mon Sep 17 00:00:00 2001 From: Nishanth Menon Date: Wed, 31 May 2023 16:32:15 -0500 Subject: arm64: dts: ti: k3-j784s4: Configure pinctrl for timer IO There are timer IO pads in the MCU domain, and in the MAIN domain. These pads can be muxed for the related timers. The details of the multiplexing can be found in the register documentation and Technical Reference Manual[1]. These are similar to J721e/J7200, but have different mux capabilities. [1] http://www.ti.com/lit/zip/spruj52 Signed-off-by: Nishanth Menon Reviewed-by: Tony Lindgren Link: https://lore.kernel.org/r/20230531213215.602395-7-nm@ti.com Signed-off-by: Vignesh Raghavendra --- arch/arm64/boot/dts/ti/k3-j784s4-main.dtsi | 18 ++++++++++++++++++ arch/arm64/boot/dts/ti/k3-j784s4-mcu-wakeup.dtsi | 22 ++++++++++++++++++++++ 2 files changed, 40 insertions(+) diff --git a/arch/arm64/boot/dts/ti/k3-j784s4-main.dtsi b/arch/arm64/boot/dts/ti/k3-j784s4-main.dtsi index 446350f099f3..2ea0adae6832 100644 --- a/arch/arm64/boot/dts/ti/k3-j784s4-main.dtsi +++ b/arch/arm64/boot/dts/ti/k3-j784s4-main.dtsi @@ -72,6 +72,24 @@ pinctrl-single,function-mask = <0xffffffff>; }; + /* TIMERIO pad input CTRLMMR_TIMER*_CTRL registers */ + main_timerio_input: pinctrl@104200 { + compatible = "pinctrl-single"; + reg = <0x00 0x104200 0x00 0x50>; + #pinctrl-cells = <1>; + pinctrl-single,register-width = <32>; + pinctrl-single,function-mask = <0x00000007>; + }; + + /* TIMERIO pad output CTCTRLMMR_TIMERIO*_CTRL registers */ + main_timerio_output: pinctrl@104280 { + compatible = "pinctrl-single"; + reg = <0x00 0x104280 0x00 0x20>; + #pinctrl-cells = <1>; + pinctrl-single,register-width = <32>; + pinctrl-single,function-mask = <0x0000001f>; + }; + main_crypto: crypto@4e00000 { compatible = "ti,j721e-sa2ul"; reg = <0x00 0x4e00000 0x00 0x1200>; diff --git a/arch/arm64/boot/dts/ti/k3-j784s4-mcu-wakeup.dtsi b/arch/arm64/boot/dts/ti/k3-j784s4-mcu-wakeup.dtsi index 591fce5ad56e..4dda88e777ab 100644 --- a/arch/arm64/boot/dts/ti/k3-j784s4-mcu-wakeup.dtsi +++ b/arch/arm64/boot/dts/ti/k3-j784s4-mcu-wakeup.dtsi @@ -83,6 +83,28 @@ ti,interrupt-ranges = <16 928 16>; }; + /* MCU_TIMERIO pad input CTRLMMR_MCU_TIMER*_CTRL registers */ + mcu_timerio_input: pinctrl@40f04200 { + compatible = "pinctrl-single"; + reg = <0x00 0x40f04200 0x00 0x28>; + #pinctrl-cells = <1>; + pinctrl-single,register-width = <32>; + pinctrl-single,function-mask = <0x0000000f>; + /* Non-MPU Firmware usage */ + status = "reserved"; + }; + + /* MCU_TIMERIO pad output CTRLMMR_MCU_TIMERIO*_CTRL registers */ + mcu_timerio_output: pinctrl@40f04280 { + compatible = "pinctrl-single"; + reg = <0x00 0x40f04280 0x00 0x28>; + #pinctrl-cells = <1>; + pinctrl-single,register-width = <32>; + pinctrl-single,function-mask = <0x0000000f>; + /* Non-MPU Firmware usage */ + status = "reserved"; + }; + mcu_conf: syscon@40f00000 { compatible = "ti,j721e-system-controller", "syscon", "simple-mfd"; reg = <0x00 0x40f00000 0x00 0x20000>; -- cgit From 12bf41da5c3a02a9a6f8059404ba97c39a8f1852 Mon Sep 17 00:00:00 2001 From: Nishanth Menon Date: Tue, 6 Jun 2023 13:22:07 -0500 Subject: arm64: dts: ti: k3-j721e-sk: Fixup reference to phandles array When referring to array of phandles, using <> to separate the array entries is better notation as it makes potential errors with phandle and cell arguments easier to catch. Fix the outliers to be consistent with the rest of the usage. Signed-off-by: Nishanth Menon Link: https://lore.kernel.org/r/20230606182220.3661956-2-nm@ti.com Signed-off-by: Vignesh Raghavendra --- arch/arm64/boot/dts/ti/k3-j721e-sk.dts | 20 ++++++++++---------- 1 file changed, 10 insertions(+), 10 deletions(-) diff --git a/arch/arm64/boot/dts/ti/k3-j721e-sk.dts b/arch/arm64/boot/dts/ti/k3-j721e-sk.dts index ffb9820cb61f..c8db9d7ea200 100644 --- a/arch/arm64/boot/dts/ti/k3-j721e-sk.dts +++ b/arch/arm64/boot/dts/ti/k3-j721e-sk.dts @@ -826,7 +826,7 @@ &mcu_cpsw { pinctrl-names = "default"; - pinctrl-0 = <&mcu_cpsw_pins_default &mcu_mdio_pins_default>; + pinctrl-0 = <&mcu_cpsw_pins_default>, <&mcu_mdio_pins_default>; }; &davinci_mdio { @@ -1013,55 +1013,55 @@ }; &mcu_r5fss0_core0 { - mboxes = <&mailbox0_cluster0 &mbox_mcu_r5fss0_core0>; + mboxes = <&mailbox0_cluster0>, <&mbox_mcu_r5fss0_core0>; memory-region = <&mcu_r5fss0_core0_dma_memory_region>, <&mcu_r5fss0_core0_memory_region>; }; &mcu_r5fss0_core1 { - mboxes = <&mailbox0_cluster0 &mbox_mcu_r5fss0_core1>; + mboxes = <&mailbox0_cluster0>, <&mbox_mcu_r5fss0_core1>; memory-region = <&mcu_r5fss0_core1_dma_memory_region>, <&mcu_r5fss0_core1_memory_region>; }; &main_r5fss0_core0 { - mboxes = <&mailbox0_cluster1 &mbox_main_r5fss0_core0>; + mboxes = <&mailbox0_cluster1>, <&mbox_main_r5fss0_core0>; memory-region = <&main_r5fss0_core0_dma_memory_region>, <&main_r5fss0_core0_memory_region>; }; &main_r5fss0_core1 { - mboxes = <&mailbox0_cluster1 &mbox_main_r5fss0_core1>; + mboxes = <&mailbox0_cluster1>, <&mbox_main_r5fss0_core1>; memory-region = <&main_r5fss0_core1_dma_memory_region>, <&main_r5fss0_core1_memory_region>; }; &main_r5fss1_core0 { - mboxes = <&mailbox0_cluster2 &mbox_main_r5fss1_core0>; + mboxes = <&mailbox0_cluster2>, <&mbox_main_r5fss1_core0>; memory-region = <&main_r5fss1_core0_dma_memory_region>, <&main_r5fss1_core0_memory_region>; }; &main_r5fss1_core1 { - mboxes = <&mailbox0_cluster2 &mbox_main_r5fss1_core1>; + mboxes = <&mailbox0_cluster2>, <&mbox_main_r5fss1_core1>; memory-region = <&main_r5fss1_core1_dma_memory_region>, <&main_r5fss1_core1_memory_region>; }; &c66_0 { - mboxes = <&mailbox0_cluster3 &mbox_c66_0>; + mboxes = <&mailbox0_cluster3>, <&mbox_c66_0>; memory-region = <&c66_0_dma_memory_region>, <&c66_0_memory_region>; }; &c66_1 { - mboxes = <&mailbox0_cluster3 &mbox_c66_1>; + mboxes = <&mailbox0_cluster3>, <&mbox_c66_1>; memory-region = <&c66_1_dma_memory_region>, <&c66_1_memory_region>; }; &c71_0 { - mboxes = <&mailbox0_cluster4 &mbox_c71_0>; + mboxes = <&mailbox0_cluster4>, <&mbox_c71_0>; memory-region = <&c71_0_dma_memory_region>, <&c71_0_memory_region>; }; -- cgit From 7335c987de3e4741908a032914bd3f2979898375 Mon Sep 17 00:00:00 2001 From: Nishanth Menon Date: Tue, 6 Jun 2023 13:22:08 -0500 Subject: arm64: dts: ti: k3-j721e-som-p0/common-proc-board: Fixup reference to phandles array When referring to array of phandles, using <> to separate the array entries is better notation as it makes potential errors with phandle and cell arguments easier to catch. Fix the outliers to be consistent with the rest of the usage. Signed-off-by: Nishanth Menon Link: https://lore.kernel.org/r/20230606182220.3661956-3-nm@ti.com Signed-off-by: Vignesh Raghavendra --- arch/arm64/boot/dts/ti/k3-j721e-common-proc-board.dts | 4 ++-- arch/arm64/boot/dts/ti/k3-j721e-som-p0.dtsi | 18 +++++++++--------- 2 files changed, 11 insertions(+), 11 deletions(-) diff --git a/arch/arm64/boot/dts/ti/k3-j721e-common-proc-board.dts b/arch/arm64/boot/dts/ti/k3-j721e-common-proc-board.dts index fa6ac3475290..2d5d75fffde9 100644 --- a/arch/arm64/boot/dts/ti/k3-j721e-common-proc-board.dts +++ b/arch/arm64/boot/dts/ti/k3-j721e-common-proc-board.dts @@ -23,7 +23,7 @@ compatible = "gpio-keys"; autorepeat; pinctrl-names = "default"; - pinctrl-0 = <&sw10_button_pins_default &sw11_button_pins_default>; + pinctrl-0 = <&sw10_button_pins_default>, <&sw11_button_pins_default>; sw10: switch-10 { label = "GPIO Key USER1"; @@ -702,7 +702,7 @@ &mcu_cpsw { pinctrl-names = "default"; - pinctrl-0 = <&mcu_cpsw_pins_default &mcu_mdio_pins_default>; + pinctrl-0 = <&mcu_cpsw_pins_default>, <&mcu_mdio_pins_default>; }; &davinci_mdio { diff --git a/arch/arm64/boot/dts/ti/k3-j721e-som-p0.dtsi b/arch/arm64/boot/dts/ti/k3-j721e-som-p0.dtsi index 67e52ee3a8bd..7a4c00ca9371 100644 --- a/arch/arm64/boot/dts/ti/k3-j721e-som-p0.dtsi +++ b/arch/arm64/boot/dts/ti/k3-j721e-som-p0.dtsi @@ -373,55 +373,55 @@ }; &mcu_r5fss0_core0 { - mboxes = <&mailbox0_cluster0 &mbox_mcu_r5fss0_core0>; + mboxes = <&mailbox0_cluster0>, <&mbox_mcu_r5fss0_core0>; memory-region = <&mcu_r5fss0_core0_dma_memory_region>, <&mcu_r5fss0_core0_memory_region>; }; &mcu_r5fss0_core1 { - mboxes = <&mailbox0_cluster0 &mbox_mcu_r5fss0_core1>; + mboxes = <&mailbox0_cluster0>, <&mbox_mcu_r5fss0_core1>; memory-region = <&mcu_r5fss0_core1_dma_memory_region>, <&mcu_r5fss0_core1_memory_region>; }; &main_r5fss0_core0 { - mboxes = <&mailbox0_cluster1 &mbox_main_r5fss0_core0>; + mboxes = <&mailbox0_cluster1>, <&mbox_main_r5fss0_core0>; memory-region = <&main_r5fss0_core0_dma_memory_region>, <&main_r5fss0_core0_memory_region>; }; &main_r5fss0_core1 { - mboxes = <&mailbox0_cluster1 &mbox_main_r5fss0_core1>; + mboxes = <&mailbox0_cluster1>, <&mbox_main_r5fss0_core1>; memory-region = <&main_r5fss0_core1_dma_memory_region>, <&main_r5fss0_core1_memory_region>; }; &main_r5fss1_core0 { - mboxes = <&mailbox0_cluster2 &mbox_main_r5fss1_core0>; + mboxes = <&mailbox0_cluster2>, <&mbox_main_r5fss1_core0>; memory-region = <&main_r5fss1_core0_dma_memory_region>, <&main_r5fss1_core0_memory_region>; }; &main_r5fss1_core1 { - mboxes = <&mailbox0_cluster2 &mbox_main_r5fss1_core1>; + mboxes = <&mailbox0_cluster2>, <&mbox_main_r5fss1_core1>; memory-region = <&main_r5fss1_core1_dma_memory_region>, <&main_r5fss1_core1_memory_region>; }; &c66_0 { - mboxes = <&mailbox0_cluster3 &mbox_c66_0>; + mboxes = <&mailbox0_cluster3>, <&mbox_c66_0>; memory-region = <&c66_0_dma_memory_region>, <&c66_0_memory_region>; }; &c66_1 { - mboxes = <&mailbox0_cluster3 &mbox_c66_1>; + mboxes = <&mailbox0_cluster3>, <&mbox_c66_1>; memory-region = <&c66_1_dma_memory_region>, <&c66_1_memory_region>; }; &c71_0 { - mboxes = <&mailbox0_cluster4 &mbox_c71_0>; + mboxes = <&mailbox0_cluster4>, <&mbox_c71_0>; memory-region = <&c71_0_dma_memory_region>, <&c71_0_memory_region>; }; -- cgit From d528c29fa7526adf7074fb166b99df7d5fd90670 Mon Sep 17 00:00:00 2001 From: Nishanth Menon Date: Tue, 6 Jun 2023 13:22:09 -0500 Subject: arm64: dts: ti: k3-j721e-beagleboneai64: Move camera gpio pinctrl to gpio node Move the GPIO mux configuration needed for camera module to work to the GPIO node instead of the I2C node. Camera nodes are maintained as overlay files, but the common mux is always needed to ensure that camera probes fine and ensuring the mux is configured as part of the GPIO module allows for the multiple overlay files to be simpler. Cc: Robert Nelson Suggested-by: Udit Kumar Signed-off-by: Nishanth Menon Link: https://lore.kernel.org/r/20230606182220.3661956-4-nm@ti.com Signed-off-by: Vignesh Raghavendra --- arch/arm64/boot/dts/ti/k3-j721e-beagleboneai64.dts | 9 +++++++-- 1 file changed, 7 insertions(+), 2 deletions(-) diff --git a/arch/arm64/boot/dts/ti/k3-j721e-beagleboneai64.dts b/arch/arm64/boot/dts/ti/k3-j721e-beagleboneai64.dts index a7b686cab3e6..e9fadacb4d5a 100644 --- a/arch/arm64/boot/dts/ti/k3-j721e-beagleboneai64.dts +++ b/arch/arm64/boot/dts/ti/k3-j721e-beagleboneai64.dts @@ -593,7 +593,7 @@ &main_i2c1 { status = "okay"; pinctrl-names = "default"; - pinctrl-0 = <&main_i2c1_pins_default &csi1_gpio_pins_default>; + pinctrl-0 = <&main_i2c1_pins_default>; clock-frequency = <400000>; }; @@ -623,7 +623,7 @@ &main_i2c5 { status = "okay"; pinctrl-names = "default"; - pinctrl-0 = <&main_i2c5_pins_default &csi0_gpio_pins_default>; + pinctrl-0 = <&main_i2c5_pins_default>; clock-frequency = <400000>; }; @@ -688,6 +688,11 @@ status = "disabled"; }; +&main_gpio0 { + pinctrl-names = "default"; + pinctrl-0 = <&csi1_gpio_pins_default>, <&csi0_gpio_pins_default>; +}; + &usb_serdes_mux { idle-states = <1>, <1>; /* USB0 to SERDES3, USB1 to SERDES2 */ }; -- cgit From 88875d4c70cabcb509e9836086fdf2064ef89468 Mon Sep 17 00:00:00 2001 From: Nishanth Menon Date: Tue, 6 Jun 2023 13:22:10 -0500 Subject: arm64: dts: ti: k3-j721e-beagleboneai64: Move eeprom WP gpio pinctrl to eeprom node Move the eeprom WP GPIO mux configuration to be part of the eeprom node instead of the I2C node. Cc: Robert Nelson Suggested-by: Udit Kumar Signed-off-by: Nishanth Menon Link: https://lore.kernel.org/r/20230606182220.3661956-5-nm@ti.com Signed-off-by: Vignesh Raghavendra --- arch/arm64/boot/dts/ti/k3-j721e-beagleboneai64.dts | 4 +++- 1 file changed, 3 insertions(+), 1 deletion(-) diff --git a/arch/arm64/boot/dts/ti/k3-j721e-beagleboneai64.dts b/arch/arm64/boot/dts/ti/k3-j721e-beagleboneai64.dts index e9fadacb4d5a..ecf7811ca8ff 100644 --- a/arch/arm64/boot/dts/ti/k3-j721e-beagleboneai64.dts +++ b/arch/arm64/boot/dts/ti/k3-j721e-beagleboneai64.dts @@ -639,12 +639,14 @@ &wkup_i2c0 { status = "okay"; pinctrl-names = "default"; - pinctrl-0 = <&wkup_i2c0_pins_default &eeprom_wp_pins_default>; + pinctrl-0 = <&wkup_i2c0_pins_default>; clock-frequency = <400000>; eeprom@50 { compatible = "atmel,24c04"; reg = <0x50>; + pinctrl-names = "default"; + pinctrl-0 = <&eeprom_wp_pins_default>; }; }; -- cgit From 4a701c01e7ff96966fcf2cf9df0d3dd851197317 Mon Sep 17 00:00:00 2001 From: Nishanth Menon Date: Tue, 6 Jun 2023 13:22:11 -0500 Subject: arm64: dts: ti: k3-j721e-beagleboneai64: Fixup reference to phandles array When referring to array of phandles, using <> to separate the array entries is better notation as it makes potential errors with phandle and cell arguments easier to catch. Fix the outliers to be consistent with the rest of the usage. Cc: Robert Nelson Signed-off-by: Nishanth Menon Link: https://lore.kernel.org/r/20230606182220.3661956-6-nm@ti.com Signed-off-by: Vignesh Raghavendra --- arch/arm64/boot/dts/ti/k3-j721e-beagleboneai64.dts | 23 +++++++++++----------- 1 file changed, 12 insertions(+), 11 deletions(-) diff --git a/arch/arm64/boot/dts/ti/k3-j721e-beagleboneai64.dts b/arch/arm64/boot/dts/ti/k3-j721e-beagleboneai64.dts index ecf7811ca8ff..961ca4fb3a43 100644 --- a/arch/arm64/boot/dts/ti/k3-j721e-beagleboneai64.dts +++ b/arch/arm64/boot/dts/ti/k3-j721e-beagleboneai64.dts @@ -682,7 +682,8 @@ &wkup_gpio0 { pinctrl-names = "default"; - pinctrl-0 = <&mcu_adc0_pins_default &mcu_adc1_pins_default &mikro_bus_pins_default>; + pinctrl-0 = <&mcu_adc0_pins_default>, <&mcu_adc1_pins_default>, + <&mikro_bus_pins_default>; }; &wkup_gpio1 { @@ -766,7 +767,7 @@ &usbss1 { pinctrl-names = "default"; - pinctrl-0 = <&main_usbss1_pins_default &mcu_usbss1_pins_default>; + pinctrl-0 = <&main_usbss1_pins_default>, <&mcu_usbss1_pins_default>; ti,vbus-divider; }; @@ -965,55 +966,55 @@ }; &mcu_r5fss0_core0 { - mboxes = <&mailbox0_cluster0 &mbox_mcu_r5fss0_core0>; + mboxes = <&mailbox0_cluster0>, <&mbox_mcu_r5fss0_core0>; memory-region = <&mcu_r5fss0_core0_dma_memory_region>, <&mcu_r5fss0_core0_memory_region>; }; &mcu_r5fss0_core1 { - mboxes = <&mailbox0_cluster0 &mbox_mcu_r5fss0_core1>; + mboxes = <&mailbox0_cluster0>, <&mbox_mcu_r5fss0_core1>; memory-region = <&mcu_r5fss0_core1_dma_memory_region>, <&mcu_r5fss0_core1_memory_region>; }; &main_r5fss0_core0 { - mboxes = <&mailbox0_cluster1 &mbox_main_r5fss0_core0>; + mboxes = <&mailbox0_cluster1>, <&mbox_main_r5fss0_core0>; memory-region = <&main_r5fss0_core0_dma_memory_region>, <&main_r5fss0_core0_memory_region>; }; &main_r5fss0_core1 { - mboxes = <&mailbox0_cluster1 &mbox_main_r5fss0_core1>; + mboxes = <&mailbox0_cluster1>, <&mbox_main_r5fss0_core1>; memory-region = <&main_r5fss0_core1_dma_memory_region>, <&main_r5fss0_core1_memory_region>; }; &main_r5fss1_core0 { - mboxes = <&mailbox0_cluster2 &mbox_main_r5fss1_core0>; + mboxes = <&mailbox0_cluster2>, <&mbox_main_r5fss1_core0>; memory-region = <&main_r5fss1_core0_dma_memory_region>, <&main_r5fss1_core0_memory_region>; }; &main_r5fss1_core1 { - mboxes = <&mailbox0_cluster2 &mbox_main_r5fss1_core1>; + mboxes = <&mailbox0_cluster2>, <&mbox_main_r5fss1_core1>; memory-region = <&main_r5fss1_core1_dma_memory_region>, <&main_r5fss1_core1_memory_region>; }; &c66_0 { - mboxes = <&mailbox0_cluster3 &mbox_c66_0>; + mboxes = <&mailbox0_cluster3>, <&mbox_c66_0>; memory-region = <&c66_0_dma_memory_region>, <&c66_0_memory_region>; }; &c66_1 { - mboxes = <&mailbox0_cluster3 &mbox_c66_1>; + mboxes = <&mailbox0_cluster3>, <&mbox_c66_1>; memory-region = <&c66_1_dma_memory_region>, <&c66_1_memory_region>; }; &c71_0 { - mboxes = <&mailbox0_cluster4 &mbox_c71_0>; + mboxes = <&mailbox0_cluster4>, <&mbox_c71_0>; memory-region = <&c71_0_dma_memory_region>, <&c71_0_memory_region>; }; -- cgit From 56ccd4b1eb52e153d557c7c7ae19f849e5d5c2e1 Mon Sep 17 00:00:00 2001 From: Nishanth Menon Date: Tue, 6 Jun 2023 13:22:12 -0500 Subject: arm64: dts: ti: k3-am642-phyboard-electra-rdk: Fixup reference to phandles array When referring to array of phandles, using <> to separate the array entries is better notation as it makes potential errors with phandle and cell arguments easier to catch. Fix the outliers to be consistent with the rest of the usage. Cc: Wadim Egorov Signed-off-by: Nishanth Menon Link: https://lore.kernel.org/r/20230606182220.3661956-7-nm@ti.com Signed-off-by: Vignesh Raghavendra --- arch/arm64/boot/dts/ti/k3-am642-phyboard-electra-rdk.dts | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm64/boot/dts/ti/k3-am642-phyboard-electra-rdk.dts b/arch/arm64/boot/dts/ti/k3-am642-phyboard-electra-rdk.dts index 8199ac06c09a..8d9ca6e5b087 100644 --- a/arch/arm64/boot/dts/ti/k3-am642-phyboard-electra-rdk.dts +++ b/arch/arm64/boot/dts/ti/k3-am642-phyboard-electra-rdk.dts @@ -76,7 +76,7 @@ leds { compatible = "gpio-leds"; pinctrl-names = "default"; - pinctrl-0 = <&leds_pins_default &user_leds_pins_default>; + pinctrl-0 = <&leds_pins_default>, <&user_leds_pins_default>; led-1 { color = ; -- cgit From a6550e2547acbcd7b01ea26d447a437140df7c43 Mon Sep 17 00:00:00 2001 From: Nishanth Menon Date: Tue, 6 Jun 2023 13:22:13 -0500 Subject: arm64: dts: ti: k3-j7200-som/common-proc-board: Fixup reference to phandles array When referring to array of phandles, using <> to separate the array entries is better notation as it makes potential errors with phandle and cell arguments easier to catch. Fix the outliers to be consistent with the rest of the usage. Signed-off-by: Nishanth Menon Link: https://lore.kernel.org/r/20230606182220.3661956-8-nm@ti.com Signed-off-by: Vignesh Raghavendra --- arch/arm64/boot/dts/ti/k3-j7200-common-proc-board.dts | 2 +- arch/arm64/boot/dts/ti/k3-j7200-som-p0.dtsi | 8 ++++---- 2 files changed, 5 insertions(+), 5 deletions(-) diff --git a/arch/arm64/boot/dts/ti/k3-j7200-common-proc-board.dts b/arch/arm64/boot/dts/ti/k3-j7200-common-proc-board.dts index e1017027d649..e8a2997289ba 100644 --- a/arch/arm64/boot/dts/ti/k3-j7200-common-proc-board.dts +++ b/arch/arm64/boot/dts/ti/k3-j7200-common-proc-board.dts @@ -203,7 +203,7 @@ &mcu_cpsw { pinctrl-names = "default"; - pinctrl-0 = <&mcu_cpsw_pins_default &mcu_mdio_pins_default>; + pinctrl-0 = <&mcu_cpsw_pins_default>, <&mcu_mdio_pins_default>; }; &davinci_mdio { diff --git a/arch/arm64/boot/dts/ti/k3-j7200-som-p0.dtsi b/arch/arm64/boot/dts/ti/k3-j7200-som-p0.dtsi index 2a743b895074..e763d571b916 100644 --- a/arch/arm64/boot/dts/ti/k3-j7200-som-p0.dtsi +++ b/arch/arm64/boot/dts/ti/k3-j7200-som-p0.dtsi @@ -214,25 +214,25 @@ }; &mcu_r5fss0_core0 { - mboxes = <&mailbox0_cluster0 &mbox_mcu_r5fss0_core0>; + mboxes = <&mailbox0_cluster0>, <&mbox_mcu_r5fss0_core0>; memory-region = <&mcu_r5fss0_core0_dma_memory_region>, <&mcu_r5fss0_core0_memory_region>; }; &mcu_r5fss0_core1 { - mboxes = <&mailbox0_cluster0 &mbox_mcu_r5fss0_core1>; + mboxes = <&mailbox0_cluster0>, <&mbox_mcu_r5fss0_core1>; memory-region = <&mcu_r5fss0_core1_dma_memory_region>, <&mcu_r5fss0_core1_memory_region>; }; &main_r5fss0_core0 { - mboxes = <&mailbox0_cluster1 &mbox_main_r5fss0_core0>; + mboxes = <&mailbox0_cluster1>, <&mbox_main_r5fss0_core0>; memory-region = <&main_r5fss0_core0_dma_memory_region>, <&main_r5fss0_core0_memory_region>; }; &main_r5fss0_core1 { - mboxes = <&mailbox0_cluster1 &mbox_main_r5fss0_core1>; + mboxes = <&mailbox0_cluster1>, <&mbox_main_r5fss0_core1>; memory-region = <&main_r5fss0_core1_dma_memory_region>, <&main_r5fss0_core1_memory_region>; }; -- cgit From 6a2baa853500d1bbe986f29aacce4a0c859bf017 Mon Sep 17 00:00:00 2001 From: Nishanth Menon Date: Tue, 6 Jun 2023 13:22:14 -0500 Subject: arm64: dts: ti: k3-j721s2-common-proc-board: Fixup reference to phandles array When referring to array of phandles, using <> to separate the array entries is better notation as it makes potential errors with phandle and cell arguments easier to catch. Fix the outliers to be consistent with the rest of the usage. Signed-off-by: Nishanth Menon Link: https://lore.kernel.org/r/20230606182220.3661956-9-nm@ti.com Signed-off-by: Vignesh Raghavendra --- arch/arm64/boot/dts/ti/k3-j721s2-common-proc-board.dts | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm64/boot/dts/ti/k3-j721s2-common-proc-board.dts b/arch/arm64/boot/dts/ti/k3-j721s2-common-proc-board.dts index 924e0dc4ac1e..a5ba2945c35f 100644 --- a/arch/arm64/boot/dts/ti/k3-j721s2-common-proc-board.dts +++ b/arch/arm64/boot/dts/ti/k3-j721s2-common-proc-board.dts @@ -327,7 +327,7 @@ &mcu_cpsw { pinctrl-names = "default"; - pinctrl-0 = <&mcu_cpsw_pins_default &mcu_mdio_pins_default>; + pinctrl-0 = <&mcu_cpsw_pins_default>, <&mcu_mdio_pins_default>; }; &davinci_mdio { -- cgit From 875aad10d219494bb0ef0880b1b4a33f99c98a13 Mon Sep 17 00:00:00 2001 From: Nishanth Menon Date: Tue, 6 Jun 2023 13:22:15 -0500 Subject: arm64: dts: ti: k3-am625-sk: Fixup reference to phandles array When referring to array of phandles, using <> to separate the array entries is better notation as it makes potential errors with phandle and cell arguments easier to catch. Fix the outliers to be consistent with the rest of the usage. Signed-off-by: Nishanth Menon Link: https://lore.kernel.org/r/20230606182220.3661956-10-nm@ti.com Signed-off-by: Vignesh Raghavendra --- arch/arm64/boot/dts/ti/k3-am625-sk.dts | 3 +-- 1 file changed, 1 insertion(+), 2 deletions(-) diff --git a/arch/arm64/boot/dts/ti/k3-am625-sk.dts b/arch/arm64/boot/dts/ti/k3-am625-sk.dts index 729f95e19042..c0a69093c324 100644 --- a/arch/arm64/boot/dts/ti/k3-am625-sk.dts +++ b/arch/arm64/boot/dts/ti/k3-am625-sk.dts @@ -183,8 +183,7 @@ &cpsw3g { pinctrl-names = "default"; - pinctrl-0 = <&main_rgmii1_pins_default - &main_rgmii2_pins_default>; + pinctrl-0 = <&main_rgmii1_pins_default>, <&main_rgmii2_pins_default>; }; &cpsw_port2 { -- cgit From bb867df51d3b7f305222405c4e01373efc8866c7 Mon Sep 17 00:00:00 2001 From: Nishanth Menon Date: Tue, 6 Jun 2023 13:22:16 -0500 Subject: arm64: dts: ti: k3-am64-evm: Fixup reference to phandles array When referring to array of phandles, using <> to separate the array entries is better notation as it makes potential errors with phandle and cell arguments easier to catch. Fix the outliers to be consistent with the rest of the usage. Signed-off-by: Nishanth Menon Link: https://lore.kernel.org/r/20230606182220.3661956-11-nm@ti.com Signed-off-by: Vignesh Raghavendra --- arch/arm64/boot/dts/ti/k3-am642-evm.dts | 11 +++++------ 1 file changed, 5 insertions(+), 6 deletions(-) diff --git a/arch/arm64/boot/dts/ti/k3-am642-evm.dts b/arch/arm64/boot/dts/ti/k3-am642-evm.dts index 309500e4c237..c3fd417f3842 100644 --- a/arch/arm64/boot/dts/ti/k3-am642-evm.dts +++ b/arch/arm64/boot/dts/ti/k3-am642-evm.dts @@ -487,8 +487,7 @@ &cpsw3g { pinctrl-names = "default"; - pinctrl-0 = <&rgmii1_pins_default - &rgmii2_pins_default>; + pinctrl-0 = <&rgmii1_pins_default>, <&rgmii2_pins_default>; }; &cpsw_port1 { @@ -615,25 +614,25 @@ }; &main_r5fss0_core0 { - mboxes = <&mailbox0_cluster2 &mbox_main_r5fss0_core0>; + mboxes = <&mailbox0_cluster2>, <&mbox_main_r5fss0_core0>; memory-region = <&main_r5fss0_core0_dma_memory_region>, <&main_r5fss0_core0_memory_region>; }; &main_r5fss0_core1 { - mboxes = <&mailbox0_cluster2 &mbox_main_r5fss0_core1>; + mboxes = <&mailbox0_cluster2>, <&mbox_main_r5fss0_core1>; memory-region = <&main_r5fss0_core1_dma_memory_region>, <&main_r5fss0_core1_memory_region>; }; &main_r5fss1_core0 { - mboxes = <&mailbox0_cluster4 &mbox_main_r5fss1_core0>; + mboxes = <&mailbox0_cluster4>, <&mbox_main_r5fss1_core0>; memory-region = <&main_r5fss1_core0_dma_memory_region>, <&main_r5fss1_core0_memory_region>; }; &main_r5fss1_core1 { - mboxes = <&mailbox0_cluster4 &mbox_main_r5fss1_core1>; + mboxes = <&mailbox0_cluster4>, <&mbox_main_r5fss1_core1>; memory-region = <&main_r5fss1_core1_dma_memory_region>, <&main_r5fss1_core1_memory_region>; }; -- cgit From 0e97d245633bffc0ae348c95f98a2af5b973811c Mon Sep 17 00:00:00 2001 From: Nishanth Menon Date: Tue, 6 Jun 2023 13:22:17 -0500 Subject: arm64: dts: ti: k3-am64-sk: Fixup reference to phandles array When referring to array of phandles, using <> to separate the array entries is better notation as it makes potential errors with phandle and cell arguments easier to catch. Fix the outliers to be consistent with the rest of the usage. Signed-off-by: Nishanth Menon Link: https://lore.kernel.org/r/20230606182220.3661956-12-nm@ti.com Signed-off-by: Vignesh Raghavendra --- arch/arm64/boot/dts/ti/k3-am642-sk.dts | 11 +++++------ 1 file changed, 5 insertions(+), 6 deletions(-) diff --git a/arch/arm64/boot/dts/ti/k3-am642-sk.dts b/arch/arm64/boot/dts/ti/k3-am642-sk.dts index 9ea012b883e8..3e27bd65cb2e 100644 --- a/arch/arm64/boot/dts/ti/k3-am642-sk.dts +++ b/arch/arm64/boot/dts/ti/k3-am642-sk.dts @@ -480,8 +480,7 @@ &cpsw3g { pinctrl-names = "default"; - pinctrl-0 = <&rgmii1_pins_default - &rgmii2_pins_default>; + pinctrl-0 = <&rgmii1_pins_default>, <&rgmii2_pins_default>; }; &cpsw_port1 { @@ -613,25 +612,25 @@ }; &main_r5fss0_core0 { - mboxes = <&mailbox0_cluster2 &mbox_main_r5fss0_core0>; + mboxes = <&mailbox0_cluster2>, <&mbox_main_r5fss0_core0>; memory-region = <&main_r5fss0_core0_dma_memory_region>, <&main_r5fss0_core0_memory_region>; }; &main_r5fss0_core1 { - mboxes = <&mailbox0_cluster2 &mbox_main_r5fss0_core1>; + mboxes = <&mailbox0_cluster2>, <&mbox_main_r5fss0_core1>; memory-region = <&main_r5fss0_core1_dma_memory_region>, <&main_r5fss0_core1_memory_region>; }; &main_r5fss1_core0 { - mboxes = <&mailbox0_cluster4 &mbox_main_r5fss1_core0>; + mboxes = <&mailbox0_cluster4>, <&mbox_main_r5fss1_core0>; memory-region = <&main_r5fss1_core0_dma_memory_region>, <&main_r5fss1_core0_memory_region>; }; &main_r5fss1_core1 { - mboxes = <&mailbox0_cluster4 &mbox_main_r5fss1_core1>; + mboxes = <&mailbox0_cluster4>, <&mbox_main_r5fss1_core1>; memory-region = <&main_r5fss1_core1_dma_memory_region>, <&main_r5fss1_core1_memory_region>; }; -- cgit From f722090aeb70ca67b5f5a37a39a26fca29664dce Mon Sep 17 00:00:00 2001 From: Nishanth Menon Date: Tue, 6 Jun 2023 13:22:18 -0500 Subject: arm64: dts: ti: k3-am65-iot*: Fixup reference to phandles array When referring to array of phandles, using <> to separate the array entries is better notation as it makes potential errors with phandle and cell arguments easier to catch. Fix the outliers to be consistent with the rest of the usage. Cc: Jan Kiszka Reviewed-by: Jan Kiszka Signed-off-by: Nishanth Menon Link: https://lore.kernel.org/r/20230606182220.3661956-13-nm@ti.com Signed-off-by: Vignesh Raghavendra --- arch/arm64/boot/dts/ti/k3-am65-iot2050-common.dtsi | 17 ++++++++--------- .../boot/dts/ti/k3-am6548-iot2050-advanced-m2.dts | 18 ++++++++---------- 2 files changed, 16 insertions(+), 19 deletions(-) diff --git a/arch/arm64/boot/dts/ti/k3-am65-iot2050-common.dtsi b/arch/arm64/boot/dts/ti/k3-am65-iot2050-common.dtsi index 6b052a0ecfa1..bbbb5c169ccc 100644 --- a/arch/arm64/boot/dts/ti/k3-am65-iot2050-common.dtsi +++ b/arch/arm64/boot/dts/ti/k3-am65-iot2050-common.dtsi @@ -384,13 +384,12 @@ &wkup_gpio0 { pinctrl-names = "default"; - pinctrl-0 = < - &arduino_io_d2_to_d3_pins_default - &arduino_i2c_aio_switch_pins_default - &arduino_io_oe_pins_default - &push_button_pins_default - &db9_com_mode_pins_default - >; + pinctrl-0 = + <&arduino_io_d2_to_d3_pins_default>, + <&arduino_i2c_aio_switch_pins_default>, + <&arduino_io_oe_pins_default>, + <&push_button_pins_default>, + <&db9_com_mode_pins_default>; gpio-line-names = /* 0..9 */ "wkup_gpio0-base", "", "", "", "UART0-mode1", "UART0-mode0", @@ -711,11 +710,11 @@ &mcu_r5fss0_core0 { memory-region = <&mcu_r5fss0_core0_dma_memory_region>, <&mcu_r5fss0_core0_memory_region>; - mboxes = <&mailbox0_cluster0 &mbox_mcu_r5fss0_core0>; + mboxes = <&mailbox0_cluster0>, <&mbox_mcu_r5fss0_core0>; }; &mcu_r5fss0_core1 { memory-region = <&mcu_r5fss0_core1_dma_memory_region>, <&mcu_r5fss0_core1_memory_region>; - mboxes = <&mailbox0_cluster1 &mbox_mcu_r5fss0_core1>; + mboxes = <&mailbox0_cluster1>, <&mbox_mcu_r5fss0_core1>; }; diff --git a/arch/arm64/boot/dts/ti/k3-am6548-iot2050-advanced-m2.dts b/arch/arm64/boot/dts/ti/k3-am6548-iot2050-advanced-m2.dts index 9400e35882a6..9209b5a7baa4 100644 --- a/arch/arm64/boot/dts/ti/k3-am6548-iot2050-advanced-m2.dts +++ b/arch/arm64/boot/dts/ti/k3-am6548-iot2050-advanced-m2.dts @@ -66,20 +66,18 @@ &main_gpio0 { pinctrl-names = "default"; - pinctrl-0 = < - &main_m2_pcie_mux_control - &arduino_io_d4_to_d9_pins_default - >; + pinctrl-0 = + <&main_m2_pcie_mux_control>, + <&arduino_io_d4_to_d9_pins_default>; }; &main_gpio1 { pinctrl-names = "default"; - pinctrl-0 = < - &main_m2_enable_pins_default - &main_pmx0_m2_config_pins_default - &main_pmx1_m2_config_pins_default - &cp2102n_reset_pin_default - >; + pinctrl-0 = + <&main_m2_enable_pins_default>, + <&main_pmx0_m2_config_pins_default>, + <&main_pmx1_m2_config_pins_default>, + <&cp2102n_reset_pin_default>; }; /* -- cgit From 9da060be7491cc67323b8f4386ebc4524eba5970 Mon Sep 17 00:00:00 2001 From: Nishanth Menon Date: Tue, 6 Jun 2023 13:22:19 -0500 Subject: arm64: dts: ti: k3-am654-base-board: Fixup reference to phandles array When referring to array of phandles, using <> to separate the array entries is better notation as it makes potential errors with phandle and cell arguments easier to catch. Fix the outliers to be consistent with the rest of the usage. Signed-off-by: Nishanth Menon Link: https://lore.kernel.org/r/20230606182220.3661956-14-nm@ti.com Signed-off-by: Vignesh Raghavendra --- arch/arm64/boot/dts/ti/k3-am654-base-board.dts | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/arch/arm64/boot/dts/ti/k3-am654-base-board.dts b/arch/arm64/boot/dts/ti/k3-am654-base-board.dts index 73dd50586c64..c8c80cd756d9 100644 --- a/arch/arm64/boot/dts/ti/k3-am654-base-board.dts +++ b/arch/arm64/boot/dts/ti/k3-am654-base-board.dts @@ -520,13 +520,13 @@ &mcu_r5fss0_core0 { memory-region = <&mcu_r5fss0_core0_dma_memory_region>, <&mcu_r5fss0_core0_memory_region>; - mboxes = <&mailbox0_cluster0 &mbox_mcu_r5fss0_core0>; + mboxes = <&mailbox0_cluster0>, <&mbox_mcu_r5fss0_core0>; }; &mcu_r5fss0_core1 { memory-region = <&mcu_r5fss0_core1_dma_memory_region>, <&mcu_r5fss0_core1_memory_region>; - mboxes = <&mailbox0_cluster1 &mbox_mcu_r5fss0_core1>; + mboxes = <&mailbox0_cluster1>, <&mbox_mcu_r5fss0_core1>; }; &ospi0 { -- cgit From 918ef215db22b18b75292b6e5bcb763ce27e0483 Mon Sep 17 00:00:00 2001 From: Nishanth Menon Date: Tue, 6 Jun 2023 13:22:20 -0500 Subject: arm64: dts: ti: k3-am68-sk-base-board: Fixup reference to phandles array When referring to array of phandles, using <> to separate the array entries is better notation as it makes potential errors with phandle and cell arguments easier to catch. Fix the outliers to be consistent with the rest of the usage. Signed-off-by: Nishanth Menon Link: https://lore.kernel.org/r/20230606182220.3661956-15-nm@ti.com Signed-off-by: Vignesh Raghavendra --- arch/arm64/boot/dts/ti/k3-am68-sk-base-board.dts | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm64/boot/dts/ti/k3-am68-sk-base-board.dts b/arch/arm64/boot/dts/ti/k3-am68-sk-base-board.dts index 27a43a8ecffd..ae9116655a83 100644 --- a/arch/arm64/boot/dts/ti/k3-am68-sk-base-board.dts +++ b/arch/arm64/boot/dts/ti/k3-am68-sk-base-board.dts @@ -287,7 +287,7 @@ &mcu_cpsw { pinctrl-names = "default"; - pinctrl-0 = <&mcu_cpsw_pins_default &mcu_mdio_pins_default>; + pinctrl-0 = <&mcu_cpsw_pins_default>, <&mcu_mdio_pins_default>; }; &davinci_mdio { -- cgit From 74428680d71a37e6ee458b6eccf085114e0e4167 Mon Sep 17 00:00:00 2001 From: Dasnavis Sabiya Date: Mon, 5 Jun 2023 23:15:51 +0530 Subject: arm64: dts: ti: k3-am69-sk: Add eMMC mmc0 support Add support for eMMC card connected to main sdhci0 instance. Signed-off-by: Dasnavis Sabiya Reviewed-by: Nishanth Menon Link: https://lore.kernel.org/r/20230605174551.160262-1-sabiya.d@ti.com Signed-off-by: Vignesh Raghavendra --- arch/arm64/boot/dts/ti/k3-am69-sk.dts | 9 +++++++++ 1 file changed, 9 insertions(+) diff --git a/arch/arm64/boot/dts/ti/k3-am69-sk.dts b/arch/arm64/boot/dts/ti/k3-am69-sk.dts index bc49ba534790..3099c0098ca6 100644 --- a/arch/arm64/boot/dts/ti/k3-am69-sk.dts +++ b/arch/arm64/boot/dts/ti/k3-am69-sk.dts @@ -22,6 +22,7 @@ aliases { serial2 = &main_uart8; + mmc0 = &main_sdhci0; mmc1 = &main_sdhci1; i2c0 = &main_i2c0; }; @@ -165,6 +166,14 @@ }; }; +&main_sdhci0 { + /* eMMC */ + status = "okay"; + non-removable; + ti,driver-strength-ohm = <50>; + disable-wp; +}; + &main_sdhci1 { /* SD card */ status = "okay"; -- cgit From 1f36d0e8be3ae7717c801e954275fba6247b2f46 Mon Sep 17 00:00:00 2001 From: Neha Malcom Francis Date: Mon, 5 Jun 2023 16:34:43 +0530 Subject: arm64: dts: ti: k3-j721s2: Change CPTS clock parent MAIN_PLL0 has a flag set in DM (Device Manager) that removes it's capability to re-initialise clock frequencies. CPTS and RGMII has MAIN_PLL3 as their parent which does not have this flag. While RGMII needs this reinitialisation to default frequency to be able to get 250MHz with its divider, CPTS can not get its required 200MHz with its divider. Thus, move CPTS clock parent on J721S2 from MAIN_PLL3_HSDIV1 to MAIN_PLL0_HSDIV6. (Note: even GTC will be moved from MAIN_PLL3 to MAIN_PLL0 in U-Boot side for the same reason) Signed-off-by: Neha Malcom Francis Link: https://lore.kernel.org/r/20230605110443.84568-1-n-francis@ti.com Signed-off-by: Vignesh Raghavendra --- arch/arm64/boot/dts/ti/k3-j721s2-main.dtsi | 2 ++ arch/arm64/boot/dts/ti/k3-j721s2-mcu-wakeup.dtsi | 2 ++ 2 files changed, 4 insertions(+) diff --git a/arch/arm64/boot/dts/ti/k3-j721s2-main.dtsi b/arch/arm64/boot/dts/ti/k3-j721s2-main.dtsi index 12a5b7008aca..ed79ab3a3271 100644 --- a/arch/arm64/boot/dts/ti/k3-j721s2-main.dtsi +++ b/arch/arm64/boot/dts/ti/k3-j721s2-main.dtsi @@ -1030,6 +1030,8 @@ reg-names = "cpts"; clocks = <&k3_clks 226 5>; clock-names = "cpts"; + assigned-clocks = <&k3_clks 226 5>; /* NAVSS0_CPTS_0_RCLK */ + assigned-clock-parents = <&k3_clks 226 7>; /* MAIN_0_HSDIVOUT6_CLK */ interrupts-extended = <&main_navss_intr 391>; interrupt-names = "cpts"; ti,cpts-periodic-outputs = <6>; diff --git a/arch/arm64/boot/dts/ti/k3-j721s2-mcu-wakeup.dtsi b/arch/arm64/boot/dts/ti/k3-j721s2-mcu-wakeup.dtsi index 939cd037a814..5734c67b6763 100644 --- a/arch/arm64/boot/dts/ti/k3-j721s2-mcu-wakeup.dtsi +++ b/arch/arm64/boot/dts/ti/k3-j721s2-mcu-wakeup.dtsi @@ -525,6 +525,8 @@ reg = <0x0 0x3d000 0x0 0x400>; clocks = <&k3_clks 29 3>; clock-names = "cpts"; + assigned-clocks = <&k3_clks 29 3>; /* CPTS_RFT_CLK */ + assigned-clock-parents = <&k3_clks 29 5>; /* MAIN_0_HSDIVOUT6_CLK */ interrupts-extended = <&gic500 GIC_SPI 858 IRQ_TYPE_LEVEL_HIGH>; interrupt-names = "cpts"; ti,cpts-ext-ts-inputs = <4>; -- cgit From c10a9df30e3401bd5a5ee43f1afd6c2b2ca75ad7 Mon Sep 17 00:00:00 2001 From: Nishanth Menon Date: Fri, 2 Jun 2023 16:49:30 -0500 Subject: arm64: dts: ti: k3-j784s4-evm: Fix main_i2c0 alias main_i2c0 is aliased as i2c0 which creates a problem for u-boot R5 SPL attempting to reuse the same definition in the common board detection logic as it looks for the first i2c instance as the bus on which to detect the eeprom to understand the board variant involved. Switch main_i2c0 to i2c3 alias allowing us to introduce wkup_i2c0 and potentially space for mcu_i2c instances in the gap for follow on patches. Fixes: e20a06aca5c9 ("arm64: dts: ti: Add support for J784S4 EVM board") Signed-off-by: Nishanth Menon Reviewed-by: Udit Kumar Link: https://lore.kernel.org/r/20230602214937.2349545-2-nm@ti.com Signed-off-by: Vignesh Raghavendra --- arch/arm64/boot/dts/ti/k3-j784s4-evm.dts | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm64/boot/dts/ti/k3-j784s4-evm.dts b/arch/arm64/boot/dts/ti/k3-j784s4-evm.dts index 8271ac16b319..bf22b86cca93 100644 --- a/arch/arm64/boot/dts/ti/k3-j784s4-evm.dts +++ b/arch/arm64/boot/dts/ti/k3-j784s4-evm.dts @@ -23,7 +23,7 @@ serial2 = &main_uart8; mmc0 = &main_sdhci0; mmc1 = &main_sdhci1; - i2c0 = &main_i2c0; + i2c3 = &main_i2c0; }; memory@80000000 { -- cgit From 14462bd0b247d05070d48d0f02eb7ca2680ab7bd Mon Sep 17 00:00:00 2001 From: Thejasvi Konduru Date: Wed, 3 May 2023 14:01:43 +0530 Subject: arm64: dts: ti: k3-j784s4: Fix wakeup pinmux range and pinctrl node offsets The wkup_pmx register region in j784s4 has multiple non-addressable regions, hence the existing wkup_pmx region is split as follows to avoid the non-addressable regions. The pinctrl node offsets are also corrected as per the newly split wkup_pmx* nodes. wkup_pmx0 -> 13 pins (WKUP_PADCONFIG 0 - 12) wkup_pmx1 -> 11 pins (WKUP_PADCONFIG 14 - 24) wkup_pmx2 -> 72 pins (WKUP_PADCONFIG 26 - 97) wkup_pmx3 -> 1 pin (WKUP_PADCONFIG 100) Fixes: 4664ebd8346a ("arm64: dts: ti: Add initial support for J784S4 SoC") Signed-off-by: Thejasvi Konduru Reviewed-by: Nishanth Menon Link: https://lore.kernel.org/r/20230503083143.32369-1-t-konduru@ti.com Signed-off-by: Vignesh Raghavendra --- arch/arm64/boot/dts/ti/k3-j784s4-evm.dts | 30 ++++++++++++------------ arch/arm64/boot/dts/ti/k3-j784s4-mcu-wakeup.dtsi | 29 ++++++++++++++++++++++- 2 files changed, 43 insertions(+), 16 deletions(-) diff --git a/arch/arm64/boot/dts/ti/k3-j784s4-evm.dts b/arch/arm64/boot/dts/ti/k3-j784s4-evm.dts index bf22b86cca93..e51471f8e1fd 100644 --- a/arch/arm64/boot/dts/ti/k3-j784s4-evm.dts +++ b/arch/arm64/boot/dts/ti/k3-j784s4-evm.dts @@ -285,28 +285,28 @@ }; }; -&wkup_pmx0 { +&wkup_pmx2 { mcu_cpsw_pins_default: mcu-cpsw-pins-default { pinctrl-single,pins = < - J784S4_WKUP_IOPAD(0x094, PIN_INPUT, 0) /* (A35) MCU_RGMII1_RD0 */ - J784S4_WKUP_IOPAD(0x090, PIN_INPUT, 0) /* (B36) MCU_RGMII1_RD1 */ - J784S4_WKUP_IOPAD(0x08c, PIN_INPUT, 0) /* (C36) MCU_RGMII1_RD2 */ - J784S4_WKUP_IOPAD(0x088, PIN_INPUT, 0) /* (D36) MCU_RGMII1_RD3 */ - J784S4_WKUP_IOPAD(0x084, PIN_INPUT, 0) /* (B37) MCU_RGMII1_RXC */ - J784S4_WKUP_IOPAD(0x06c, PIN_INPUT, 0) /* (C37) MCU_RGMII1_RX_CTL */ - J784S4_WKUP_IOPAD(0x07c, PIN_OUTPUT, 0) /* (D37) MCU_RGMII1_TD0 */ - J784S4_WKUP_IOPAD(0x078, PIN_OUTPUT, 0) /* (D38) MCU_RGMII1_TD1 */ - J784S4_WKUP_IOPAD(0x074, PIN_OUTPUT, 0) /* (E37) MCU_RGMII1_TD2 */ - J784S4_WKUP_IOPAD(0x070, PIN_OUTPUT, 0) /* (E38) MCU_RGMII1_TD3 */ - J784S4_WKUP_IOPAD(0x080, PIN_OUTPUT, 0) /* (E36) MCU_RGMII1_TXC */ - J784S4_WKUP_IOPAD(0x068, PIN_OUTPUT, 0) /* (C38) MCU_RGMII1_TX_CTL */ + J784S4_WKUP_IOPAD(0x02c, PIN_INPUT, 0) /* (A35) MCU_RGMII1_RD0 */ + J784S4_WKUP_IOPAD(0x028, PIN_INPUT, 0) /* (B36) MCU_RGMII1_RD1 */ + J784S4_WKUP_IOPAD(0x024, PIN_INPUT, 0) /* (C36) MCU_RGMII1_RD2 */ + J784S4_WKUP_IOPAD(0x020, PIN_INPUT, 0) /* (D36) MCU_RGMII1_RD3 */ + J784S4_WKUP_IOPAD(0x01c, PIN_INPUT, 0) /* (B37) MCU_RGMII1_RXC */ + J784S4_WKUP_IOPAD(0x004, PIN_INPUT, 0) /* (C37) MCU_RGMII1_RX_CTL */ + J784S4_WKUP_IOPAD(0x014, PIN_OUTPUT, 0) /* (D37) MCU_RGMII1_TD0 */ + J784S4_WKUP_IOPAD(0x010, PIN_OUTPUT, 0) /* (D38) MCU_RGMII1_TD1 */ + J784S4_WKUP_IOPAD(0x00c, PIN_OUTPUT, 0) /* (E37) MCU_RGMII1_TD2 */ + J784S4_WKUP_IOPAD(0x008, PIN_OUTPUT, 0) /* (E38) MCU_RGMII1_TD3 */ + J784S4_WKUP_IOPAD(0x018, PIN_OUTPUT, 0) /* (E36) MCU_RGMII1_TXC */ + J784S4_WKUP_IOPAD(0x000, PIN_OUTPUT, 0) /* (C38) MCU_RGMII1_TX_CTL */ >; }; mcu_mdio_pins_default: mcu-mdio-pins-default { pinctrl-single,pins = < - J784S4_WKUP_IOPAD(0x09c, PIN_OUTPUT, 0) /* (A36) MCU_MDIO0_MDC */ - J784S4_WKUP_IOPAD(0x098, PIN_INPUT, 0) /* (B35) MCU_MDIO0_MDIO */ + J784S4_WKUP_IOPAD(0x034, PIN_OUTPUT, 0) /* (A36) MCU_MDIO0_MDC */ + J784S4_WKUP_IOPAD(0x030, PIN_INPUT, 0) /* (B35) MCU_MDIO0_MDIO */ >; }; diff --git a/arch/arm64/boot/dts/ti/k3-j784s4-mcu-wakeup.dtsi b/arch/arm64/boot/dts/ti/k3-j784s4-mcu-wakeup.dtsi index 4dda88e777ab..657fb1d72512 100644 --- a/arch/arm64/boot/dts/ti/k3-j784s4-mcu-wakeup.dtsi +++ b/arch/arm64/boot/dts/ti/k3-j784s4-mcu-wakeup.dtsi @@ -65,7 +65,34 @@ wkup_pmx0: pinctrl@4301c000 { compatible = "pinctrl-single"; /* Proxy 0 addressing */ - reg = <0x00 0x4301c000 0x00 0x178>; + reg = <0x00 0x4301c000 0x00 0x034>; + #pinctrl-cells = <1>; + pinctrl-single,register-width = <32>; + pinctrl-single,function-mask = <0xffffffff>; + }; + + wkup_pmx1: pinctrl@4301c038 { + compatible = "pinctrl-single"; + /* Proxy 0 addressing */ + reg = <0x00 0x4301c038 0x00 0x02c>; + #pinctrl-cells = <1>; + pinctrl-single,register-width = <32>; + pinctrl-single,function-mask = <0xffffffff>; + }; + + wkup_pmx2: pinctrl@4301c068 { + compatible = "pinctrl-single"; + /* Proxy 0 addressing */ + reg = <0x00 0x4301c068 0x00 0x120>; + #pinctrl-cells = <1>; + pinctrl-single,register-width = <32>; + pinctrl-single,function-mask = <0xffffffff>; + }; + + wkup_pmx3: pinctrl@4301c190 { + compatible = "pinctrl-single"; + /* Proxy 0 addressing */ + reg = <0x00 0x4301c190 0x00 0x004>; #pinctrl-cells = <1>; pinctrl-single,register-width = <32>; pinctrl-single,function-mask = <0xffffffff>; -- cgit From 6fa5d37a2f34476613012789d4618c3dc6c68b35 Mon Sep 17 00:00:00 2001 From: Nishanth Menon Date: Fri, 2 Jun 2023 16:49:31 -0500 Subject: arm64: dts: ti: k3-j784s4-evm: Add mcu and wakeup uarts Add wakeup and MCU uart. This allows the device tree usage in bootloader and firmwares that can configure the same appropriately. Signed-off-by: Nishanth Menon Reviewed-by: Udit Kumar Link: https://lore.kernel.org/r/20230602214937.2349545-3-nm@ti.com Signed-off-by: Vignesh Raghavendra --- arch/arm64/boot/dts/ti/k3-j784s4-evm.dts | 33 ++++++++++++++++++++++++++++++++ 1 file changed, 33 insertions(+) diff --git a/arch/arm64/boot/dts/ti/k3-j784s4-evm.dts b/arch/arm64/boot/dts/ti/k3-j784s4-evm.dts index e51471f8e1fd..de7c44af3bec 100644 --- a/arch/arm64/boot/dts/ti/k3-j784s4-evm.dts +++ b/arch/arm64/boot/dts/ti/k3-j784s4-evm.dts @@ -20,6 +20,8 @@ }; aliases { + serial0 = &wkup_uart0; + serial1 = &mcu_uart0; serial2 = &main_uart8; mmc0 = &main_sdhci0; mmc1 = &main_sdhci1; @@ -286,6 +288,24 @@ }; &wkup_pmx2 { + wkup_uart0_pins_default: wkup-uart0-pins-default { + pinctrl-single,pins = < + J721S2_WKUP_IOPAD(0x070, PIN_INPUT, 0) /* (L37) WKUP_GPIO0_6.WKUP_UART0_CTSn */ + J721S2_WKUP_IOPAD(0x074, PIN_INPUT, 0) /* (L36) WKUP_GPIO0_7.WKUP_UART0_RTSn */ + J721S2_WKUP_IOPAD(0x048, PIN_INPUT, 0) /* (K35) WKUP_UART0_RXD */ + J721S2_WKUP_IOPAD(0x04c, PIN_INPUT, 0) /* (K34) WKUP_UART0_TXD */ + >; + }; + + mcu_uart0_pins_default: mcu-uart0-pins-default { + pinctrl-single,pins = < + J784S4_WKUP_IOPAD(0x090, PIN_INPUT, 0) /* (H37) WKUP_GPIO0_14.MCU_UART0_CTSn */ + J784S4_WKUP_IOPAD(0x094, PIN_OUTPUT, 0) /* (K37) WKUP_GPIO0_15.MCU_UART0_RTSn */ + J784S4_WKUP_IOPAD(0x08c, PIN_INPUT, 0) /* (K38) WKUP_GPIO0_13.MCU_UART0_RXD */ + J784S4_WKUP_IOPAD(0x088, PIN_OUTPUT, 0) /* (J37) WKUP_GPIO0_12.MCU_UART0_TXD */ + >; + }; + mcu_cpsw_pins_default: mcu-cpsw-pins-default { pinctrl-single,pins = < J784S4_WKUP_IOPAD(0x02c, PIN_INPUT, 0) /* (A35) MCU_RGMII1_RD0 */ @@ -370,6 +390,19 @@ }; }; +&wkup_uart0 { + /* Firmware usage */ + status = "reserved"; + pinctrl-names = "default"; + pinctrl-0 = <&wkup_uart0_pins_default>; +}; + +&mcu_uart0 { + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&mcu_uart0_pins_default>; +}; + &main_uart8 { status = "okay"; pinctrl-names = "default"; -- cgit From 5dfbd1debc8ce5123310265cd44b5d99d272b1fe Mon Sep 17 00:00:00 2001 From: Nishanth Menon Date: Fri, 2 Jun 2023 16:49:32 -0500 Subject: arm64: dts: ti: k3-j784s4-evm: Enable wakeup_i2c0 and eeprom Enable wakeup_i2c and use un-used pinmux. While at it, describe the board detection eeprom present on the board. Signed-off-by: Nishanth Menon Reviewed-by: Udit Kumar Link: https://lore.kernel.org/r/20230602214937.2349545-4-nm@ti.com Signed-off-by: Vignesh Raghavendra --- arch/arm64/boot/dts/ti/k3-j784s4-evm.dts | 21 +++++++++++++++++++++ 1 file changed, 21 insertions(+) diff --git a/arch/arm64/boot/dts/ti/k3-j784s4-evm.dts b/arch/arm64/boot/dts/ti/k3-j784s4-evm.dts index de7c44af3bec..09f052c94844 100644 --- a/arch/arm64/boot/dts/ti/k3-j784s4-evm.dts +++ b/arch/arm64/boot/dts/ti/k3-j784s4-evm.dts @@ -25,6 +25,7 @@ serial2 = &main_uart8; mmc0 = &main_sdhci0; mmc1 = &main_sdhci1; + i2c0 = &wkup_i2c0; i2c3 = &main_i2c0; }; @@ -297,6 +298,13 @@ >; }; + wkup_i2c0_pins_default: wkup-i2c0-pins-default { + pinctrl-single,pins = < + J721S2_WKUP_IOPAD(0x98, PIN_INPUT, 0) /* (N33) WKUP_I2C0_SCL */ + J721S2_WKUP_IOPAD(0x9c, PIN_INPUT, 0) /* (N35) WKUP_I2C0_SDA */ + >; + }; + mcu_uart0_pins_default: mcu-uart0-pins-default { pinctrl-single,pins = < J784S4_WKUP_IOPAD(0x090, PIN_INPUT, 0) /* (H37) WKUP_GPIO0_14.MCU_UART0_CTSn */ @@ -397,6 +405,19 @@ pinctrl-0 = <&wkup_uart0_pins_default>; }; +&wkup_i2c0 { + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&wkup_i2c0_pins_default>; + clock-frequency = <400000>; + + eeprom@50 { + /* CAV24C256WE-GT3 */ + compatible = "atmel,24c256"; + reg = <0x50>; + }; +}; + &mcu_uart0 { status = "okay"; pinctrl-names = "default"; -- cgit From b38c6ced4ec5b3f6260ff6cc2b71e8a3d8c897d7 Mon Sep 17 00:00:00 2001 From: Nishanth Menon Date: Fri, 2 Jun 2023 16:49:33 -0500 Subject: arm64: dts: ti: k3-am69-sk: Fix main_i2c0 alias main_i2c0 is aliased as i2c0 which creates a problem for u-boot R5 SPL attempting to reuse the same definition in the common board detection logic as it looks for the first i2c instance as the bus on which to detect the eeprom to understand the board variant involved. Switch main_i2c0 to i2c3 alias allowing us to introduce wkup_i2c0 and potentially space for mcu_i2c instances in the gap for follow on patches. Fixes: 635fb18ba008 ("arch: arm64: dts: Add support for AM69 Starter Kit") Signed-off-by: Nishanth Menon Reviewed-by: Udit Kumar Link: https://lore.kernel.org/r/20230602214937.2349545-5-nm@ti.com Signed-off-by: Vignesh Raghavendra --- arch/arm64/boot/dts/ti/k3-am69-sk.dts | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm64/boot/dts/ti/k3-am69-sk.dts b/arch/arm64/boot/dts/ti/k3-am69-sk.dts index 3099c0098ca6..d51e1123e6b1 100644 --- a/arch/arm64/boot/dts/ti/k3-am69-sk.dts +++ b/arch/arm64/boot/dts/ti/k3-am69-sk.dts @@ -24,7 +24,7 @@ serial2 = &main_uart8; mmc0 = &main_sdhci0; mmc1 = &main_sdhci1; - i2c0 = &main_i2c0; + i2c3 = &main_i2c0; }; memory@80000000 { -- cgit From 7b72bd25508de6a5eee2cb1679b9d4b8bc25de5a Mon Sep 17 00:00:00 2001 From: Nishanth Menon Date: Fri, 2 Jun 2023 16:49:34 -0500 Subject: arm64: dts: ti: k3-am69-sk: Enable mcu network port Enable networking for NFS and basic networking functionality. Signed-off-by: Nishanth Menon Reviewed-by: Udit Kumar Link: https://lore.kernel.org/r/20230602214937.2349545-6-nm@ti.com Signed-off-by: Vignesh Raghavendra --- arch/arm64/boot/dts/ti/k3-am69-sk.dts | 48 +++++++++++++++++++++++++++++++++++ 1 file changed, 48 insertions(+) diff --git a/arch/arm64/boot/dts/ti/k3-am69-sk.dts b/arch/arm64/boot/dts/ti/k3-am69-sk.dts index d51e1123e6b1..21949106a107 100644 --- a/arch/arm64/boot/dts/ti/k3-am69-sk.dts +++ b/arch/arm64/boot/dts/ti/k3-am69-sk.dts @@ -25,6 +25,7 @@ mmc0 = &main_sdhci0; mmc1 = &main_sdhci1; i2c3 = &main_i2c0; + ethernet0 = &mcu_cpsw_port1; }; memory@80000000 { @@ -140,6 +141,32 @@ }; }; +&wkup_pmx2 { + mcu_cpsw_pins_default: mcu-cpsw-pins-default { + pinctrl-single,pins = < + J784S4_WKUP_IOPAD(0x02c, PIN_INPUT, 0) /* (A35) MCU_RGMII1_RD0 */ + J784S4_WKUP_IOPAD(0x028, PIN_INPUT, 0) /* (B36) MCU_RGMII1_RD1 */ + J784S4_WKUP_IOPAD(0x024, PIN_INPUT, 0) /* (C36) MCU_RGMII1_RD2 */ + J784S4_WKUP_IOPAD(0x020, PIN_INPUT, 0) /* (D36) MCU_RGMII1_RD3 */ + J784S4_WKUP_IOPAD(0x01c, PIN_INPUT, 0) /* (B37) MCU_RGMII1_RXC */ + J784S4_WKUP_IOPAD(0x004, PIN_INPUT, 0) /* (C37) MCU_RGMII1_RX_CTL */ + J784S4_WKUP_IOPAD(0x014, PIN_OUTPUT, 0) /* (D37) MCU_RGMII1_TD0 */ + J784S4_WKUP_IOPAD(0x010, PIN_OUTPUT, 0) /* (D38) MCU_RGMII1_TD1 */ + J784S4_WKUP_IOPAD(0x00c, PIN_OUTPUT, 0) /* (E37) MCU_RGMII1_TD2 */ + J784S4_WKUP_IOPAD(0x008, PIN_OUTPUT, 0) /* (E38) MCU_RGMII1_TD3 */ + J784S4_WKUP_IOPAD(0x018, PIN_OUTPUT, 0) /* (E36) MCU_RGMII1_TXC */ + J784S4_WKUP_IOPAD(0x000, PIN_OUTPUT, 0) /* (C38) MCU_RGMII1_TX_CTL */ + >; + }; + + mcu_mdio_pins_default: mcu-mdio-pins-default { + pinctrl-single,pins = < + J784S4_WKUP_IOPAD(0x034, PIN_OUTPUT, 0) /* (A36) MCU_MDIO0_MDC */ + J784S4_WKUP_IOPAD(0x030, PIN_INPUT, 0) /* (B35) MCU_MDIO0_MDIO */ + >; + }; +}; + &main_uart8 { status = "okay"; pinctrl-names = "default"; @@ -187,3 +214,24 @@ &main_gpio0 { status = "okay"; }; + +&mcu_cpsw { + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&mcu_cpsw_pins_default>, <&mcu_mdio_pins_default>; +}; + +&davinci_mdio { + mcu_phy0: ethernet-phy@0 { + reg = <0>; + ti,rx-internal-delay = ; + ti,fifo-depth = ; + ti,min-output-impedance; + }; +}; + +&mcu_cpsw_port1 { + status = "okay"; + phy-mode = "rgmii-rxid"; + phy-handle = <&mcu_phy0>; +}; -- cgit From 45299dd1991b496ddab5ab4a86d7ae601e0e4c7f Mon Sep 17 00:00:00 2001 From: Nishanth Menon Date: Fri, 2 Jun 2023 16:49:35 -0500 Subject: arm64: dts: ti: k3-am69-sk: Add mcu and wakeup uarts Add wakeup and MCU uart. This allows the device tree usage in bootloader and firmwares that can configure the same appropriately. Signed-off-by: Nishanth Menon Reviewed-by: Udit Kumar Link: https://lore.kernel.org/r/20230602214937.2349545-7-nm@ti.com Signed-off-by: Vignesh Raghavendra --- arch/arm64/boot/dts/ti/k3-am69-sk.dts | 31 +++++++++++++++++++++++++++++++ 1 file changed, 31 insertions(+) diff --git a/arch/arm64/boot/dts/ti/k3-am69-sk.dts b/arch/arm64/boot/dts/ti/k3-am69-sk.dts index 21949106a107..125e4af174f6 100644 --- a/arch/arm64/boot/dts/ti/k3-am69-sk.dts +++ b/arch/arm64/boot/dts/ti/k3-am69-sk.dts @@ -21,6 +21,8 @@ }; aliases { + serial0 = &wkup_uart0; + serial1 = &mcu_uart0; serial2 = &main_uart8; mmc0 = &main_sdhci0; mmc1 = &main_sdhci1; @@ -142,6 +144,22 @@ }; &wkup_pmx2 { + wkup_uart0_pins_default: wkup-uart0-pins-default { + pinctrl-single,pins = < + J721S2_WKUP_IOPAD(0x070, PIN_INPUT, 0) /* (L37) WKUP_GPIO0_6.WKUP_UART0_CTSn */ + J721S2_WKUP_IOPAD(0x074, PIN_INPUT, 0) /* (L36) WKUP_GPIO0_7.WKUP_UART0_RTSn */ + J721S2_WKUP_IOPAD(0x048, PIN_INPUT, 0) /* (K35) WKUP_UART0_RXD */ + J721S2_WKUP_IOPAD(0x04c, PIN_INPUT, 0) /* (K34) WKUP_UART0_TXD */ + >; + }; + + mcu_uart0_pins_default: mcu-uart0-pins-default { + pinctrl-single,pins = < + J784S4_WKUP_IOPAD(0x08c, PIN_INPUT, 0) /* (K38) WKUP_GPIO0_13.MCU_UART0_RXD */ + J784S4_WKUP_IOPAD(0x088, PIN_OUTPUT, 0) /* (J37) WKUP_GPIO0_12.MCU_UART0_TXD */ + >; + }; + mcu_cpsw_pins_default: mcu-cpsw-pins-default { pinctrl-single,pins = < J784S4_WKUP_IOPAD(0x02c, PIN_INPUT, 0) /* (A35) MCU_RGMII1_RD0 */ @@ -167,6 +185,19 @@ }; }; +&wkup_uart0 { + /* Firmware usage */ + status = "reserved"; + pinctrl-names = "default"; + pinctrl-0 = <&wkup_uart0_pins_default>; +}; + +&mcu_uart0 { + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&mcu_uart0_pins_default>; +}; + &main_uart8 { status = "okay"; pinctrl-names = "default"; -- cgit From 08ae12b637507cd22fbcdb82521b8b8a5ae96222 Mon Sep 17 00:00:00 2001 From: Nishanth Menon Date: Fri, 2 Jun 2023 16:49:36 -0500 Subject: arm64: dts: ti: k3-am69-sk: Enable wakeup_i2c0 and eeprom Enable wakeup_i2c and use un-used pinmux. While at it, describe the board detection eeprom present on the board. Signed-off-by: Nishanth Menon Reviewed-by: Udit Kumar Link: https://lore.kernel.org/r/20230602214937.2349545-8-nm@ti.com Signed-off-by: Vignesh Raghavendra --- arch/arm64/boot/dts/ti/k3-am69-sk.dts | 21 +++++++++++++++++++++ 1 file changed, 21 insertions(+) diff --git a/arch/arm64/boot/dts/ti/k3-am69-sk.dts b/arch/arm64/boot/dts/ti/k3-am69-sk.dts index 125e4af174f6..08ec94289beb 100644 --- a/arch/arm64/boot/dts/ti/k3-am69-sk.dts +++ b/arch/arm64/boot/dts/ti/k3-am69-sk.dts @@ -26,6 +26,7 @@ serial2 = &main_uart8; mmc0 = &main_sdhci0; mmc1 = &main_sdhci1; + i2c0 = &wkup_i2c0; i2c3 = &main_i2c0; ethernet0 = &mcu_cpsw_port1; }; @@ -153,6 +154,13 @@ >; }; + wkup_i2c0_pins_default: wkup-i2c0-pins-default { + pinctrl-single,pins = < + J721S2_WKUP_IOPAD(0x98, PIN_INPUT, 0) /* (N33) WKUP_I2C0_SCL */ + J721S2_WKUP_IOPAD(0x9c, PIN_INPUT, 0) /* (N35) WKUP_I2C0_SDA */ + >; + }; + mcu_uart0_pins_default: mcu-uart0-pins-default { pinctrl-single,pins = < J784S4_WKUP_IOPAD(0x08c, PIN_INPUT, 0) /* (K38) WKUP_GPIO0_13.MCU_UART0_RXD */ @@ -192,6 +200,19 @@ pinctrl-0 = <&wkup_uart0_pins_default>; }; +&wkup_i2c0 { + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&wkup_i2c0_pins_default>; + clock-frequency = <400000>; + + eeprom@51 { + /* AT24C512C-MAHM-T */ + compatible = "atmel,24c512"; + reg = <0x51>; + }; +}; + &mcu_uart0 { status = "okay"; pinctrl-names = "default"; -- cgit From 0ec1a48d99ddd11c265f7f1b2573fb2c8e0db0ab Mon Sep 17 00:00:00 2001 From: Dasnavis Sabiya Date: Fri, 2 Jun 2023 16:49:37 -0500 Subject: arm64: dts: ti: k3-am69-sk: Add pinmux for RPi Header Add pinmux required to bring out the i2c and gpios on 40 pin RPi expansion header on AM69 SK board. Signed-off-by: Dasnavis Sabiya Signed-off-by: Nishanth Menon Reviewed-by: Udit Kumar Link: https://lore.kernel.org/r/20230602214937.2349545-9-nm@ti.com Signed-off-by: Vignesh Raghavendra --- arch/arm64/boot/dts/ti/k3-am69-sk.dts | 63 +++++++++++++++++++++++++++++++++++ 1 file changed, 63 insertions(+) diff --git a/arch/arm64/boot/dts/ti/k3-am69-sk.dts b/arch/arm64/boot/dts/ti/k3-am69-sk.dts index 08ec94289beb..6e12a45a2287 100644 --- a/arch/arm64/boot/dts/ti/k3-am69-sk.dts +++ b/arch/arm64/boot/dts/ti/k3-am69-sk.dts @@ -142,6 +142,25 @@ J784S4_IOPAD(0x0C4, PIN_INPUT, 7) /* (AD36) ECAP0_IN_APWM_OUT.GPIO0_49 */ >; }; + + rpi_header_gpio0_pins_default: rpi-header-gpio0-pins-default { + pinctrl-single,pins = < + J784S4_IOPAD(0x0BC, PIN_INPUT, 7) /* (AD33) MCASP1_AFSX.GPIO0_47 */ + J784S4_IOPAD(0x06C, PIN_INPUT, 7) /* (AJ37) MCASP4_AFSX.GPIO0_27 */ + J784S4_IOPAD(0x0B4, PIN_INPUT, 7) /* (AL34) MCASP1_AXR4.GPIO0_45 */ + J784S4_IOPAD(0x0C0, PIN_INPUT, 7) /* (AD38) MCASP1_AXR0.GPIO0_48 */ + J784S4_IOPAD(0x00C, PIN_INPUT, 7) /* (AF33) MCAN13_TX.GPIO0_3 */ + J784S4_IOPAD(0x0B8, PIN_INPUT, 7) /* (AC34) MCASP1_ACLKX.GPIO0_46 */ + J784S4_IOPAD(0x090, PIN_INPUT, 7) /* (AC35) MCASP0_AXR8.GPIO0_36 */ + J784S4_IOPAD(0x0A8, PIN_INPUT, 7) /* (AF34) MCASP0_AXR14.GPIO0_42 */ + J784S4_IOPAD(0x0A4, PIN_INPUT, 7) /* (AJ36) MCASP0_AXR13.GPIO0_41 */ + J784S4_IOPAD(0x034, PIN_INPUT, 7) /* (AJ34) PMIC_WAKE0n.GPIO0_13 */ + J784S4_IOPAD(0x0CC, PIN_INPUT, 7) /* (AM37) SPI0_CS0.GPIO0_51 */ + J784S4_IOPAD(0x08C, PIN_INPUT, 7) /* (AE35) MCASP0_AXR7.GPIO0_35 */ + J784S4_IOPAD(0x008, PIN_INPUT, 7) /* (AJ33) MCAN12_RX.GPIO0_2 */ + J784S4_IOPAD(0x004, PIN_INPUT, 7) /* (AG36) MCAN12_TX.GPIO0_1 */ + >; + }; }; &wkup_pmx2 { @@ -168,6 +187,13 @@ >; }; + mcu_i2c0_pins_default: mcu-i2c0-pins-default { + pinctrl-single,pins = < + J784S4_WKUP_IOPAD(0x0a0, PIN_INPUT_PULLUP, 0) /* (M35) MCU_I2C0_SCL */ + J784S4_WKUP_IOPAD(0x0a4, PIN_INPUT_PULLUP, 0) /* (G34) MCU_I2C0_SDA */ + >; + }; + mcu_cpsw_pins_default: mcu-cpsw-pins-default { pinctrl-single,pins = < J784S4_WKUP_IOPAD(0x02c, PIN_INPUT, 0) /* (A35) MCU_RGMII1_RD0 */ @@ -191,6 +217,28 @@ J784S4_WKUP_IOPAD(0x030, PIN_INPUT, 0) /* (B35) MCU_MDIO0_MDIO */ >; }; + + mcu_rpi_hdr1_gpio0_pins_default: mcu-rpi-hdr1-gpio0-pins-default { + pinctrl-single,pins = < + J784S4_WKUP_IOPAD(0x118, PIN_INPUT, 7) /* (N34) WKUP_GPIO0_66 */ + J784S4_WKUP_IOPAD(0x05c, PIN_INPUT, 7) /* (J34) WKUP_GPIO0_1 */ + J784S4_WKUP_IOPAD(0x060, PIN_INPUT, 7) /* (J35) WKUP_GPIO0_2 */ + J784S4_WKUP_IOPAD(0x058, PIN_INPUT, 7) /* (H38) WKUP_GPIO0_0 */ + J784S4_WKUP_IOPAD(0x0b8, PIN_INPUT, 7) /* (M37) WKUP_GPIO0_56 */ + J784S4_WKUP_IOPAD(0x114, PIN_INPUT, 7) /* (M36) WKUP_GPIO0_57 */ + J784S4_WKUP_IOPAD(0x094, PIN_INPUT, 7) /* (K37) WKUP_GPIO0_15 */ + J784S4_WKUP_IOPAD(0x064, PIN_INPUT, 7) /* (J36) WKUP_GPIO0_3 */ + J784S4_WKUP_IOPAD(0x11c, PIN_INPUT, 7) /* (M34) WKUP_GPIO0_67 */ + >; + }; +}; + +&wkup_pmx3 { + mcu_rpi_hdr2_gpio0_pins_default: mcu-rpi-hdr2-gpio0-pins-default { + pinctrl-single,pins = < + J784S4_WKUP_IOPAD(0x0, PIN_INPUT, 7) /* (M33) WKUP_GPIO0_49 */ + >; + }; }; &wkup_uart0 { @@ -213,12 +261,25 @@ }; }; +&wkup_gpio0 { + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&mcu_rpi_hdr1_gpio0_pins_default>, <&mcu_rpi_hdr2_gpio0_pins_default>; +}; + &mcu_uart0 { status = "okay"; pinctrl-names = "default"; pinctrl-0 = <&mcu_uart0_pins_default>; }; +&mcu_i2c0 { + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&mcu_i2c0_pins_default>; + clock-frequency = <400000>; +}; + &main_uart8 { status = "okay"; pinctrl-names = "default"; @@ -265,6 +326,8 @@ &main_gpio0 { status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&rpi_header_gpio0_pins_default>; }; &mcu_cpsw { -- cgit From 27f98f3eca7334fec668ec637ed5e0514458bba8 Mon Sep 17 00:00:00 2001 From: Andrew Davis Date: Thu, 1 Jun 2023 13:49:32 -0500 Subject: arm64: dts: ti: k3-am64: Only set UART baud for used ports As the binding for "current-speed" states, this should only be used when the baud rate of an attached device cannot be detected. This is the case for our attached on-board USB-to-UART converter used for early kernel console. For all other unconnected/disabled ports this can be configured in userspace later, DT is not the place for device configuration, especially when there are already standard ways to set serial baud in userspace. Remove setting baud for all disabled serial ports and move setting it for the couple enabled ports down into the board files. Signed-off-by: Andrew Davis Link: https://lore.kernel.org/r/20230601184933.358731-1-afd@ti.com Signed-off-by: Vignesh Raghavendra --- arch/arm64/boot/dts/ti/k3-am64-main.dtsi | 7 ------- arch/arm64/boot/dts/ti/k3-am64-mcu.dtsi | 2 -- arch/arm64/boot/dts/ti/k3-am642-evm.dts | 1 + arch/arm64/boot/dts/ti/k3-am642-phyboard-electra-rdk.dts | 2 ++ arch/arm64/boot/dts/ti/k3-am642-sk.dts | 1 + 5 files changed, 4 insertions(+), 9 deletions(-) diff --git a/arch/arm64/boot/dts/ti/k3-am64-main.dtsi b/arch/arm64/boot/dts/ti/k3-am64-main.dtsi index 3c387d479b36..71081970edd8 100644 --- a/arch/arm64/boot/dts/ti/k3-am64-main.dtsi +++ b/arch/arm64/boot/dts/ti/k3-am64-main.dtsi @@ -377,7 +377,6 @@ reg = <0x00 0x02800000 0x00 0x100>; interrupts = ; clock-frequency = <48000000>; - current-speed = <115200>; power-domains = <&k3_pds 146 TI_SCI_PD_EXCLUSIVE>; clocks = <&k3_clks 146 0>; clock-names = "fclk"; @@ -389,7 +388,6 @@ reg = <0x00 0x02810000 0x00 0x100>; interrupts = ; clock-frequency = <48000000>; - current-speed = <115200>; power-domains = <&k3_pds 152 TI_SCI_PD_EXCLUSIVE>; clocks = <&k3_clks 152 0>; clock-names = "fclk"; @@ -401,7 +399,6 @@ reg = <0x00 0x02820000 0x00 0x100>; interrupts = ; clock-frequency = <48000000>; - current-speed = <115200>; power-domains = <&k3_pds 153 TI_SCI_PD_EXCLUSIVE>; clocks = <&k3_clks 153 0>; clock-names = "fclk"; @@ -413,7 +410,6 @@ reg = <0x00 0x02830000 0x00 0x100>; interrupts = ; clock-frequency = <48000000>; - current-speed = <115200>; power-domains = <&k3_pds 154 TI_SCI_PD_EXCLUSIVE>; clocks = <&k3_clks 154 0>; clock-names = "fclk"; @@ -425,7 +421,6 @@ reg = <0x00 0x02840000 0x00 0x100>; interrupts = ; clock-frequency = <48000000>; - current-speed = <115200>; power-domains = <&k3_pds 155 TI_SCI_PD_EXCLUSIVE>; clocks = <&k3_clks 155 0>; clock-names = "fclk"; @@ -437,7 +432,6 @@ reg = <0x00 0x02850000 0x00 0x100>; interrupts = ; clock-frequency = <48000000>; - current-speed = <115200>; power-domains = <&k3_pds 156 TI_SCI_PD_EXCLUSIVE>; clocks = <&k3_clks 156 0>; clock-names = "fclk"; @@ -449,7 +443,6 @@ reg = <0x00 0x02860000 0x00 0x100>; interrupts = ; clock-frequency = <48000000>; - current-speed = <115200>; power-domains = <&k3_pds 158 TI_SCI_PD_EXCLUSIVE>; clocks = <&k3_clks 158 0>; clock-names = "fclk"; diff --git a/arch/arm64/boot/dts/ti/k3-am64-mcu.dtsi b/arch/arm64/boot/dts/ti/k3-am64-mcu.dtsi index 31336b0e290e..67ad414a5eab 100644 --- a/arch/arm64/boot/dts/ti/k3-am64-mcu.dtsi +++ b/arch/arm64/boot/dts/ti/k3-am64-mcu.dtsi @@ -55,7 +55,6 @@ compatible = "ti,am64-uart", "ti,am654-uart"; reg = <0x00 0x04a00000 0x00 0x100>; interrupts = ; - current-speed = <115200>; power-domains = <&k3_pds 149 TI_SCI_PD_EXCLUSIVE>; clocks = <&k3_clks 149 0>; clock-names = "fclk"; @@ -66,7 +65,6 @@ compatible = "ti,am64-uart", "ti,am654-uart"; reg = <0x00 0x04a10000 0x00 0x100>; interrupts = ; - current-speed = <115200>; power-domains = <&k3_pds 160 TI_SCI_PD_EXCLUSIVE>; clocks = <&k3_clks 160 0>; clock-names = "fclk"; diff --git a/arch/arm64/boot/dts/ti/k3-am642-evm.dts b/arch/arm64/boot/dts/ti/k3-am642-evm.dts index c3fd417f3842..4fd5c398a165 100644 --- a/arch/arm64/boot/dts/ti/k3-am642-evm.dts +++ b/arch/arm64/boot/dts/ti/k3-am642-evm.dts @@ -375,6 +375,7 @@ status = "okay"; pinctrl-names = "default"; pinctrl-0 = <&main_uart0_pins_default>; + current-speed = <115200>; }; /* main_uart1 is reserved for firmware usage */ diff --git a/arch/arm64/boot/dts/ti/k3-am642-phyboard-electra-rdk.dts b/arch/arm64/boot/dts/ti/k3-am642-phyboard-electra-rdk.dts index 8d9ca6e5b087..59c091bc30ab 100644 --- a/arch/arm64/boot/dts/ti/k3-am642-phyboard-electra-rdk.dts +++ b/arch/arm64/boot/dts/ti/k3-am642-phyboard-electra-rdk.dts @@ -251,6 +251,7 @@ status = "okay"; pinctrl-names = "default"; pinctrl-0 = <&main_uart0_pins_default>; + current-speed = <115200>; }; &main_uart1 { @@ -258,6 +259,7 @@ pinctrl-names = "default"; pinctrl-0 = <&main_uart1_pins_default>; uart-has-rtscts; + current-speed = <115200>; }; &sdhci1 { diff --git a/arch/arm64/boot/dts/ti/k3-am642-sk.dts b/arch/arm64/boot/dts/ti/k3-am642-sk.dts index 3e27bd65cb2e..44e18c89beda 100644 --- a/arch/arm64/boot/dts/ti/k3-am642-sk.dts +++ b/arch/arm64/boot/dts/ti/k3-am642-sk.dts @@ -369,6 +369,7 @@ status = "okay"; pinctrl-names = "default"; pinctrl-0 = <&main_uart0_pins_default>; + current-speed = <115200>; }; &main_uart1 { -- cgit From 6b343136388fe1ef5837e45ab921705de76665ee Mon Sep 17 00:00:00 2001 From: Andrew Davis Date: Thu, 1 Jun 2023 13:49:33 -0500 Subject: arm64: dts: ti: k3-am64: Use phandle to stdout UART node Using a phandle makes it clear which UART we are choosing without needing to resolve through an alias first. Especially useful for boards like the TI J721s2-EVM where the alias is "serial2" but it actually resolves to the 8th UART instance(main_uart8). Signed-off-by: Andrew Davis Link: https://lore.kernel.org/r/20230601184933.358731-2-afd@ti.com Signed-off-by: Vignesh Raghavendra --- arch/arm64/boot/dts/ti/k3-am642-evm.dts | 2 +- arch/arm64/boot/dts/ti/k3-am642-sk.dts | 2 +- 2 files changed, 2 insertions(+), 2 deletions(-) diff --git a/arch/arm64/boot/dts/ti/k3-am642-evm.dts b/arch/arm64/boot/dts/ti/k3-am642-evm.dts index 4fd5c398a165..e897feacd122 100644 --- a/arch/arm64/boot/dts/ti/k3-am642-evm.dts +++ b/arch/arm64/boot/dts/ti/k3-am642-evm.dts @@ -17,7 +17,7 @@ model = "Texas Instruments AM642 EVM"; chosen { - stdout-path = "serial2:115200n8"; + stdout-path = &main_uart0; }; aliases { diff --git a/arch/arm64/boot/dts/ti/k3-am642-sk.dts b/arch/arm64/boot/dts/ti/k3-am642-sk.dts index 44e18c89beda..78ae490a0c76 100644 --- a/arch/arm64/boot/dts/ti/k3-am642-sk.dts +++ b/arch/arm64/boot/dts/ti/k3-am642-sk.dts @@ -17,7 +17,7 @@ model = "Texas Instruments AM642 SK"; chosen { - stdout-path = "serial2:115200n8"; + stdout-path = &main_uart0; }; aliases { -- cgit From acfb362a9c78d6708080cdd850b036225c78371b Mon Sep 17 00:00:00 2001 From: Nishanth Menon Date: Thu, 1 Jun 2023 13:31:43 -0500 Subject: arm64: dts: ti: k3-j721e-sk: Add missing uart pinmuxes Rather than depend on the default pinmuxes, explicitly describe the pinmux Signed-off-by: Nishanth Menon Link: https://lore.kernel.org/r/20230601183151.1000157-2-nm@ti.com Signed-off-by: Vignesh Raghavendra --- arch/arm64/boot/dts/ti/k3-j721e-sk.dts | 31 +++++++++++++++++++++++++++++-- 1 file changed, 29 insertions(+), 2 deletions(-) diff --git a/arch/arm64/boot/dts/ti/k3-j721e-sk.dts b/arch/arm64/boot/dts/ti/k3-j721e-sk.dts index c8db9d7ea200..1969c62262a2 100644 --- a/arch/arm64/boot/dts/ti/k3-j721e-sk.dts +++ b/arch/arm64/boot/dts/ti/k3-j721e-sk.dts @@ -302,6 +302,13 @@ >; }; + main_uart1_pins_default: main-uart1-pins-default { + pinctrl-single,pins = < + J721E_IOPAD(0x1f8, PIN_INPUT, 0) /* (AA4) UART1_RXD */ + J721E_IOPAD(0x1fc, PIN_OUTPUT, 0) /* (AB4) UART1_TXD */ + >; + }; + main_i2c0_pins_default: main-i2c0-pins-default { pinctrl-single,pins = < J721E_IOPAD(0x220, PIN_INPUT_PULLUP, 0) /* (AC5) I2C0_SCL */ @@ -495,6 +502,22 @@ >; }; + wkup_uart0_pins_default: wkup-uart0-pins-default { + pinctrl-single,pins = < + J721E_WKUP_IOPAD(0xa0, PIN_INPUT, 0) /* (J29) WKUP_UART0_RXD */ + J721E_WKUP_IOPAD(0xa4, PIN_OUTPUT, 0) /* (J28) WKUP_UART0_TXD */ + >; + }; + + mcu_uart0_pins_default: mcu-uart0-pins-default { + pinctrl-single,pins = < + J721E_WKUP_IOPAD(0xf0, PIN_INPUT, 2) /* (D26) MCU_I3C0_SCL.MCU_UART0_CTSn */ + J721E_WKUP_IOPAD(0xf4, PIN_OUTPUT, 2)/* (D25) MCU_I3C0_SDA.MCU_UART0_RTSn */ + J721E_WKUP_IOPAD(0xe4, PIN_INPUT, 0) /* (H28) WKUP_GPIO0_13.MCU_UART0_RXD */ + J721E_WKUP_IOPAD(0xe0, PIN_OUTPUT, 0)/* (G29) WKUP_GPIO0_12.MCU_UART0_TXD */ + >; + }; + wkup_i2c0_pins_default: wkup-i2c0-pins-default { pinctrl-single,pins = < J721E_WKUP_IOPAD(0xf8, PIN_INPUT_PULLUP, 0) /* (J25) WKUP_I2C0_SCL */ @@ -513,11 +536,14 @@ &wkup_uart0 { /* Wakeup UART is used by System firmware */ status = "reserved"; + pinctrl-names = "default"; + pinctrl-0 = <&wkup_uart0_pins_default>; }; &mcu_uart0 { status = "okay"; - /* Default pinmux */ + pinctrl-names = "default"; + pinctrl-0 = <&mcu_uart0_pins_default>; }; &main_uart0 { @@ -530,7 +556,8 @@ &main_uart1 { status = "okay"; - /* Default pinmux */ + pinctrl-names = "default"; + pinctrl-0 = <&main_uart1_pins_default>; }; &main_sdhci0 { -- cgit From 1b4b376c878b36d1a1c848ebc885487e4cad2546 Mon Sep 17 00:00:00 2001 From: Nishanth Menon Date: Thu, 1 Jun 2023 13:31:44 -0500 Subject: arm64: dts: ti: k3-j721e-sk: Enable wakeup_i2c0 and eeprom Enable wakeup_i2c and use un-used pinmux. While at it, describe the board detection eeprom present on the board. Signed-off-by: Nishanth Menon Link: https://lore.kernel.org/r/20230601183151.1000157-3-nm@ti.com Signed-off-by: Vignesh Raghavendra --- arch/arm64/boot/dts/ti/k3-j721e-sk.dts | 13 +++++++++++++ 1 file changed, 13 insertions(+) diff --git a/arch/arm64/boot/dts/ti/k3-j721e-sk.dts b/arch/arm64/boot/dts/ti/k3-j721e-sk.dts index 1969c62262a2..0b15c44e0e66 100644 --- a/arch/arm64/boot/dts/ti/k3-j721e-sk.dts +++ b/arch/arm64/boot/dts/ti/k3-j721e-sk.dts @@ -540,6 +540,19 @@ pinctrl-0 = <&wkup_uart0_pins_default>; }; +&wkup_i2c0 { + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&wkup_i2c0_pins_default>; + clock-frequency = <400000>; + + eeprom@51 { + /* AT24C512C-MAHM-T */ + compatible = "atmel,24c512"; + reg = <0x51>; + }; +}; + &mcu_uart0 { status = "okay"; pinctrl-names = "default"; -- cgit From 26efc8d1ad0cc14e2740d310935fa146b1fc5a58 Mon Sep 17 00:00:00 2001 From: Nishanth Menon Date: Thu, 1 Jun 2023 13:31:45 -0500 Subject: arm64: dts: ti: j721e-som/common-proc-board: Add product links Add product links to get reference to schematics and design files Signed-off-by: Nishanth Menon Link: https://lore.kernel.org/r/20230601183151.1000157-4-nm@ti.com Signed-off-by: Vignesh Raghavendra --- arch/arm64/boot/dts/ti/k3-j721e-common-proc-board.dts | 2 ++ arch/arm64/boot/dts/ti/k3-j721e-som-p0.dtsi | 2 ++ 2 files changed, 4 insertions(+) diff --git a/arch/arm64/boot/dts/ti/k3-j721e-common-proc-board.dts b/arch/arm64/boot/dts/ti/k3-j721e-common-proc-board.dts index 2d5d75fffde9..84336376aad1 100644 --- a/arch/arm64/boot/dts/ti/k3-j721e-common-proc-board.dts +++ b/arch/arm64/boot/dts/ti/k3-j721e-common-proc-board.dts @@ -1,6 +1,8 @@ // SPDX-License-Identifier: GPL-2.0 /* * Copyright (C) 2019 Texas Instruments Incorporated - https://www.ti.com/ + * + * Product Link: https://www.ti.com/tool/J721EXCPXEVM */ /dts-v1/; diff --git a/arch/arm64/boot/dts/ti/k3-j721e-som-p0.dtsi b/arch/arm64/boot/dts/ti/k3-j721e-som-p0.dtsi index 7a4c00ca9371..1326b09a9c36 100644 --- a/arch/arm64/boot/dts/ti/k3-j721e-som-p0.dtsi +++ b/arch/arm64/boot/dts/ti/k3-j721e-som-p0.dtsi @@ -1,6 +1,8 @@ // SPDX-License-Identifier: GPL-2.0 /* * Copyright (C) 2019-2020 Texas Instruments Incorporated - https://www.ti.com/ + * + * Product Link: https://www.ti.com/tool/J721EXSOMXEVM */ /dts-v1/; -- cgit From 86718345b4d3c0d386b3f73ef43e7f72ff04cf4a Mon Sep 17 00:00:00 2001 From: Nishanth Menon Date: Thu, 1 Jun 2023 13:31:46 -0500 Subject: arm64: dts: ti: j721e-common-proc-board: Add uart pinmux Explicitly define the pinmux rather than depend on bootloader configured pinmux for the platform. Signed-off-by: Nishanth Menon Link: https://lore.kernel.org/r/20230601183151.1000157-5-nm@ti.com Signed-off-by: Vignesh Raghavendra --- .../boot/dts/ti/k3-j721e-common-proc-board.dts | 62 ++++++++++++++++++++-- 1 file changed, 58 insertions(+), 4 deletions(-) diff --git a/arch/arm64/boot/dts/ti/k3-j721e-common-proc-board.dts b/arch/arm64/boot/dts/ti/k3-j721e-common-proc-board.dts index 84336376aad1..fa9094321729 100644 --- a/arch/arm64/boot/dts/ti/k3-j721e-common-proc-board.dts +++ b/arch/arm64/boot/dts/ti/k3-j721e-common-proc-board.dts @@ -174,6 +174,36 @@ }; &main_pmx0 { + main_uart0_pins_default: main-uart0-pins-default { + pinctrl-single,pins = < + J721E_IOPAD(0x1d4, PIN_INPUT, 1) /* (Y3) SPI1_CS0.UART0_CTSn */ + J721E_IOPAD(0x1c0, PIN_OUTPUT, 1) /* (AA2) SPI0_CS0.UART0_RTSn */ + J721E_IOPAD(0x1e8, PIN_INPUT, 0) /* (AB2) UART0_RXD */ + J721E_IOPAD(0x1ec, PIN_OUTPUT, 0) /* (AB3) UART0_TXD */ + >; + }; + + main_uart1_pins_default: main-uart1-pins-default { + pinctrl-single,pins = < + J721E_IOPAD(0x1f8, PIN_INPUT, 0) /* (AA4) UART1_RXD */ + J721E_IOPAD(0x1fc, PIN_OUTPUT, 0) /* (AB4) UART1_TXD */ + >; + }; + + main_uart2_pins_default: main-uart2-pins-default { + pinctrl-single,pins = < + J721E_IOPAD(0x1dc, PIN_INPUT, 3) /* (Y1) SPI1_CLK.UART2_RXD */ + J721E_IOPAD(0x1e0, PIN_OUTPUT, 3) /* (Y5) SPI1_D0.UART2_TXD */ + >; + }; + + main_uart4_pins_default: main-uart4-pins-default { + pinctrl-single,pins = < + J721E_IOPAD(0x190, PIN_INPUT, 1) /* (W23) RGMII6_TD3.UART4_RXD */ + J721E_IOPAD(0x194, PIN_OUTPUT, 1) /* (W28) RGMII6_TD2.UART4_TXD */ + >; + }; + sw10_button_pins_default: sw10-button-pins-default { pinctrl-single,pins = < J721E_IOPAD(0x0, PIN_INPUT, 7) /* (AC18) EXTINTn.GPIO0_0 */ @@ -295,6 +325,22 @@ }; &wkup_pmx0 { + wkup_uart0_pins_default: wkup-uart0-pins-default { + pinctrl-single,pins = < + J721E_WKUP_IOPAD(0xa0, PIN_INPUT, 0) /* (J29) WKUP_UART0_RXD */ + J721E_WKUP_IOPAD(0xa4, PIN_OUTPUT, 0) /* (J28) WKUP_UART0_TXD */ + >; + }; + + mcu_uart0_pins_default: mcu-uart0-pins-default { + pinctrl-single,pins = < + J721E_WKUP_IOPAD(0xe8, PIN_INPUT, 0) /* (H29) WKUP_GPIO0_14.MCU_UART0_CTSn */ + J721E_WKUP_IOPAD(0xec, PIN_OUTPUT, 0) /* (J27) WKUP_GPIO0_15.MCU_UART0_RTSn */ + J721E_WKUP_IOPAD(0xe4, PIN_INPUT, 0) /* (H28) WKUP_GPIO0_13.MCU_UART0_RXD */ + J721E_WKUP_IOPAD(0xe0, PIN_OUTPUT, 0) /* (G29) WKUP_GPIO0_12.MCU_UART0_TXD */ + >; + }; + sw11_button_pins_default: sw11-button-pins-default { pinctrl-single,pins = < J721E_WKUP_IOPAD(0xcc, PIN_INPUT, 7) /* (G28) WKUP_GPIO0_7 */ @@ -375,32 +421,40 @@ &wkup_uart0 { /* Wakeup UART is used by System firmware */ status = "reserved"; + pinctrl-names = "default"; + pinctrl-0 = <&wkup_uart0_pins_default>; }; &mcu_uart0 { status = "okay"; - /* Default pinmux */ + pinctrl-names = "default"; + pinctrl-0 = <&mcu_uart0_pins_default>; }; &main_uart0 { status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&main_uart0_pins_default>; /* Shared with ATF on this platform */ power-domains = <&k3_pds 146 TI_SCI_PD_SHARED>; }; &main_uart1 { status = "okay"; - /* Default pinmux */ + pinctrl-names = "default"; + pinctrl-0 = <&main_uart1_pins_default>; }; &main_uart2 { status = "okay"; - /* Default pinmux */ + pinctrl-names = "default"; + pinctrl-0 = <&main_uart2_pins_default>; }; &main_uart4 { status = "okay"; - /* Default pinmux */ + pinctrl-names = "default"; + pinctrl-0 = <&main_uart4_pins_default>; }; &main_gpio2 { -- cgit From b04b18ccb3d5c19c864c10f7cc7b014218aecb22 Mon Sep 17 00:00:00 2001 From: Nishanth Menon Date: Thu, 1 Jun 2023 13:31:47 -0500 Subject: arm64: dts: ti: k3-j721e-som-p0: Enable wakeup_i2c0 and eeprom Enable wakeup_i2c and use un-used pinmux. While at it, describe the board detection eeprom present on the board. Signed-off-by: Nishanth Menon Link: https://lore.kernel.org/r/20230601183151.1000157-6-nm@ti.com Signed-off-by: Vignesh Raghavendra --- arch/arm64/boot/dts/ti/k3-j721e-som-p0.dtsi | 13 +++++++++++++ 1 file changed, 13 insertions(+) diff --git a/arch/arm64/boot/dts/ti/k3-j721e-som-p0.dtsi b/arch/arm64/boot/dts/ti/k3-j721e-som-p0.dtsi index 1326b09a9c36..643ecac9effe 100644 --- a/arch/arm64/boot/dts/ti/k3-j721e-som-p0.dtsi +++ b/arch/arm64/boot/dts/ti/k3-j721e-som-p0.dtsi @@ -188,6 +188,19 @@ }; }; +&wkup_i2c0 { + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&wkup_i2c0_pins_default>; + clock-frequency = <400000>; + + eeprom@50 { + /* CAV24C256WE-GT3 */ + compatible = "atmel,24c256"; + reg = <0x50>; + }; +}; + &ospi0 { pinctrl-names = "default"; pinctrl-0 = <&mcu_fss0_ospi0_pins_default>; -- cgit From 4c2c99026ca1525912b40cbc1b69306145ce7082 Mon Sep 17 00:00:00 2001 From: Nishanth Menon Date: Thu, 1 Jun 2023 13:31:48 -0500 Subject: arm64: dts: ti: k3-j721e-beagleboneai64: Add wakeup_uart pinmux Define the wakeup uart pin-mux for completeness. This allows the device tree usage in bootloader and firmwares that can configure the same appropriately. Signed-off-by: Nishanth Menon Link: https://lore.kernel.org/r/20230601183151.1000157-7-nm@ti.com Signed-off-by: Vignesh Raghavendra --- arch/arm64/boot/dts/ti/k3-j721e-beagleboneai64.dts | 10 ++++++++++ 1 file changed, 10 insertions(+) diff --git a/arch/arm64/boot/dts/ti/k3-j721e-beagleboneai64.dts b/arch/arm64/boot/dts/ti/k3-j721e-beagleboneai64.dts index 961ca4fb3a43..27347a07d330 100644 --- a/arch/arm64/boot/dts/ti/k3-j721e-beagleboneai64.dts +++ b/arch/arm64/boot/dts/ti/k3-j721e-beagleboneai64.dts @@ -20,6 +20,7 @@ model = "BeagleBoard.org BeagleBone AI-64"; aliases { + serial0 = &wkup_uart0; serial2 = &main_uart0; mmc0 = &main_sdhci0; mmc1 = &main_sdhci1; @@ -531,6 +532,13 @@ >; }; + wkup_uart0_pins_default: wkup-uart0-pins-default { + pinctrl-single,pins = < + J721E_WKUP_IOPAD(0xa0, PIN_INPUT, 0) /* (J29) WKUP_UART0_RXD */ + J721E_WKUP_IOPAD(0xa4, PIN_OUTPUT, 0) /* (J28) WKUP_UART0_TXD */ + >; + }; + mcu_usbss1_pins_default: mcu-usbss1-pins-default { pinctrl-single,pins = < J721E_WKUP_IOPAD(0x3c, PIN_OUTPUT_PULLUP, 5) /* (A23) MCU_OSPI1_LBCLKO.WKUP_GPIO0_30 */ @@ -541,6 +549,8 @@ &wkup_uart0 { /* Wakeup UART is used by TIFS firmware. */ status = "reserved"; + pinctrl-names = "default"; + pinctrl-0 = <&wkup_uart0_pins_default>; }; &main_uart0 { -- cgit From d1a4304c149d1a26a912d532501ead42e5952501 Mon Sep 17 00:00:00 2001 From: Nishanth Menon Date: Thu, 1 Jun 2023 13:31:49 -0500 Subject: arm64: dts: ti: k3-j721e-sk: Define aliases at board level Define the aliases at the board level instead of using generic aliases at SoC level. Signed-off-by: Nishanth Menon Link: https://lore.kernel.org/r/20230601183151.1000157-8-nm@ti.com Signed-off-by: Vignesh Raghavendra --- arch/arm64/boot/dts/ti/k3-j721e-sk.dts | 9 +++++++++ 1 file changed, 9 insertions(+) diff --git a/arch/arm64/boot/dts/ti/k3-j721e-sk.dts b/arch/arm64/boot/dts/ti/k3-j721e-sk.dts index 0b15c44e0e66..ce6eb93fca9e 100644 --- a/arch/arm64/boot/dts/ti/k3-j721e-sk.dts +++ b/arch/arm64/boot/dts/ti/k3-j721e-sk.dts @@ -16,6 +16,15 @@ compatible = "ti,j721e-sk", "ti,j721e"; model = "Texas Instruments J721E SK"; + aliases { + serial0 = &wkup_uart0; + serial1 = &mcu_uart0; + serial2 = &main_uart0; + serial3 = &main_uart1; + ethernet0 = &cpsw_port1; + mmc1 = &main_sdhci1; + }; + chosen { stdout-path = "serial2:115200n8"; }; -- cgit From ff59580bf2580ec262098399aab03dfca537bec8 Mon Sep 17 00:00:00 2001 From: Nishanth Menon Date: Thu, 1 Jun 2023 13:31:50 -0500 Subject: arm64: dts: ti: k3-j721e-common-proc-board: Define aliases at board level Define the aliases at the board level instead of using generic aliases at SoC level. Signed-off-by: Nishanth Menon Link: https://lore.kernel.org/r/20230601183151.1000157-9-nm@ti.com Signed-off-by: Vignesh Raghavendra --- arch/arm64/boot/dts/ti/k3-j721e-common-proc-board.dts | 12 ++++++++++++ 1 file changed, 12 insertions(+) diff --git a/arch/arm64/boot/dts/ti/k3-j721e-common-proc-board.dts b/arch/arm64/boot/dts/ti/k3-j721e-common-proc-board.dts index fa9094321729..5fc002e5a18c 100644 --- a/arch/arm64/boot/dts/ti/k3-j721e-common-proc-board.dts +++ b/arch/arm64/boot/dts/ti/k3-j721e-common-proc-board.dts @@ -17,6 +17,18 @@ compatible = "ti,j721e-evm", "ti,j721e"; model = "Texas Instruments J721e EVM"; + aliases { + serial0 = &wkup_uart0; + serial1 = &mcu_uart0; + serial2 = &main_uart0; + serial3 = &main_uart1; + serial4 = &main_uart2; + serial6 = &main_uart4; + ethernet0 = &cpsw_port1; + mmc0 = &main_sdhci0; + mmc1 = &main_sdhci1; + }; + chosen { stdout-path = "serial2:115200n8"; }; -- cgit From 8be20986e0c54420e52048d20bdc31e3a8aec93f Mon Sep 17 00:00:00 2001 From: Nishanth Menon Date: Thu, 1 Jun 2023 13:31:51 -0500 Subject: arm64: dts: ti: k3-j721e: Drop SoC level aliases Drop the SoC level aliases as these need to be done at board level. Signed-off-by: Nishanth Menon Link: https://lore.kernel.org/r/20230601183151.1000157-10-nm@ti.com Signed-off-by: Vignesh Raghavendra --- arch/arm64/boot/dts/ti/k3-j721e.dtsi | 19 ------------------- 1 file changed, 19 deletions(-) diff --git a/arch/arm64/boot/dts/ti/k3-j721e.dtsi b/arch/arm64/boot/dts/ti/k3-j721e.dtsi index 99436105ada1..95f67e1d0c01 100644 --- a/arch/arm64/boot/dts/ti/k3-j721e.dtsi +++ b/arch/arm64/boot/dts/ti/k3-j721e.dtsi @@ -18,25 +18,6 @@ #address-cells = <2>; #size-cells = <2>; - aliases { - serial0 = &wkup_uart0; - serial1 = &mcu_uart0; - serial2 = &main_uart0; - serial3 = &main_uart1; - serial4 = &main_uart2; - serial5 = &main_uart3; - serial6 = &main_uart4; - serial7 = &main_uart5; - serial8 = &main_uart6; - serial9 = &main_uart7; - serial10 = &main_uart8; - serial11 = &main_uart9; - ethernet0 = &cpsw_port1; - mmc0 = &main_sdhci0; - mmc1 = &main_sdhci1; - mmc2 = &main_sdhci2; - }; - chosen { }; cpus { -- cgit From c8a28ed4837ce03254e0941f4fbc8364b1e78543 Mon Sep 17 00:00:00 2001 From: Udit Kumar Date: Sun, 11 Jun 2023 16:41:35 +0530 Subject: arm64: dts: ti: k3-j7200: Add general purpose timers There are 20 general purpose timers on j721e that can be used for things like PWM using pwm-omap-dmtimer driver. There are also additional ten timers in the MCU domain which are meant for MCU firmware usage and hence marked reserved by default. The odd numbered timers have the option of being cascaded to even timers to create a 64 bit non-atomic counter which is racy in simple usage, hence the clock muxes are explicitly setup to individual 32 bit counters driven off system crystal (HFOSC) as default. Signed-off-by: Udit Kumar Reviewed-by: Tony Lindgren Reviewed-by: Nishanth Menon Link: https://lore.kernel.org/r/20230611111140.3189111-2-u-kumar1@ti.com Signed-off-by: Vignesh Raghavendra --- arch/arm64/boot/dts/ti/k3-j7200-main.dtsi | 240 ++++++++++++++++++++++++ arch/arm64/boot/dts/ti/k3-j7200-mcu-wakeup.dtsi | 130 +++++++++++++ 2 files changed, 370 insertions(+) diff --git a/arch/arm64/boot/dts/ti/k3-j7200-main.dtsi b/arch/arm64/boot/dts/ti/k3-j7200-main.dtsi index ef352e32f19d..c6b15aceea82 100644 --- a/arch/arm64/boot/dts/ti/k3-j7200-main.dtsi +++ b/arch/arm64/boot/dts/ti/k3-j7200-main.dtsi @@ -971,6 +971,246 @@ assigned-clock-parents = <&k3_clks 253 5>; }; + main_timer0: timer@2400000 { + compatible = "ti,am654-timer"; + reg = <0x00 0x2400000 0x00 0x400>; + interrupts = ; + clocks = <&k3_clks 49 1>; + clock-names = "fck"; + assigned-clocks = <&k3_clks 49 1>; + assigned-clock-parents = <&k3_clks 49 2>; + power-domains = <&k3_pds 49 TI_SCI_PD_EXCLUSIVE>; + ti,timer-pwm; + }; + + main_timer1: timer@2410000 { + compatible = "ti,am654-timer"; + reg = <0x00 0x2410000 0x00 0x400>; + interrupts = ; + clocks = <&k3_clks 50 1>; + clock-names = "fck"; + assigned-clocks = <&k3_clks 50 1>, <&k3_clks 313 0>; + assigned-clock-parents = <&k3_clks 50 2>, <&k3_clks 313 1>; + power-domains = <&k3_pds 50 TI_SCI_PD_EXCLUSIVE>; + ti,timer-pwm; + }; + + main_timer2: timer@2420000 { + compatible = "ti,am654-timer"; + reg = <0x00 0x2420000 0x00 0x400>; + interrupts = ; + clocks = <&k3_clks 51 1>; + clock-names = "fck"; + assigned-clocks = <&k3_clks 51 1>; + assigned-clock-parents = <&k3_clks 51 2>; + power-domains = <&k3_pds 49 TI_SCI_PD_EXCLUSIVE>; + ti,timer-pwm; + }; + + main_timer3: timer@2430000 { + compatible = "ti,am654-timer"; + reg = <0x00 0x2430000 0x00 0x400>; + interrupts = ; + clocks = <&k3_clks 52 1>; + clock-names = "fck"; + assigned-clocks = <&k3_clks 52 1>, <&k3_clks 314 0>; + assigned-clock-parents = <&k3_clks 52 2>, <&k3_clks 314 1>; + power-domains = <&k3_pds 52 TI_SCI_PD_EXCLUSIVE>; + ti,timer-pwm; + }; + + main_timer4: timer@2440000 { + compatible = "ti,am654-timer"; + reg = <0x00 0x2440000 0x00 0x400>; + interrupts = ; + clocks = <&k3_clks 53 1>; + clock-names = "fck"; + assigned-clocks = <&k3_clks 53 1>; + assigned-clock-parents = <&k3_clks 53 2>; + power-domains = <&k3_pds 53 TI_SCI_PD_EXCLUSIVE>; + ti,timer-pwm; + }; + + main_timer5: timer@2450000 { + compatible = "ti,am654-timer"; + reg = <0x00 0x2450000 0x00 0x400>; + interrupts = ; + clocks = <&k3_clks 54 1>; + clock-names = "fck"; + assigned-clocks = <&k3_clks 54 1>, <&k3_clks 315 0>; + assigned-clock-parents = <&k3_clks 54 2>, <&k3_clks 315 1>; + power-domains = <&k3_pds 54 TI_SCI_PD_EXCLUSIVE>; + ti,timer-pwm; + }; + + main_timer6: timer@2460000 { + compatible = "ti,am654-timer"; + reg = <0x00 0x2460000 0x00 0x400>; + interrupts = ; + clocks = <&k3_clks 55 1>; + clock-names = "fck"; + assigned-clocks = <&k3_clks 55 1>; + assigned-clock-parents = <&k3_clks 55 2>; + power-domains = <&k3_pds 55 TI_SCI_PD_EXCLUSIVE>; + ti,timer-pwm; + }; + + main_timer7: timer@2470000 { + compatible = "ti,am654-timer"; + reg = <0x00 0x2470000 0x00 0x400>; + interrupts = ; + clocks = <&k3_clks 57 1>; + clock-names = "fck"; + assigned-clocks = <&k3_clks 57 1>, <&k3_clks 316 0>; + assigned-clock-parents = <&k3_clks 57 2>, <&k3_clks 316 1>; + power-domains = <&k3_pds 57 TI_SCI_PD_EXCLUSIVE>; + ti,timer-pwm; + }; + + main_timer8: timer@2480000 { + compatible = "ti,am654-timer"; + reg = <0x00 0x2480000 0x00 0x400>; + interrupts = ; + clocks = <&k3_clks 58 1>; + clock-names = "fck"; + assigned-clocks = <&k3_clks 58 1>; + assigned-clock-parents = <&k3_clks 58 2>; + power-domains = <&k3_pds 58 TI_SCI_PD_EXCLUSIVE>; + ti,timer-pwm; + }; + + main_timer9: timer@2490000 { + compatible = "ti,am654-timer"; + reg = <0x00 0x2490000 0x00 0x400>; + interrupts = ; + clocks = <&k3_clks 59 1>; + clock-names = "fck"; + assigned-clocks = <&k3_clks 59 1>, <&k3_clks 317 0>; + assigned-clock-parents = <&k3_clks 59 2>, <&k3_clks 317 1>; + power-domains = <&k3_pds 59 TI_SCI_PD_EXCLUSIVE>; + ti,timer-pwm; + }; + + main_timer10: timer@24a0000 { + compatible = "ti,am654-timer"; + reg = <0x00 0x24a0000 0x00 0x400>; + interrupts = ; + clocks = <&k3_clks 60 1>; + clock-names = "fck"; + assigned-clocks = <&k3_clks 60 1>; + assigned-clock-parents = <&k3_clks 60 2>; + power-domains = <&k3_pds 60 TI_SCI_PD_EXCLUSIVE>; + ti,timer-pwm; + }; + + main_timer11: timer@24b0000 { + compatible = "ti,am654-timer"; + reg = <0x00 0x24b0000 0x00 0x400>; + interrupts = ; + clocks = <&k3_clks 62 1>; + clock-names = "fck"; + assigned-clocks = <&k3_clks 62 1>, <&k3_clks 318 0>; + assigned-clock-parents = <&k3_clks 62 2>, <&k3_clks 318 1>; + power-domains = <&k3_pds 62 TI_SCI_PD_EXCLUSIVE>; + ti,timer-pwm; + }; + + main_timer12: timer@24c0000 { + compatible = "ti,am654-timer"; + reg = <0x00 0x24c0000 0x00 0x400>; + interrupts = ; + clocks = <&k3_clks 63 1>; + clock-names = "fck"; + assigned-clocks = <&k3_clks 63 1>; + assigned-clock-parents = <&k3_clks 63 2>; + power-domains = <&k3_pds 63 TI_SCI_PD_EXCLUSIVE>; + ti,timer-pwm; + }; + + main_timer13: timer@24d0000 { + compatible = "ti,am654-timer"; + reg = <0x00 0x24d0000 0x00 0x400>; + interrupts = ; + clocks = <&k3_clks 64 1>; + clock-names = "fck"; + assigned-clocks = <&k3_clks 64 1>, <&k3_clks 319 0>; + assigned-clock-parents = <&k3_clks 64 2>, <&k3_clks 319 1>; + power-domains = <&k3_pds 64 TI_SCI_PD_EXCLUSIVE>; + ti,timer-pwm; + }; + + main_timer14: timer@24e0000 { + compatible = "ti,am654-timer"; + reg = <0x00 0x24e0000 0x00 0x400>; + interrupts = ; + clocks = <&k3_clks 65 1>; + clock-names = "fck"; + assigned-clocks = <&k3_clks 65 1>; + assigned-clock-parents = <&k3_clks 65 2>; + power-domains = <&k3_pds 65 TI_SCI_PD_EXCLUSIVE>; + ti,timer-pwm; + }; + + main_timer15: timer@24f0000 { + compatible = "ti,am654-timer"; + reg = <0x00 0x24f0000 0x00 0x400>; + interrupts = ; + clocks = <&k3_clks 66 1>; + clock-names = "fck"; + assigned-clocks = <&k3_clks 66 1>, <&k3_clks 320 0>; + assigned-clock-parents = <&k3_clks 66 2>, <&k3_clks 320 1>; + power-domains = <&k3_pds 66 TI_SCI_PD_EXCLUSIVE>; + ti,timer-pwm; + }; + + main_timer16: timer@2500000 { + compatible = "ti,am654-timer"; + reg = <0x00 0x2500000 0x00 0x400>; + interrupts = ; + clocks = <&k3_clks 67 1>; + clock-names = "fck"; + assigned-clocks = <&k3_clks 67 1>; + assigned-clock-parents = <&k3_clks 67 2>; + power-domains = <&k3_pds 67 TI_SCI_PD_EXCLUSIVE>; + ti,timer-pwm; + }; + + main_timer17: timer@2510000 { + compatible = "ti,am654-timer"; + reg = <0x00 0x2510000 0x00 0x400>; + interrupts = ; + clocks = <&k3_clks 68 1>; + clock-names = "fck"; + assigned-clocks = <&k3_clks 68 1>, <&k3_clks 321 0>; + assigned-clock-parents = <&k3_clks 68 2>, <&k3_clks 321 1>; + power-domains = <&k3_pds 68 TI_SCI_PD_EXCLUSIVE>; + ti,timer-pwm; + }; + + main_timer18: timer@2520000 { + compatible = "ti,am654-timer"; + reg = <0x00 0x2520000 0x00 0x400>; + interrupts = ; + clocks = <&k3_clks 69 1>; + clock-names = "fck"; + assigned-clocks = <&k3_clks 69 1>; + assigned-clock-parents = <&k3_clks 69 2>; + power-domains = <&k3_pds 69 TI_SCI_PD_EXCLUSIVE>; + ti,timer-pwm; + }; + + main_timer19: timer@2530000 { + compatible = "ti,am654-timer"; + reg = <0x00 0x2530000 0x00 0x400>; + interrupts = ; + clocks = <&k3_clks 70 1>; + clock-names = "fck"; + assigned-clocks = <&k3_clks 70 1>, <&k3_clks 322 0>; + assigned-clock-parents = <&k3_clks 70 2>, <&k3_clks 322 1>; + power-domains = <&k3_pds 70 TI_SCI_PD_EXCLUSIVE>; + ti,timer-pwm; + }; + main_r5fss0: r5fss@5c00000 { compatible = "ti,j7200-r5fss"; ti,cluster-mode = <1>; diff --git a/arch/arm64/boot/dts/ti/k3-j7200-mcu-wakeup.dtsi b/arch/arm64/boot/dts/ti/k3-j7200-mcu-wakeup.dtsi index 22084bdf6d26..d76510b55af6 100644 --- a/arch/arm64/boot/dts/ti/k3-j7200-mcu-wakeup.dtsi +++ b/arch/arm64/boot/dts/ti/k3-j7200-mcu-wakeup.dtsi @@ -34,6 +34,136 @@ }; }; + mcu_timer0: timer@40400000 { + status = "reserved"; + compatible = "ti,am654-timer"; + reg = <0x00 0x40400000 0x00 0x400>; + interrupts = ; + clocks = <&k3_clks 35 1>; + clock-names = "fck"; + assigned-clocks = <&k3_clks 35 1>; + assigned-clock-parents = <&k3_clks 35 2>; + power-domains = <&k3_pds 35 TI_SCI_PD_EXCLUSIVE>; + ti,timer-pwm; + }; + + mcu_timer1: timer@40410000 { + status = "reserved"; + compatible = "ti,am654-timer"; + reg = <0x00 0x40410000 0x00 0x400>; + interrupts = ; + clocks = <&k3_clks 71 1>; + clock-names = "fck"; + assigned-clocks = <&k3_clks 71 1>, <&k3_clks 308 0>; + assigned-clock-parents = <&k3_clks 71 2>, <&k3_clks 308 1>; + power-domains = <&k3_pds 71 TI_SCI_PD_EXCLUSIVE>; + ti,timer-pwm; + }; + + mcu_timer2: timer@40420000 { + status = "reserved"; + compatible = "ti,am654-timer"; + reg = <0x00 0x40420000 0x00 0x400>; + interrupts = ; + clocks = <&k3_clks 72 1>; + clock-names = "fck"; + assigned-clocks = <&k3_clks 72 1>; + assigned-clock-parents = <&k3_clks 72 2>; + power-domains = <&k3_pds 72 TI_SCI_PD_EXCLUSIVE>; + ti,timer-pwm; + }; + + mcu_timer3: timer@40430000 { + status = "reserved"; + compatible = "ti,am654-timer"; + reg = <0x00 0x40430000 0x00 0x400>; + interrupts = ; + clocks = <&k3_clks 73 1>; + clock-names = "fck"; + assigned-clocks = <&k3_clks 73 1>, <&k3_clks 309 0>; + assigned-clock-parents = <&k3_clks 73 2>, <&k3_clks 309 1>; + power-domains = <&k3_pds 73 TI_SCI_PD_EXCLUSIVE>; + ti,timer-pwm; + }; + + mcu_timer4: timer@40440000 { + status = "reserved"; + compatible = "ti,am654-timer"; + reg = <0x00 0x40440000 0x00 0x400>; + interrupts = ; + clocks = <&k3_clks 74 1>; + clock-names = "fck"; + assigned-clocks = <&k3_clks 74 1>; + assigned-clock-parents = <&k3_clks 74 2>; + power-domains = <&k3_pds 74 TI_SCI_PD_EXCLUSIVE>; + ti,timer-pwm; + }; + + mcu_timer5: timer@40450000 { + status = "reserved"; + compatible = "ti,am654-timer"; + reg = <0x00 0x40450000 0x00 0x400>; + interrupts = ; + clocks = <&k3_clks 75 1>; + clock-names = "fck"; + assigned-clocks = <&k3_clks 75 1>, <&k3_clks 310 0>; + assigned-clock-parents = <&k3_clks 75 2>, <&k3_clks 310 1>; + power-domains = <&k3_pds 75 TI_SCI_PD_EXCLUSIVE>; + ti,timer-pwm; + }; + + mcu_timer6: timer@40460000 { + status = "reserved"; + compatible = "ti,am654-timer"; + reg = <0x00 0x40460000 0x00 0x400>; + interrupts = ; + clocks = <&k3_clks 76 1>; + clock-names = "fck"; + assigned-clocks = <&k3_clks 76 1>; + assigned-clock-parents = <&k3_clks 76 2>; + power-domains = <&k3_pds 35 TI_SCI_PD_EXCLUSIVE>; + ti,timer-pwm; + }; + + mcu_timer7: timer@40470000 { + status = "reserved"; + compatible = "ti,am654-timer"; + reg = <0x00 0x40470000 0x00 0x400>; + interrupts = ; + clocks = <&k3_clks 77 1>; + clock-names = "fck"; + assigned-clocks = <&k3_clks 77 1>, <&k3_clks 311 0>; + assigned-clock-parents = <&k3_clks 77 2>, <&k3_clks 311 1>; + power-domains = <&k3_pds 77 TI_SCI_PD_EXCLUSIVE>; + ti,timer-pwm; + }; + + mcu_timer8: timer@40480000 { + status = "reserved"; + compatible = "ti,am654-timer"; + reg = <0x00 0x40480000 0x00 0x400>; + interrupts = ; + clocks = <&k3_clks 78 1>; + clock-names = "fck"; + assigned-clocks = <&k3_clks 78 1>; + assigned-clock-parents = <&k3_clks 78 2>; + power-domains = <&k3_pds 78 TI_SCI_PD_EXCLUSIVE>; + ti,timer-pwm; + }; + + mcu_timer9: timer@40490000 { + status = "reserved"; + compatible = "ti,am654-timer"; + reg = <0x00 0x40490000 0x00 0x400>; + interrupts = ; + clocks = <&k3_clks 79 1>; + clock-names = "fck"; + assigned-clocks = <&k3_clks 79 1>, <&k3_clks 312 0>; + assigned-clock-parents = <&k3_clks 79 2>, <&k3_clks 312 1>; + power-domains = <&k3_pds 79 TI_SCI_PD_EXCLUSIVE>; + ti,timer-pwm; + }; + mcu_conf: syscon@40f00000 { compatible = "syscon", "simple-mfd"; reg = <0x00 0x40f00000 0x00 0x20000>; -- cgit From 03612d384621ffe21c6d338de916251d1bfd84fa Mon Sep 17 00:00:00 2001 From: Udit Kumar Date: Sun, 11 Jun 2023 16:41:36 +0530 Subject: arm64: dts: ti: k3-j7200: Configure pinctrl for timer IO pads There are timer IO pads in the MCU domain, and in the MAIN domain. These pads can be muxed for the related timers. There are timer IO control registers for input and output. The registers for CTRLMMR_TIMER*_CTRL and CTRLMMR_MCU_TIMER*_CTRL are used to control the input. The registers for CTCTRLMMR_TIMERIO*_CTRL and CTRLMMR_MCU_TIMERIO*_CTRL the output. The multiplexing is documented in TRM "5.1.2.3.1.4 Timer IO Muxing Control Registers" and "5.1.3.3.1.5 Timer IO Muxing Control Registers", and the CASCADE_EN bit is documented in TRM "12.6.3.1 Timers Overview". For chaining timers, the timer IO control registers also have a CASCADE_EN input bit in the CTRLMMR_TIMER*_CTRL in the registers. The CASCADE_EN bit muxes the previous timer output, or possibly and external TIMER_IO pad source, to the input clock of the selected timer instance for odd numered timers. For the even numbered timers, the CASCADE_EN bit does not do anything. The timer cascade input routing options are shown in TRM "Figure 12-3224. Timers Overview". For handling beyond multiplexing, the driver support for timer cascading should be likely be handled via the clock framework. The MCU timer controls are also marked as reserved for usage by the MCU firmware. Cc: Nishanth Menon Cc: Vignesh Raghavendra Cc: Tony Lindgren Reviewed-by: Tony Lindgren Signed-off-by: Udit Kumar Reviewed-by: Nishanth Menon Link: https://lore.kernel.org/r/20230611111140.3189111-3-u-kumar1@ti.com Signed-off-by: Vignesh Raghavendra --- arch/arm64/boot/dts/ti/k3-j7200-main.dtsi | 18 ++++++++++++++++++ arch/arm64/boot/dts/ti/k3-j7200-mcu-wakeup.dtsi | 20 ++++++++++++++++++++ 2 files changed, 38 insertions(+) diff --git a/arch/arm64/boot/dts/ti/k3-j7200-main.dtsi b/arch/arm64/boot/dts/ti/k3-j7200-main.dtsi index c6b15aceea82..a9b3bf8a5c6a 100644 --- a/arch/arm64/boot/dts/ti/k3-j7200-main.dtsi +++ b/arch/arm64/boot/dts/ti/k3-j7200-main.dtsi @@ -392,6 +392,24 @@ }; }; + /* TIMERIO pad input CTRLMMR_TIMER*_CTRL registers */ + main_timerio_input: pinctrl@104200 { + compatible = "pinctrl-single"; + reg = <0x0 0x104200 0x0 0x50>; + #pinctrl-cells = <1>; + pinctrl-single,register-width = <32>; + pinctrl-single,function-mask = <0x000001ff>; + }; + + /* TIMERIO pad output CTCTRLMMR_TIMERIO*_CTRL registers */ + main_timerio_output: pinctrl@104280 { + compatible = "pinctrl-single"; + reg = <0x0 0x104280 0x0 0x20>; + #pinctrl-cells = <1>; + pinctrl-single,register-width = <32>; + pinctrl-single,function-mask = <0x0000001f>; + }; + main_pmx0: pinctrl@11c000 { compatible = "pinctrl-single"; /* Proxy 0 addressing */ diff --git a/arch/arm64/boot/dts/ti/k3-j7200-mcu-wakeup.dtsi b/arch/arm64/boot/dts/ti/k3-j7200-mcu-wakeup.dtsi index d76510b55af6..e66c2495f54d 100644 --- a/arch/arm64/boot/dts/ti/k3-j7200-mcu-wakeup.dtsi +++ b/arch/arm64/boot/dts/ti/k3-j7200-mcu-wakeup.dtsi @@ -183,6 +183,26 @@ reg = <0x00 0x43000014 0x00 0x4>; }; + /* MCU_TIMERIO pad input CTRLMMR_MCU_TIMER*_CTRL registers */ + mcu_timerio_input: pinctrl@40f04200 { + compatible = "pinctrl-single"; + reg = <0x0 0x40f04200 0x0 0x28>; + #pinctrl-cells = <1>; + pinctrl-single,register-width = <32>; + pinctrl-single,function-mask = <0x0000000F>; + status = "reserved"; + }; + + /* MCU_TIMERIO pad output CTRLMMR_MCU_TIMERIO*_CTRL registers */ + mcu_timerio_output: pinctrl@40f04280 { + compatible = "pinctrl-single"; + reg = <0x0 0x40f04280 0x0 0x28>; + #pinctrl-cells = <1>; + pinctrl-single,register-width = <32>; + pinctrl-single,function-mask = <0x0000000F>; + status = "reserved"; + }; + wkup_pmx0: pinctrl@4301c000 { compatible = "pinctrl-single"; /* Proxy 0 addressing */ -- cgit From 7f58e2b418d89f38f242b04da5a1dd93a2c514fd Mon Sep 17 00:00:00 2001 From: Udit Kumar Date: Sun, 11 Jun 2023 16:41:37 +0530 Subject: arm64: dts: ti: k3-j7200-common-proc-board: remove duplicate main_i2c0 pin mux main_i2c0 pin mux was duplicated in som and common file. So removing duplicated node from common file. Signed-off-by: Udit Kumar Reviewed-by: Nishanth Menon Link: https://lore.kernel.org/r/20230611111140.3189111-4-u-kumar1@ti.com Signed-off-by: Vignesh Raghavendra --- arch/arm64/boot/dts/ti/k3-j7200-common-proc-board.dts | 7 ------- 1 file changed, 7 deletions(-) diff --git a/arch/arm64/boot/dts/ti/k3-j7200-common-proc-board.dts b/arch/arm64/boot/dts/ti/k3-j7200-common-proc-board.dts index e8a2997289ba..ea5a4a61e531 100644 --- a/arch/arm64/boot/dts/ti/k3-j7200-common-proc-board.dts +++ b/arch/arm64/boot/dts/ti/k3-j7200-common-proc-board.dts @@ -112,13 +112,6 @@ }; &main_pmx0 { - main_i2c0_pins_default: main-i2c0-pins-default { - pinctrl-single,pins = < - J721E_IOPAD(0xd4, PIN_INPUT_PULLUP, 0) /* (V3) I2C0_SCL */ - J721E_IOPAD(0xd8, PIN_INPUT_PULLUP, 0) /* (W2) I2C0_SDA */ - >; - }; - main_i2c1_pins_default: main-i2c1-pins-default { pinctrl-single,pins = < J721E_IOPAD(0xdc, PIN_INPUT_PULLUP, 3) /* (U3) ECAP0_IN_APWM_OUT.I2C1_SCL */ -- cgit From 3709ea7f960ed77ac29af692c9e32351060400d9 Mon Sep 17 00:00:00 2001 From: Udit Kumar Date: Sun, 11 Jun 2023 16:41:38 +0530 Subject: arm64: dts: ti: k3-j7200-common-proc-board: Add uart pinmux Add main, mcu, wakeup domain uart0 pin mux into common board file and it's reference to uart node. Signed-off-by: Udit Kumar Reviewed-by: Nishanth Menon Link: https://lore.kernel.org/r/20230611111140.3189111-5-u-kumar1@ti.com Signed-off-by: Vignesh Raghavendra --- .../boot/dts/ti/k3-j7200-common-proc-board.dts | 58 +++++++++++++++++++++- 1 file changed, 57 insertions(+), 1 deletion(-) diff --git a/arch/arm64/boot/dts/ti/k3-j7200-common-proc-board.dts b/arch/arm64/boot/dts/ti/k3-j7200-common-proc-board.dts index ea5a4a61e531..7d67e4b731b2 100644 --- a/arch/arm64/boot/dts/ti/k3-j7200-common-proc-board.dts +++ b/arch/arm64/boot/dts/ti/k3-j7200-common-proc-board.dts @@ -79,6 +79,24 @@ }; }; +&wkup_pmx0 { + mcu_uart0_pins_default: mcu-uart0-pins-default { + pinctrl-single,pins = < + J721E_WKUP_IOPAD(0xf4, PIN_INPUT, 0) /* (D20) MCU_UART0_RXD */ + J721E_WKUP_IOPAD(0xf0, PIN_OUTPUT, 0) /* (D19) MCU_UART0_TXD */ + J721E_WKUP_IOPAD(0xf8, PIN_INPUT, 0) /* (E20) MCU_UART0_CTSn */ + J721E_WKUP_IOPAD(0xfc, PIN_OUTPUT, 0) /* (E21) MCU_UART0_RTSn */ + >; + }; + + wkup_uart0_pins_default: wkup-uart0-pins-default { + pinctrl-single,pins = < + J721E_WKUP_IOPAD(0xb0, PIN_INPUT, 0) /* (B14) WKUP_UART0_RXD */ + J721E_WKUP_IOPAD(0xb4, PIN_OUTPUT, 0) /* (A14) WKUP_UART0_TXD */ + >; + }; +}; + &wkup_pmx2 { mcu_cpsw_pins_default: mcu-cpsw-pins-default { pinctrl-single,pins = < @@ -112,6 +130,29 @@ }; &main_pmx0 { + main_uart0_pins_default: main-uart0-pins-default { + pinctrl-single,pins = < + J721E_IOPAD(0xb0, PIN_INPUT, 0) /* (T16) UART0_RXD */ + J721E_IOPAD(0xb4, PIN_OUTPUT, 0) /* (T17) UART0_TXD */ + J721E_IOPAD(0xc0, PIN_INPUT, 2) /* (W3) SPI0_CS0.UART0_CTSn */ + J721E_IOPAD(0xc4, PIN_OUTPUT, 2) /* (U5) SPI0_CS1.UART0_RTSn */ + >; + }; + + main_uart1_pins_default: main-uart1-pins-default { + pinctrl-single,pins = < + J721E_IOPAD(0xb8, PIN_INPUT, 0) /* (T18) UART1_RXD */ + J721E_IOPAD(0xbc, PIN_INPUT, 0) /* (T20) UART1_TXD */ + >; + }; + + main_uart3_pins_default: main-uart3-pins-default { + pinctrl-single,pins = < + J721E_IOPAD(0x60, PIN_INPUT, 11) /* (T15) MCAN8_TX.UART3_CTSn */ + J721E_IOPAD(0x30, PIN_INPUT, 11) /* (Y18) MCAN2_TX.UART3_RXD */ + >; + }; + main_i2c1_pins_default: main-i2c1-pins-default { pinctrl-single,pins = < J721E_IOPAD(0xdc, PIN_INPUT_PULLUP, 3) /* (U3) ECAP0_IN_APWM_OUT.I2C1_SCL */ @@ -150,22 +191,30 @@ &wkup_uart0 { /* Wakeup UART is used by System firmware */ status = "reserved"; + pinctrl-names = "default"; + pinctrl-0 = <&wkup_uart0_pins_default>; }; &mcu_uart0 { status = "okay"; - /* Default pinmux */ + pinctrl-names = "default"; + pinctrl-0 = <&mcu_uart0_pins_default>; + clock-frequency = <96000000>; }; &main_uart0 { status = "okay"; /* Shared with ATF on this platform */ power-domains = <&k3_pds 146 TI_SCI_PD_SHARED>; + pinctrl-names = "default"; + pinctrl-0 = <&main_uart0_pins_default>; }; &main_uart1 { status = "okay"; /* Default pinmux */ + pinctrl-names = "default"; + pinctrl-0 = <&main_uart1_pins_default>; }; &main_uart2 { @@ -173,6 +222,13 @@ status = "reserved"; }; +&main_uart3 { + /* Shared with MCAN Interface */ + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&main_uart3_pins_default>; +}; + &main_gpio2 { status = "disabled"; }; -- cgit From c4ba159fff90791956370ce93c130aadea87dbb6 Mon Sep 17 00:00:00 2001 From: Udit Kumar Date: Sun, 11 Jun 2023 16:41:39 +0530 Subject: arm64: dts: ti: k3-j7200-common-proc-board: Define aliases at board level Define aliases at board level Signed-off-by: Udit Kumar Reviewed-by: Nishanth Menon Link: https://lore.kernel.org/r/20230611111140.3189111-6-u-kumar1@ti.com Signed-off-by: Vignesh Raghavendra --- arch/arm64/boot/dts/ti/k3-j7200-common-proc-board.dts | 10 ++++++++++ 1 file changed, 10 insertions(+) diff --git a/arch/arm64/boot/dts/ti/k3-j7200-common-proc-board.dts b/arch/arm64/boot/dts/ti/k3-j7200-common-proc-board.dts index 7d67e4b731b2..b5159a30108c 100644 --- a/arch/arm64/boot/dts/ti/k3-j7200-common-proc-board.dts +++ b/arch/arm64/boot/dts/ti/k3-j7200-common-proc-board.dts @@ -15,6 +15,16 @@ compatible = "ti,j7200-evm", "ti,j7200"; model = "Texas Instruments J7200 EVM"; + aliases { + serial0 = &wkup_uart0; + serial1 = &mcu_uart0; + serial2 = &main_uart0; + serial3 = &main_uart1; + serial5 = &main_uart3; + mmc0 = &main_sdhci0; + mmc1 = &main_sdhci1; + }; + chosen { stdout-path = "serial2:115200n8"; }; -- cgit From 858dde8a3f56f0b7a0c217ac4abf56e34c34ae74 Mon Sep 17 00:00:00 2001 From: Udit Kumar Date: Sun, 11 Jun 2023 16:41:40 +0530 Subject: arm64: dts: ti: k3-j7200: Drop SoC level aliases Aiases are defined at board level, so dropping from soc level Signed-off-by: Udit Kumar Reviewed-by: Nishanth Menon Link: https://lore.kernel.org/r/20230611111140.3189111-7-u-kumar1@ti.com Signed-off-by: Vignesh Raghavendra --- arch/arm64/boot/dts/ti/k3-j7200.dtsi | 17 ----------------- 1 file changed, 17 deletions(-) diff --git a/arch/arm64/boot/dts/ti/k3-j7200.dtsi b/arch/arm64/boot/dts/ti/k3-j7200.dtsi index 6c96759e8752..3b3a1af7d60d 100644 --- a/arch/arm64/boot/dts/ti/k3-j7200.dtsi +++ b/arch/arm64/boot/dts/ti/k3-j7200.dtsi @@ -18,23 +18,6 @@ #address-cells = <2>; #size-cells = <2>; - aliases { - serial0 = &wkup_uart0; - serial1 = &mcu_uart0; - serial2 = &main_uart0; - serial3 = &main_uart1; - serial4 = &main_uart2; - serial5 = &main_uart3; - serial6 = &main_uart4; - serial7 = &main_uart5; - serial8 = &main_uart6; - serial9 = &main_uart7; - serial10 = &main_uart8; - serial11 = &main_uart9; - mmc0 = &main_sdhci0; - mmc1 = &main_sdhci1; - }; - chosen { }; cpus { -- cgit From 6bc829ceea4158c7aeb3a9e73d5c52634d78fb6f Mon Sep 17 00:00:00 2001 From: Sinthu Raja Date: Fri, 2 Jun 2023 10:35:49 -0500 Subject: arm64: dts: ti: k3-j721s2: Fix wkup pinmux range The WKUP_PADCONFIG register region in J721S2 has multiple non-addressable regions, accordingly split the existing wkup_pmx region as follows to avoid the non-addressable regions and include the rest of valid WKUP_PADCONFIG registers. Also update references to old nodes with new ones. wkup_pmx0 -> 13 pins (WKUP_PADCONFIG 0 - 12) wkup_pmx1 -> 11 pins (WKUP_PADCONFIG 14 - 24) wkup_pmx2 -> 72 pins (WKUP_PADCONFIG 26 - 97) wkup_pmx3 -> 1 pin (WKUP_PADCONFIG 100) Fixes: b8545f9d3a54 ("arm64: dts: ti: Add initial support for J721S2 SoC") Cc: # 6.3 Signed-off-by: Sinthu Raja Signed-off-by: Thejasvi Konduru Signed-off-by: Nishanth Menon Reviewed-by: Udit Kumar Link: https://lore.kernel.org/r/20230602153554.1571128-2-nm@ti.com Signed-off-by: Vignesh Raghavendra --- arch/arm64/boot/dts/ti/k3-am68-sk-base-board.dts | 42 ++++++------ .../boot/dts/ti/k3-j721s2-common-proc-board.dts | 76 +++++++++++----------- arch/arm64/boot/dts/ti/k3-j721s2-mcu-wakeup.dtsi | 29 ++++++++- 3 files changed, 87 insertions(+), 60 deletions(-) diff --git a/arch/arm64/boot/dts/ti/k3-am68-sk-base-board.dts b/arch/arm64/boot/dts/ti/k3-am68-sk-base-board.dts index ae9116655a83..37b598e98f8b 100644 --- a/arch/arm64/boot/dts/ti/k3-am68-sk-base-board.dts +++ b/arch/arm64/boot/dts/ti/k3-am68-sk-base-board.dts @@ -175,49 +175,49 @@ }; }; -&wkup_pmx0 { +&wkup_pmx2 { mcu_cpsw_pins_default: mcu-cpsw-pins-default { pinctrl-single,pins = < - J721S2_WKUP_IOPAD(0x094, PIN_INPUT, 0) /* (B22) MCU_RGMII1_RD0 */ - J721S2_WKUP_IOPAD(0x090, PIN_INPUT, 0) /* (B21) MCU_RGMII1_RD1 */ - J721S2_WKUP_IOPAD(0x08c, PIN_INPUT, 0) /* (C22) MCU_RGMII1_RD2 */ - J721S2_WKUP_IOPAD(0x088, PIN_INPUT, 0) /* (D23) MCU_RGMII1_RD3 */ - J721S2_WKUP_IOPAD(0x084, PIN_INPUT, 0) /* (D22) MCU_RGMII1_RXC */ - J721S2_WKUP_IOPAD(0x06c, PIN_INPUT, 0) /* (E23) MCU_RGMII1_RX_CTL */ - J721S2_WKUP_IOPAD(0x07c, PIN_OUTPUT, 0) /* (F23) MCU_RGMII1_TD0 */ - J721S2_WKUP_IOPAD(0x078, PIN_OUTPUT, 0) /* (G22) MCU_RGMII1_TD1 */ - J721S2_WKUP_IOPAD(0x074, PIN_OUTPUT, 0) /* (E21) MCU_RGMII1_TD2 */ - J721S2_WKUP_IOPAD(0x070, PIN_OUTPUT, 0) /* (E22) MCU_RGMII1_TD3 */ - J721S2_WKUP_IOPAD(0x080, PIN_OUTPUT, 0) /* (F21) MCU_RGMII1_TXC */ - J721S2_WKUP_IOPAD(0x068, PIN_OUTPUT, 0) /* (F22) MCU_RGMII1_TX_CTL */ + J721S2_WKUP_IOPAD(0x02C, PIN_INPUT, 0) /* (B22) MCU_RGMII1_RD0 */ + J721S2_WKUP_IOPAD(0x028, PIN_INPUT, 0) /* (B21) MCU_RGMII1_RD1 */ + J721S2_WKUP_IOPAD(0x024, PIN_INPUT, 0) /* (C22) MCU_RGMII1_RD2 */ + J721S2_WKUP_IOPAD(0x020, PIN_INPUT, 0) /* (D23) MCU_RGMII1_RD3 */ + J721S2_WKUP_IOPAD(0x01C, PIN_INPUT, 0) /* (D22) MCU_RGMII1_RXC */ + J721S2_WKUP_IOPAD(0x004, PIN_INPUT, 0) /* (E23) MCU_RGMII1_RX_CTL */ + J721S2_WKUP_IOPAD(0x014, PIN_OUTPUT, 0) /* (F23) MCU_RGMII1_TD0 */ + J721S2_WKUP_IOPAD(0x010, PIN_OUTPUT, 0) /* (G22) MCU_RGMII1_TD1 */ + J721S2_WKUP_IOPAD(0x00C, PIN_OUTPUT, 0) /* (E21) MCU_RGMII1_TD2 */ + J721S2_WKUP_IOPAD(0x008, PIN_OUTPUT, 0) /* (E22) MCU_RGMII1_TD3 */ + J721S2_WKUP_IOPAD(0x018, PIN_OUTPUT, 0) /* (F21) MCU_RGMII1_TXC */ + J721S2_WKUP_IOPAD(0x000, PIN_OUTPUT, 0) /* (F22) MCU_RGMII1_TX_CTL */ >; }; mcu_mdio_pins_default: mcu-mdio-pins-default { pinctrl-single,pins = < - J721S2_WKUP_IOPAD(0x09c, PIN_OUTPUT, 0) /* (A21) MCU_MDIO0_MDC */ - J721S2_WKUP_IOPAD(0x098, PIN_INPUT, 0) /* (A22) MCU_MDIO0_MDIO */ + J721S2_WKUP_IOPAD(0x034, PIN_OUTPUT, 0) /* (A21) MCU_MDIO0_MDC */ + J721S2_WKUP_IOPAD(0x030, PIN_INPUT, 0) /* (A22) MCU_MDIO0_MDIO */ >; }; mcu_mcan0_pins_default: mcu-mcan0-pins-default { pinctrl-single,pins = < - J721S2_WKUP_IOPAD(0x0bc, PIN_INPUT, 0) /* (E28) MCU_MCAN0_RX */ - J721S2_WKUP_IOPAD(0x0b8, PIN_OUTPUT, 0) /* (E27) MCU_MCAN0_TX */ + J721S2_WKUP_IOPAD(0x054, PIN_INPUT, 0) /* (E28) MCU_MCAN0_RX */ + J721S2_WKUP_IOPAD(0x050, PIN_OUTPUT, 0) /* (E27) MCU_MCAN0_TX */ >; }; mcu_mcan1_pins_default: mcu-mcan1-pins-default { pinctrl-single,pins = < - J721S2_WKUP_IOPAD(0x0d4, PIN_INPUT, 0) /* (F26) WKUP_GPIO0_5.MCU_MCAN1_RX */ - J721S2_WKUP_IOPAD(0x0d0, PIN_OUTPUT, 0) /* (C23) WKUP_GPIO0_4.MCU_MCAN1_TX*/ + J721S2_WKUP_IOPAD(0x06C, PIN_INPUT, 0) /* (F26) WKUP_GPIO0_5.MCU_MCAN1_RX */ + J721S2_WKUP_IOPAD(0x068, PIN_OUTPUT, 0) /* (C23) WKUP_GPIO0_4.MCU_MCAN1_TX*/ >; }; mcu_i2c1_pins_default: mcu-i2c1-pins-default { pinctrl-single,pins = < - J721S2_WKUP_IOPAD(0x0e0, PIN_INPUT, 0) /* (F24) WKUP_GPIO0_8.MCU_I2C1_SCL */ - J721S2_WKUP_IOPAD(0x0e4, PIN_INPUT, 0) /* (H26) WKUP_GPIO0_9.MCU_I2C1_SDA */ + J721S2_WKUP_IOPAD(0x078, PIN_INPUT, 0) /* (F24) WKUP_GPIO0_8.MCU_I2C1_SCL */ + J721S2_WKUP_IOPAD(0x07c, PIN_INPUT, 0) /* (H26) WKUP_GPIO0_9.MCU_I2C1_SDA */ >; }; }; diff --git a/arch/arm64/boot/dts/ti/k3-j721s2-common-proc-board.dts b/arch/arm64/boot/dts/ti/k3-j721s2-common-proc-board.dts index a5ba2945c35f..aef62ac9b689 100644 --- a/arch/arm64/boot/dts/ti/k3-j721s2-common-proc-board.dts +++ b/arch/arm64/boot/dts/ti/k3-j721s2-common-proc-board.dts @@ -154,81 +154,81 @@ }; }; -&wkup_pmx0 { +&wkup_pmx2 { mcu_cpsw_pins_default: mcu-cpsw-pins-default { pinctrl-single,pins = < - J721S2_WKUP_IOPAD(0x094, PIN_INPUT, 0) /* (B22) MCU_RGMII1_RD0 */ - J721S2_WKUP_IOPAD(0x090, PIN_INPUT, 0) /* (B21) MCU_RGMII1_RD1 */ - J721S2_WKUP_IOPAD(0x08c, PIN_INPUT, 0) /* (C22) MCU_RGMII1_RD2 */ - J721S2_WKUP_IOPAD(0x088, PIN_INPUT, 0) /* (D23) MCU_RGMII1_RD3 */ - J721S2_WKUP_IOPAD(0x084, PIN_INPUT, 0) /* (D22) MCU_RGMII1_RXC */ - J721S2_WKUP_IOPAD(0x06c, PIN_INPUT, 0) /* (E23) MCU_RGMII1_RX_CTL */ - J721S2_WKUP_IOPAD(0x07c, PIN_OUTPUT, 0) /* (F23) MCU_RGMII1_TD0 */ - J721S2_WKUP_IOPAD(0x078, PIN_OUTPUT, 0) /* (G22) MCU_RGMII1_TD1 */ - J721S2_WKUP_IOPAD(0x074, PIN_OUTPUT, 0) /* (E21) MCU_RGMII1_TD2 */ - J721S2_WKUP_IOPAD(0x070, PIN_OUTPUT, 0) /* (E22) MCU_RGMII1_TD3 */ - J721S2_WKUP_IOPAD(0x080, PIN_OUTPUT, 0) /* (F21) MCU_RGMII1_TXC */ - J721S2_WKUP_IOPAD(0x068, PIN_OUTPUT, 0) /* (F22) MCU_RGMII1_TX_CTL */ + J721S2_WKUP_IOPAD(0x02c, PIN_INPUT, 0) /* (B22) MCU_RGMII1_RD0 */ + J721S2_WKUP_IOPAD(0x028, PIN_INPUT, 0) /* (B21) MCU_RGMII1_RD1 */ + J721S2_WKUP_IOPAD(0x024, PIN_INPUT, 0) /* (C22) MCU_RGMII1_RD2 */ + J721S2_WKUP_IOPAD(0x020, PIN_INPUT, 0) /* (D23) MCU_RGMII1_RD3 */ + J721S2_WKUP_IOPAD(0x01c, PIN_INPUT, 0) /* (D22) MCU_RGMII1_RXC */ + J721S2_WKUP_IOPAD(0x004, PIN_INPUT, 0) /* (E23) MCU_RGMII1_RX_CTL */ + J721S2_WKUP_IOPAD(0x014, PIN_OUTPUT, 0) /* (F23) MCU_RGMII1_TD0 */ + J721S2_WKUP_IOPAD(0x010, PIN_OUTPUT, 0) /* (G22) MCU_RGMII1_TD1 */ + J721S2_WKUP_IOPAD(0x00c, PIN_OUTPUT, 0) /* (E21) MCU_RGMII1_TD2 */ + J721S2_WKUP_IOPAD(0x008, PIN_OUTPUT, 0) /* (E22) MCU_RGMII1_TD3 */ + J721S2_WKUP_IOPAD(0x018, PIN_OUTPUT, 0) /* (F21) MCU_RGMII1_TXC */ + J721S2_WKUP_IOPAD(0x000, PIN_OUTPUT, 0) /* (F22) MCU_RGMII1_TX_CTL */ >; }; mcu_mdio_pins_default: mcu-mdio-pins-default { pinctrl-single,pins = < - J721S2_WKUP_IOPAD(0x09c, PIN_OUTPUT, 0) /* (A21) MCU_MDIO0_MDC */ - J721S2_WKUP_IOPAD(0x098, PIN_INPUT, 0) /* (A22) MCU_MDIO0_MDIO */ + J721S2_WKUP_IOPAD(0x034, PIN_OUTPUT, 0) /* (A21) MCU_MDIO0_MDC */ + J721S2_WKUP_IOPAD(0x030, PIN_INPUT, 0) /* (A22) MCU_MDIO0_MDIO */ >; }; mcu_mcan0_pins_default: mcu-mcan0-pins-default { pinctrl-single,pins = < - J721S2_WKUP_IOPAD(0x0bc, PIN_INPUT, 0) /* (E28) MCU_MCAN0_RX */ - J721S2_WKUP_IOPAD(0x0b8, PIN_OUTPUT, 0) /* (E27) MCU_MCAN0_TX */ + J721S2_WKUP_IOPAD(0x054, PIN_INPUT, 0) /* (E28) MCU_MCAN0_RX */ + J721S2_WKUP_IOPAD(0x050, PIN_OUTPUT, 0) /* (E27) MCU_MCAN0_TX */ >; }; mcu_mcan1_pins_default: mcu-mcan1-pins-default { pinctrl-single,pins = < - J721S2_WKUP_IOPAD(0x0d4, PIN_INPUT, 0) /* (F26) WKUP_GPIO0_5.MCU_MCAN1_RX */ - J721S2_WKUP_IOPAD(0x0d0, PIN_OUTPUT, 0) /* (C23) WKUP_GPIO0_4.MCU_MCAN1_TX */ + J721S2_WKUP_IOPAD(0x06c, PIN_INPUT, 0) /* (F26) WKUP_GPIO0_5.MCU_MCAN1_RX */ + J721S2_WKUP_IOPAD(0x068, PIN_OUTPUT, 0) /*(C23) WKUP_GPIO0_4.MCU_MCAN1_TX */ >; }; mcu_mcan0_gpio_pins_default: mcu-mcan0-gpio-pins-default { pinctrl-single,pins = < - J721S2_WKUP_IOPAD(0x0c0, PIN_INPUT, 7) /* (D26) WKUP_GPIO0_0 */ - J721S2_WKUP_IOPAD(0x0a8, PIN_INPUT, 7) /* (B25) MCU_SPI0_D1.WKUP_GPIO0_69 */ + J721S2_WKUP_IOPAD(0x058, PIN_INPUT, 7) /* (D26) WKUP_GPIO0_0 */ + J721S2_WKUP_IOPAD(0x040, PIN_INPUT, 7) /* (B25) MCU_SPI0_D1.WKUP_GPIO0_69 */ >; }; mcu_mcan1_gpio_pins_default: mcu-mcan1-gpio-pins-default { pinctrl-single,pins = < - J721S2_WKUP_IOPAD(0x0c8, PIN_INPUT, 7) /* (C28) WKUP_GPIO0_2 */ + J721S2_WKUP_IOPAD(0x060, PIN_INPUT, 7) /* (C28) WKUP_GPIO0_2 */ >; }; mcu_adc0_pins_default: mcu-adc0-pins-default { pinctrl-single,pins = < - J721S2_WKUP_IOPAD(0x134, PIN_INPUT, 0) /* (L25) MCU_ADC0_AIN0 */ - J721S2_WKUP_IOPAD(0x138, PIN_INPUT, 0) /* (K25) MCU_ADC0_AIN1 */ - J721S2_WKUP_IOPAD(0x13c, PIN_INPUT, 0) /* (M24) MCU_ADC0_AIN2 */ - J721S2_WKUP_IOPAD(0x140, PIN_INPUT, 0) /* (L24) MCU_ADC0_AIN3 */ - J721S2_WKUP_IOPAD(0x144, PIN_INPUT, 0) /* (L27) MCU_ADC0_AIN4 */ - J721S2_WKUP_IOPAD(0x148, PIN_INPUT, 0) /* (K24) MCU_ADC0_AIN5 */ - J721S2_WKUP_IOPAD(0x14c, PIN_INPUT, 0) /* (M27) MCU_ADC0_AIN6 */ - J721S2_WKUP_IOPAD(0x150, PIN_INPUT, 0) /* (M26) MCU_ADC0_AIN7 */ + J721S2_WKUP_IOPAD(0x0cc, PIN_INPUT, 0) /* (L25) MCU_ADC0_AIN0 */ + J721S2_WKUP_IOPAD(0x0d0, PIN_INPUT, 0) /* (K25) MCU_ADC0_AIN1 */ + J721S2_WKUP_IOPAD(0x0d4, PIN_INPUT, 0) /* (M24) MCU_ADC0_AIN2 */ + J721S2_WKUP_IOPAD(0x0d8, PIN_INPUT, 0) /* (L24) MCU_ADC0_AIN3 */ + J721S2_WKUP_IOPAD(0x0dc, PIN_INPUT, 0) /* (L27) MCU_ADC0_AIN4 */ + J721S2_WKUP_IOPAD(0x0e0, PIN_INPUT, 0) /* (K24) MCU_ADC0_AIN5 */ + J721S2_WKUP_IOPAD(0x0e4, PIN_INPUT, 0) /* (M27) MCU_ADC0_AIN6 */ + J721S2_WKUP_IOPAD(0x0e8, PIN_INPUT, 0) /* (M26) MCU_ADC0_AIN7 */ >; }; mcu_adc1_pins_default: mcu-adc1-pins-default { pinctrl-single,pins = < - J721S2_WKUP_IOPAD(0x154, PIN_INPUT, 0) /* (P25) MCU_ADC1_AIN0 */ - J721S2_WKUP_IOPAD(0x158, PIN_INPUT, 0) /* (R25) MCU_ADC1_AIN1 */ - J721S2_WKUP_IOPAD(0x15c, PIN_INPUT, 0) /* (P28) MCU_ADC1_AIN2 */ - J721S2_WKUP_IOPAD(0x160, PIN_INPUT, 0) /* (P27) MCU_ADC1_AIN3 */ - J721S2_WKUP_IOPAD(0x164, PIN_INPUT, 0) /* (N25) MCU_ADC1_AIN4 */ - J721S2_WKUP_IOPAD(0x168, PIN_INPUT, 0) /* (P26) MCU_ADC1_AIN5 */ - J721S2_WKUP_IOPAD(0x16c, PIN_INPUT, 0) /* (N26) MCU_ADC1_AIN6 */ - J721S2_WKUP_IOPAD(0x170, PIN_INPUT, 0) /* (N27) MCU_ADC1_AIN7 */ + J721S2_WKUP_IOPAD(0x0ec, PIN_INPUT, 0) /* (P25) MCU_ADC1_AIN0 */ + J721S2_WKUP_IOPAD(0x0f0, PIN_INPUT, 0) /* (R25) MCU_ADC1_AIN1 */ + J721S2_WKUP_IOPAD(0x0f4, PIN_INPUT, 0) /* (P28) MCU_ADC1_AIN2 */ + J721S2_WKUP_IOPAD(0x0f8, PIN_INPUT, 0) /* (P27) MCU_ADC1_AIN3 */ + J721S2_WKUP_IOPAD(0x0fc, PIN_INPUT, 0) /* (N25) MCU_ADC1_AIN4 */ + J721S2_WKUP_IOPAD(0x100, PIN_INPUT, 0) /* (P26) MCU_ADC1_AIN5 */ + J721S2_WKUP_IOPAD(0x104, PIN_INPUT, 0) /* (N26) MCU_ADC1_AIN6 */ + J721S2_WKUP_IOPAD(0x108, PIN_INPUT, 0) /* (N27) MCU_ADC1_AIN7 */ >; }; diff --git a/arch/arm64/boot/dts/ti/k3-j721s2-mcu-wakeup.dtsi b/arch/arm64/boot/dts/ti/k3-j721s2-mcu-wakeup.dtsi index 5734c67b6763..e7dd947a1814 100644 --- a/arch/arm64/boot/dts/ti/k3-j721s2-mcu-wakeup.dtsi +++ b/arch/arm64/boot/dts/ti/k3-j721s2-mcu-wakeup.dtsi @@ -65,7 +65,34 @@ wkup_pmx0: pinctrl@4301c000 { compatible = "pinctrl-single"; /* Proxy 0 addressing */ - reg = <0x00 0x4301c000 0x00 0x178>; + reg = <0x00 0x4301c000 0x00 0x034>; + #pinctrl-cells = <1>; + pinctrl-single,register-width = <32>; + pinctrl-single,function-mask = <0xffffffff>; + }; + + wkup_pmx1: pinctrl@4301c038 { + compatible = "pinctrl-single"; + /* Proxy 0 addressing */ + reg = <0x00 0x4301c038 0x00 0x02C>; + #pinctrl-cells = <1>; + pinctrl-single,register-width = <32>; + pinctrl-single,function-mask = <0xffffffff>; + }; + + wkup_pmx2: pinctrl@4301c068 { + compatible = "pinctrl-single"; + /* Proxy 0 addressing */ + reg = <0x00 0x4301c068 0x00 0x120>; + #pinctrl-cells = <1>; + pinctrl-single,register-width = <32>; + pinctrl-single,function-mask = <0xffffffff>; + }; + + wkup_pmx3: pinctrl@4301c190 { + compatible = "pinctrl-single"; + /* Proxy 0 addressing */ + reg = <0x00 0x4301c190 0x00 0x004>; #pinctrl-cells = <1>; pinctrl-single,register-width = <32>; pinctrl-single,function-mask = <0xffffffff>; -- cgit From 92fee724058d5272f1b1be7805fe3cdf0f561c8f Mon Sep 17 00:00:00 2001 From: Sinthu Raja Date: Fri, 2 Jun 2023 10:35:50 -0500 Subject: arm64: dts: ti: k3-am68-sk-base-board: Add pinmux for RPi Header Add pinmux required to bring out the i2c and gpios on 40-pin RPi expansion header on the AM68 SK board. Signed-off-by: Sinthu Raja Signed-off-by: Nishanth Menon Reviewed-by: Udit Kumar Link: https://lore.kernel.org/r/20230602153554.1571128-3-nm@ti.com Signed-off-by: Vignesh Raghavendra --- arch/arm64/boot/dts/ti/k3-am68-sk-base-board.dts | 77 +++++++++++++++++++++++- 1 file changed, 76 insertions(+), 1 deletion(-) diff --git a/arch/arm64/boot/dts/ti/k3-am68-sk-base-board.dts b/arch/arm64/boot/dts/ti/k3-am68-sk-base-board.dts index 37b598e98f8b..014ff13d1032 100644 --- a/arch/arm64/boot/dts/ti/k3-am68-sk-base-board.dts +++ b/arch/arm64/boot/dts/ti/k3-am68-sk-base-board.dts @@ -173,6 +173,32 @@ J721S2_IOPAD(0x09c, PIN_INPUT, 0) /* (T24) MCASP0_AXR11.MCAN7_TX */ >; }; + + main_i2c4_pins_default: main-i2c4-pins-default { + pinctrl-single,pins = < + J721S2_IOPAD(0x010, PIN_INPUT_PULLUP, 8) /* (AF28) MCAN13_RX.I2C4_SDA */ + J721S2_IOPAD(0x014, PIN_INPUT_PULLUP, 8) /* (AD25) MCAN14_TX.I2C4_SCL */ + >; + }; + + rpi_header_gpio0_pins_default: rpi-header-gpio0-pins-default { + pinctrl-single,pins = < + J721S2_IOPAD(0x0a8, PIN_INPUT, 7) /* (U24) MCASP0_AXR14.GPIO0_42 */ + J721S2_IOPAD(0x090, PIN_INPUT, 7) /* (W24) MCASP0_AXR8.GPIO0_36 */ + J721S2_IOPAD(0x0bc, PIN_INPUT, 7) /* (V28) MCASP1_AFSX.GPIO0_47 */ + J721S2_IOPAD(0x06c, PIN_INPUT, 7) /* (V26) MCAN1_TX.GPIO0_27 */ + J721S2_IOPAD(0x004, PIN_INPUT, 7) /* (W25) MCAN12_TX.GPIO0_1 */ + J721S2_IOPAD(0x008, PIN_INPUT, 7) /* (AC24) MCAN12_RX.GPIO0_2 */ + J721S2_IOPAD(0x0b8, PIN_INPUT, 7) /* (AA24) MCASP1_ACLKX.GPIO0_46 */ + J721S2_IOPAD(0x00c, PIN_INPUT, 7) /* (AE28) MCAN13_TX.GPIO0_3 */ + J721S2_IOPAD(0x034, PIN_INPUT, 7) /* (AD24) PMIC_WAKE0.GPIO0_13 */ + J721S2_IOPAD(0x0a4, PIN_INPUT, 7) /* (T23) MCASP0_AXR13.GPIO0_41 */ + J721S2_IOPAD(0x0c0, PIN_INPUT, 7) /* (T28) MCASP1_AXR0.GPIO0_48 */ + J721S2_IOPAD(0x0b4, PIN_INPUT, 7) /* (U25) MCASP1_AXR4.GPIO0_45 */ + J721S2_IOPAD(0x0cc, PIN_INPUT, 7) /* (AE27) SPI0_CS0.GPIO0_51 */ + J721S2_IOPAD(0x08c, PIN_INPUT, 7) /* (T25) MCASP0_AXR7.GPIO0_35 */ + >; + }; }; &wkup_pmx2 { @@ -214,12 +240,46 @@ >; }; + mcu_i2c0_pins_default: mcu-i2c0-pins-default { + pinctrl-single,pins = < + J721S2_WKUP_IOPAD(0x0a0, PIN_INPUT, 0) /* (G24) MCU_I2C0_SCL */ + J721S2_WKUP_IOPAD(0x0a4, PIN_INPUT, 0) /* (J25) MCU_I2C0_SDA */ + >; + }; + mcu_i2c1_pins_default: mcu-i2c1-pins-default { pinctrl-single,pins = < J721S2_WKUP_IOPAD(0x078, PIN_INPUT, 0) /* (F24) WKUP_GPIO0_8.MCU_I2C1_SCL */ J721S2_WKUP_IOPAD(0x07c, PIN_INPUT, 0) /* (H26) WKUP_GPIO0_9.MCU_I2C1_SDA */ >; }; + + mcu_rpi_header_gpio0_pins0_default: mcu-rpi-header-gpio0-pins0-default { + pinctrl-single,pins = < + J721S2_WKUP_IOPAD(0x118, PIN_INPUT, 7) /* (G25) WKUP_GPIO0_66 */ + J721S2_WKUP_IOPAD(0x05C, PIN_INPUT, 7) /* (E24) MCU_SPI1_D0.WKUP_GPIO0_1 */ + J721S2_WKUP_IOPAD(0x060, PIN_INPUT, 7) /* (C28) MCU_SPI1_D1.WKUP_GPIO0_2 */ + J721S2_WKUP_IOPAD(0x058, PIN_INPUT, 7) /* (D26) MCU_SPI1_CLK.WKUP_GPIO0_0 */ + J721S2_WKUP_IOPAD(0x094, PIN_INPUT, 7) /* (D25) MCU_SPI1_CS2.WKUP_GPIO0_15*/ + J721S2_WKUP_IOPAD(0x0B8, PIN_INPUT, 7) /* (G27) WKUP_GPIO0_56 */ + J721S2_WKUP_IOPAD(0x114, PIN_INPUT, 7) /* (J26) WKUP_GPIO0_57 */ + J721S2_WKUP_IOPAD(0x11C, PIN_INPUT, 7) /* (J27) WKUP_GPIO0_67 */ + J721S2_WKUP_IOPAD(0x064, PIN_INPUT, 7) /* (C27) MCU_SPI1_CS0.WKUP_GPIO0_3 */ + >; + }; +}; + +&wkup_pmx3 { + mcu_rpi_header_gpio0_pins1_default: mcu-rpi-header-gpio0-pins1-default { + pinctrl-single,pins = < + J721S2_WKUP_IOPAD(0x000, PIN_INPUT, 7) /* (K26) WKUP_GPIO0_49 */ + >; + }; +}; + +&main_gpio0 { + pinctrl-names = "default"; + pinctrl-0 = <&rpi_header_gpio0_pins_default>; }; &main_gpio2 { @@ -235,7 +295,8 @@ }; &wkup_gpio0 { - status = "disabled"; + pinctrl-names = "default"; + pinctrl-0 = <&mcu_rpi_header_gpio0_pins0_default>, <&mcu_rpi_header_gpio0_pins1_default>; }; &wkup_gpio1 { @@ -271,6 +332,20 @@ }; }; +&main_i2c4 { + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&main_i2c4_pins_default>; + clock-frequency = <400000>; +}; + +&mcu_i2c0 { + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&mcu_i2c0_pins_default>; + clock-frequency = <400000>; +}; + &main_sdhci0 { /* Unused */ status = "disabled"; -- cgit From 4c8c2471c7b6230fc41cf839c7b2ead836e71a6c Mon Sep 17 00:00:00 2001 From: Nishanth Menon Date: Fri, 2 Jun 2023 10:35:51 -0500 Subject: arm64: dts: ti: k3-am68-sk-base-board: Add uart pinmux Define the wakeup uart pin-mux for completeness and add explicit muxing for mcu_uart0. This allows the device tree usage in bootloader and firmwares that can configure the same appropriately. Signed-off-by: Nishanth Menon Reviewed-by: Udit Kumar Link: https://lore.kernel.org/r/20230602153554.1571128-4-nm@ti.com Signed-off-by: Vignesh Raghavendra --- arch/arm64/boot/dts/ti/k3-am68-sk-base-board.dts | 26 ++++++++++++++++++++++++ 1 file changed, 26 insertions(+) diff --git a/arch/arm64/boot/dts/ti/k3-am68-sk-base-board.dts b/arch/arm64/boot/dts/ti/k3-am68-sk-base-board.dts index 014ff13d1032..979898bc5b02 100644 --- a/arch/arm64/boot/dts/ti/k3-am68-sk-base-board.dts +++ b/arch/arm64/boot/dts/ti/k3-am68-sk-base-board.dts @@ -22,6 +22,8 @@ }; aliases { + serial0 = &wkup_uart0; + serial1 = &mcu_uart0; serial2 = &main_uart8; mmc1 = &main_sdhci1; can0 = &mcu_mcan0; @@ -202,6 +204,15 @@ }; &wkup_pmx2 { + wkup_uart0_pins_default: wkup-uart0-pins-default { + pinctrl-single,pins = < + J721S2_WKUP_IOPAD(0x070, PIN_INPUT, 0) /* (E25) WKUP_GPIO0_6.WKUP_UART0_CTSn */ + J721S2_WKUP_IOPAD(0x074, PIN_OUTPUT, 0) /* (F28) WKUP_GPIO0_7.WKUP_UART0_RTSn */ + J721S2_WKUP_IOPAD(0x048, PIN_INPUT, 0) /* (D28) WKUP_UART0_RXD */ + J721S2_WKUP_IOPAD(0x04c, PIN_OUTPUT, 0) /* (D27) WKUP_UART0_TXD */ + >; + }; + mcu_cpsw_pins_default: mcu-cpsw-pins-default { pinctrl-single,pins = < J721S2_WKUP_IOPAD(0x02C, PIN_INPUT, 0) /* (B22) MCU_RGMII1_RD0 */ @@ -254,6 +265,13 @@ >; }; + mcu_uart0_pins_default: mcu-uart0-pins-default { + pinctrl-single,pins = < + J721S2_WKUP_IOPAD(0x08c, PIN_INPUT, 0) /* (C24) WKUP_GPIO0_13.MCU_UART0_RXD */ + J721S2_WKUP_IOPAD(0x088, PIN_OUTPUT, 0) /* (C25) WKUP_GPIO0_12.MCU_UART0_TXD */ + >; + }; + mcu_rpi_header_gpio0_pins0_default: mcu-rpi-header-gpio0-pins0-default { pinctrl-single,pins = < J721S2_WKUP_IOPAD(0x118, PIN_INPUT, 7) /* (G25) WKUP_GPIO0_66 */ @@ -305,6 +323,14 @@ &wkup_uart0 { status = "reserved"; + pinctrl-names = "default"; + pinctrl-0 = <&wkup_uart0_pins_default>; +}; + +&mcu_uart0 { + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&mcu_uart0_pins_default>; }; &main_uart8 { -- cgit From 7d9b3820d756584939ed6d5e4c010aa5927edcc8 Mon Sep 17 00:00:00 2001 From: Nishanth Menon Date: Fri, 2 Jun 2023 10:35:52 -0500 Subject: arm64: dts: ti: k3-am68-sk-som: Enable wakeup_i2c0 and eeprom Enable wakeup_i2c. While at it, describe the board detection eeprom present on the board. Signed-off-by: Nishanth Menon Reviewed-by: Sinthu Raja Reviewed-by: Udit Kumar Link: https://lore.kernel.org/r/20230602153554.1571128-5-nm@ti.com Signed-off-by: Vignesh Raghavendra --- arch/arm64/boot/dts/ti/k3-am68-sk-som.dtsi | 22 ++++++++++++++++++++++ 1 file changed, 22 insertions(+) diff --git a/arch/arm64/boot/dts/ti/k3-am68-sk-som.dtsi b/arch/arm64/boot/dts/ti/k3-am68-sk-som.dtsi index e92431250729..e2c80fff7478 100644 --- a/arch/arm64/boot/dts/ti/k3-am68-sk-som.dtsi +++ b/arch/arm64/boot/dts/ti/k3-am68-sk-som.dtsi @@ -27,3 +27,25 @@ }; }; }; + +&wkup_pmx2 { + wkup_i2c0_pins_default: wkup-i2c0-pins-default { + pinctrl-single,pins = < + J721S2_WKUP_IOPAD(0x098, PIN_INPUT, 0) /* (H24) WKUP_I2C0_SCL */ + J721S2_WKUP_IOPAD(0x09c, PIN_INPUT, 0) /* (H27) WKUP_I2C0_SDA */ + >; + }; +}; + +&wkup_i2c0 { + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&wkup_i2c0_pins_default>; + clock-frequency = <400000>; + + eeprom@51 { + /* AT24C512C-MAHM-T */ + compatible = "atmel,24c512"; + reg = <0x51>; + }; +}; -- cgit From f5e9ee0b354ac5a02871959c4dad80acfc0fda6b Mon Sep 17 00:00:00 2001 From: Nishanth Menon Date: Fri, 2 Jun 2023 10:35:53 -0500 Subject: arm64: dts: ti: k3-j721s2-common-proc-board: Add uart pinmux Define the wakeup uart pin-mux for completeness and add explicit muxing for mcu_uart0. This allows the device tree usage in bootloader and firmwares that can configure the same appropriately. Signed-off-by: Nishanth Menon Reviewed-by: Udit Kumar Link: https://lore.kernel.org/r/20230602153554.1571128-6-nm@ti.com Signed-off-by: Vignesh Raghavendra --- .../boot/dts/ti/k3-j721s2-common-proc-board.dts | 23 +++++++++++++++++++++- 1 file changed, 22 insertions(+), 1 deletion(-) diff --git a/arch/arm64/boot/dts/ti/k3-j721s2-common-proc-board.dts b/arch/arm64/boot/dts/ti/k3-j721s2-common-proc-board.dts index aef62ac9b689..e7136ddb9178 100644 --- a/arch/arm64/boot/dts/ti/k3-j721s2-common-proc-board.dts +++ b/arch/arm64/boot/dts/ti/k3-j721s2-common-proc-board.dts @@ -155,6 +155,24 @@ }; &wkup_pmx2 { + wkup_uart0_pins_default: wkup-uart0-pins-default { + pinctrl-single,pins = < + J721S2_WKUP_IOPAD(0x070, PIN_INPUT, 0) /* (E25) WKUP_GPIO0_6.WKUP_UART0_CTSn */ + J721S2_WKUP_IOPAD(0x074, PIN_OUTPUT, 0) /* (F28) WKUP_GPIO0_7.WKUP_UART0_RTSn */ + J721S2_WKUP_IOPAD(0x048, PIN_INPUT, 0) /* (D28) WKUP_UART0_RXD */ + J721S2_WKUP_IOPAD(0x04c, PIN_OUTPUT, 0) /* (D27) WKUP_UART0_TXD */ + >; + }; + + mcu_uart0_pins_default: mcu-uart0-pins-default { + pinctrl-single,pins = < + J721S2_WKUP_IOPAD(0x090, PIN_INPUT, 0) /* (B24) WKUP_GPIO0_14.MCU_UART0_CTSn */ + J721S2_WKUP_IOPAD(0x094, PIN_OUTPUT, 0) /* (D25) WKUP_GPIO0_15.MCU_UART0_RTSn */ + J721S2_WKUP_IOPAD(0x08c, PIN_INPUT, 0) /* (C24) WKUP_GPIO0_13.MCU_UART0_RXD */ + J721S2_WKUP_IOPAD(0x088, PIN_OUTPUT, 0) /* (C25) WKUP_GPIO0_12.MCU_UART0_TXD */ + >; + }; + mcu_cpsw_pins_default: mcu-cpsw-pins-default { pinctrl-single,pins = < J721S2_WKUP_IOPAD(0x02c, PIN_INPUT, 0) /* (B22) MCU_RGMII1_RD0 */ @@ -265,11 +283,14 @@ &wkup_uart0 { status = "reserved"; + pinctrl-names = "default"; + pinctrl-0 = <&wkup_uart0_pins_default>; }; &mcu_uart0 { status = "okay"; - /* Default pinmux */ + pinctrl-names = "default"; + pinctrl-0 = <&mcu_uart0_pins_default>; }; &main_uart8 { -- cgit From 9d0350e8a46cae9c77abef1c8193b01a39e64f71 Mon Sep 17 00:00:00 2001 From: Nishanth Menon Date: Fri, 2 Jun 2023 10:35:54 -0500 Subject: arm64: dts: ti: k3-j721s2-som-p0: Enable wakeup_i2c0 and eeprom Enable wakeup_i2c and use un-used pinmux. While at it, describe the board detection eeprom present on the board. Signed-off-by: Nishanth Menon Reviewed-by: Udit Kumar Link: https://lore.kernel.org/r/20230602153554.1571128-7-nm@ti.com Signed-off-by: Vignesh Raghavendra --- arch/arm64/boot/dts/ti/k3-j721s2-som-p0.dtsi | 22 ++++++++++++++++++++++ 1 file changed, 22 insertions(+) diff --git a/arch/arm64/boot/dts/ti/k3-j721s2-som-p0.dtsi b/arch/arm64/boot/dts/ti/k3-j721s2-som-p0.dtsi index d473d79c2757..c1a6c36cde1d 100644 --- a/arch/arm64/boot/dts/ti/k3-j721s2-som-p0.dtsi +++ b/arch/arm64/boot/dts/ti/k3-j721s2-som-p0.dtsi @@ -61,6 +61,15 @@ }; }; +&wkup_pmx2 { + wkup_i2c0_pins_default: wkup-i2c0-pins-default { + pinctrl-single,pins = < + J721S2_WKUP_IOPAD(0x98, PIN_INPUT, 0) /* (H24) WKUP_I2C0_SCL */ + J721S2_WKUP_IOPAD(0x9c, PIN_INPUT, 0) /* (H27) WKUP_I2C0_SDA */ + >; + }; +}; + &main_pmx0 { main_i2c0_pins_default: main-i2c0-pins-default { pinctrl-single,pins = < @@ -77,6 +86,19 @@ }; }; +&wkup_i2c0 { + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&wkup_i2c0_pins_default>; + clock-frequency = <400000>; + + eeprom@50 { + /* CAV24C256WE-GT3 */ + compatible = "atmel,24c256"; + reg = <0x50>; + }; +}; + &main_i2c0 { status = "okay"; pinctrl-names = "default"; -- cgit From 444f312a73f789bb9f10bbb423f7ae6c3aa76198 Mon Sep 17 00:00:00 2001 From: Neha Malcom Francis Date: Thu, 4 May 2023 13:35:24 +0530 Subject: dt-bindings: misc: esm: Add ESM support for TI K3 devices Document the binding for TI K3 ESM (Error Signaling Module) block. Signed-off-by: Neha Malcom Francis Reviewed-by: Krzysztof Kozlowski Link: https://lore.kernel.org/r/20230504080526.133149-2-n-francis@ti.com Signed-off-by: Vignesh Raghavendra --- .../devicetree/bindings/misc/ti,j721e-esm.yaml | 53 ++++++++++++++++++++++ 1 file changed, 53 insertions(+) create mode 100644 Documentation/devicetree/bindings/misc/ti,j721e-esm.yaml diff --git a/Documentation/devicetree/bindings/misc/ti,j721e-esm.yaml b/Documentation/devicetree/bindings/misc/ti,j721e-esm.yaml new file mode 100644 index 000000000000..0c9a8444844c --- /dev/null +++ b/Documentation/devicetree/bindings/misc/ti,j721e-esm.yaml @@ -0,0 +1,53 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +# Copyright (C) 2022 Texas Instruments Incorporated +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/misc/ti,j721e-esm.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Texas Instruments K3 ESM + +maintainers: + - Neha Malcom Francis + +description: + The ESM (Error Signaling Module) is an IP block on TI K3 devices + that allows handling of safety events somewhat similar to what interrupt + controller would do. The safety signals have their separate paths within + the SoC, and they are handled by the ESM, which routes them to the proper + destination, which can be system reset, interrupt controller, etc. In the + simplest configuration the signals are just routed to reset the SoC. + +properties: + compatible: + const: ti,j721e-esm + + reg: + maxItems: 1 + + ti,esm-pins: + $ref: /schemas/types.yaml#/definitions/uint32-array + description: + integer array of ESM interrupt pins to route to external event pin + which can be used to reset the SoC. + minItems: 1 + maxItems: 255 + +required: + - compatible + - reg + - ti,esm-pins + +additionalProperties: false + +examples: + - | + bus { + #address-cells = <2>; + #size-cells = <2>; + esm@700000 { + compatible = "ti,j721e-esm"; + reg = <0x0 0x700000 0x0 0x1000>; + ti,esm-pins = <344>, <345>; + }; + }; -- cgit From 19bfd51845d551c6f4e39969c13c6b8285b94d1c Mon Sep 17 00:00:00 2001 From: Neha Malcom Francis Date: Thu, 4 May 2023 13:35:25 +0530 Subject: arm64: dts: ti: k3-j721e: Add ESM support Add address entry mapping ESM on J721E. Signed-off-by: Neha Malcom Francis Link: https://lore.kernel.org/r/20230504080526.133149-3-n-francis@ti.com Signed-off-by: Vignesh Raghavendra --- arch/arm64/boot/dts/ti/k3-j721e-main.dtsi | 6 ++++++ arch/arm64/boot/dts/ti/k3-j721e.dtsi | 1 + 2 files changed, 7 insertions(+) diff --git a/arch/arm64/boot/dts/ti/k3-j721e-main.dtsi b/arch/arm64/boot/dts/ti/k3-j721e-main.dtsi index a40d34f43abc..2ded1ee1a854 100644 --- a/arch/arm64/boot/dts/ti/k3-j721e-main.dtsi +++ b/arch/arm64/boot/dts/ti/k3-j721e-main.dtsi @@ -2716,4 +2716,10 @@ clocks = <&k3_clks 273 1>; status = "disabled"; }; + + main_esm: esm@700000 { + compatible = "ti,j721e-esm"; + reg = <0x0 0x700000 0x0 0x1000>; + ti,esm-pins = <344>, <345>; + }; }; diff --git a/arch/arm64/boot/dts/ti/k3-j721e.dtsi b/arch/arm64/boot/dts/ti/k3-j721e.dtsi index 95f67e1d0c01..a200810df54a 100644 --- a/arch/arm64/boot/dts/ti/k3-j721e.dtsi +++ b/arch/arm64/boot/dts/ti/k3-j721e.dtsi @@ -113,6 +113,7 @@ #size-cells = <2>; ranges = <0x00 0x00100000 0x00 0x00100000 0x00 0x00020000>, /* ctrl mmr */ <0x00 0x00600000 0x00 0x00600000 0x00 0x00031100>, /* GPIO */ + <0x00 0x00700000 0x00 0x00700000 0x00 0x00001000>, /* ESM */ <0x00 0x00900000 0x00 0x00900000 0x00 0x00012000>, /* serdes */ <0x00 0x00a40000 0x00 0x00a40000 0x00 0x00000800>, /* timesync router */ <0x00 0x06000000 0x00 0x06000000 0x00 0x00400000>, /* USBSS0 */ -- cgit From e3d1f2768853f375b87a1c6fc00501165ddae49d Mon Sep 17 00:00:00 2001 From: Neha Malcom Francis Date: Thu, 4 May 2023 13:35:26 +0530 Subject: arm64: dts: ti: k3-j7200: Add ESM support Add address entry mapping ESM on J7200. Signed-off-by: Neha Malcom Francis Link: https://lore.kernel.org/r/20230504080526.133149-4-n-francis@ti.com Signed-off-by: Vignesh Raghavendra --- arch/arm64/boot/dts/ti/k3-j7200-main.dtsi | 6 ++++++ arch/arm64/boot/dts/ti/k3-j7200.dtsi | 1 + 2 files changed, 7 insertions(+) diff --git a/arch/arm64/boot/dts/ti/k3-j7200-main.dtsi b/arch/arm64/boot/dts/ti/k3-j7200-main.dtsi index a9b3bf8a5c6a..ac62bbc1660d 100644 --- a/arch/arm64/boot/dts/ti/k3-j7200-main.dtsi +++ b/arch/arm64/boot/dts/ti/k3-j7200-main.dtsi @@ -1268,4 +1268,10 @@ ti,loczrama = <1>; }; }; + + main_esm: esm@700000 { + compatible = "ti,j721e-esm"; + reg = <0x0 0x700000 0x0 0x1000>; + ti,esm-pins = <656>, <657>; + }; }; diff --git a/arch/arm64/boot/dts/ti/k3-j7200.dtsi b/arch/arm64/boot/dts/ti/k3-j7200.dtsi index 3b3a1af7d60d..ef73e6d7e858 100644 --- a/arch/arm64/boot/dts/ti/k3-j7200.dtsi +++ b/arch/arm64/boot/dts/ti/k3-j7200.dtsi @@ -112,6 +112,7 @@ #size-cells = <2>; ranges = <0x00 0x00100000 0x00 0x00100000 0x00 0x00020000>, /* ctrl mmr */ <0x00 0x00600000 0x00 0x00600000 0x00 0x00031100>, /* GPIO */ + <0x00 0x00700000 0x00 0x00700000 0x00 0x00001000>, /* ESM */ <0x00 0x00a40000 0x00 0x00a40000 0x00 0x00000800>, /* timesync router */ <0x00 0x01000000 0x00 0x01000000 0x00 0x0d000000>, /* Most peripherals */ <0x00 0x30000000 0x00 0x30000000 0x00 0x0c400000>, /* MAIN NAVSS */ -- cgit From a58eedd1d195f17418c327482a79de5b84bc5aa8 Mon Sep 17 00:00:00 2001 From: Nishanth Menon Date: Tue, 30 May 2023 13:53:34 -0500 Subject: arm64: dts: ti: k3-am62: Add ESM support Add Error Signaling Module (ESM) instances in MCU and MAIN domains. Signed-off-by: Nishanth Menon Link: https://lore.kernel.org/r/20230530185335.79942-2-nm@ti.com Signed-off-by: Vignesh Raghavendra --- arch/arm64/boot/dts/ti/k3-am62-main.dtsi | 6 ++++++ arch/arm64/boot/dts/ti/k3-am62-mcu.dtsi | 6 ++++++ 2 files changed, 12 insertions(+) diff --git a/arch/arm64/boot/dts/ti/k3-am62-main.dtsi b/arch/arm64/boot/dts/ti/k3-am62-main.dtsi index bf3e054c72ce..2488e3a537fe 100644 --- a/arch/arm64/boot/dts/ti/k3-am62-main.dtsi +++ b/arch/arm64/boot/dts/ti/k3-am62-main.dtsi @@ -207,6 +207,12 @@ pinctrl-single,function-mask = <0xffffffff>; }; + main_esm: esm@420000 { + compatible = "ti,j721e-esm"; + reg = <0x00 0x420000 0x00 0x1000>; + ti,esm-pins = <160>, <161>, <162>, <163>, <177>, <178>; + }; + main_timer0: timer@2400000 { compatible = "ti,am654-timer"; reg = <0x00 0x2400000 0x00 0x400>; diff --git a/arch/arm64/boot/dts/ti/k3-am62-mcu.dtsi b/arch/arm64/boot/dts/ti/k3-am62-mcu.dtsi index 076601a41e84..19fc38157d94 100644 --- a/arch/arm64/boot/dts/ti/k3-am62-mcu.dtsi +++ b/arch/arm64/boot/dts/ti/k3-am62-mcu.dtsi @@ -14,6 +14,12 @@ pinctrl-single,function-mask = <0xffffffff>; }; + mcu_esm: esm@4100000 { + compatible = "ti,j721e-esm"; + reg = <0x00 0x4100000 0x00 0x1000>; + ti,esm-pins = <0>, <1>, <2>, <85>; + }; + /* * The MCU domain timer interrupts are routed only to the ESM module, * and not currently available for Linux. The MCU domain timers are -- cgit From f049b541b81acd88133c2c2247d4fae6c33f1b99 Mon Sep 17 00:00:00 2001 From: Nishanth Menon Date: Tue, 30 May 2023 13:53:35 -0500 Subject: arm64: dts: ti: k3-am64: Add ESM support Add Error Signaling Module (ESM) instances in MCU and MAIN domains. Signed-off-by: Nishanth Menon Link: https://lore.kernel.org/r/20230530185335.79942-3-nm@ti.com Signed-off-by: Vignesh Raghavendra --- arch/arm64/boot/dts/ti/k3-am64-main.dtsi | 6 ++++++ arch/arm64/boot/dts/ti/k3-am64-mcu.dtsi | 6 ++++++ 2 files changed, 12 insertions(+) diff --git a/arch/arm64/boot/dts/ti/k3-am64-main.dtsi b/arch/arm64/boot/dts/ti/k3-am64-main.dtsi index 71081970edd8..1664d9f0241c 100644 --- a/arch/arm64/boot/dts/ti/k3-am64-main.dtsi +++ b/arch/arm64/boot/dts/ti/k3-am64-main.dtsi @@ -372,6 +372,12 @@ ti,timer-pwm; }; + main_esm: esm@420000 { + compatible = "ti,j721e-esm"; + reg = <0x00 0x420000 0x00 0x1000>; + ti,esm-pins = <160>, <161>; + }; + main_uart0: serial@2800000 { compatible = "ti,am64-uart", "ti,am654-uart"; reg = <0x00 0x02800000 0x00 0x100>; diff --git a/arch/arm64/boot/dts/ti/k3-am64-mcu.dtsi b/arch/arm64/boot/dts/ti/k3-am64-mcu.dtsi index 67ad414a5eab..686d49790721 100644 --- a/arch/arm64/boot/dts/ti/k3-am64-mcu.dtsi +++ b/arch/arm64/boot/dts/ti/k3-am64-mcu.dtsi @@ -152,4 +152,10 @@ pinctrl-single,register-width = <32>; pinctrl-single,function-mask = <0xffffffff>; }; + + mcu_esm: esm@4100000 { + compatible = "ti,j721e-esm"; + reg = <0x00 0x4100000 0x00 0x1000>; + ti,esm-pins = <0>, <1>; + }; }; -- cgit From 4af0332876f945ea1784970727c231f2cfaa3b23 Mon Sep 17 00:00:00 2001 From: Nishanth Menon Date: Thu, 1 Jun 2023 13:31:47 -0500 Subject: arm64: dts: ti: k3-j721e-som-p0: Enable wakeup_i2c0 and eeprom Enable wakeup_i2c and use un-used pinmux. While at it, describe the board detection eeprom present on the board. Signed-off-by: Nishanth Menon Link: https://lore.kernel.org/r/20230601183151.1000157-6-nm@ti.com Signed-off-by: Vignesh Raghavendra --- arch/arm64/boot/dts/ti/k3-j721e-som-p0.dtsi | 13 +++++++++++++ 1 file changed, 13 insertions(+) diff --git a/arch/arm64/boot/dts/ti/k3-j721e-som-p0.dtsi b/arch/arm64/boot/dts/ti/k3-j721e-som-p0.dtsi index 643ecac9effe..8431f5f57cd2 100644 --- a/arch/arm64/boot/dts/ti/k3-j721e-som-p0.dtsi +++ b/arch/arm64/boot/dts/ti/k3-j721e-som-p0.dtsi @@ -201,6 +201,19 @@ }; }; +&wkup_i2c0 { + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&wkup_i2c0_pins_default>; + clock-frequency = <400000>; + + eeprom@50 { + /* CAV24C256WE-GT3 */ + compatible = "atmel,24c256"; + reg = <0x50>; + }; +}; + &ospi0 { pinctrl-names = "default"; pinctrl-0 = <&mcu_fss0_ospi0_pins_default>; -- cgit From 4c3cdac1955a5274a42d915e98827ba0f136c286 Mon Sep 17 00:00:00 2001 From: Nishanth Menon Date: Mon, 24 Apr 2023 12:36:21 -0500 Subject: arm64: dts: ti: k3-j7200-mcu-wakeup: Remove 0x unit address prefix from nodename unit-address should not use a 0x prefix. Signed-off-by: Nishanth Menon Link: https://lore.kernel.org/r/20230424173623.477577-2-nm@ti.com Signed-off-by: Vignesh Raghavendra --- arch/arm64/boot/dts/ti/k3-j7200-mcu-wakeup.dtsi | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/arch/arm64/boot/dts/ti/k3-j7200-mcu-wakeup.dtsi b/arch/arm64/boot/dts/ti/k3-j7200-mcu-wakeup.dtsi index e66c2495f54d..c5e4c41effd1 100644 --- a/arch/arm64/boot/dts/ti/k3-j7200-mcu-wakeup.dtsi +++ b/arch/arm64/boot/dts/ti/k3-j7200-mcu-wakeup.dtsi @@ -212,7 +212,7 @@ pinctrl-single,function-mask = <0xffffffff>; }; - wkup_pmx1: pinctrl@0x4301c038 { + wkup_pmx1: pinctrl@4301c038 { compatible = "pinctrl-single"; /* Proxy 0 addressing */ reg = <0x00 0x4301c038 0x00 0x8>; @@ -221,7 +221,7 @@ pinctrl-single,function-mask = <0xffffffff>; }; - wkup_pmx2: pinctrl@0x4301c068 { + wkup_pmx2: pinctrl@4301c068 { compatible = "pinctrl-single"; /* Proxy 0 addressing */ reg = <0x00 0x4301c068 0x00 0xec>; @@ -230,7 +230,7 @@ pinctrl-single,function-mask = <0xffffffff>; }; - wkup_pmx3: pinctrl@0x4301c174 { + wkup_pmx3: pinctrl@4301c174 { compatible = "pinctrl-single"; /* Proxy 0 addressing */ reg = <0x00 0x4301c174 0x00 0x20>; -- cgit From 94a58c5f131d7f0cf735af24574b7626aab77ab1 Mon Sep 17 00:00:00 2001 From: Wadim Egorov Date: Thu, 4 May 2023 16:01:42 +0200 Subject: dt-bindings: arm: ti: Add bindings for PHYTEC AM62x based hardware Add devicetree bindings for AM62x based phyCORE-AM62 SoM and phyBOARD-Lyra RDK. Signed-off-by: Wadim Egorov Acked-by: Krzysztof Kozlowski Reviewed-by: Tony Lindgren Link: https://lore.kernel.org/r/20230504140143.1425951-1-w.egorov@phytec.de Signed-off-by: Vignesh Raghavendra --- Documentation/devicetree/bindings/arm/ti/k3.yaml | 6 ++++++ 1 file changed, 6 insertions(+) diff --git a/Documentation/devicetree/bindings/arm/ti/k3.yaml b/Documentation/devicetree/bindings/arm/ti/k3.yaml index e1183f90bb06..254b5ec51f34 100644 --- a/Documentation/devicetree/bindings/arm/ti/k3.yaml +++ b/Documentation/devicetree/bindings/arm/ti/k3.yaml @@ -25,6 +25,12 @@ properties: - ti,am62a7-sk - const: ti,am62a7 + - description: K3 AM625 SoC PHYTEC phyBOARD-Lyra + items: + - const: phytec,am625-phyboard-lyra-rdk + - const: phytec,am62-phycore-som + - const: ti,am625 + - description: K3 AM625 SoC items: - enum: -- cgit From 3443c1c4ed61c3b9d0d211f81ebfa0b559836646 Mon Sep 17 00:00:00 2001 From: Wadim Egorov Date: Thu, 4 May 2023 16:01:43 +0200 Subject: arm64: dts: ti: Add basic support for phyBOARD-Lyra-AM625 The phyCORE-AM62x [1] is a SoM (System on Module) featuring TI's AM62x SoC. It can be used in combination with different carrier boards. This module can come with different sizes and models for DDR, eMMC, SPI NOR Flash and various SoCs from the AM62x family. A development Kit, called phyBOARD-Lyra [2] is used as a carrier board reference design around the AM62x SoM. Supported features: * Debug UART * SPI NOR Flash * eMMC * 2x Ethernet * Micro SD card * I2C EEPROM * I2C RTC * GPIO Expander * LEDs * USB For more details, see: [1] Product page SoM: https://www.phytec.com/product/phycore-am62x [2] Product page CB: https://www.phytec.com/product/phyboard-am62x Signed-off-by: Wadim Egorov Reviewed-by: Tony Lindgren Link: https://lore.kernel.org/r/20230504140143.1425951-2-w.egorov@phytec.de Signed-off-by: Vignesh Raghavendra --- arch/arm64/boot/dts/ti/Makefile | 1 + arch/arm64/boot/dts/ti/k3-am62-phycore-som.dtsi | 324 +++++++++++++++++++++ .../boot/dts/ti/k3-am625-phyboard-lyra-rdk.dts | 266 +++++++++++++++++ 3 files changed, 591 insertions(+) create mode 100644 arch/arm64/boot/dts/ti/k3-am62-phycore-som.dtsi create mode 100644 arch/arm64/boot/dts/ti/k3-am625-phyboard-lyra-rdk.dts diff --git a/arch/arm64/boot/dts/ti/Makefile b/arch/arm64/boot/dts/ti/Makefile index 47b0d257b508..acd8f97d57b6 100644 --- a/arch/arm64/boot/dts/ti/Makefile +++ b/arch/arm64/boot/dts/ti/Makefile @@ -10,6 +10,7 @@ # Boards with AM62x SoC dtb-$(CONFIG_ARCH_K3) += k3-am625-beagleplay.dtb +dtb-$(CONFIG_ARCH_K3) += k3-am625-phyboard-lyra-rdk.dtb dtb-$(CONFIG_ARCH_K3) += k3-am625-sk.dtb dtb-$(CONFIG_ARCH_K3) += k3-am62-lp-sk.dtb diff --git a/arch/arm64/boot/dts/ti/k3-am62-phycore-som.dtsi b/arch/arm64/boot/dts/ti/k3-am62-phycore-som.dtsi new file mode 100644 index 000000000000..056ffe6f6f6a --- /dev/null +++ b/arch/arm64/boot/dts/ti/k3-am62-phycore-som.dtsi @@ -0,0 +1,324 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Copyright (C) 2022 - 2023 PHYTEC Messtechnik GmbH + * Author: Wadim Egorov + * + * Product homepage: + * https://www.phytec.com/product/phycore-am62x + */ + +#include +#include +#include + +/ { + model = "PHYTEC phyCORE-AM62x"; + compatible = "phytec,am62-phycore-som", "ti,am625"; + + aliases { + ethernet0 = &cpsw_port1; + gpio0 = &main_gpio0; + gpio1 = &main_gpio1; + i2c0 = &main_i2c0; + mmc0 = &sdhci0; + rtc0 = &i2c_som_rtc; + rtc1 = &wkup_rtc0; + spi0 = &ospi0; + }; + + memory@80000000 { + device_type = "memory"; + reg = <0x00000000 0x80000000 0x00000000 0x80000000>; + }; + + reserved_memory: reserved-memory { + #address-cells = <2>; + #size-cells = <2>; + ranges; + + ramoops@9ca00000 { + compatible = "ramoops"; + reg = <0x00 0x9ca00000 0x00 0x00100000>; + record-size = <0x8000>; + console-size = <0x8000>; + ftrace-size = <0x00>; + pmsg-size = <0x8000>; + }; + + secure_tfa_ddr: tfa@9e780000 { + reg = <0x00 0x9e780000 0x00 0x80000>; + alignment = <0x1000>; + no-map; + }; + + secure_ddr: optee@9e800000 { + reg = <0x00 0x9e800000 0x00 0x01800000>; /* for OP-TEE */ + alignment = <0x1000>; + no-map; + }; + + wkup_r5fss0_core0_dma_memory_region: r5f-dma-memory@9db00000 { + compatible = "shared-dma-pool"; + reg = <0x00 0x9db00000 0x00 0x00c00000>; + no-map; + }; + }; + + vcc_5v0_som: regulator-vcc-5v0-som { + compatible = "regulator-fixed"; + regulator-name = "VCC_5V0_SOM"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + regulator-always-on; + regulator-boot-on; + }; + + vdd_1v8: regulator-vdd-1v8 { + compatible = "regulator-fixed"; + regulator-name = "VDD_1V8"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + vin-supply = <&vcc_5v0_som>; + regulator-always-on; + regulator-boot-on; + }; + + leds { + compatible = "gpio-leds"; + pinctrl-names = "default"; + pinctrl-0 = <&leds_pins_default>; + + led-0 { + color = ; + gpios = <&main_gpio0 13 GPIO_ACTIVE_HIGH>; + linux,default-trigger = "heartbeat"; + function = LED_FUNCTION_HEARTBEAT; + }; + }; +}; + +&main_pmx0 { + leds_pins_default: leds-pins-default { + pinctrl-single,pins = < + AM62X_IOPAD(0x034, PIN_OUTPUT, 7) /* (H21) OSPI0_CSN2.GPIO0_13 */ + >; + }; + + main_i2c0_pins_default: main-i2c0-pins-default { + pinctrl-single,pins = < + AM62X_IOPAD(0x1e0, PIN_INPUT_PULLUP, 0) /* (B16) I2C0_SCL */ + AM62X_IOPAD(0x1e4, PIN_INPUT_PULLUP, 0) /* (A16) I2C0_SDA */ + >; + }; + + main_mdio1_pins_default: main-mdio1-pins-default { + pinctrl-single,pins = < + AM62X_IOPAD(0x160, PIN_OUTPUT, 0) /* (AD24) MDIO0_MDC */ + AM62X_IOPAD(0x15c, PIN_INPUT, 0) /* (AB22) MDIO0_MDIO */ + >; + }; + + main_mmc0_pins_default: main-mmc0-pins-default { + pinctrl-single,pins = < + AM62X_IOPAD(0x220, PIN_INPUT_PULLUP, 0) /* (Y3) MMC0_CMD */ + AM62X_IOPAD(0x218, PIN_INPUT_PULLDOWN, 0) /* (AB1) MMC0_CLK */ + AM62X_IOPAD(0x214, PIN_INPUT_PULLUP, 0) /* (AA2) MMC0_DAT0 */ + AM62X_IOPAD(0x210, PIN_INPUT_PULLUP, 0) /* (AA1) MMC0_DAT1 */ + AM62X_IOPAD(0x20c, PIN_INPUT_PULLUP, 0) /* (AA3) MMC0_DAT2 */ + AM62X_IOPAD(0x208, PIN_INPUT_PULLUP, 0) /* (Y4) MMC0_DAT3 */ + AM62X_IOPAD(0x204, PIN_INPUT_PULLUP, 0) /* (AB2) MMC0_DAT4 */ + AM62X_IOPAD(0x200, PIN_INPUT_PULLUP, 0) /* (AC1) MMC0_DAT5 */ + AM62X_IOPAD(0x1fc, PIN_INPUT_PULLUP, 0) /* (AD2) MMC0_DAT6 */ + AM62X_IOPAD(0x1f8, PIN_INPUT_PULLUP, 0) /* (AC2) MMC0_DAT7 */ + >; + }; + + main_rgmii1_pins_default: main-rgmii1-pins-default { + pinctrl-single,pins = < + AM62X_IOPAD(0x14c, PIN_INPUT, 0) /* (AB17) RGMII1_RD0 */ + AM62X_IOPAD(0x150, PIN_INPUT, 0) /* (AC17) RGMII1_RD1 */ + AM62X_IOPAD(0x154, PIN_INPUT, 0) /* (AB16) RGMII1_RD2 */ + AM62X_IOPAD(0x158, PIN_INPUT, 0) /* (AA15) RGMII1_RD3 */ + AM62X_IOPAD(0x148, PIN_INPUT, 0) /* (AD17) RGMII1_RXC */ + AM62X_IOPAD(0x144, PIN_INPUT, 0) /* (AE17) RGMII1_RX_CTL */ + AM62X_IOPAD(0x134, PIN_OUTPUT, 0) /* (AE20) RGMII1_TD0 */ + AM62X_IOPAD(0x138, PIN_OUTPUT, 0) /* (AD20) RGMII1_TD1 */ + AM62X_IOPAD(0x13c, PIN_OUTPUT, 0) /* (AE18) RGMII1_TD2 */ + AM62X_IOPAD(0x140, PIN_OUTPUT, 0) /* (AD18) RGMII1_TD3 */ + AM62X_IOPAD(0x130, PIN_OUTPUT, 0) /* (AE19) RGMII1_TXC */ + AM62X_IOPAD(0x12c, PIN_OUTPUT, 0) /* (AD19) RGMII1_TX_CTL */ + >; + }; + + ospi0_pins_default: ospi0-pins-default { + pinctrl-single,pins = < + AM62X_IOPAD(0x000, PIN_OUTPUT, 0) /* (H24) OSPI0_CLK */ + AM62X_IOPAD(0x02c, PIN_OUTPUT, 0) /* (F23) OSPI0_CSn0 */ + AM62X_IOPAD(0x00c, PIN_INPUT, 0) /* (E25) OSPI0_D0 */ + AM62X_IOPAD(0x010, PIN_INPUT, 0) /* (G24) OSPI0_D1 */ + AM62X_IOPAD(0x014, PIN_INPUT, 0) /* (F25) OSPI0_D2 */ + AM62X_IOPAD(0x018, PIN_INPUT, 0) /* (F24) OSPI0_D3 */ + AM62X_IOPAD(0x01c, PIN_INPUT, 0) /* (J23) OSPI0_D4 */ + AM62X_IOPAD(0x020, PIN_INPUT, 0) /* (J25) OSPI0_D5 */ + AM62X_IOPAD(0x024, PIN_INPUT, 0) /* (H25) OSPI0_D6 */ + AM62X_IOPAD(0x028, PIN_INPUT, 0) /* (J22) OSPI0_D7 */ + AM62X_IOPAD(0x008, PIN_INPUT, 0) /* (J24) OSPI0_DQS */ + >; + }; + + pmic_irq_pins_default: pmic-irq-pins-default { + pinctrl-single,pins = < + AM62X_IOPAD(0x01f4, PIN_INPUT, 0) /* (D16) EXTINTn */ + >; + }; +}; + +&cpsw3g { + pinctrl-names = "default"; + pinctrl-0 = <&main_rgmii1_pins_default>; +}; + +&cpsw_port1 { + phy-mode = "rgmii-rxid"; + phy-handle = <&cpsw3g_phy1>; +}; + +&cpsw3g_mdio { + pinctrl-names = "default"; + pinctrl-0 = <&main_mdio1_pins_default>; + status = "okay"; + + cpsw3g_phy1: ethernet-phy@1 { + compatible = "ethernet-phy-id2000.a231", "ethernet-phy-ieee802.3-c22"; + reg = <1>; + ti,rx-internal-delay = ; + ti,fifo-depth = ; + }; +}; + +&main_i2c0 { + pinctrl-names = "default"; + pinctrl-0 = <&main_i2c0_pins_default>; + clock-frequency = <400000>; + status = "okay"; + + pmic@30 { + compatible = "ti,tps65219"; + reg = <0x30>; + buck1-supply = <&vcc_5v0_som>; + buck2-supply = <&vcc_5v0_som>; + buck3-supply = <&vcc_5v0_som>; + ldo1-supply = <&vdd_3v3>; + ldo2-supply = <&vdd_1v8>; + ldo3-supply = <&vcc_5v0_som>; + ldo4-supply = <&vcc_5v0_som>; + + pinctrl-names = "default"; + pinctrl-0 = <&pmic_irq_pins_default>; + interrupt-parent = <&gic500>; + interrupts = ; + interrupt-controller; + #interrupt-cells = <1>; + + ti,power-button; + system-power-controller; + + regulators { + vdd_core: buck1 { + regulator-name = "VDD_CORE"; + regulator-min-microvolt = <750000>; + regulator-max-microvolt = <750000>; + regulator-boot-on; + regulator-always-on; + }; + + vdd_3v3: buck2 { + regulator-name = "VDD_3V3"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-boot-on; + regulator-always-on; + }; + + vdd_ddr4: buck3 { + regulator-name = "VDD_DDR4"; + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1200000>; + regulator-boot-on; + regulator-always-on; + }; + + vddshv5_sdio: ldo1 { + regulator-name = "VDDSHV5_SDIO"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-allow-bypass; + regulator-boot-on; + regulator-always-on; + }; + + vddr_core: ldo2 { + regulator-name = "VDDR_CORE"; + regulator-min-microvolt = <850000>; + regulator-max-microvolt = <850000>; + regulator-boot-on; + regulator-always-on; + }; + + vdda_1v8: ldo3 { + regulator-name = "VDDA_1V8"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-boot-on; + regulator-always-on; + }; + + vdd_2v5: ldo4 { + regulator-name = "VDD_2V5"; + regulator-min-microvolt = <2500000>; + regulator-max-microvolt = <2500000>; + regulator-boot-on; + regulator-always-on; + }; + }; + }; + + eeprom@50 { + compatible = "atmel,24c32"; + pagesize = <32>; + reg = <0x50>; + }; + + i2c_som_rtc: rtc@52 { + compatible = "microcrystal,rv3028"; + reg = <0x52>; + }; +}; + +&ospi0 { + pinctrl-names = "default"; + pinctrl-0 = <&ospi0_pins_default>; + status = "okay"; + + serial_flash: flash@0 { + compatible = "jedec,spi-nor"; + reg = <0x0>; + spi-tx-bus-width = <8>; + spi-rx-bus-width = <8>; + spi-max-frequency = <25000000>; + cdns,tshsl-ns = <60>; + cdns,tsd2d-ns = <60>; + cdns,tchsh-ns = <60>; + cdns,tslch-ns = <60>; + cdns,read-delay = <0>; + }; +}; + +&sdhci0 { + pinctrl-names = "default"; + pinctrl-0 = <&main_mmc0_pins_default>; + ti,driver-strength-ohm = <50>; + disable-wp; + non-removable; + status = "okay"; +}; diff --git a/arch/arm64/boot/dts/ti/k3-am625-phyboard-lyra-rdk.dts b/arch/arm64/boot/dts/ti/k3-am625-phyboard-lyra-rdk.dts new file mode 100644 index 000000000000..3a10b21fec1b --- /dev/null +++ b/arch/arm64/boot/dts/ti/k3-am625-phyboard-lyra-rdk.dts @@ -0,0 +1,266 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Copyright (C) 2022 - 2023 PHYTEC Messtechnik GmbH + * Author: Wadim Egorov + * + * Product homepage: + * https://www.phytec.com/product/phyboard-am62x + */ + +#include +#include +#include +#include +#include "k3-am625.dtsi" +#include "k3-am62-phycore-som.dtsi" + +/ { + compatible = "phytec,am625-phyboard-lyra-rdk", + "phytec,am62-phycore-som", "ti,am625"; + model = "PHYTEC phyBOARD-Lyra AM625"; + + aliases { + serial2 = &main_uart0; + serial3 = &main_uart1; + mmc1 = &sdhci1; + usb0 = &usb0; + usb1 = &usb1; + ethernet1 = &cpsw_port2; + }; + + can_tc1: can-phy0 { + compatible = "ti,tcan1042"; + #phy-cells = <0>; + max-bitrate = <5000000>; + standby-gpios = <&gpio_exp 1 GPIO_ACTIVE_HIGH>; + }; + + keys { + compatible = "gpio-keys"; + autorepeat; + pinctrl-names = "default"; + pinctrl-0 = <&gpio_keys_pins_default>; + + key-home { + label = "home"; + linux,code = ; + gpios = <&main_gpio1 23 GPIO_ACTIVE_HIGH>; + }; + + key-menu { + label = "menu"; + linux,code = ; + gpios = <&gpio_exp 4 GPIO_ACTIVE_HIGH>; + }; + }; + + leds { + compatible = "gpio-leds"; + pinctrl-names = "default"; + pinctrl-0 = <&leds_pins_default>, <&user_leds_pins_default>; + + led-1 { + gpios = <&main_gpio0 32 GPIO_ACTIVE_HIGH>; + linux,default-trigger = "mmc0"; + }; + + led-2 { + gpios = <&gpio_exp 2 GPIO_ACTIVE_HIGH>; + linux,default-trigger = "mmc1"; + }; + }; + + vcc_3v3_mmc: regulator-vcc-3v3-mmc { + compatible = "regulator-fixed"; + regulator-name = "VCC_3V3_MMC"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + regulator-boot-on; + }; +}; + +&main_pmx0 { + gpio_keys_pins_default: gpio-keys-pins-default { + pinctrl-single,pins = < + AM62X_IOPAD(0x1d4, PIN_INPUT, 7) /* (B15) UART0_RTSn.GPIO1_23 */ + >; + }; + + gpio_exp_int_pins_default: gpio-exp-int-pins-default { + pinctrl-single,pins = < + AM62X_IOPAD(0x244, PIN_INPUT, 7) /* (C17) MMC1_SDWP.GPIO1_49 */ + >; + }; + + main_i2c1_pins_default: main-i2c1-pins-default { + pinctrl-single,pins = < + AM62X_IOPAD(0x1e8, PIN_INPUT_PULLUP, 0) /* (B17) I2C1_SCL */ + AM62X_IOPAD(0x1ec, PIN_INPUT_PULLUP, 0) /* (A17) I2C1_SDA */ + >; + }; + + main_mcan0_pins_default: main-mcan0-pins-default { + pinctrl-single,pins = < + AM62X_IOPAD(0x1dc, PIN_INPUT, 0) /* (E15) MCAN0_RX */ + AM62X_IOPAD(0x1d8, PIN_OUTPUT, 0) /* (C15) MCAN0_TX */ + >; + }; + + main_mmc1_pins_default: main-mmc1-pins-default { + pinctrl-single,pins = < + AM62X_IOPAD(0x23c, PIN_INPUT_PULLUP, 0) /* (A21) MMC1_CMD */ + AM62X_IOPAD(0x234, PIN_INPUT_PULLDOWN, 0) /* (B22) MMC1_CLK */ + AM62X_IOPAD(0x230, PIN_INPUT_PULLUP, 0) /* (A22) MMC1_DAT0 */ + AM62X_IOPAD(0x22c, PIN_INPUT_PULLUP, 0) /* (B21) MMC1_DAT1 */ + AM62X_IOPAD(0x228, PIN_INPUT_PULLUP, 0) /* (C21) MMC1_DAT2 */ + AM62X_IOPAD(0x224, PIN_INPUT_PULLUP, 0) /* (D22) MMC1_DAT3 */ + AM62X_IOPAD(0x240, PIN_INPUT_PULLUP, 0) /* (D17) MMC1_SDCD */ + >; + }; + + main_rgmii2_pins_default: main-rgmii2-pins-default { + pinctrl-single,pins = < + AM62X_IOPAD(0x184, PIN_INPUT, 0) /* (AE23) RGMII2_RD0 */ + AM62X_IOPAD(0x188, PIN_INPUT, 0) /* (AB20) RGMII2_RD1 */ + AM62X_IOPAD(0x18c, PIN_INPUT, 0) /* (AC21) RGMII2_RD2 */ + AM62X_IOPAD(0x190, PIN_INPUT, 0) /* (AE22) RGMII2_RD3 */ + AM62X_IOPAD(0x180, PIN_INPUT, 0) /* (AD23) RGMII2_RXC */ + AM62X_IOPAD(0x17c, PIN_INPUT, 0) /* (AD22) RGMII2_RX_CTL */ + AM62X_IOPAD(0x16c, PIN_OUTPUT, 0) /* (Y18) RGMII2_TD0 */ + AM62X_IOPAD(0x170, PIN_OUTPUT, 0) /* (AA18) RGMII2_TD1 */ + AM62X_IOPAD(0x174, PIN_OUTPUT, 0) /* (AD21) RGMII2_TD2 */ + AM62X_IOPAD(0x178, PIN_OUTPUT, 0) /* (AC20) RGMII2_TD3 */ + AM62X_IOPAD(0x168, PIN_OUTPUT, 0) /* (AE21) RGMII2_TXC */ + AM62X_IOPAD(0x164, PIN_OUTPUT, 0) /* (AA19) RGMII2_TX_CTL */ + >; + }; + + main_uart0_pins_default: main-uart0-pins-default { + pinctrl-single,pins = < + AM62X_IOPAD(0x1c8, PIN_INPUT, 0) /* (D14) UART0_RXD */ + AM62X_IOPAD(0x1cc, PIN_OUTPUT, 0) /* (E14) UART0_TXD */ + >; + }; + + main_uart1_pins_default: main-uart1-pins-default { + pinctrl-single,pins = < + AM62X_IOPAD(0x194, PIN_INPUT, 2) /* (B19) MCASP0_AXR3.UART1_CTSn */ + AM62X_IOPAD(0x198, PIN_OUTPUT, 2) /* (A19) MCASP0_AXR2.UART1_RTSn */ + AM62X_IOPAD(0x1ac, PIN_INPUT, 2) /* (E19) MCASP0_AFSR.UART1_RXD */ + AM62X_IOPAD(0x1b0, PIN_OUTPUT, 2) /* (A20) MCASP0_ACLKR.UART1_TXD */ + >; + }; + + main_usb1_pins_default: main-usb1-pins-default { + pinctrl-single,pins = < + AM62X_IOPAD(0x258, PIN_OUTPUT, 0) /* (F18) USB1_DRVVBUS */ + >; + }; + + user_leds_pins_default: user-leds-pins-default { + pinctrl-single,pins = < + AM62X_IOPAD(0x084, PIN_OUTPUT, 7) /* (L23) GPMC0_ADVn_ALE.GPIO0_32 */ + >; + }; +}; + +&cpsw3g { + pinctrl-names = "default"; + pinctrl-0 = <&main_rgmii1_pins_default>, <&main_rgmii2_pins_default>; +}; + +&cpsw_port2 { + phy-mode = "rgmii-rxid"; + phy-handle = <&cpsw3g_phy3>; +}; + +&cpsw3g_mdio { + cpsw3g_phy3: ethernet-phy@3 { + compatible = "ethernet-phy-id2000.a231", "ethernet-phy-ieee802.3-c22"; + reg = <3>; + ti,rx-internal-delay = ; + ti,fifo-depth = ; + }; +}; + +&main_i2c1 { + pinctrl-names = "default"; + pinctrl-0 = <&main_i2c1_pins_default>; + clock-frequency = <400000>; + status = "okay"; + + gpio_exp: gpio-expander@21 { + pinctrl-names = "default"; + pinctrl-0 = <&gpio_exp_int_pins_default>; + compatible = "nxp,pcf8574"; + reg = <0x21>; + interrupt-parent = <&main_gpio1>; + interrupts = <49 0>; + #gpio-cells = <2>; + gpio-controller; + interrupt-controller; + #interrupt-cells = <2>; + gpio-line-names = "GPIO0_HDMI_RST", "GPIO1_CAN0_nEN", + "GPIO2_LED2", "GPIO3_LVDS_GPIO", + "GPIO4_BUT2", "GPIO5_LVDS_BKLT_EN", + "GPIO6_ETH1_USER_RESET", "GPIO7_AUDIO_USER_RESET"; + }; + + eeprom@51 { + compatible = "atmel,24c02"; + pagesize = <16>; + reg = <0x51>; + }; +}; + +&main_mcan0 { + pinctrl-names = "default"; + pinctrl-0 = <&main_mcan0_pins_default>; + phys = <&can_tc1>; + status = "okay"; +}; + +&main_uart0 { + pinctrl-names = "default"; + pinctrl-0 = <&main_uart0_pins_default>; + status = "okay"; +}; + +&main_uart1 { + pinctrl-names = "default"; + pinctrl-0 = <&main_uart1_pins_default>; + /* Main UART1 may be used by TIFS firmware */ + status = "okay"; +}; + +&sdhci1 { + vmmc-supply = <&vcc_3v3_mmc>; + vqmmc-supply = <&vddshv5_sdio>; + pinctrl-names = "default"; + pinctrl-0 = <&main_mmc1_pins_default>; + ti,driver-strength-ohm = <50>; + disable-wp; + no-1-8-v; + status = "okay"; +}; + +&usbss0 { + ti,vbus-divider; + status = "okay"; +}; + +&usbss1 { + ti,vbus-divider; + status = "okay"; +}; + +&usb0 { + dr_mode = "peripheral"; +}; + +&usb1 { + dr_mode = "host"; + pinctrl-names = "default"; + pinctrl-0 = <&main_usb1_pins_default>; +}; -- cgit From cf04083c59fbd5e0172dfcdc1f3735dcce42fc28 Mon Sep 17 00:00:00 2001 From: Francesco Dolcini Date: Thu, 15 Jun 2023 11:50:54 +0200 Subject: dt-bindings: arm: ti: add toradex,verdin-am62 et al. Add toradex,verdin-am62 for Toradex Verdin AM62 SoM, its nonwifi and wifi variants and the carrier boards (Dahlia, Verdin Development Board and Yavia) they may be mated in. Link: https://developer.toradex.com/hardware/verdin-som-family/modules/verdin-am62/ Link: https://www.toradex.com/computer-on-modules/verdin-arm-family/ti-am62 Signed-off-by: Francesco Dolcini Reviewed-by: Conor Dooley Link: https://lore.kernel.org/r/20230615095058.33890-2-francesco@dolcini.it Signed-off-by: Vignesh Raghavendra --- Documentation/devicetree/bindings/arm/ti/k3.yaml | 20 ++++++++++++++++++++ 1 file changed, 20 insertions(+) diff --git a/Documentation/devicetree/bindings/arm/ti/k3.yaml b/Documentation/devicetree/bindings/arm/ti/k3.yaml index 254b5ec51f34..577eee95c893 100644 --- a/Documentation/devicetree/bindings/arm/ti/k3.yaml +++ b/Documentation/devicetree/bindings/arm/ti/k3.yaml @@ -39,6 +39,26 @@ properties: - ti,am62-lp-sk - const: ti,am625 + - description: K3 AM62x SoC Toradex Verdin Modules and Carrier Boards + items: + - enum: + - toradex,verdin-am62-nonwifi-dahlia # Verdin AM62 Module on Dahlia + - toradex,verdin-am62-nonwifi-dev # Verdin AM62 Module on Verdin Development Board + - toradex,verdin-am62-nonwifi-yavia # Verdin AM62 Module on Yavia + - const: toradex,verdin-am62-nonwifi # Verdin AM62 Module without Wi-Fi / BT + - const: toradex,verdin-am62 # Verdin AM62 Module + - const: ti,am625 + + - description: K3 AM62x SoC Toradex Verdin Modules and Carrier Boards with Wi-Fi / BT + items: + - enum: + - toradex,verdin-am62-wifi-dahlia # Verdin AM62 Wi-Fi / BT Module on Dahlia + - toradex,verdin-am62-wifi-dev # Verdin AM62 Wi-Fi / BT M. on Verdin Development B. + - toradex,verdin-am62-wifi-yavia # Verdin AM62 Wi-Fi / BT Module on Yavia + - const: toradex,verdin-am62-wifi # Verdin AM62 Wi-Fi / BT Module + - const: toradex,verdin-am62 # Verdin AM62 Module + - const: ti,am625 + - description: K3 AM642 SoC items: - enum: -- cgit From 316b80246b16bd1063e41e74ec7bae85e0813dd2 Mon Sep 17 00:00:00 2001 From: Francesco Dolcini Date: Thu, 15 Jun 2023 11:50:56 +0200 Subject: arm64: dts: ti: add verdin am62 This patch adds the device tree to support Toradex Verdin AM62 a computer on module which can be used on different carrier boards and the Toradex Verdin Development Board carrier board. The module consists of an TI AM62 family SoC (either AM623 or AM625), a TPS65219 PMIC, a Gigabit Ethernet PHY, 512MB to 2GB of LPDDR4 RAM, an eMMC, a TLA2024 ADC, an I2C EEPROM, an RX8130 RTC, and optional Parallel RGB to MIPI DSI bridge plus an optional Bluetooth/Wi-Fi module. Anything that is not self-contained on the module is disabled by default. So far there is no display nor USB role switch supported, apart of that all the other functionalities are fine. Link: https://developer.toradex.com/hardware/verdin-som-family/modules/verdin-am62/ Link: https://www.toradex.com/computer-on-modules/verdin-arm-family/ti-am62 Link: https://www.toradex.com/products/carrier-board/verdin-development-board-kit Signed-off-by: Francesco Dolcini Link: https://lore.kernel.org/r/20230615095058.33890-4-francesco@dolcini.it Signed-off-by: Vignesh Raghavendra --- arch/arm64/boot/dts/ti/Makefile | 2 + arch/arm64/boot/dts/ti/k3-am62-verdin-dev.dtsi | 190 +++ arch/arm64/boot/dts/ti/k3-am62-verdin-nonwifi.dtsi | 20 + arch/arm64/boot/dts/ti/k3-am62-verdin-wifi.dtsi | 39 + arch/arm64/boot/dts/ti/k3-am62-verdin.dtsi | 1401 ++++++++++++++++++++ .../boot/dts/ti/k3-am625-verdin-nonwifi-dev.dts | 22 + .../arm64/boot/dts/ti/k3-am625-verdin-wifi-dev.dts | 22 + 7 files changed, 1696 insertions(+) create mode 100644 arch/arm64/boot/dts/ti/k3-am62-verdin-dev.dtsi create mode 100644 arch/arm64/boot/dts/ti/k3-am62-verdin-nonwifi.dtsi create mode 100644 arch/arm64/boot/dts/ti/k3-am62-verdin-wifi.dtsi create mode 100644 arch/arm64/boot/dts/ti/k3-am62-verdin.dtsi create mode 100644 arch/arm64/boot/dts/ti/k3-am625-verdin-nonwifi-dev.dts create mode 100644 arch/arm64/boot/dts/ti/k3-am625-verdin-wifi-dev.dts diff --git a/arch/arm64/boot/dts/ti/Makefile b/arch/arm64/boot/dts/ti/Makefile index acd8f97d57b6..2b8ec3546273 100644 --- a/arch/arm64/boot/dts/ti/Makefile +++ b/arch/arm64/boot/dts/ti/Makefile @@ -12,6 +12,8 @@ dtb-$(CONFIG_ARCH_K3) += k3-am625-beagleplay.dtb dtb-$(CONFIG_ARCH_K3) += k3-am625-phyboard-lyra-rdk.dtb dtb-$(CONFIG_ARCH_K3) += k3-am625-sk.dtb +dtb-$(CONFIG_ARCH_K3) += k3-am625-verdin-nonwifi-dev.dtb +dtb-$(CONFIG_ARCH_K3) += k3-am625-verdin-wifi-dev.dtb dtb-$(CONFIG_ARCH_K3) += k3-am62-lp-sk.dtb # Boards with AM62Ax SoC diff --git a/arch/arm64/boot/dts/ti/k3-am62-verdin-dev.dtsi b/arch/arm64/boot/dts/ti/k3-am62-verdin-dev.dtsi new file mode 100644 index 000000000000..846caee7dfa4 --- /dev/null +++ b/arch/arm64/boot/dts/ti/k3-am62-verdin-dev.dtsi @@ -0,0 +1,190 @@ +// SPDX-License-Identifier: GPL-2.0-or-later OR MIT +/* + * Copyright 2023 Toradex + * + * Common dtsi for Verdin AM62 SoM on Development carrier board + * + * https://www.toradex.com/computer-on-modules/verdin-arm-family/ti-am62 + * https://www.toradex.com/products/carrier-board/verdin-development-board-kit + */ + +/* Verdin ETHs */ +&cpsw3g { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_rgmii1>, <&pinctrl_rgmii2>; + status = "okay"; +}; + +/* MDIO, shared by Verdin ETH_1 (On-module PHY) and Verdin ETH_2_RGMII */ +&cpsw3g_mdio { + status = "okay"; + + cpsw3g_phy1: ethernet-phy@7 { + compatible = "ethernet-phy-ieee802.3-c22"; + reg = <7>; + interrupt-parent = <&main_gpio0>; + interrupts = <38 IRQ_TYPE_EDGE_FALLING>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_eth2_rgmii_int>; + micrel,led-mode = <0>; + }; +}; + +/* Verdin ETH_1 (On-module PHY) */ +&cpsw_port1 { + status = "okay"; +}; + +/* Verdin ETH_2_RGMII */ +&cpsw_port2 { + phy-handle = <&cpsw3g_phy1>; + phy-mode = "rgmii-rxid"; + status = "okay"; +}; + +/* Verdin PWM_1, PWM_2 */ +&epwm0 { + status = "okay"; +}; + +/* Verdin PWM_3_DSI */ +&epwm1 { + status = "okay"; +}; + +&main_gpio0 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_ctrl_sleep_moci>, + <&pinctrl_gpio_5>, + <&pinctrl_gpio_6>, + <&pinctrl_gpio_7>, + <&pinctrl_gpio_8>; +}; + +/* Verdin I2C_1 */ +&main_i2c1 { + status = "okay"; + + /* IO Expander */ + gpio_expander_21: gpio@21 { + compatible = "nxp,pcal6416"; + reg = <0x21>; + #gpio-cells = <2>; + gpio-controller; + }; + + /* Current measurement into module VCC */ + hwmon@40 { + compatible = "ti,ina219"; + reg = <0x40>; + shunt-resistor = <10000>; + }; + + /* Temperature sensor */ + sensor@4f { + compatible = "ti,tmp75c"; + reg = <0x4f>; + }; + + /* EEPROM */ + eeprom@57 { + compatible = "st,24c02", "atmel,24c02"; + reg = <0x57>; + pagesize = <16>; + }; +}; + +/* Verdin I2C_2_DSI */ +&main_i2c2 { + status = "okay"; +}; + +/* Verdin I2C_4_CSI */ +&main_i2c3 { + status = "okay"; +}; + +/* Verdin CAN_1 */ +&main_mcan0 { + status = "okay"; +}; + +/* Verdin SPI_1 */ +&main_spi1 { + status = "okay"; +}; + +/* Verdin UART_3 */ +&main_uart0 { + status = "okay"; +}; + +/* Verdin UART_1, connector X50 through RS485 transceiver. */ +&main_uart1 { + linux,rs485-enabled-at-boot-time; + rs485-rx-during-tx; + status = "okay"; +}; + +/* Verdin I2S_1 */ +&mcasp0 { + status = "okay"; +}; + +&mcu_gpio0 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_gpio_1>, + <&pinctrl_gpio_2>, + <&pinctrl_gpio_3>, + <&pinctrl_gpio_4>; +}; + +/* Verdin I2C_3_HDMI */ +&mcu_i2c0 { + status = "okay"; +}; + +/* Verdin UART_4 */ +&mcu_uart0 { + status = "okay"; +}; + +/* Verdin QSPI_1 */ +&ospi0 { + status = "okay"; +}; + +/* Verdin SD_1 */ +&sdhci1 { + ti,driver-strength-ohm = <33>; + status = "okay"; +}; + +/* Verdin USB_1 */ +&usbss0 { + status = "okay"; +}; + +&usb0 { + status = "okay"; +}; + +/* Verdin USB_2 */ +&usbss1 { + status = "okay"; +}; + +&usb1 { + status = "okay"; +}; + +/* Verdin CTRL_WAKE1_MICO# */ +&verdin_gpio_keys { + status = "okay"; +}; + +/* Verdin UART_2 */ +&wkup_uart0 { + /* FIXME: WKUP UART0 is used by DM firmware */ + status = "reserved"; +}; diff --git a/arch/arm64/boot/dts/ti/k3-am62-verdin-nonwifi.dtsi b/arch/arm64/boot/dts/ti/k3-am62-verdin-nonwifi.dtsi new file mode 100644 index 000000000000..68d07695e1db --- /dev/null +++ b/arch/arm64/boot/dts/ti/k3-am62-verdin-nonwifi.dtsi @@ -0,0 +1,20 @@ +// SPDX-License-Identifier: GPL-2.0-or-later OR MIT +/* + * Copyright 2023 Toradex + * + * Common dtsi for Verdin AM62 SoM non-WB variant + * + * https://www.toradex.com/computer-on-modules/verdin-arm-family/ti-am62 + */ + +&sdhci2 { + pinctrl-0 = <&pinctrl_sdhci2>; + bus-width = <4>; + status = "disabled"; +}; + +&main_uart5 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart5>; + status = "disabled"; +}; diff --git a/arch/arm64/boot/dts/ti/k3-am62-verdin-wifi.dtsi b/arch/arm64/boot/dts/ti/k3-am62-verdin-wifi.dtsi new file mode 100644 index 000000000000..90ddc71bcd30 --- /dev/null +++ b/arch/arm64/boot/dts/ti/k3-am62-verdin-wifi.dtsi @@ -0,0 +1,39 @@ +// SPDX-License-Identifier: GPL-2.0-or-later OR MIT +/* + * Copyright 2023 Toradex + * + * Common dtsi for Verdin AM62 SoM WB variant + * + * https://www.toradex.com/computer-on-modules/verdin-arm-family/ti-am62 + */ + +/ { + wifi_pwrseq: wifi-pwrseq { + compatible = "mmc-pwrseq-simple"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_wifi_en>; + reset-gpios = <&main_gpio0 22 GPIO_ACTIVE_LOW>; + }; +}; + +/* On-module Wi-Fi */ +&sdhci2 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_sdhci2>; + bus-width = <4>; + cap-power-off-card; + keep-power-in-suspend; + mmc-pwrseq = <&wifi_pwrseq>; + non-removable; + ti,fails-without-test-cd; + ti,driver-strength-ohm = <50>; + vmmc-supply = <®_3v3>; + status = "okay"; +}; + +/* On-module Bluetooth */ +&main_uart5 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart5>; + status = "okay"; +}; diff --git a/arch/arm64/boot/dts/ti/k3-am62-verdin.dtsi b/arch/arm64/boot/dts/ti/k3-am62-verdin.dtsi new file mode 100644 index 000000000000..432968bd7ec3 --- /dev/null +++ b/arch/arm64/boot/dts/ti/k3-am62-verdin.dtsi @@ -0,0 +1,1401 @@ +// SPDX-License-Identifier: GPL-2.0-or-later OR MIT +/* + * Copyright 2023 Toradex + * + * Common dtsi for Verdin AM62 SoM + * + * https://www.toradex.com/computer-on-modules/verdin-arm-family/ti-am62 + */ + +#include +#include +#include +#include +#include + +/ { + chosen { + stdout-path = "serial2:115200n8"; + }; + + aliases { + ethernet0 = &cpsw_port1; + ethernet1 = &cpsw_port2; + i2c0 = &main_i2c0; + i2c1 = &main_i2c1; + i2c2 = &main_i2c2; + i2c3 = &mcu_i2c0; + i2c4 = &main_i2c3; + mmc0 = &sdhci0; + mmc1 = &sdhci1; + mmc2 = &sdhci2; + rtc0 = &rtc_i2c; + rtc1 = &wkup_rtc0; + serial0 = &main_uart1; + serial1 = &wkup_uart0; + serial2 = &main_uart0; + serial3 = &mcu_uart0; + serial4 = &main_uart5; + usb0 = &usb0; + usb1 = &usb1; + }; + + verdin_gpio_keys: gpio-keys { + compatible = "gpio-keys"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_ctrl_wake1_mico>; + status = "disabled"; + + verdin_key_wakeup: key-wakeup { + debounce-interval = <10>; + /* Verdin CTRL_WAKE1_MICO# (SODIMM 252) */ + gpios = <&main_gpio0 32 GPIO_ACTIVE_LOW>; + label = "Wake-Up"; + linux,code = ; + wakeup-source; + }; + }; + + memory@80000000 { + device_type = "memory"; + reg = <0x00000000 0x80000000 0x00000000 0x40000000>; /* 1G RAM */ + }; + + opp-table { + /* Add 1.4GHz OPP. Requires VDD_CORE to be at 0.85V */ + opp-1400000000 { + opp-hz = /bits/ 64 <1400000000>; + opp-supported-hw = <0x01 0x0004>; + clock-latency-ns = <6000000>; + }; + }; + + /* Module Power Supply */ + reg_vsodimm: regulator-vsodimm { + compatible = "regulator-fixed"; + regulator-name = "+V_SODIMM"; + }; + + /* Non PMIC On-module Supplies */ + reg_3v3: regulator-3v3 { + compatible = "regulator-fixed"; + regulator-max-microvolt = <3300000>; + regulator-min-microvolt = <3300000>; + regulator-name = "On-module +V3.3"; + vin-supply = <®_vsodimm>; + }; + + reg_1v2_dsi: regulator-1v2-dsi { + compatible = "regulator-fixed"; + regulator-max-microvolt = <1200000>; + regulator-min-microvolt = <1200000>; + regulator-name = "On-module +V1.2_DSI"; + vin-supply = <®_1v8>; + }; + + /* Enabled by +V1.2_DSI */ + reg_1v8_dsi: regulator-1v8-dsi { + compatible = "regulator-fixed"; + regulator-max-microvolt = <1800000>; + regulator-min-microvolt = <1800000>; + regulator-name = "On-module +V1.8_DSI"; + vin-supply = <®_1v8>; + }; + + /* Enabled by +V2.5_ETH */ + reg_1v0_eth: regulator-1v0-eth { + compatible = "regulator-fixed"; + regulator-max-microvolt = <1000000>; + regulator-min-microvolt = <1000000>; + regulator-name = "On-module +V1.0_ETH"; + vin-supply = <®_1v8>; + }; + + /* Enabled by +V2.5_ETH */ + reg_1v8_eth: regulator-1v8-eth { + compatible = "regulator-fixed"; + regulator-max-microvolt = <1800000>; + regulator-min-microvolt = <1800000>; + regulator-name = "On-module +V1.8_ETH"; + vin-supply = <®_1v8>; + }; + + /* Verdin SD_1 Power Supply */ + reg_sdhc1_vmmc: regulator-sdhci1 { + compatible = "regulator-fixed"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_sd1_pwr_en>; + enable-active-high; + /* Verdin SD_1_PWR_EN (SODIMM 76) */ + gpio = <&main_gpio0 29 GPIO_ACTIVE_HIGH>; + off-on-delay-us = <100000>; + regulator-max-microvolt = <3300000>; + regulator-min-microvolt = <3300000>; + regulator-name = "+V3.3_SD"; + startup-delay-us = <2000>; + }; + + reg_sdhc1_vqmmc: regulator-sdhci1-vqmmc { + compatible = "regulator-gpio"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_vsel_sd>; + /* PMIC_VSEL_SD */ + gpios = <&main_gpio0 21 GPIO_ACTIVE_HIGH>; + regulator-name = "LDO1-VSEL-SD (PMIC)"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <3300000>; + states = <1800000 0x0>, + <3300000 0x1>; + vin-supply = <®_sd_3v3_1v8>; + }; + + reserved-memory { + #address-cells = <2>; + #size-cells = <2>; + ranges; + + secure_tfa_ddr: tfa@9e780000 { + reg = <0x00 0x9e780000 0x00 0x80000>; + alignment = <0x1000>; + no-map; + }; + + secure_ddr: optee@9e800000 { + reg = <0x00 0x9e800000 0x00 0x01800000>; /* for OP-TEE */ + alignment = <0x1000>; + no-map; + }; + + wkup_r5fss0_core0_dma_memory_region: r5f-dma-memory@9db00000 { + compatible = "shared-dma-pool"; + reg = <0x00 0x9db00000 0x00 0xc00000>; + no-map; + }; + }; +}; + +&main_pmx0 { + /* Verdin PWM_1 */ + pinctrl_epwm0_a: main-epwm0a-pins-default { + pinctrl-single,pins = < + AM62X_IOPAD(0x01b4, PIN_OUTPUT, 2) /* (A13) SPI0_CS0.EHRPWM0_A */ /* SODIMM 15 */ + >; + }; + + /* Verdin PWM_2 */ + pinctrl_epwm0_b: main-epwm0b-pins-default { + pinctrl-single,pins = < + AM62X_IOPAD(0x01b8, PIN_OUTPUT, 2) /* (C13) SPI0_CS1.EHRPWM0_B */ /* SODIMM 16 */ + >; + }; + + /* Verdin PWM_3_DSI */ + pinctrl_epwm1_a: main-epwm1a-pins-default { + pinctrl-single,pins = < + AM62X_IOPAD(0x01bc, PIN_OUTPUT, 2) /* (A14) SPI0_CLK.EHRPWM1_A */ /* SODIMM 19 */ + >; + }; + + /* Verdin QSPI_1_CLK as GPIO (conflict with Verdin QSPI_1 interface) */ + pinctrl_qspi1_clk_gpio: main-gpio0-0-pins-default { + pinctrl-single,pins = < + AM62X_IOPAD(0x0000, PIN_INPUT, 7) /* (H24) OSPI0_CLK.GPIO0_0 */ /* SODIMM 52 */ + >; + }; + + /* Verdin QSPI_1_IO0 as GPIO (conflict with Verdin QSPI_1 interface) */ + pinctrl_qspi1_io0_gpio: main-gpio0-3-pins-default { + pinctrl-single,pins = < + AM62X_IOPAD(0x000c, PIN_INPUT, 7) /* (E25) OSPI0_D0.GPIO0_3 */ /* SODIMM 56 */ + >; + }; + + /* Verdin QSPI_1_IO1 as GPIO (conflict with Verdin QSPI_1 interface) */ + pinctrl_qspi1_io1_gpio: main-gpio0-4-pins-default { + pinctrl-single,pins = < + AM62X_IOPAD(0x0010, PIN_INPUT, 7) /* (G24) OSPI0_D1.GPIO0_4 */ /* SODIMM 58 */ + >; + }; + + /* Verdin QSPI_1_IO2 as GPIO (conflict with Verdin QSPI_1 interface) */ + pinctrl_qspi1_io2_gpio: main-gpio0-5-pins-default { + pinctrl-single,pins = < + AM62X_IOPAD(0x0014, PIN_INPUT, 7) /* (F25) OSPI0_D2.GPIO0_5 */ /* SODIMM 60 */ + >; + }; + + /* Verdin QSPI_1_IO3 as GPIO (conflict with Verdin QSPI_1 interface) */ + pinctrl_qspi1_io3_gpio: main-gpio0-6-pins-default { + pinctrl-single,pins = < + AM62X_IOPAD(0x0018, PIN_INPUT, 7) /* (F24) OSPI0_D3.GPIO0_6 */ /* SODIMM 62 */ + >; + }; + + /* Verdin QSPI_1_CS# as GPIO (conflict with Verdin QSPI_1 interface) */ + pinctrl_qspi1_cs_gpio: main-gpio0-11-pins-default { + pinctrl-single,pins = < + AM62X_IOPAD(0x002c, PIN_INPUT, 7) /* (F23) OSPI0_CSn0.GPIO0_11 */ /* SODIMM 54 */ + >; + }; + + /* Verdin QSPI_1_CS2# as GPIO (conflict with Verdin QSPI_1 interface) */ + pinctrl_qspi1_cs2_gpio: main-gpio0-12-pins-default { + pinctrl-single,pins = < + AM62X_IOPAD(0x0030, PIN_INPUT, 7) /* (G21) OSPI0_CSn1.GPIO0_12 */ /* SODIMM 64 */ + >; + }; + + /* WiFi_W_WKUP_HOST# */ + pinctrl_wifi_w_wkup_host: main-gpio0-15-pins-default { + pinctrl-single,pins = < + AM62X_IOPAD(0x003c, PIN_INPUT, 7) /* (M25) GPMC0_AD0.GPIO0_15 */ /* SODIMM 174 */ + >; + }; + + /* WiFi_BT_WKUP_HOST# */ + pinctrl_bt_wkup_host: main-gpio0-16-pins-default { + pinctrl-single,pins = < + AM62X_IOPAD(0x0040, PIN_INPUT, 7) /* (N23) GPMC0_AD1.GPIO0_16 */ /* SODIMM 172 */ + >; + }; + + /* PMIC_ETH_RESET# */ + pinctrl_eth_reset: main-gpio0-17-pins-default { + pinctrl-single,pins = < + AM62X_IOPAD(0x0044, PIN_INPUT, 7) /* (N24) GPMC0_AD2.GPIO0_17 */ + >; + }; + + /* PMIC_BRIDGE_RESET# */ + pinctrl_bridge_reset: main-gpio0-20-pins-default { + pinctrl-single,pins = < + AM62X_IOPAD(0x0050, PIN_INPUT, 7) /* (P22) GPMC0_AD5.GPIO0_20 */ + >; + }; + + /* PMIC_VSEL_SD */ + pinctrl_vsel_sd: main-gpio0-21-pins-default { + pinctrl-single,pins = < + AM62X_IOPAD(0x0054, PIN_INPUT, 7) /* (P21) GPMC0_AD6.GPIO0_21 */ + >; + }; + + /* PMIC_EN_WIFI */ + pinctrl_wifi_en: main-gpio0-22-pins-default { + pinctrl-single,pins = < + AM62X_IOPAD(0x0058, PIN_INPUT, 7) /* (R23) GPMC0_AD7.GPIO0_22 */ + >; + }; + + /* PMIC_ETH_INT# */ + pinctrl_eth_int: main-gpio0-25-pins-default { + pinctrl-single,pins = < + AM62X_IOPAD(0x0064, PIN_INPUT_PULLUP, 7) /* (T25) GPMC0_AD10.GPIO0_25 */ + >; + }; + + /* WiFi_WKUP_BT# */ + pinctrl_wifi_wkup_bt: main-gpio0-26-pins-default { + pinctrl-single,pins = < + AM62X_IOPAD(0x0068, PIN_INPUT, 7) /* (R21) GPMC0_AD11.GPIO0_26 */ + >; + }; + + /* WiFi_WKUP_WLAN# */ + pinctrl_wifi_wkup_wlan: main-gpio0-27-pins-default { + pinctrl-single,pins = < + AM62X_IOPAD(0x006c, PIN_INPUT, 7) /* (T22) GPMC0_AD12.GPIO0_27 */ + >; + }; + + /* Verdin SD_1_PWR_EN */ + pinctrl_sd1_pwr_en: main-gpio0-29-pins-default { + pinctrl-single,pins = < + AM62X_IOPAD(0x0074, PIN_INPUT, 7) /* (U25) GPMC0_AD14.GPIO0_29 */ /* SODIMM 76 */ + >; + }; + + /* Verdin DSI_1_BKL_EN */ + pinctrl_dsi1_bkl_en: main-gpio0-30-pins-default { + pinctrl-single,pins = < + AM62X_IOPAD(0x0078, PIN_INPUT, 7) /* (U24) GPMC0_AD15.GPIO0_30 */ /* SODIMM 21 */ + >; + }; + + /* Verdin CTRL_SLEEP_MOCI# */ + pinctrl_ctrl_sleep_moci: main-gpio0-31-pins-default { + pinctrl-single,pins = < + AM62X_IOPAD(0x007c, PIN_INPUT, 7) /* (P25) GPMC0_CLK.GPIO0_31 */ /* SODIMM 256 */ + >; + }; + + /* Verdin CTRL_WAKE1_MICO# */ + pinctrl_ctrl_wake1_mico: main-gpio0-32-pins-default { + pinctrl-single,pins = < + AM62X_IOPAD(0x0084, PIN_INPUT_PULLUP, 7) /* (L23) GPMC0_ADVn_ALE.GPIO0_32 */ /* SODIMM 252 */ + >; + }; + + /* Verdin I2S_2_D_OUT as GPIO (conflict with Verdin I2S_2 interface) */ + pinctrl_i2s_2_d_out_gpio: main-gpio0-34-pins-default { + pinctrl-single,pins = < + AM62X_IOPAD(0x008c, PIN_INPUT, 7) /* (L25) GPMC0_WEn.GPIO0_34 */ /* SODIMM 46 */ + >; + }; + + /* Verdin I2S_2_BCLK as GPIO (conflict with Verdin I2S_2 interface) */ + pinctrl_i2s_2_bclk_gpio: main-gpio0-35-pins-default { + pinctrl-single,pins = < + AM62X_IOPAD(0x0090, PIN_INPUT, 7) /* (M24) GPMC0_BE0n_CLE.GPIO0_35 */ /* SODIMM 42 */ + >; + }; + + /* Verdin GPIO_6 */ + pinctrl_gpio_6: main-gpio0-36-pins-default { + pinctrl-single,pins = < + AM62X_IOPAD(0x0094, PIN_INPUT, 7) /* (N20) GPMC0_BE1n.GPIO0_36 */ /* SODIMM 218 */ + >; + }; + + /* Verdin ETH_2_RGMII_INT# */ + pinctrl_eth2_rgmii_int: main-gpio0-38-pins-default { + pinctrl-single,pins = < + AM62X_IOPAD(0x009c, PIN_INPUT, 7) /* (V25) GPMC0_WAIT1.GPIO0_38 */ /* SODIMM 189 */ + >; + }; + + /* Verdin GPIO_5 */ + pinctrl_gpio_5: main-gpio0-40-pins-default { + pinctrl-single,pins = < + AM62X_IOPAD(0x00a4, PIN_INPUT, 7) /* (M22) GPMC0_DIR.GPIO0_40 */ /* SODIMM 216 */ + >; + }; + + /* Verdin GPIO_7 */ + pinctrl_gpio_7: main-gpio0-41-pins-default { + pinctrl-single,pins = < + AM62X_IOPAD(0x00a8, PIN_INPUT, 7) /* (M21) GPMC0_CSn0.GPIO0_41 */ /* SODIMM 220 */ + >; + }; + + /* Verdin GPIO_8 */ + pinctrl_gpio_8: main-gpio0-42-pins-default { + pinctrl-single,pins = < + AM62X_IOPAD(0x00ac, PIN_INPUT, 7) /* (L21) GPMC0_CSn1.GPIO0_42 */ /* SODIMM 222 */ + >; + }; + + /* Verdin USB_1_OC# */ + pinctrl_usb1_oc: main-gpio0-71-pins-default { + pinctrl-single,pins = < + AM62X_IOPAD(0x0124, PIN_INPUT, 7) /* (A23) MMC2_SDCD.GPIO0_71 */ /* SODIMM 157 */ + >; + }; + + /* Verdin USB_2_OC# */ + pinctrl_usb2_oc: main-gpio0-72-pins-default { + pinctrl-single,pins = < + AM62X_IOPAD(0x0128, PIN_INPUT, 7) /* (B23) MMC2_SDWP.GPIO0_72 */ /* SODIMM 187 */ + >; + }; + + /* Verdin PWM_3_DSI as GPIO */ + pinctrl_pwm3_dsi_gpio: main-gpio1-17-pins-default { + pinctrl-single,pins = < + AM62X_IOPAD(0x01bc, PIN_INPUT, 7) /* (A14) SPI0_CLK.GPIO1_17 */ /* SODIMM 19 */ + >; + }; + + /* Verdin QSPI_1_DQS as GPIO */ + pinctrl_qspi1_dqs_gpio: main-gpio1-18-pins-default { + pinctrl-single,pins = < + AM62X_IOPAD(0x01c0, PIN_INPUT, 7) /* (B13) SPI0_D0.GPIO1_18 */ /* SODIMM 66 */ + >; + }; + + /* Verdin USB_1_ID */ + pinctrl_usb0_id: main-gpio1-19-pins-default { + pinctrl-single,pins = < + AM62X_IOPAD(0x01c4, PIN_INPUT, 7) /* (B14) SPI0_D1.GPIO1_19 */ /* SODIMM 161 */ + >; + }; + + /* Verdin DSI_1_INT# (pulled-up as active-low) */ + pinctrl_dsi1_int: main-gpio1-49-pins-default { + pinctrl-single,pins = < + AM62X_IOPAD(0x0244, PIN_INPUT_PULLUP, 7) /* (C17) MMC1_SDWP.GPIO1_49 */ /* SODIMM 17 */ + >; + }; + + /* On-module I2C - PMIC_I2C */ + pinctrl_i2c0: main-i2c0-pins-default { + pinctrl-single,pins = < + AM62X_IOPAD(0x01e0, PIN_INPUT, 0) /* (B16) I2C0_SCL */ /* PMIC_I2C_SCL */ + AM62X_IOPAD(0x01e4, PIN_INPUT, 0) /* (A16) I2C0_SDA */ /* PMIC_I2C_SDA */ + >; + }; + + /* Verdin I2C_1 */ + pinctrl_i2c1: main-i2c1-pins-default { + pinctrl-single,pins = < + AM62X_IOPAD(0x01e8, PIN_INPUT_PULLUP, 0) /* (B17) I2C1_SCL */ /* SODIMM 14 */ + AM62X_IOPAD(0x01ec, PIN_INPUT_PULLUP, 0) /* (A17) I2C1_SDA */ /* SODIMM 12 */ + >; + }; + + /* Verdin I2C_2_DSI */ + pinctrl_i2c2: main-i2c2-pins-default { + pinctrl-single,pins = < + AM62X_IOPAD(0x00b0, PIN_INPUT, 1) /* (K22) GPMC0_CSn2.I2C2_SCL */ /* SODIMM 55 */ + AM62X_IOPAD(0x00b4, PIN_INPUT, 1) /* (K24) GPMC0_CSn3.I2C2_SDA */ /* SODIMM 53 */ + >; + }; + + /* Verdin I2C_4_CSI */ + pinctrl_i2c3: main-i2c3-pins-default { + pinctrl-single,pins = < + AM62X_IOPAD(0x01d0, PIN_INPUT, 2) /* (A15) UART0_CTSn.I2C3_SCL */ /* SODIMM 95 */ + AM62X_IOPAD(0x01d4, PIN_INPUT, 2) /* (B15) UART0_RTSn.I2C3_SDA */ /* SODIMM 93 */ + >; + }; + + /* I2S_1_MCLK */ + pinctrl_i2s1_mclk: main-system-audio-ext-reflock1-pins-default { + pinctrl-single,pins = < + AM62X_IOPAD(0x00a0, PIN_OUTPUT, 1) /* (K25) GPMC0_WPn.AUDIO_EXT_REFCLK1 */ /* SODIMM 38 */ + >; + }; + + /* Verdin I2S_1 */ + pinctrl_mcasp0: main-mcasp0-pins-default { + pinctrl-single,pins = < + AM62X_IOPAD(0x01a4, PIN_INPUT, 0) /* (B20) MCASP0_ACLKX */ /* SODIMM 30 */ + AM62X_IOPAD(0x01a8, PIN_INPUT, 0) /* (D20) MCASP0_AFSX */ /* SODIMM 32 */ + AM62X_IOPAD(0x01a0, PIN_OUTPUT, 0) /* (E18) MCASP0_AXR0 */ /* SODIMM 34 */ + AM62X_IOPAD(0x019c, PIN_INPUT, 0) /* (B18) MCASP0_AXR1 */ /* SODIMM 36 */ + >; + }; + + /* Verdin I2S_2 */ + pinctrl_mcasp1: main-mcasp1-pins-default { + pinctrl-single,pins = < + AM62X_IOPAD(0x0090, PIN_INPUT, 2) /* (M24) GPMC0_BE0n_CLE.MCASP1_ACLKX */ /* SODIMM 42 */ + AM62X_IOPAD(0x0098, PIN_INPUT, 2) /* (U23) GPMC0_WAIT0.MCASP1_AFSX */ /* SODIMM 44 */ + AM62X_IOPAD(0x008c, PIN_OUTPUT, 2) /* (L25) GPMC0_WEn.MCASP1_AXR0 */ /* SODIMM 46 */ + AM62X_IOPAD(0x0088, PIN_INPUT, 2) /* (L24) GPMC0_OEn_REn.MCASP1_AXR1 */ /* SODIMM 48 */ + >; + }; + + /* Verdin CAN_1 */ + pinctrl_mcan0: main-mcan0-pins-default { + pinctrl-single,pins = < + AM62X_IOPAD(0x01dc, PIN_INPUT, 0) /* (E15) MCAN0_RX */ /* SODIMM 22 */ + AM62X_IOPAD(0x01d8, PIN_OUTPUT, 0) /* (C15) MCAN0_TX */ /* SODIMM 20 */ + >; + }; + + /* MDIO, shared by Verdin ETH_1 (On-module PHY) and Verdin ETH_2_RGMII */ + pinctrl_mdio: main-mdio1-pins-default { + pinctrl-single,pins = < + AM62X_IOPAD(0x160, PIN_OUTPUT, 0) /* (AD24) MDIO0_MDC */ /* ETH_1_MDC, SODIMM 193 */ + AM62X_IOPAD(0x15c, PIN_INPUT, 0) /* (AB22) MDIO0_MDIO */ /* ETH_1_MDIO, SODIMM 191 */ + >; + }; + + /* On-module eMMC */ + pinctrl_sdhci0: main-mmc0-pins-default { + pinctrl-single,pins = < + AM62X_IOPAD(0x220, PIN_INPUT, 0) /* (Y3) MMC0_CMD */ + AM62X_IOPAD(0x218, PIN_INPUT, 0) /* (AB1) MMC0_CLK */ + AM62X_IOPAD(0x214, PIN_INPUT, 0) /* (AA2) MMC0_DAT0 */ + AM62X_IOPAD(0x210, PIN_INPUT, 0) /* (AA1) MMC0_DAT1 */ + AM62X_IOPAD(0x20c, PIN_INPUT, 0) /* (AA3) MMC0_DAT2 */ + AM62X_IOPAD(0x208, PIN_INPUT, 0) /* (Y4) MMC0_DAT3 */ + AM62X_IOPAD(0x204, PIN_INPUT, 0) /* (AB2) MMC0_DAT4 */ + AM62X_IOPAD(0x200, PIN_INPUT, 0) /* (AC1) MMC0_DAT5 */ + AM62X_IOPAD(0x1fc, PIN_INPUT, 0) /* (AD2) MMC0_DAT6 */ + AM62X_IOPAD(0x1f8, PIN_INPUT, 0) /* (AC2) MMC0_DAT7 */ + >; + }; + + /* Verdin SD_1 */ + pinctrl_sdhci1: main-mmc1-pins-default { + pinctrl-single,pins = < + AM62X_IOPAD(0x23c, PIN_INPUT, 0) /* (A21) MMC1_CMD */ /* SODIMM 74 */ + AM62X_IOPAD(0x234, PIN_INPUT, 0) /* (B22) MMC1_CLK */ /* SODIMM 78 */ + AM62X_IOPAD(0x230, PIN_INPUT, 0) /* (A22) MMC1_DAT0 */ /* SODIMM 80 */ + AM62X_IOPAD(0x22c, PIN_INPUT, 0) /* (B21) MMC1_DAT1 */ /* SODIMM 82 */ + AM62X_IOPAD(0x228, PIN_INPUT, 0) /* (C21) MMC1_DAT2 */ /* SODIMM 70 */ + AM62X_IOPAD(0x224, PIN_INPUT, 0) /* (D22) MMC1_DAT3 */ /* SODIMM 72 */ + AM62X_IOPAD(0x240, PIN_INPUT_PULLUP, 0) /* (D17) MMC1_SDCD */ /* SODIMM 84 */ + >; + }; + + /* On-module Wi-Fi on WB SKUs, module-specific SDIO otherwise */ + pinctrl_sdhci2: main-mmc2-pins-default { + pinctrl-single,pins = < + AM62X_IOPAD(0x120, PIN_INPUT, 0) /* (C24) MMC2_CMD */ /* WiFi_SDIO_CMD */ + AM62X_IOPAD(0x118, PIN_INPUT, 0) /* (D25) MMC2_CLK */ /* WiFi_SDIO_CLK */ + AM62X_IOPAD(0x114, PIN_INPUT, 0) /* (B24) MMC2_DAT0 */ /* WiFi_SDIO_DATA0 */ + AM62X_IOPAD(0x110, PIN_INPUT, 0) /* (C25) MMC2_DAT1 */ /* WiFi_SDIO_DATA1 */ + AM62X_IOPAD(0x10c, PIN_INPUT, 0) /* (E23) MMC2_DAT2 */ /* WiFi_SDIO_DATA2 */ + AM62X_IOPAD(0x108, PIN_INPUT, 0) /* (D24) MMC2_DAT3 */ /* WiFi_SDIO_DATA3 */ + AM62X_IOPAD(0x11c, PIN_INPUT, 0) /* (#N/A) MMC2_CLKB */ + >; + }; + + /* Verdin QSPI_1 */ + pinctrl_ospi0: main-ospi0-pins-default { + pinctrl-single,pins = < + AM62X_IOPAD(0x0000, PIN_OUTPUT, 0) /* (H24) OSPI0_CLK */ /* SODIMM 52 */ + AM62X_IOPAD(0x002c, PIN_OUTPUT, 0) /* (F23) OSPI0_CSn0 */ /* SODIMM 54 */ + AM62X_IOPAD(0x0030, PIN_OUTPUT, 0) /* (G21) OSPI0_CSn1 */ /* SODIMM 64 */ + AM62X_IOPAD(0x000c, PIN_INPUT, 0) /* (E25) OSPI0_D0 */ /* SODIMM 56 */ + AM62X_IOPAD(0x0010, PIN_INPUT, 0) /* (G24) OSPI0_D1 */ /* SODIMM 58 */ + AM62X_IOPAD(0x0014, PIN_INPUT, 0) /* (F25) OSPI0_D2 */ /* SODIMM 60 */ + AM62X_IOPAD(0x0018, PIN_INPUT, 0) /* (F24) OSPI0_D3 */ /* SODIMM 62 */ + >; + }; + + /* Verdin ETH_1 RGMII (On-module PHY) */ + pinctrl_rgmii1: main-rgmii1-pins-default { + pinctrl-single,pins = < + AM62X_IOPAD(0x14c, PIN_INPUT, 0) /* (AB17) RGMII1_RD0 */ + AM62X_IOPAD(0x150, PIN_INPUT, 0) /* (AC17) RGMII1_RD1 */ + AM62X_IOPAD(0x154, PIN_INPUT, 0) /* (AB16) RGMII1_RD2 */ + AM62X_IOPAD(0x158, PIN_INPUT, 0) /* (AA15) RGMII1_RD3 */ + AM62X_IOPAD(0x148, PIN_INPUT, 0) /* (AD17) RGMII1_RXC */ + AM62X_IOPAD(0x144, PIN_INPUT, 0) /* (AE17) RGMII1_RX_CTL */ + AM62X_IOPAD(0x134, PIN_OUTPUT, 0) /* (AE20) RGMII1_TD0 */ + AM62X_IOPAD(0x138, PIN_OUTPUT, 0) /* (AD20) RGMII1_TD1 */ + AM62X_IOPAD(0x13c, PIN_OUTPUT, 0) /* (AE18) RGMII1_TD2 */ + AM62X_IOPAD(0x140, PIN_OUTPUT, 0) /* (AD18) RGMII1_TD3 */ + AM62X_IOPAD(0x130, PIN_OUTPUT, 0) /* (AE19) RGMII1_TXC */ + AM62X_IOPAD(0x12c, PIN_OUTPUT, 0) /* (AD19) RGMII1_TX_CTL */ + >; + }; + + /* Verdin ETH_2 RGMII */ + pinctrl_rgmii2: main-rgmii2-pins-default { + pinctrl-single,pins = < + AM62X_IOPAD(0x184, PIN_INPUT, 0) /* (AE23) RGMII2_RD0 */ /* SODIMM 201 */ + AM62X_IOPAD(0x188, PIN_INPUT, 0) /* (AB20) RGMII2_RD1 */ /* SODIMM 203 */ + AM62X_IOPAD(0x18c, PIN_INPUT, 0) /* (AC21) RGMII2_RD2 */ /* SODIMM 205 */ + AM62X_IOPAD(0x190, PIN_INPUT, 0) /* (AE22) RGMII2_RD3 */ /* SODIMM 207 */ + AM62X_IOPAD(0x180, PIN_INPUT, 0) /* (AD23) RGMII2_RXC */ /* SODIMM 197 */ + AM62X_IOPAD(0x17c, PIN_INPUT, 0) /* (AD22) RGMII2_RX_CTL */ /* SODIMM 199 */ + AM62X_IOPAD(0x16c, PIN_OUTPUT, 0) /* (Y18) RGMII2_TD0 */ /* SODIMM 221 */ + AM62X_IOPAD(0x170, PIN_OUTPUT, 0) /* (AA18) RGMII2_TD1 */ /* SODIMM 219 */ + AM62X_IOPAD(0x174, PIN_OUTPUT, 0) /* (AD21) RGMII2_TD2 */ /* SODIMM 217 */ + AM62X_IOPAD(0x178, PIN_OUTPUT, 0) /* (AC20) RGMII2_TD3 */ /* SODIMM 215 */ + AM62X_IOPAD(0x168, PIN_OUTPUT, 0) /* (AE21) RGMII2_TXC */ /* SODIMM 213 */ + AM62X_IOPAD(0x164, PIN_OUTPUT, 0) /* (AA19) RGMII2_TX_CTL */ /* SODIMM 211 */ + >; + }; + + /* Verdin SPI_1 */ + pinctrl_spi1: main-spi1-pins-default { + pinctrl-single,pins = < + AM62X_IOPAD(0x0020, PIN_INPUT, 1) /* (J25) OSPI0_D5.SPI1_CLK */ /* SODIMM 196 */ + AM62X_IOPAD(0x001c, PIN_INPUT, 1) /* (J23) OSPI0_D4.SPI1_CS0 */ /* SODIMM 202 */ + AM62X_IOPAD(0x0024, PIN_INPUT, 1) /* (H25) OSPI0_D6.SPI1_D0 */ /* SODIMM 200 */ + AM62X_IOPAD(0x0028, PIN_INPUT, 1) /* (J22) OSPI0_D7.SPI1_D1 */ /* SODIMM 198 */ + >; + }; + + /* ETH_25MHz_CLK */ + pinctrl_eth_clock: main-system-clkout0-pins-default { + pinctrl-single,pins = < + AM62X_IOPAD(0x01f0, PIN_OUTPUT_PULLUP, 5) /* (A18) EXT_REFCLK1.CLKOUT0 */ + >; + }; + + /* PMIC_EXTINT# */ + pinctrl_pmic_extint: main-system-extint-pins-default { + pinctrl-single,pins = < + AM62X_IOPAD(0x01f4, PIN_INPUT, 0) /* (D16) EXTINTn */ + >; + }; + + /* Verdin UART_3, used as the Linux console */ + pinctrl_uart0: main-uart0-pins-default { + pinctrl-single,pins = < + AM62X_IOPAD(0x1c8, PIN_INPUT_PULLUP, 0) /* (D14) UART0_RXD */ /* SODIMM 147 */ + AM62X_IOPAD(0x1cc, PIN_OUTPUT, 0) /* (E14) UART0_TXD */ /* SODIMM 149 */ + >; + }; + + /* Verdin UART_1 */ + pinctrl_uart1: main-uart1-pins-default { + pinctrl-single,pins = < + AM62X_IOPAD(0x0194, PIN_INPUT_PULLUP, 2) /* (B19) MCASP0_AXR3.UART1_CTSn */ /* SODIMM 135 */ + AM62X_IOPAD(0x0198, PIN_OUTPUT, 2) /* (A19) MCASP0_AXR2.UART1_RTSn */ /* SODIMM 133 */ + AM62X_IOPAD(0x01ac, PIN_INPUT_PULLUP, 2) /* (E19) MCASP0_AFSR.UART1_RXD */ /* SODIMM 129 */ + AM62X_IOPAD(0x01b0, PIN_OUTPUT, 2) /* (A20) MCASP0_ACLKR.UART1_TXD */ /* SODIMM 131 */ + >; + }; + + /* Bluetooth on WB SKUs, module-specific UART otherwise */ + pinctrl_uart5: main-uart5-pins-default { + pinctrl-single,pins = < + AM62X_IOPAD(0x0008, PIN_INPUT_PULLUP, 5) /* (J24) OSPI0_DQS.UART5_CTSn */ /* WiFi_UART_CTS */ + AM62X_IOPAD(0x0004, PIN_OUTPUT, 5) /* (G25) OSPI0_LBCLKO.UART5_RTSn */ /* WiFi_UART_RTS */ + AM62X_IOPAD(0x0034, PIN_INPUT_PULLUP, 5) /* (H21) OSPI0_CSn2.UART5_RXD */ /* WiFi_UART_RXD */ + AM62X_IOPAD(0x0038, PIN_OUTPUT, 5) /* (E24) OSPI0_CSn3.UART5_TXD */ /* WiFi_UART_TXD */ + >; + }; + + /* Verdin USB_1 */ + pinctrl_usb0: main-usb0-pins-default { + pinctrl-single,pins = < + AM62X_IOPAD(0x0254, PIN_OUTPUT, 0) /* (C20) USB0_DRVVBUS */ /* SODIMM 155 */ + >; + }; + + /* Verdin USB_2 */ + pinctrl_usb1: main-usb1-pins-default { + pinctrl-single,pins = < + AM62X_IOPAD(0x0258, PIN_OUTPUT, 0) /* (F18) USB1_DRVVBUS */ /* SODIMM 185 */ + >; + }; + + /* DSS VOUT0 RGB */ + pinctrl_parallel_rgb: main-vout-pins-default { + pinctrl-single,pins = < + AM62X_IOPAD(0x0100, PIN_OUTPUT, 0) /* (AC25) VOUT0_VSYNC */ + AM62X_IOPAD(0x00f8, PIN_OUTPUT, 0) /* (AB24) VOUT0_HSYNC */ + AM62X_IOPAD(0x0104, PIN_OUTPUT, 0) /* (AC24) VOUT0_PCLK */ + AM62X_IOPAD(0x00fc, PIN_OUTPUT, 0) /* (Y20) VOUT0_DE */ + AM62X_IOPAD(0x00b8, PIN_OUTPUT, 0) /* (U22) VOUT0_DATA0 */ + AM62X_IOPAD(0x00bc, PIN_OUTPUT, 0) /* (V24) VOUT0_DATA1 */ + AM62X_IOPAD(0x00c0, PIN_OUTPUT, 0) /* (W25) VOUT0_DATA2 */ + AM62X_IOPAD(0x00c4, PIN_OUTPUT, 0) /* (W24) VOUT0_DATA3 */ + AM62X_IOPAD(0x00c8, PIN_OUTPUT, 0) /* (Y25) VOUT0_DATA4 */ + AM62X_IOPAD(0x00cc, PIN_OUTPUT, 0) /* (Y24) VOUT0_DATA5 */ + AM62X_IOPAD(0x00d0, PIN_OUTPUT, 0) /* (Y23) VOUT0_DATA6 */ + AM62X_IOPAD(0x00d4, PIN_OUTPUT, 0) /* (AA25) VOUT0_DATA7 */ + AM62X_IOPAD(0x00d8, PIN_OUTPUT, 0) /* (V21) VOUT0_DATA8 */ + AM62X_IOPAD(0x00dc, PIN_OUTPUT, 0) /* (W21) VOUT0_DATA9 */ + AM62X_IOPAD(0x00e0, PIN_OUTPUT, 0) /* (V20) VOUT0_DATA10 */ + AM62X_IOPAD(0x00e4, PIN_OUTPUT, 0) /* (AA23) VOUT0_DATA11 */ + AM62X_IOPAD(0x00e8, PIN_OUTPUT, 0) /* (AB25) VOUT0_DATA12 */ + AM62X_IOPAD(0x00ec, PIN_OUTPUT, 0) /* (AA24) VOUT0_DATA13 */ + AM62X_IOPAD(0x00f0, PIN_OUTPUT, 0) /* (Y22) VOUT0_DATA14 */ + AM62X_IOPAD(0x00f4, PIN_OUTPUT, 0) /* (AA21) VOUT0_DATA15 */ + AM62X_IOPAD(0x005c, PIN_OUTPUT, 1) /* (R24) GPMC0_AD8.VOUT0_DATA16 */ + AM62X_IOPAD(0x0060, PIN_OUTPUT, 1) /* (R25) GPMC0_AD9.VOUT0_DATA17 */ + >; + }; +}; + +&mcu_pmx0 { + /* Verdin PCIE_1_RESET# */ + pinctrl_pcie_1_reset: mcu-gpio0-0-pins-default { + pinctrl-single,pins = < + AM62X_MCU_IOPAD(0x0000, PIN_INPUT, 7) /* (E8) MCU_SPI0_CS0.MCU_GPIO0_0 */ /* SODIMM 244 */ + >; + }; + + /* Verdin GPIO_1 */ + pinctrl_gpio_1: mcu-gpio0-1-pins-default { + pinctrl-single,pins = < + AM62X_MCU_IOPAD(0x0004, PIN_INPUT, 7) /* (B8) MCU_SPI0_CS1.MCU_GPIO0_1 */ /* SODIMM 206 */ + >; + }; + + /* Verdin GPIO_2 */ + pinctrl_gpio_2: mcu-gpio0-2-pins-default { + pinctrl-single,pins = < + AM62X_MCU_IOPAD(0x0008, PIN_INPUT, 7) /* (A7) MCU_SPI0_CLK.MCU_GPIO0_2 */ /* SODIMM 208 */ + >; + }; + + /* Verdin GPIO_3 */ + pinctrl_gpio_3: mcu-gpio0-3-pins-default { + pinctrl-single,pins = < + AM62X_MCU_IOPAD(0x000c, PIN_INPUT, 7) /* (D9) MCU_SPI0_D0.MCU_GPIO0_3 */ /* SODIMM 210 */ + >; + }; + + /* Verdin GPIO_4 */ + pinctrl_gpio_4: mcu-gpio0-4-pins-default { + pinctrl-single,pins = < + AM62X_MCU_IOPAD(0x0010, PIN_INPUT, 7) /* (C9) MCU_SPI0_D1.MCU_GPIO0_4 */ /* SODIMM 212 */ + >; + }; + + /* Verdin I2C_3_HDMI */ + pinctrl_mcu_i2c0: mcu-i2c0-pins-default { + pinctrl-single,pins = < + AM62X_MCU_IOPAD(0x0044, PIN_INPUT, 0) /* (A8) MCU_I2C0_SCL */ /* SODIMM 59 */ + AM62X_MCU_IOPAD(0x0048, PIN_INPUT, 0) /* (D10) MCU_I2C0_SDA */ /* SODIMM 57 */ + >; + }; + + /* Verdin UART_4 - Reserved to Cortex-M4 */ + pinctrl_mcu_uart0: mcu-uart0-pins-default { + pinctrl-single,pins = < + AM62X_MCU_IOPAD(0x0014, PIN_INPUT_PULLUP, 0) /* (B5) MCU_UART0_RXD */ /* SODIMM 151 */ + AM62X_MCU_IOPAD(0x0018, PIN_OUTPUT, 0) /* (A5) MCU_UART0_TXD */ /* SODIMM 153 */ + >; + }; + + /* Verdin CSI_1_MCLK */ + pinctrl_csi1_mclk: wkup-clkout0-pins-default { + pinctrl-single,pins = < + AM62X_MCU_IOPAD(0x0084, PIN_OUTPUT, 0) /* (A12) WKUP_CLKOUT0 */ /* SODIMM 91 */ + >; + }; + + /* Verdin UART_2 */ + pinctrl_wkup_uart0: wkup-uart0-pins-default { + pinctrl-single,pins = < + AM62X_MCU_IOPAD(0x002c, PIN_INPUT_PULLUP, 0) /* (C6) WKUP_UART0_CTSn */ /* SODIMM 143 */ + AM62X_MCU_IOPAD(0x0030, PIN_OUTPUT, 0) /* (A4) WKUP_UART0_RTSn */ /* SODIMM 141 */ + AM62X_MCU_IOPAD(0x0024, PIN_INPUT_PULLUP, 0) /* (B4) WKUP_UART0_RXD */ /* SODIMM 137 */ + AM62X_MCU_IOPAD(0x0028, PIN_OUTPUT, 0) /* (C5) WKUP_UART0_TXD */ /* SODIMM 139 */ + >; + }; +}; + +&cpsw3g { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_rgmii1>; + status = "disabled"; +}; + +/* Verdin ETH_1 (On-module PHY) */ +&cpsw_port1 { + phy-handle = <&cpsw3g_phy0>; + phy-mode = "rgmii-rxid"; + status = "disabled"; +}; + +/* Verdin ETH_2_RGMII */ +&cpsw_port2 { + status = "disabled"; +}; + +/* MDIO, shared by Verdin ETH_1 (On-module PHY) and Verdin ETH_2_RGMII */ +&cpsw3g_mdio { + assigned-clocks = <&k3_clks 157 20>; + assigned-clock-parents = <&k3_clks 157 22>; + assigned-clock-rates = <25000000>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_eth_clock>, <&pinctrl_mdio>; + status = "disabled"; + + cpsw3g_phy0: ethernet-phy@0 { + compatible = "ethernet-phy-id2000.a231"; + reg = <0>; + interrupt-parent = <&main_gpio0>; + interrupts = <25 IRQ_TYPE_EDGE_FALLING>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_eth_int>, <&pinctrl_eth_reset>; + reset-gpios = <&main_gpio0 17 GPIO_ACTIVE_LOW>; + reset-assert-us = <10>; + reset-deassert-us = <1000>; + ti,fifo-depth = ; + ti,rx-internal-delay = ; + }; +}; + +/* Verdin PWM_1, PWM_2 */ +&epwm0 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_epwm0_a>, <&pinctrl_epwm0_b>; + status = "disabled"; +}; + +/* Verdin PWM_3_DSI */ +&epwm1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_epwm1_a>; + status = "disabled"; +}; + +&main_gpio0 { + gpio-line-names = + "SODIMM_52", /* 0 */ + "", + "", + "SODIMM_56", + "SODIMM_58", + "SODIMM_60", + "SODIMM_62", + "", + "", + "", + "", /* 10 */ + "SODIMM_54", + "SODIMM_64", + "", + "", + "SODIMM_174", + "SODIMM_172", + "", + "", + "", + "", /* 20 */ + "", + "", + "", + "", + "", + "", + "", + "", + "SODIMM_76", + "SODIMM_21", /* 30 */ + "SODIMM_256", + "SODIMM_252", + "", + "SODIMM_46", + "SODIMM_42", + "SODIMM_218", + "", + "SODIMM_189", + "", + "SODIMM_216", /* 40 */ + "SODIMM_220", + "SODIMM_222", + "", + "", + "", + "", + "", + "", + "", + "", /* 50 */ + "", + "", + "", + "", + "", + "", + "", + "", + "", + "", /* 60 */ + "", + "", + "", + "", + "", + "", + "", + "", + "", + "", /* 70 */ + "SODIMM_157", + "SODIMM_187", + "", + "", + "", + "", + "", + "", + "", + "", /* 80 */ + "", + "", + "", + "", + "", + ""; + + verdin_ctrl_sleep_moci: ctrl-sleep-moci-hog { + gpio-hog; + /* Verdin CTRL_SLEEP_MOCI# (SODIMM 256) */ + gpios = <31 GPIO_ACTIVE_HIGH>; + line-name = "CTRL_SLEEP_MOCI#"; + output-high; + }; +}; + +&main_gpio1 { + gpio-line-names = + "", /* 0 */ + "", + "", + "", + "", + "", + "", + "", + "", + "", + "", /* 10 */ + "", + "", + "", + "", + "SODIMM_15", + "SODIMM_16", + "SODIMM_19", + "SODIMM_66", + "SODIMM_161", + "", /* 20 */ + "", + "", + "", + "", + "", + "", + "", + "", + "", + "", /* 30 */ + "", + "", + "", + "", + "", + "", + "", + "", + "", + "", /* 40 */ + "", + "", + "", + "", + "", + "", + "", + "", + "SODIMM_17", + "", /* 50 */ + "", + "", + "", + "", + "", + "", + "", + "", + "", + "", /* 60 */ + "", + "", + "", + "", + "", + "", + "", + "", + "", + "", /* 70 */ + "", + "", + "", + "", + "", + "", + "", + "", + "", + "", /* 80 */ + "", + "", + "", + "", + "", + "", + ""; +}; + +/* On-module I2C - PMIC_I2C */ +&main_i2c0 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c0>; + clock-frequency = <400000>; + status = "okay"; + + dsi_bridge: dsi@e { + compatible = "toshiba,tc358778"; + reg = <0xe>; + assigned-clocks = <&k3_clks 157 20>; + assigned-clock-parents = <&k3_clks 157 22>; + assigned-clock-rates = <25000000>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_bridge_reset>; + clocks = <&k3_clks 157 20>; + clock-names = "refclk"; + reset-gpios = <&main_gpio0 20 GPIO_ACTIVE_LOW>; + vddc-supply = <®_1v2_dsi>; + vddmipi-supply = <®_1v2_dsi>; + vddio-supply = <®_1v8_dsi>; + + dsi_bridge_ports: ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + + rgb_in: endpoint { + data-lines = <18>; + }; + }; + + port@1 { + reg = <1>; + }; + }; + }; + + pmic@30 { + compatible = "ti,tps65219"; + reg = <0x30>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_pmic_extint>; + interrupt-parent = <&gic500>; + interrupts = ; + + buck1-supply = <®_vsodimm>; + buck2-supply = <®_vsodimm>; + buck3-supply = <®_vsodimm>; + ldo1-supply = <®_3v3>; + ldo2-supply = <®_1v8>; + ldo3-supply = <®_3v3>; + ldo4-supply = <®_3v3>; + system-power-controller; + ti,power-button; + + regulators { + reg_vdd_core: buck1 { + regulator-always-on; + regulator-boot-on; + regulator-max-microvolt = <850000>; + regulator-min-microvolt = <850000>; + regulator-name = "+VDD_CORE (PMIC BUCK1)"; + }; + + reg_1v8: buck2 { + regulator-always-on; + regulator-boot-on; + regulator-max-microvolt = <1800000>; + regulator-min-microvolt = <1800000>; + regulator-name = "+V1.8 (PMIC BUCK2)"; /* On-module and SODIMM 214 */ + }; + + reg_vdd_ddr: buck3 { + regulator-always-on; + regulator-boot-on; + regulator-max-microvolt = <1100000>; + regulator-min-microvolt = <1100000>; + regulator-name = "+VDD_DDR (PMIC BUCK3)"; + }; + + reg_sd_3v3_1v8: ldo1 { + regulator-allow-bypass; + regulator-always-on; + regulator-boot-on; + regulator-max-microvolt = <3300000>; + regulator-min-microvolt = <3300000>; + regulator-name = "+V3.3_1.8_SD (PMIC LDO1)"; + }; + + reg_vddr_core: ldo2 { + regulator-always-on; + regulator-boot-on; + regulator-max-microvolt = <850000>; + regulator-min-microvolt = <850000>; + regulator-name = "+VDDR_CORE (PMIC LDO2)"; + }; + + reg_1v8a: ldo3 { + regulator-always-on; + regulator-boot-on; + regulator-max-microvolt = <1800000>; + regulator-min-microvolt = <1800000>; + regulator-name = "+V1.8A (PMIC LDO3)"; + }; + + reg_eth_2v5: ldo4 { + regulator-always-on; + regulator-boot-on; + regulator-max-microvolt = <2500000>; + regulator-min-microvolt = <2500000>; + regulator-name = "+V2.5_ETH (PMIC LDO4)"; + }; + }; + }; + + rtc_i2c: rtc@32 { + compatible = "epson,rx8130"; + reg = <0x32>; + }; + + sensor@48 { + compatible = "ti,tmp1075"; + reg = <0x48>; + }; + + adc@49 { + compatible = "ti,ads1015"; + reg = <0x49>; + #address-cells = <1>; + #size-cells = <0>; + + /* Verdin PMIC_I2C (ADC_4 - ADC_3) */ + channel@0 { + reg = <0>; + ti,datarate = <4>; + ti,gain = <2>; + }; + + /* Verdin PMIC_I2C (ADC_4 - ADC_1) */ + channel@1 { + reg = <1>; + ti,datarate = <4>; + ti,gain = <2>; + }; + + /* Verdin PMIC_I2C (ADC_3 - ADC_1) */ + channel@2 { + reg = <2>; + ti,datarate = <4>; + ti,gain = <2>; + }; + + /* Verdin PMIC_I2C (ADC_2 - ADC_1) */ + channel@3 { + reg = <3>; + ti,datarate = <4>; + ti,gain = <2>; + }; + + /* Verdin PMIC_I2C ADC_4 */ + channel@4 { + reg = <4>; + ti,datarate = <4>; + ti,gain = <2>; + }; + + /* Verdin PMIC_I2C ADC_3 */ + channel@5 { + reg = <5>; + ti,datarate = <4>; + ti,gain = <2>; + }; + + /* Verdin PMIC_I2C ADC_2 */ + channel@6 { + reg = <6>; + ti,datarate = <4>; + ti,gain = <2>; + }; + + /* Verdin PMIC_I2C ADC_1 */ + channel@7 { + reg = <7>; + ti,datarate = <4>; + ti,gain = <2>; + }; + }; + + eeprom@50 { + compatible = "st,24c02", "atmel,24c02"; + pagesize = <16>; + reg = <0x50>; + }; +}; + +/* Verdin I2C_1 */ +&main_i2c1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c1>; + status = "disabled"; +}; + +/* Verdin I2C_2_DSI */ +&main_i2c2 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c2>; + status = "disabled"; +}; + +/* Verdin I2C_4_CSI */ +&main_i2c3 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c3>; + status = "disabled"; +}; + +&mailbox0_cluster0 { + mbox_m4_0: mbox-m4-0 { + ti,mbox-rx = <0 0 0>; + ti,mbox-tx = <1 0 0>; + }; +}; + +/* Verdin CAN_1 */ +&main_mcan0 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_mcan0>; + status = "disabled"; +}; + +/* Verdin CAN_2 - Reserved to Cortex-M4 */ + +/* Verdin SPI_1 */ +&main_spi1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_spi1>; + ti,pindir-d0-out-d1-in; + status = "disabled"; +}; + +/* Verdin UART_3, used as the Linux console */ +&main_uart0 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart0>; + status = "disabled"; +}; + +/* Verdin UART_1 */ +&main_uart1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart1>; + status = "disabled"; +}; + +/* Verdin I2S_1 */ +&mcasp0 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_mcasp0>; + op-mode = <0>; /* I2S mode */ + serial-dir = < /* 0: INACTIVE, 1: TX, 2: RX */ + 1 2 0 0 + 0 0 0 0 + 0 0 0 0 + 0 0 0 0 + >; + tdm-slots = <2>; + rx-num-evt = <32>; + tx-num-evt = <32>; + #sound-dai-cells = <0>; + status = "disabled"; +}; + +/* Verdin I2S_2 */ +&mcasp1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_mcasp1>; + op-mode = <0>; /* I2S mode */ + serial-dir = < /* 0: INACTIVE, 1: TX, 2: RX */ + 1 2 0 0 + 0 0 0 0 + 0 0 0 0 + 0 0 0 0 + >; + tdm-slots = <2>; + rx-num-evt = <32>; + tx-num-evt = <32>; + #sound-dai-cells = <0>; + status = "disabled"; +}; + +/* Verdin I2C_3_HDMI */ +&mcu_i2c0 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_mcu_i2c0>; + status = "disabled"; +}; + +&mcu_gpio0 { + gpio-line-names = + "SODIMM_244", + "SODIMM_206", + "SODIMM_208", + "SODIMM_210", + "SODIMM_212", + "", + "", + "", + "", + "", + "", + "", + "", + "", + "", + "", + "", + "", + "", + "", + "", + "", + "", + ""; +}; + +/* Verdin UART_4 - Cortex-M4 UART */ +&mcu_uart0 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_mcu_uart0>; + status = "disabled"; +}; + +/* Verdin QSPI_1 */ +&ospi0 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_ospi0>; + status = "disabled"; +}; + +/* On-module eMMC */ +&sdhci0 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_sdhci0>; + non-removable; + ti,driver-strength-ohm = <50>; + status = "okay"; +}; + +/* Verdin SD_1 */ +&sdhci1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_sdhci1>; + disable-wp; + ti,driver-strength-ohm = <50>; + vmmc-supply = <®_sdhc1_vmmc>; + vqmmc-supply = <®_sdhc1_vqmmc>; + status = "disabled"; +}; + +/* Verdin USB_1 */ +&usbss0 { + ti,vbus-divider; + status = "disabled"; +}; + +/* TODO: role swich using ID pin */ +&usb0 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usb0>, <&pinctrl_usb0_id>; + status = "disabled"; +}; + +/* Verdin USB_2 */ +&usbss1 { + ti,vbus-divider; + status = "disabled"; +}; + +&usb1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usb1>; + dr_mode = "host"; + status = "disabled"; +}; + +/* Verdin UART_2 */ +&wkup_uart0 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_wkup_uart0>; + status = "disabled"; +}; diff --git a/arch/arm64/boot/dts/ti/k3-am625-verdin-nonwifi-dev.dts b/arch/arm64/boot/dts/ti/k3-am625-verdin-nonwifi-dev.dts new file mode 100644 index 000000000000..31d2a3066d43 --- /dev/null +++ b/arch/arm64/boot/dts/ti/k3-am625-verdin-nonwifi-dev.dts @@ -0,0 +1,22 @@ +// SPDX-License-Identifier: GPL-2.0-or-later OR MIT +/* + * Copyright 2023 Toradex + * + * https://www.toradex.com/computer-on-modules/verdin-arm-family/ti-am62 + * https://www.toradex.com/products/carrier-board/verdin-development-board-kit + */ + +/dts-v1/; + +#include "k3-am625.dtsi" +#include "k3-am62-verdin.dtsi" +#include "k3-am62-verdin-nonwifi.dtsi" +#include "k3-am62-verdin-dev.dtsi" + +/ { + model = "Toradex Verdin AM62 on Verdin Development Board"; + compatible = "toradex,verdin-am62-nonwifi-dev", + "toradex,verdin-am62-nonwifi", + "toradex,verdin-am62", + "ti,am625"; +}; diff --git a/arch/arm64/boot/dts/ti/k3-am625-verdin-wifi-dev.dts b/arch/arm64/boot/dts/ti/k3-am625-verdin-wifi-dev.dts new file mode 100644 index 000000000000..4b657d6d3e0d --- /dev/null +++ b/arch/arm64/boot/dts/ti/k3-am625-verdin-wifi-dev.dts @@ -0,0 +1,22 @@ +// SPDX-License-Identifier: GPL-2.0-or-later OR MIT +/* + * Copyright 2023 Toradex + * + * https://www.toradex.com/computer-on-modules/verdin-arm-family/ti-am62 + * https://www.toradex.com/products/carrier-board/verdin-development-board-kit + */ + +/dts-v1/; + +#include "k3-am625.dtsi" +#include "k3-am62-verdin.dtsi" +#include "k3-am62-verdin-wifi.dtsi" +#include "k3-am62-verdin-dev.dtsi" + +/ { + model = "Toradex Verdin AM62 WB on Verdin Development Board"; + compatible = "toradex,verdin-am62-wifi-dev", + "toradex,verdin-am62-wifi", + "toradex,verdin-am62", + "ti,am625"; +}; -- cgit From 50e3424fbb77c853d14143949cdc1c6a8152c479 Mon Sep 17 00:00:00 2001 From: Francesco Dolcini Date: Thu, 15 Jun 2023 11:50:57 +0200 Subject: arm64: dts: ti: add verdin am62 dahlia Add Toradex Verdin AM62 Dahlia. Link: https://www.toradex.com/products/carrier-board/dahlia-carrier-board-kit Signed-off-by: Francesco Dolcini Link: https://lore.kernel.org/r/20230615095058.33890-5-francesco@dolcini.it Signed-off-by: Vignesh Raghavendra --- arch/arm64/boot/dts/ti/Makefile | 2 + arch/arm64/boot/dts/ti/k3-am62-verdin-dahlia.dtsi | 161 +++++++++++++++++++++ .../boot/dts/ti/k3-am625-verdin-nonwifi-dahlia.dts | 22 +++ .../boot/dts/ti/k3-am625-verdin-wifi-dahlia.dts | 22 +++ 4 files changed, 207 insertions(+) create mode 100644 arch/arm64/boot/dts/ti/k3-am62-verdin-dahlia.dtsi create mode 100644 arch/arm64/boot/dts/ti/k3-am625-verdin-nonwifi-dahlia.dts create mode 100644 arch/arm64/boot/dts/ti/k3-am625-verdin-wifi-dahlia.dts diff --git a/arch/arm64/boot/dts/ti/Makefile b/arch/arm64/boot/dts/ti/Makefile index 2b8ec3546273..c6ba52bbca1c 100644 --- a/arch/arm64/boot/dts/ti/Makefile +++ b/arch/arm64/boot/dts/ti/Makefile @@ -12,7 +12,9 @@ dtb-$(CONFIG_ARCH_K3) += k3-am625-beagleplay.dtb dtb-$(CONFIG_ARCH_K3) += k3-am625-phyboard-lyra-rdk.dtb dtb-$(CONFIG_ARCH_K3) += k3-am625-sk.dtb +dtb-$(CONFIG_ARCH_K3) += k3-am625-verdin-nonwifi-dahlia.dtb dtb-$(CONFIG_ARCH_K3) += k3-am625-verdin-nonwifi-dev.dtb +dtb-$(CONFIG_ARCH_K3) += k3-am625-verdin-wifi-dahlia.dtb dtb-$(CONFIG_ARCH_K3) += k3-am625-verdin-wifi-dev.dtb dtb-$(CONFIG_ARCH_K3) += k3-am62-lp-sk.dtb diff --git a/arch/arm64/boot/dts/ti/k3-am62-verdin-dahlia.dtsi b/arch/arm64/boot/dts/ti/k3-am62-verdin-dahlia.dtsi new file mode 100644 index 000000000000..3abd8d1d6761 --- /dev/null +++ b/arch/arm64/boot/dts/ti/k3-am62-verdin-dahlia.dtsi @@ -0,0 +1,161 @@ +// SPDX-License-Identifier: GPL-2.0-or-later OR MIT +/* + * Copyright 2023 Toradex + * + * Common dtsi for Verdin AM62 SoM on Dahlia carrier board + * + * https://www.toradex.com/computer-on-modules/verdin-arm-family/ti-am62 + * https://www.toradex.com/products/carrier-board/dahlia-carrier-board-kit + */ + +/* Verdin ETHs */ +&cpsw3g { + status = "okay"; +}; + +/* MDIO, shared by Verdin ETH_1 (On-module PHY) and Verdin ETH_2_RGMII */ +&cpsw3g_mdio { + status = "okay"; +}; + +/* Verdin ETH_1 (On-module PHY) */ +&cpsw_port1 { + status = "okay"; +}; + +/* Verdin PWM_1, PWM_2 */ +&epwm0 { + status = "okay"; +}; + +/* Verdin PWM_3_DSI */ +&epwm1 { + status = "okay"; +}; + +&main_gpio0 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_ctrl_sleep_moci>, + <&pinctrl_gpio_5>, + <&pinctrl_gpio_6>, + <&pinctrl_gpio_7>, + <&pinctrl_gpio_8>; +}; + +/* Verdin I2C_1 */ +&main_i2c1 { + status = "okay"; + + /* Current measurement into module VCC */ + hwmon@40 { + compatible = "ti,ina219"; + reg = <0x40>; + shunt-resistor = <10000>; + }; + + /* Temperature sensor */ + sensor@4f { + compatible = "ti,tmp75c"; + reg = <0x4f>; + }; + + /* EEPROM */ + eeprom@57 { + compatible = "st,24c02"; + reg = <0x57>; + pagesize = <16>; + }; +}; + +/* Verdin I2C_2_DSI */ +&main_i2c2 { + status = "okay"; +}; + +/* Verdin I2C_4_CSI */ +&main_i2c3 { + status = "okay"; +}; + +/* Verdin CAN_1 */ +&main_mcan0 { + status = "okay"; +}; + +/* Verdin SPI_1 */ +&main_spi1 { + status = "okay"; +}; + +/* Verdin UART_3 */ +&main_uart0 { + status = "okay"; +}; + +/* Verdin UART_1 */ +&main_uart1 { + status = "okay"; +}; + +/* Verdin I2S_1 */ +&mcasp0 { + status = "okay"; +}; + +&mcu_gpio0 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_gpio_1>, + <&pinctrl_gpio_2>, + <&pinctrl_gpio_3>, + <&pinctrl_gpio_4>; +}; + +/* Verdin I2C_3_HDMI */ +&mcu_i2c0 { + status = "okay"; +}; + +/* Verdin UART_4 */ +&mcu_uart0 { + status = "okay"; +}; + +/* Verdin QSPI_1 */ +&ospi0 { + status = "okay"; +}; + +/* Verdin SD_1 */ +&sdhci1 { + ti,driver-strength-ohm = <33>; + status = "okay"; +}; + +/* Verdin USB_1 */ +&usbss0 { + status = "okay"; +}; + +&usb0 { + status = "okay"; +}; + +/* Verdin USB_2 */ +&usbss1 { + status = "okay"; +}; + +&usb1 { + status = "okay"; +}; + +/* Verdin CTRL_WAKE1_MICO# */ +&verdin_gpio_keys { + status = "okay"; +}; + +/* Verdin UART_2 */ +&wkup_uart0 { + /* FIXME: WKUP UART0 is used by DM firmware */ + status = "reserved"; +}; diff --git a/arch/arm64/boot/dts/ti/k3-am625-verdin-nonwifi-dahlia.dts b/arch/arm64/boot/dts/ti/k3-am625-verdin-nonwifi-dahlia.dts new file mode 100644 index 000000000000..d38bfef29d71 --- /dev/null +++ b/arch/arm64/boot/dts/ti/k3-am625-verdin-nonwifi-dahlia.dts @@ -0,0 +1,22 @@ +// SPDX-License-Identifier: GPL-2.0-or-later OR MIT +/* + * Copyright 2023 Toradex + * + * https://www.toradex.com/computer-on-modules/verdin-arm-family/ti-am62 + * https://www.toradex.com/products/carrier-board/dahlia-carrier-board-kit + */ + +/dts-v1/; + +#include "k3-am625.dtsi" +#include "k3-am62-verdin.dtsi" +#include "k3-am62-verdin-nonwifi.dtsi" +#include "k3-am62-verdin-dahlia.dtsi" + +/ { + model = "Toradex Verdin AM62 on Dahlia Board"; + compatible = "toradex,verdin-am62-nonwifi-dahlia", + "toradex,verdin-am62-nonwifi", + "toradex,verdin-am62", + "ti,am625"; +}; diff --git a/arch/arm64/boot/dts/ti/k3-am625-verdin-wifi-dahlia.dts b/arch/arm64/boot/dts/ti/k3-am625-verdin-wifi-dahlia.dts new file mode 100644 index 000000000000..3850a706edb7 --- /dev/null +++ b/arch/arm64/boot/dts/ti/k3-am625-verdin-wifi-dahlia.dts @@ -0,0 +1,22 @@ +// SPDX-License-Identifier: GPL-2.0-or-later OR MIT +/* + * Copyright 2023 Toradex + * + * https://www.toradex.com/computer-on-modules/verdin-arm-family/ti-am62 + * https://www.toradex.com/products/carrier-board/dahlia-carrier-board-kit + */ + +/dts-v1/; + +#include "k3-am625.dtsi" +#include "k3-am62-verdin.dtsi" +#include "k3-am62-verdin-wifi.dtsi" +#include "k3-am62-verdin-dahlia.dtsi" + +/ { + model = "Toradex Verdin AM62 WB on Dahlia Board"; + compatible = "toradex,verdin-am62-wifi-dahlia", + "toradex,verdin-am62-wifi", + "toradex,verdin-am62", + "ti,am625"; +}; -- cgit From 7f066473e49ace276274336cd95f3c828ae4d2f8 Mon Sep 17 00:00:00 2001 From: Francesco Dolcini Date: Thu, 15 Jun 2023 11:50:58 +0200 Subject: arm64: dts: ti: add verdin am62 yavia Add Toradex Verdin AM62 Yavia. Link: https://www.toradex.com/products/carrier-board/yavia Signed-off-by: Francesco Dolcini Link: https://lore.kernel.org/r/20230615095058.33890-6-francesco@dolcini.it Signed-off-by: Vignesh Raghavendra --- arch/arm64/boot/dts/ti/Makefile | 2 + arch/arm64/boot/dts/ti/k3-am62-verdin-yavia.dtsi | 207 +++++++++++++++++++++ .../boot/dts/ti/k3-am625-verdin-nonwifi-yavia.dts | 22 +++ .../boot/dts/ti/k3-am625-verdin-wifi-yavia.dts | 22 +++ 4 files changed, 253 insertions(+) create mode 100644 arch/arm64/boot/dts/ti/k3-am62-verdin-yavia.dtsi create mode 100644 arch/arm64/boot/dts/ti/k3-am625-verdin-nonwifi-yavia.dts create mode 100644 arch/arm64/boot/dts/ti/k3-am625-verdin-wifi-yavia.dts diff --git a/arch/arm64/boot/dts/ti/Makefile b/arch/arm64/boot/dts/ti/Makefile index c6ba52bbca1c..6dd7b6f1d6ab 100644 --- a/arch/arm64/boot/dts/ti/Makefile +++ b/arch/arm64/boot/dts/ti/Makefile @@ -14,8 +14,10 @@ dtb-$(CONFIG_ARCH_K3) += k3-am625-phyboard-lyra-rdk.dtb dtb-$(CONFIG_ARCH_K3) += k3-am625-sk.dtb dtb-$(CONFIG_ARCH_K3) += k3-am625-verdin-nonwifi-dahlia.dtb dtb-$(CONFIG_ARCH_K3) += k3-am625-verdin-nonwifi-dev.dtb +dtb-$(CONFIG_ARCH_K3) += k3-am625-verdin-nonwifi-yavia.dtb dtb-$(CONFIG_ARCH_K3) += k3-am625-verdin-wifi-dahlia.dtb dtb-$(CONFIG_ARCH_K3) += k3-am625-verdin-wifi-dev.dtb +dtb-$(CONFIG_ARCH_K3) += k3-am625-verdin-wifi-yavia.dtb dtb-$(CONFIG_ARCH_K3) += k3-am62-lp-sk.dtb # Boards with AM62Ax SoC diff --git a/arch/arm64/boot/dts/ti/k3-am62-verdin-yavia.dtsi b/arch/arm64/boot/dts/ti/k3-am62-verdin-yavia.dtsi new file mode 100644 index 000000000000..cb11d6e7f525 --- /dev/null +++ b/arch/arm64/boot/dts/ti/k3-am62-verdin-yavia.dtsi @@ -0,0 +1,207 @@ +// SPDX-License-Identifier: GPL-2.0-or-later OR MIT +/* + * Copyright 2023 Toradex + * + * Common dtsi for Verdin AM62 SoM on Yavia carrier board + * + * https://www.toradex.com/computer-on-modules/verdin-arm-family/ti-am62 + * https://www.toradex.com/products/carrier-board/yavia + */ + +#include + +/ { + leds { + compatible = "gpio-leds"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_qspi1_clk_gpio>, + <&pinctrl_qspi1_cs_gpio>, + <&pinctrl_qspi1_io0_gpio>, + <&pinctrl_qspi1_io1_gpio>, + <&pinctrl_qspi1_io2_gpio>, + <&pinctrl_qspi1_io3_gpio>; + + /* SODIMM 52 - LD1_RED */ + led-0 { + color = ; + function = LED_FUNCTION_DEBUG; + function-enumerator = <1>; + gpios = <&main_gpio0 0 GPIO_ACTIVE_HIGH>; + }; + /* SODIMM 54 - LD1_GREEN */ + led-1 { + color = ; + function = LED_FUNCTION_DEBUG; + function-enumerator = <1>; + gpios = <&main_gpio0 11 GPIO_ACTIVE_HIGH>; + }; + /* SODIMM 56 - LD1_BLUE */ + led-2 { + color = ; + function = LED_FUNCTION_DEBUG; + function-enumerator = <1>; + gpios = <&main_gpio0 3 GPIO_ACTIVE_HIGH>; + }; + /* SODIMM 58 - LD2_RED */ + led-3 { + color = ; + function = LED_FUNCTION_DEBUG; + function-enumerator = <2>; + gpios = <&main_gpio0 4 GPIO_ACTIVE_HIGH>; + }; + /* SODIMM 60 - LD2_GREEN */ + led-4 { + color = ; + function = LED_FUNCTION_DEBUG; + function-enumerator = <2>; + gpios = <&main_gpio0 5 GPIO_ACTIVE_HIGH>; + }; + /* SODIMM 62 - LD2_BLUE */ + led-5 { + color = ; + function = LED_FUNCTION_DEBUG; + function-enumerator = <2>; + gpios = <&main_gpio0 6 GPIO_ACTIVE_HIGH>; + }; + }; +}; + +/* Verdin ETHs */ +&cpsw3g { + status = "okay"; +}; + +/* MDIO, shared by Verdin ETH_1 (On-module PHY) and Verdin ETH_2_RGMII */ +&cpsw3g_mdio { + status = "okay"; +}; + +/* Verdin ETH_1 (On-module PHY) */ +&cpsw_port1 { + status = "okay"; +}; + +/* Verdin PWM_1, PWM_2 */ +&epwm0 { + status = "okay"; +}; + +/* Verdin PWM_3_DSI */ +&epwm1 { + status = "okay"; +}; + +&main_gpio0 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_ctrl_sleep_moci>, + <&pinctrl_gpio_5>, + <&pinctrl_gpio_6>, + <&pinctrl_gpio_7>, + <&pinctrl_gpio_8>, + <&pinctrl_qspi1_cs2_gpio>; +}; + +&main_gpio1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_qspi1_dqs_gpio>; +}; + +/* Verdin I2C_1 */ +&main_i2c1 { + status = "okay"; + + /* Temperature sensor */ + sensor@4f { + compatible = "ti,tmp75c"; + reg = <0x4f>; + }; + + /* EEPROM */ + eeprom@57 { + compatible = "st,24c02"; + reg = <0x57>; + pagesize = <16>; + }; +}; + +/* Verdin I2C_2_DSI */ +&main_i2c2 { + status = "okay"; +}; + +/* Verdin I2C_4_CSI */ +&main_i2c3 { + status = "okay"; +}; + +/* Verdin CAN_1 */ +&main_mcan0 { + status = "okay"; +}; + +/* Verdin SPI_1 */ +&main_spi1 { + status = "okay"; +}; + +/* Verdin UART_3 */ +&main_uart0 { + status = "okay"; +}; + +/* Verdin UART_1 */ +&main_uart1 { + status = "okay"; +}; + +&mcu_gpio0 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_gpio_1>, + <&pinctrl_gpio_2>, + <&pinctrl_gpio_3>, + <&pinctrl_gpio_4>; +}; + +/* Verdin I2C_3_HDMI */ +&mcu_i2c0 { + status = "okay"; +}; + +/* Verdin UART_4 */ +&mcu_uart0 { + status = "okay"; +}; + +/* Verdin SD_1 */ +&sdhci1 { + status = "okay"; +}; + +/* Verdin USB_1 */ +&usbss0 { + status = "okay"; +}; + +&usb0 { + status = "okay"; +}; + +/* Verdin USB_2 */ +&usbss1 { + status = "okay"; +}; + +&usb1 { + status = "okay"; +}; + +/* Verdin CTRL_WAKE1_MICO# */ +&verdin_gpio_keys { + status = "okay"; +}; + +/* Verdin UART_2 */ +&wkup_uart0 { + /* FIXME: WKUP UART0 is used by DM firmware */ + status = "reserved"; +}; diff --git a/arch/arm64/boot/dts/ti/k3-am625-verdin-nonwifi-yavia.dts b/arch/arm64/boot/dts/ti/k3-am625-verdin-nonwifi-yavia.dts new file mode 100644 index 000000000000..e80332e1f030 --- /dev/null +++ b/arch/arm64/boot/dts/ti/k3-am625-verdin-nonwifi-yavia.dts @@ -0,0 +1,22 @@ +// SPDX-License-Identifier: GPL-2.0-or-later OR MIT +/* + * Copyright 2023 Toradex + * + * https://www.toradex.com/computer-on-modules/verdin-arm-family/ti-am62 + * https://www.toradex.com/products/carrier-board/yavia + */ + +/dts-v1/; + +#include "k3-am625.dtsi" +#include "k3-am62-verdin.dtsi" +#include "k3-am62-verdin-nonwifi.dtsi" +#include "k3-am62-verdin-yavia.dtsi" + +/ { + model = "Toradex Verdin AM62 on Yavia Board"; + compatible = "toradex,verdin-am62-nonwifi-yavia", + "toradex,verdin-am62-nonwifi", + "toradex,verdin-am62", + "ti,am625"; +}; diff --git a/arch/arm64/boot/dts/ti/k3-am625-verdin-wifi-yavia.dts b/arch/arm64/boot/dts/ti/k3-am625-verdin-wifi-yavia.dts new file mode 100644 index 000000000000..8a2506068ac4 --- /dev/null +++ b/arch/arm64/boot/dts/ti/k3-am625-verdin-wifi-yavia.dts @@ -0,0 +1,22 @@ +// SPDX-License-Identifier: GPL-2.0-or-later OR MIT +/* + * Copyright 2023 Toradex + * + * https://www.toradex.com/computer-on-modules/verdin-arm-family/ti-am62 + * https://www.toradex.com/products/carrier-board/yavia + */ + +/dts-v1/; + +#include "k3-am625.dtsi" +#include "k3-am62-verdin.dtsi" +#include "k3-am62-verdin-wifi.dtsi" +#include "k3-am62-verdin-yavia.dtsi" + +/ { + model = "Toradex Verdin AM62 WB on Yavia Board"; + compatible = "toradex,verdin-am62-wifi-yavia", + "toradex,verdin-am62-wifi", + "toradex,verdin-am62", + "ti,am625"; +}; -- cgit From a49568115143435390f20965902809471b6f830c Mon Sep 17 00:00:00 2001 From: Tony Lindgren Date: Thu, 15 Jun 2023 19:34:06 +0530 Subject: arm64: dts: ti: Unify pin group node names for make dtbs checks Prepare for pinctrl-single yaml binding and unify pin group node names. Let's standardize on pin group node naming ending in -pins. As we don't necessarily have a SoC specific compatible property for pinctrl-single. I'd rather not add a pattern match for pins somewhere in the name for all the users. Trying to add matches for pins-default will be futile as on the earlier SoCs we've already seen names like pins-sleep, pins-idle, pins-off and so on that would need to be matched. And as the node is a pin group, let's prefer to use naming -pins rather than -pin as more pins may need to be added to the pin group later on. Signed-off-by: Tony Lindgren [vigneshr@ti.com: Rebase onto latest ti/next and extend to new nodes] Signed-off-by: Vignesh Raghavendra --- arch/arm64/boot/dts/ti/k3-am62-lp-sk.dts | 6 +- arch/arm64/boot/dts/ti/k3-am62-phycore-som.dtsi | 14 +-- arch/arm64/boot/dts/ti/k3-am62-verdin.dtsi | 138 ++++++++++----------- arch/arm64/boot/dts/ti/k3-am625-beagleplay.dts | 52 ++++---- .../boot/dts/ti/k3-am625-phyboard-lyra-rdk.dts | 20 +-- arch/arm64/boot/dts/ti/k3-am625-sk.dts | 8 +- arch/arm64/boot/dts/ti/k3-am62a7-sk.dts | 22 ++-- arch/arm64/boot/dts/ti/k3-am62x-sk-common.dtsi | 26 ++-- arch/arm64/boot/dts/ti/k3-am64-phycore-som.dtsi | 12 +- arch/arm64/boot/dts/ti/k3-am642-evm.dts | 30 ++--- .../boot/dts/ti/k3-am642-phyboard-electra-rdk.dts | 26 ++-- arch/arm64/boot/dts/ti/k3-am642-sk.dts | 28 ++--- arch/arm64/boot/dts/ti/k3-am65-iot2050-common.dtsi | 48 +++---- .../dts/ti/k3-am6528-iot2050-basic-common.dtsi | 2 +- arch/arm64/boot/dts/ti/k3-am654-base-board.dts | 36 +++--- .../dts/ti/k3-am6548-iot2050-advanced-common.dtsi | 2 +- .../boot/dts/ti/k3-am6548-iot2050-advanced-m2.dts | 6 +- arch/arm64/boot/dts/ti/k3-am68-sk-base-board.dts | 34 ++--- arch/arm64/boot/dts/ti/k3-am68-sk-som.dtsi | 2 +- arch/arm64/boot/dts/ti/k3-am69-sk.dts | 26 ++-- .../boot/dts/ti/k3-j7200-common-proc-board.dts | 24 ++-- .../dts/ti/k3-j7200-evm-quad-port-eth-exp.dtso | 2 +- arch/arm64/boot/dts/ti/k3-j7200-som-p0.dtsi | 8 +- arch/arm64/boot/dts/ti/k3-j721e-beagleboneai64.dts | 58 ++++----- .../boot/dts/ti/k3-j721e-common-proc-board.dts | 62 ++++----- .../dts/ti/k3-j721e-evm-quad-port-eth-exp.dtso | 2 +- arch/arm64/boot/dts/ti/k3-j721e-sk.dts | 52 ++++---- arch/arm64/boot/dts/ti/k3-j721e-som-p0.dtsi | 6 +- .../boot/dts/ti/k3-j721s2-common-proc-board.dts | 32 ++--- arch/arm64/boot/dts/ti/k3-j721s2-som-p0.dtsi | 8 +- arch/arm64/boot/dts/ti/k3-j784s4-evm.dts | 26 ++-- 31 files changed, 409 insertions(+), 409 deletions(-) diff --git a/arch/arm64/boot/dts/ti/k3-am62-lp-sk.dts b/arch/arm64/boot/dts/ti/k3-am62-lp-sk.dts index 4b94f7a86316..5e6feb8cd125 100644 --- a/arch/arm64/boot/dts/ti/k3-am62-lp-sk.dts +++ b/arch/arm64/boot/dts/ti/k3-am62-lp-sk.dts @@ -73,19 +73,19 @@ }; &main_pmx0 { - vddshv_sdio_pins_default: vddshv-sdio-pins-default { + vddshv_sdio_pins_default: vddshv-sdio-default-pins { pinctrl-single,pins = < AM62X_IOPAD(0x07c, PIN_OUTPUT, 7) /* (M19) GPMC0_CLK.GPIO0_31 */ >; }; - main_gpio1_ioexp_intr_pins_default: main-gpio1-ioexp-intr-pins-default { + main_gpio1_ioexp_intr_pins_default: main-gpio1-ioexp-intr-default-pins { pinctrl-single,pins = < AM62X_IOPAD(0x01d4, PIN_INPUT, 7) /* (C13) UART0_RTSn.GPIO1_23 */ >; }; - pmic_irq_pins_default: pmic-irq-pins-default { + pmic_irq_pins_default: pmic-irq-default-pins { pinctrl-single,pins = < AM62X_IOPAD(0x01f4, PIN_INPUT, 0) /* (B16) EXTINTn */ >; diff --git a/arch/arm64/boot/dts/ti/k3-am62-phycore-som.dtsi b/arch/arm64/boot/dts/ti/k3-am62-phycore-som.dtsi index 056ffe6f6f6a..aa43e7407eee 100644 --- a/arch/arm64/boot/dts/ti/k3-am62-phycore-som.dtsi +++ b/arch/arm64/boot/dts/ti/k3-am62-phycore-som.dtsi @@ -98,27 +98,27 @@ }; &main_pmx0 { - leds_pins_default: leds-pins-default { + leds_pins_default: leds-default-pins { pinctrl-single,pins = < AM62X_IOPAD(0x034, PIN_OUTPUT, 7) /* (H21) OSPI0_CSN2.GPIO0_13 */ >; }; - main_i2c0_pins_default: main-i2c0-pins-default { + main_i2c0_pins_default: main-i2c0-default-pins { pinctrl-single,pins = < AM62X_IOPAD(0x1e0, PIN_INPUT_PULLUP, 0) /* (B16) I2C0_SCL */ AM62X_IOPAD(0x1e4, PIN_INPUT_PULLUP, 0) /* (A16) I2C0_SDA */ >; }; - main_mdio1_pins_default: main-mdio1-pins-default { + main_mdio1_pins_default: main-mdio1-default-pins { pinctrl-single,pins = < AM62X_IOPAD(0x160, PIN_OUTPUT, 0) /* (AD24) MDIO0_MDC */ AM62X_IOPAD(0x15c, PIN_INPUT, 0) /* (AB22) MDIO0_MDIO */ >; }; - main_mmc0_pins_default: main-mmc0-pins-default { + main_mmc0_pins_default: main-mmc0-default-pins { pinctrl-single,pins = < AM62X_IOPAD(0x220, PIN_INPUT_PULLUP, 0) /* (Y3) MMC0_CMD */ AM62X_IOPAD(0x218, PIN_INPUT_PULLDOWN, 0) /* (AB1) MMC0_CLK */ @@ -133,7 +133,7 @@ >; }; - main_rgmii1_pins_default: main-rgmii1-pins-default { + main_rgmii1_pins_default: main-rgmii1-default-pins { pinctrl-single,pins = < AM62X_IOPAD(0x14c, PIN_INPUT, 0) /* (AB17) RGMII1_RD0 */ AM62X_IOPAD(0x150, PIN_INPUT, 0) /* (AC17) RGMII1_RD1 */ @@ -150,7 +150,7 @@ >; }; - ospi0_pins_default: ospi0-pins-default { + ospi0_pins_default: ospi0-default-pins { pinctrl-single,pins = < AM62X_IOPAD(0x000, PIN_OUTPUT, 0) /* (H24) OSPI0_CLK */ AM62X_IOPAD(0x02c, PIN_OUTPUT, 0) /* (F23) OSPI0_CSn0 */ @@ -166,7 +166,7 @@ >; }; - pmic_irq_pins_default: pmic-irq-pins-default { + pmic_irq_pins_default: pmic-irq-default-pins { pinctrl-single,pins = < AM62X_IOPAD(0x01f4, PIN_INPUT, 0) /* (D16) EXTINTn */ >; diff --git a/arch/arm64/boot/dts/ti/k3-am62-verdin.dtsi b/arch/arm64/boot/dts/ti/k3-am62-verdin.dtsi index 432968bd7ec3..57dd061911ab 100644 --- a/arch/arm64/boot/dts/ti/k3-am62-verdin.dtsi +++ b/arch/arm64/boot/dts/ti/k3-am62-verdin.dtsi @@ -176,259 +176,259 @@ &main_pmx0 { /* Verdin PWM_1 */ - pinctrl_epwm0_a: main-epwm0a-pins-default { + pinctrl_epwm0_a: main-epwm0a-default-pins { pinctrl-single,pins = < AM62X_IOPAD(0x01b4, PIN_OUTPUT, 2) /* (A13) SPI0_CS0.EHRPWM0_A */ /* SODIMM 15 */ >; }; /* Verdin PWM_2 */ - pinctrl_epwm0_b: main-epwm0b-pins-default { + pinctrl_epwm0_b: main-epwm0b-default-pins { pinctrl-single,pins = < AM62X_IOPAD(0x01b8, PIN_OUTPUT, 2) /* (C13) SPI0_CS1.EHRPWM0_B */ /* SODIMM 16 */ >; }; /* Verdin PWM_3_DSI */ - pinctrl_epwm1_a: main-epwm1a-pins-default { + pinctrl_epwm1_a: main-epwm1a-default-pins { pinctrl-single,pins = < AM62X_IOPAD(0x01bc, PIN_OUTPUT, 2) /* (A14) SPI0_CLK.EHRPWM1_A */ /* SODIMM 19 */ >; }; /* Verdin QSPI_1_CLK as GPIO (conflict with Verdin QSPI_1 interface) */ - pinctrl_qspi1_clk_gpio: main-gpio0-0-pins-default { + pinctrl_qspi1_clk_gpio: main-gpio0-0-default-pins { pinctrl-single,pins = < AM62X_IOPAD(0x0000, PIN_INPUT, 7) /* (H24) OSPI0_CLK.GPIO0_0 */ /* SODIMM 52 */ >; }; /* Verdin QSPI_1_IO0 as GPIO (conflict with Verdin QSPI_1 interface) */ - pinctrl_qspi1_io0_gpio: main-gpio0-3-pins-default { + pinctrl_qspi1_io0_gpio: main-gpio0-3-default-pins { pinctrl-single,pins = < AM62X_IOPAD(0x000c, PIN_INPUT, 7) /* (E25) OSPI0_D0.GPIO0_3 */ /* SODIMM 56 */ >; }; /* Verdin QSPI_1_IO1 as GPIO (conflict with Verdin QSPI_1 interface) */ - pinctrl_qspi1_io1_gpio: main-gpio0-4-pins-default { + pinctrl_qspi1_io1_gpio: main-gpio0-4-default-pins { pinctrl-single,pins = < AM62X_IOPAD(0x0010, PIN_INPUT, 7) /* (G24) OSPI0_D1.GPIO0_4 */ /* SODIMM 58 */ >; }; /* Verdin QSPI_1_IO2 as GPIO (conflict with Verdin QSPI_1 interface) */ - pinctrl_qspi1_io2_gpio: main-gpio0-5-pins-default { + pinctrl_qspi1_io2_gpio: main-gpio0-5-default-pins { pinctrl-single,pins = < AM62X_IOPAD(0x0014, PIN_INPUT, 7) /* (F25) OSPI0_D2.GPIO0_5 */ /* SODIMM 60 */ >; }; /* Verdin QSPI_1_IO3 as GPIO (conflict with Verdin QSPI_1 interface) */ - pinctrl_qspi1_io3_gpio: main-gpio0-6-pins-default { + pinctrl_qspi1_io3_gpio: main-gpio0-6-default-pins { pinctrl-single,pins = < AM62X_IOPAD(0x0018, PIN_INPUT, 7) /* (F24) OSPI0_D3.GPIO0_6 */ /* SODIMM 62 */ >; }; /* Verdin QSPI_1_CS# as GPIO (conflict with Verdin QSPI_1 interface) */ - pinctrl_qspi1_cs_gpio: main-gpio0-11-pins-default { + pinctrl_qspi1_cs_gpio: main-gpio0-11-default-pins { pinctrl-single,pins = < AM62X_IOPAD(0x002c, PIN_INPUT, 7) /* (F23) OSPI0_CSn0.GPIO0_11 */ /* SODIMM 54 */ >; }; /* Verdin QSPI_1_CS2# as GPIO (conflict with Verdin QSPI_1 interface) */ - pinctrl_qspi1_cs2_gpio: main-gpio0-12-pins-default { + pinctrl_qspi1_cs2_gpio: main-gpio0-12-default-pins { pinctrl-single,pins = < AM62X_IOPAD(0x0030, PIN_INPUT, 7) /* (G21) OSPI0_CSn1.GPIO0_12 */ /* SODIMM 64 */ >; }; /* WiFi_W_WKUP_HOST# */ - pinctrl_wifi_w_wkup_host: main-gpio0-15-pins-default { + pinctrl_wifi_w_wkup_host: main-gpio0-15-default-pins { pinctrl-single,pins = < AM62X_IOPAD(0x003c, PIN_INPUT, 7) /* (M25) GPMC0_AD0.GPIO0_15 */ /* SODIMM 174 */ >; }; /* WiFi_BT_WKUP_HOST# */ - pinctrl_bt_wkup_host: main-gpio0-16-pins-default { + pinctrl_bt_wkup_host: main-gpio0-16-default-pins { pinctrl-single,pins = < AM62X_IOPAD(0x0040, PIN_INPUT, 7) /* (N23) GPMC0_AD1.GPIO0_16 */ /* SODIMM 172 */ >; }; /* PMIC_ETH_RESET# */ - pinctrl_eth_reset: main-gpio0-17-pins-default { + pinctrl_eth_reset: main-gpio0-17-default-pins { pinctrl-single,pins = < AM62X_IOPAD(0x0044, PIN_INPUT, 7) /* (N24) GPMC0_AD2.GPIO0_17 */ >; }; /* PMIC_BRIDGE_RESET# */ - pinctrl_bridge_reset: main-gpio0-20-pins-default { + pinctrl_bridge_reset: main-gpio0-20-default-pins { pinctrl-single,pins = < AM62X_IOPAD(0x0050, PIN_INPUT, 7) /* (P22) GPMC0_AD5.GPIO0_20 */ >; }; /* PMIC_VSEL_SD */ - pinctrl_vsel_sd: main-gpio0-21-pins-default { + pinctrl_vsel_sd: main-gpio0-21-default-pins { pinctrl-single,pins = < AM62X_IOPAD(0x0054, PIN_INPUT, 7) /* (P21) GPMC0_AD6.GPIO0_21 */ >; }; /* PMIC_EN_WIFI */ - pinctrl_wifi_en: main-gpio0-22-pins-default { + pinctrl_wifi_en: main-gpio0-22-default-pins { pinctrl-single,pins = < AM62X_IOPAD(0x0058, PIN_INPUT, 7) /* (R23) GPMC0_AD7.GPIO0_22 */ >; }; /* PMIC_ETH_INT# */ - pinctrl_eth_int: main-gpio0-25-pins-default { + pinctrl_eth_int: main-gpio0-25-default-pins { pinctrl-single,pins = < AM62X_IOPAD(0x0064, PIN_INPUT_PULLUP, 7) /* (T25) GPMC0_AD10.GPIO0_25 */ >; }; /* WiFi_WKUP_BT# */ - pinctrl_wifi_wkup_bt: main-gpio0-26-pins-default { + pinctrl_wifi_wkup_bt: main-gpio0-26-default-pins { pinctrl-single,pins = < AM62X_IOPAD(0x0068, PIN_INPUT, 7) /* (R21) GPMC0_AD11.GPIO0_26 */ >; }; /* WiFi_WKUP_WLAN# */ - pinctrl_wifi_wkup_wlan: main-gpio0-27-pins-default { + pinctrl_wifi_wkup_wlan: main-gpio0-27-default-pins { pinctrl-single,pins = < AM62X_IOPAD(0x006c, PIN_INPUT, 7) /* (T22) GPMC0_AD12.GPIO0_27 */ >; }; /* Verdin SD_1_PWR_EN */ - pinctrl_sd1_pwr_en: main-gpio0-29-pins-default { + pinctrl_sd1_pwr_en: main-gpio0-29-default-pins { pinctrl-single,pins = < AM62X_IOPAD(0x0074, PIN_INPUT, 7) /* (U25) GPMC0_AD14.GPIO0_29 */ /* SODIMM 76 */ >; }; /* Verdin DSI_1_BKL_EN */ - pinctrl_dsi1_bkl_en: main-gpio0-30-pins-default { + pinctrl_dsi1_bkl_en: main-gpio0-30-default-pins { pinctrl-single,pins = < AM62X_IOPAD(0x0078, PIN_INPUT, 7) /* (U24) GPMC0_AD15.GPIO0_30 */ /* SODIMM 21 */ >; }; /* Verdin CTRL_SLEEP_MOCI# */ - pinctrl_ctrl_sleep_moci: main-gpio0-31-pins-default { + pinctrl_ctrl_sleep_moci: main-gpio0-31-default-pins { pinctrl-single,pins = < AM62X_IOPAD(0x007c, PIN_INPUT, 7) /* (P25) GPMC0_CLK.GPIO0_31 */ /* SODIMM 256 */ >; }; /* Verdin CTRL_WAKE1_MICO# */ - pinctrl_ctrl_wake1_mico: main-gpio0-32-pins-default { + pinctrl_ctrl_wake1_mico: main-gpio0-32-default-pins { pinctrl-single,pins = < AM62X_IOPAD(0x0084, PIN_INPUT_PULLUP, 7) /* (L23) GPMC0_ADVn_ALE.GPIO0_32 */ /* SODIMM 252 */ >; }; /* Verdin I2S_2_D_OUT as GPIO (conflict with Verdin I2S_2 interface) */ - pinctrl_i2s_2_d_out_gpio: main-gpio0-34-pins-default { + pinctrl_i2s_2_d_out_gpio: main-gpio0-34-default-pins { pinctrl-single,pins = < AM62X_IOPAD(0x008c, PIN_INPUT, 7) /* (L25) GPMC0_WEn.GPIO0_34 */ /* SODIMM 46 */ >; }; /* Verdin I2S_2_BCLK as GPIO (conflict with Verdin I2S_2 interface) */ - pinctrl_i2s_2_bclk_gpio: main-gpio0-35-pins-default { + pinctrl_i2s_2_bclk_gpio: main-gpio0-35-default-pins { pinctrl-single,pins = < AM62X_IOPAD(0x0090, PIN_INPUT, 7) /* (M24) GPMC0_BE0n_CLE.GPIO0_35 */ /* SODIMM 42 */ >; }; /* Verdin GPIO_6 */ - pinctrl_gpio_6: main-gpio0-36-pins-default { + pinctrl_gpio_6: main-gpio0-36-default-pins { pinctrl-single,pins = < AM62X_IOPAD(0x0094, PIN_INPUT, 7) /* (N20) GPMC0_BE1n.GPIO0_36 */ /* SODIMM 218 */ >; }; /* Verdin ETH_2_RGMII_INT# */ - pinctrl_eth2_rgmii_int: main-gpio0-38-pins-default { + pinctrl_eth2_rgmii_int: main-gpio0-38-default-pins { pinctrl-single,pins = < AM62X_IOPAD(0x009c, PIN_INPUT, 7) /* (V25) GPMC0_WAIT1.GPIO0_38 */ /* SODIMM 189 */ >; }; /* Verdin GPIO_5 */ - pinctrl_gpio_5: main-gpio0-40-pins-default { + pinctrl_gpio_5: main-gpio0-40-default-pins { pinctrl-single,pins = < AM62X_IOPAD(0x00a4, PIN_INPUT, 7) /* (M22) GPMC0_DIR.GPIO0_40 */ /* SODIMM 216 */ >; }; /* Verdin GPIO_7 */ - pinctrl_gpio_7: main-gpio0-41-pins-default { + pinctrl_gpio_7: main-gpio0-41-default-pins { pinctrl-single,pins = < AM62X_IOPAD(0x00a8, PIN_INPUT, 7) /* (M21) GPMC0_CSn0.GPIO0_41 */ /* SODIMM 220 */ >; }; /* Verdin GPIO_8 */ - pinctrl_gpio_8: main-gpio0-42-pins-default { + pinctrl_gpio_8: main-gpio0-42-default-pins { pinctrl-single,pins = < AM62X_IOPAD(0x00ac, PIN_INPUT, 7) /* (L21) GPMC0_CSn1.GPIO0_42 */ /* SODIMM 222 */ >; }; /* Verdin USB_1_OC# */ - pinctrl_usb1_oc: main-gpio0-71-pins-default { + pinctrl_usb1_oc: main-gpio0-71-default-pins { pinctrl-single,pins = < AM62X_IOPAD(0x0124, PIN_INPUT, 7) /* (A23) MMC2_SDCD.GPIO0_71 */ /* SODIMM 157 */ >; }; /* Verdin USB_2_OC# */ - pinctrl_usb2_oc: main-gpio0-72-pins-default { + pinctrl_usb2_oc: main-gpio0-72-default-pins { pinctrl-single,pins = < AM62X_IOPAD(0x0128, PIN_INPUT, 7) /* (B23) MMC2_SDWP.GPIO0_72 */ /* SODIMM 187 */ >; }; /* Verdin PWM_3_DSI as GPIO */ - pinctrl_pwm3_dsi_gpio: main-gpio1-17-pins-default { + pinctrl_pwm3_dsi_gpio: main-gpio1-17-default-pins { pinctrl-single,pins = < AM62X_IOPAD(0x01bc, PIN_INPUT, 7) /* (A14) SPI0_CLK.GPIO1_17 */ /* SODIMM 19 */ >; }; /* Verdin QSPI_1_DQS as GPIO */ - pinctrl_qspi1_dqs_gpio: main-gpio1-18-pins-default { + pinctrl_qspi1_dqs_gpio: main-gpio1-18-default-pins { pinctrl-single,pins = < AM62X_IOPAD(0x01c0, PIN_INPUT, 7) /* (B13) SPI0_D0.GPIO1_18 */ /* SODIMM 66 */ >; }; /* Verdin USB_1_ID */ - pinctrl_usb0_id: main-gpio1-19-pins-default { + pinctrl_usb0_id: main-gpio1-19-default-pins { pinctrl-single,pins = < AM62X_IOPAD(0x01c4, PIN_INPUT, 7) /* (B14) SPI0_D1.GPIO1_19 */ /* SODIMM 161 */ >; }; /* Verdin DSI_1_INT# (pulled-up as active-low) */ - pinctrl_dsi1_int: main-gpio1-49-pins-default { + pinctrl_dsi1_int: main-gpio1-49-default-pins { pinctrl-single,pins = < AM62X_IOPAD(0x0244, PIN_INPUT_PULLUP, 7) /* (C17) MMC1_SDWP.GPIO1_49 */ /* SODIMM 17 */ >; }; /* On-module I2C - PMIC_I2C */ - pinctrl_i2c0: main-i2c0-pins-default { + pinctrl_i2c0: main-i2c0-default-pins { pinctrl-single,pins = < AM62X_IOPAD(0x01e0, PIN_INPUT, 0) /* (B16) I2C0_SCL */ /* PMIC_I2C_SCL */ AM62X_IOPAD(0x01e4, PIN_INPUT, 0) /* (A16) I2C0_SDA */ /* PMIC_I2C_SDA */ @@ -436,7 +436,7 @@ }; /* Verdin I2C_1 */ - pinctrl_i2c1: main-i2c1-pins-default { + pinctrl_i2c1: main-i2c1-default-pins { pinctrl-single,pins = < AM62X_IOPAD(0x01e8, PIN_INPUT_PULLUP, 0) /* (B17) I2C1_SCL */ /* SODIMM 14 */ AM62X_IOPAD(0x01ec, PIN_INPUT_PULLUP, 0) /* (A17) I2C1_SDA */ /* SODIMM 12 */ @@ -444,7 +444,7 @@ }; /* Verdin I2C_2_DSI */ - pinctrl_i2c2: main-i2c2-pins-default { + pinctrl_i2c2: main-i2c2-default-pins { pinctrl-single,pins = < AM62X_IOPAD(0x00b0, PIN_INPUT, 1) /* (K22) GPMC0_CSn2.I2C2_SCL */ /* SODIMM 55 */ AM62X_IOPAD(0x00b4, PIN_INPUT, 1) /* (K24) GPMC0_CSn3.I2C2_SDA */ /* SODIMM 53 */ @@ -452,7 +452,7 @@ }; /* Verdin I2C_4_CSI */ - pinctrl_i2c3: main-i2c3-pins-default { + pinctrl_i2c3: main-i2c3-default-pins { pinctrl-single,pins = < AM62X_IOPAD(0x01d0, PIN_INPUT, 2) /* (A15) UART0_CTSn.I2C3_SCL */ /* SODIMM 95 */ AM62X_IOPAD(0x01d4, PIN_INPUT, 2) /* (B15) UART0_RTSn.I2C3_SDA */ /* SODIMM 93 */ @@ -460,14 +460,14 @@ }; /* I2S_1_MCLK */ - pinctrl_i2s1_mclk: main-system-audio-ext-reflock1-pins-default { + pinctrl_i2s1_mclk: main-system-audio-ext-reflock1-default-pins { pinctrl-single,pins = < AM62X_IOPAD(0x00a0, PIN_OUTPUT, 1) /* (K25) GPMC0_WPn.AUDIO_EXT_REFCLK1 */ /* SODIMM 38 */ >; }; /* Verdin I2S_1 */ - pinctrl_mcasp0: main-mcasp0-pins-default { + pinctrl_mcasp0: main-mcasp0-default-pins { pinctrl-single,pins = < AM62X_IOPAD(0x01a4, PIN_INPUT, 0) /* (B20) MCASP0_ACLKX */ /* SODIMM 30 */ AM62X_IOPAD(0x01a8, PIN_INPUT, 0) /* (D20) MCASP0_AFSX */ /* SODIMM 32 */ @@ -477,7 +477,7 @@ }; /* Verdin I2S_2 */ - pinctrl_mcasp1: main-mcasp1-pins-default { + pinctrl_mcasp1: main-mcasp1-default-pins { pinctrl-single,pins = < AM62X_IOPAD(0x0090, PIN_INPUT, 2) /* (M24) GPMC0_BE0n_CLE.MCASP1_ACLKX */ /* SODIMM 42 */ AM62X_IOPAD(0x0098, PIN_INPUT, 2) /* (U23) GPMC0_WAIT0.MCASP1_AFSX */ /* SODIMM 44 */ @@ -487,7 +487,7 @@ }; /* Verdin CAN_1 */ - pinctrl_mcan0: main-mcan0-pins-default { + pinctrl_mcan0: main-mcan0-default-pins { pinctrl-single,pins = < AM62X_IOPAD(0x01dc, PIN_INPUT, 0) /* (E15) MCAN0_RX */ /* SODIMM 22 */ AM62X_IOPAD(0x01d8, PIN_OUTPUT, 0) /* (C15) MCAN0_TX */ /* SODIMM 20 */ @@ -495,7 +495,7 @@ }; /* MDIO, shared by Verdin ETH_1 (On-module PHY) and Verdin ETH_2_RGMII */ - pinctrl_mdio: main-mdio1-pins-default { + pinctrl_mdio: main-mdio1-default-pins { pinctrl-single,pins = < AM62X_IOPAD(0x160, PIN_OUTPUT, 0) /* (AD24) MDIO0_MDC */ /* ETH_1_MDC, SODIMM 193 */ AM62X_IOPAD(0x15c, PIN_INPUT, 0) /* (AB22) MDIO0_MDIO */ /* ETH_1_MDIO, SODIMM 191 */ @@ -503,7 +503,7 @@ }; /* On-module eMMC */ - pinctrl_sdhci0: main-mmc0-pins-default { + pinctrl_sdhci0: main-mmc0-default-pins { pinctrl-single,pins = < AM62X_IOPAD(0x220, PIN_INPUT, 0) /* (Y3) MMC0_CMD */ AM62X_IOPAD(0x218, PIN_INPUT, 0) /* (AB1) MMC0_CLK */ @@ -519,7 +519,7 @@ }; /* Verdin SD_1 */ - pinctrl_sdhci1: main-mmc1-pins-default { + pinctrl_sdhci1: main-mmc1-default-pins { pinctrl-single,pins = < AM62X_IOPAD(0x23c, PIN_INPUT, 0) /* (A21) MMC1_CMD */ /* SODIMM 74 */ AM62X_IOPAD(0x234, PIN_INPUT, 0) /* (B22) MMC1_CLK */ /* SODIMM 78 */ @@ -532,7 +532,7 @@ }; /* On-module Wi-Fi on WB SKUs, module-specific SDIO otherwise */ - pinctrl_sdhci2: main-mmc2-pins-default { + pinctrl_sdhci2: main-mmc2-default-pins { pinctrl-single,pins = < AM62X_IOPAD(0x120, PIN_INPUT, 0) /* (C24) MMC2_CMD */ /* WiFi_SDIO_CMD */ AM62X_IOPAD(0x118, PIN_INPUT, 0) /* (D25) MMC2_CLK */ /* WiFi_SDIO_CLK */ @@ -545,7 +545,7 @@ }; /* Verdin QSPI_1 */ - pinctrl_ospi0: main-ospi0-pins-default { + pinctrl_ospi0: main-ospi0-default-pins { pinctrl-single,pins = < AM62X_IOPAD(0x0000, PIN_OUTPUT, 0) /* (H24) OSPI0_CLK */ /* SODIMM 52 */ AM62X_IOPAD(0x002c, PIN_OUTPUT, 0) /* (F23) OSPI0_CSn0 */ /* SODIMM 54 */ @@ -558,7 +558,7 @@ }; /* Verdin ETH_1 RGMII (On-module PHY) */ - pinctrl_rgmii1: main-rgmii1-pins-default { + pinctrl_rgmii1: main-rgmii1-default-pins { pinctrl-single,pins = < AM62X_IOPAD(0x14c, PIN_INPUT, 0) /* (AB17) RGMII1_RD0 */ AM62X_IOPAD(0x150, PIN_INPUT, 0) /* (AC17) RGMII1_RD1 */ @@ -576,7 +576,7 @@ }; /* Verdin ETH_2 RGMII */ - pinctrl_rgmii2: main-rgmii2-pins-default { + pinctrl_rgmii2: main-rgmii2-default-pins { pinctrl-single,pins = < AM62X_IOPAD(0x184, PIN_INPUT, 0) /* (AE23) RGMII2_RD0 */ /* SODIMM 201 */ AM62X_IOPAD(0x188, PIN_INPUT, 0) /* (AB20) RGMII2_RD1 */ /* SODIMM 203 */ @@ -594,7 +594,7 @@ }; /* Verdin SPI_1 */ - pinctrl_spi1: main-spi1-pins-default { + pinctrl_spi1: main-spi1-default-pins { pinctrl-single,pins = < AM62X_IOPAD(0x0020, PIN_INPUT, 1) /* (J25) OSPI0_D5.SPI1_CLK */ /* SODIMM 196 */ AM62X_IOPAD(0x001c, PIN_INPUT, 1) /* (J23) OSPI0_D4.SPI1_CS0 */ /* SODIMM 202 */ @@ -604,21 +604,21 @@ }; /* ETH_25MHz_CLK */ - pinctrl_eth_clock: main-system-clkout0-pins-default { + pinctrl_eth_clock: main-system-clkout0-default-pins { pinctrl-single,pins = < AM62X_IOPAD(0x01f0, PIN_OUTPUT_PULLUP, 5) /* (A18) EXT_REFCLK1.CLKOUT0 */ >; }; /* PMIC_EXTINT# */ - pinctrl_pmic_extint: main-system-extint-pins-default { + pinctrl_pmic_extint: main-system-extint-default-pins { pinctrl-single,pins = < AM62X_IOPAD(0x01f4, PIN_INPUT, 0) /* (D16) EXTINTn */ >; }; /* Verdin UART_3, used as the Linux console */ - pinctrl_uart0: main-uart0-pins-default { + pinctrl_uart0: main-uart0-default-pins { pinctrl-single,pins = < AM62X_IOPAD(0x1c8, PIN_INPUT_PULLUP, 0) /* (D14) UART0_RXD */ /* SODIMM 147 */ AM62X_IOPAD(0x1cc, PIN_OUTPUT, 0) /* (E14) UART0_TXD */ /* SODIMM 149 */ @@ -626,7 +626,7 @@ }; /* Verdin UART_1 */ - pinctrl_uart1: main-uart1-pins-default { + pinctrl_uart1: main-uart1-default-pins { pinctrl-single,pins = < AM62X_IOPAD(0x0194, PIN_INPUT_PULLUP, 2) /* (B19) MCASP0_AXR3.UART1_CTSn */ /* SODIMM 135 */ AM62X_IOPAD(0x0198, PIN_OUTPUT, 2) /* (A19) MCASP0_AXR2.UART1_RTSn */ /* SODIMM 133 */ @@ -636,7 +636,7 @@ }; /* Bluetooth on WB SKUs, module-specific UART otherwise */ - pinctrl_uart5: main-uart5-pins-default { + pinctrl_uart5: main-uart5-default-pins { pinctrl-single,pins = < AM62X_IOPAD(0x0008, PIN_INPUT_PULLUP, 5) /* (J24) OSPI0_DQS.UART5_CTSn */ /* WiFi_UART_CTS */ AM62X_IOPAD(0x0004, PIN_OUTPUT, 5) /* (G25) OSPI0_LBCLKO.UART5_RTSn */ /* WiFi_UART_RTS */ @@ -646,21 +646,21 @@ }; /* Verdin USB_1 */ - pinctrl_usb0: main-usb0-pins-default { + pinctrl_usb0: main-usb0-default-pins { pinctrl-single,pins = < AM62X_IOPAD(0x0254, PIN_OUTPUT, 0) /* (C20) USB0_DRVVBUS */ /* SODIMM 155 */ >; }; /* Verdin USB_2 */ - pinctrl_usb1: main-usb1-pins-default { + pinctrl_usb1: main-usb1-default-pins { pinctrl-single,pins = < AM62X_IOPAD(0x0258, PIN_OUTPUT, 0) /* (F18) USB1_DRVVBUS */ /* SODIMM 185 */ >; }; /* DSS VOUT0 RGB */ - pinctrl_parallel_rgb: main-vout-pins-default { + pinctrl_parallel_rgb: main-vout-default-pins { pinctrl-single,pins = < AM62X_IOPAD(0x0100, PIN_OUTPUT, 0) /* (AC25) VOUT0_VSYNC */ AM62X_IOPAD(0x00f8, PIN_OUTPUT, 0) /* (AB24) VOUT0_HSYNC */ @@ -690,42 +690,42 @@ &mcu_pmx0 { /* Verdin PCIE_1_RESET# */ - pinctrl_pcie_1_reset: mcu-gpio0-0-pins-default { + pinctrl_pcie_1_reset: mcu-gpio0-0-default-pins { pinctrl-single,pins = < AM62X_MCU_IOPAD(0x0000, PIN_INPUT, 7) /* (E8) MCU_SPI0_CS0.MCU_GPIO0_0 */ /* SODIMM 244 */ >; }; /* Verdin GPIO_1 */ - pinctrl_gpio_1: mcu-gpio0-1-pins-default { + pinctrl_gpio_1: mcu-gpio0-1-default-pins { pinctrl-single,pins = < AM62X_MCU_IOPAD(0x0004, PIN_INPUT, 7) /* (B8) MCU_SPI0_CS1.MCU_GPIO0_1 */ /* SODIMM 206 */ >; }; /* Verdin GPIO_2 */ - pinctrl_gpio_2: mcu-gpio0-2-pins-default { + pinctrl_gpio_2: mcu-gpio0-2-default-pins { pinctrl-single,pins = < AM62X_MCU_IOPAD(0x0008, PIN_INPUT, 7) /* (A7) MCU_SPI0_CLK.MCU_GPIO0_2 */ /* SODIMM 208 */ >; }; /* Verdin GPIO_3 */ - pinctrl_gpio_3: mcu-gpio0-3-pins-default { + pinctrl_gpio_3: mcu-gpio0-3-default-pins { pinctrl-single,pins = < AM62X_MCU_IOPAD(0x000c, PIN_INPUT, 7) /* (D9) MCU_SPI0_D0.MCU_GPIO0_3 */ /* SODIMM 210 */ >; }; /* Verdin GPIO_4 */ - pinctrl_gpio_4: mcu-gpio0-4-pins-default { + pinctrl_gpio_4: mcu-gpio0-4-default-pins { pinctrl-single,pins = < AM62X_MCU_IOPAD(0x0010, PIN_INPUT, 7) /* (C9) MCU_SPI0_D1.MCU_GPIO0_4 */ /* SODIMM 212 */ >; }; /* Verdin I2C_3_HDMI */ - pinctrl_mcu_i2c0: mcu-i2c0-pins-default { + pinctrl_mcu_i2c0: mcu-i2c0-default-pins { pinctrl-single,pins = < AM62X_MCU_IOPAD(0x0044, PIN_INPUT, 0) /* (A8) MCU_I2C0_SCL */ /* SODIMM 59 */ AM62X_MCU_IOPAD(0x0048, PIN_INPUT, 0) /* (D10) MCU_I2C0_SDA */ /* SODIMM 57 */ @@ -733,7 +733,7 @@ }; /* Verdin UART_4 - Reserved to Cortex-M4 */ - pinctrl_mcu_uart0: mcu-uart0-pins-default { + pinctrl_mcu_uart0: mcu-uart0-default-pins { pinctrl-single,pins = < AM62X_MCU_IOPAD(0x0014, PIN_INPUT_PULLUP, 0) /* (B5) MCU_UART0_RXD */ /* SODIMM 151 */ AM62X_MCU_IOPAD(0x0018, PIN_OUTPUT, 0) /* (A5) MCU_UART0_TXD */ /* SODIMM 153 */ @@ -741,14 +741,14 @@ }; /* Verdin CSI_1_MCLK */ - pinctrl_csi1_mclk: wkup-clkout0-pins-default { + pinctrl_csi1_mclk: wkup-clkout0-default-pins { pinctrl-single,pins = < AM62X_MCU_IOPAD(0x0084, PIN_OUTPUT, 0) /* (A12) WKUP_CLKOUT0 */ /* SODIMM 91 */ >; }; /* Verdin UART_2 */ - pinctrl_wkup_uart0: wkup-uart0-pins-default { + pinctrl_wkup_uart0: wkup-uart0-default-pins { pinctrl-single,pins = < AM62X_MCU_IOPAD(0x002c, PIN_INPUT_PULLUP, 0) /* (C6) WKUP_UART0_CTSn */ /* SODIMM 143 */ AM62X_MCU_IOPAD(0x0030, PIN_OUTPUT, 0) /* (A4) WKUP_UART0_RTSn */ /* SODIMM 141 */ diff --git a/arch/arm64/boot/dts/ti/k3-am625-beagleplay.dts b/arch/arm64/boot/dts/ti/k3-am625-beagleplay.dts index cb46c38ce2cc..589bf998bc52 100644 --- a/arch/arm64/boot/dts/ti/k3-am625-beagleplay.dts +++ b/arch/arm64/boot/dts/ti/k3-am625-beagleplay.dts @@ -216,7 +216,7 @@ }; &main_pmx0 { - gpio0_pins_default: gpio0-pins-default { + gpio0_pins_default: gpio0-default-pins { pinctrl-single,pins = < AM62X_IOPAD(0x0004, PIN_INPUT, 7) /* (G25) OSPI0_LBCLKO.GPIO0_1 */ AM62X_IOPAD(0x0008, PIN_INPUT, 7) /* (J24) OSPI0_DQS.GPIO0_2 */ @@ -235,47 +235,47 @@ >; }; - vdd_sd_dv_pins_default: vdd-sd-pins-default { + vdd_sd_dv_pins_default: vdd-sd-default-pins { pinctrl-single,pins = < AM62X_IOPAD(0x0244, PIN_OUTPUT, 7) /* (C17) MMC1_SDWP.GPIO1_49 */ >; }; - usr_button_pins_default: usr-button-pins-default { + usr_button_pins_default: usr-button-default-pins { pinctrl-single,pins = < AM62X_IOPAD(0x0048, PIN_INPUT, 7) /* (N25) GPMC0_AD3.GPIO0_18 */ >; }; - grove_pins_default: grove-pins-default { + grove_pins_default: grove-default-pins { pinctrl-single,pins = < AM62X_IOPAD(0x01e8, PIN_INPUT_PULLUP, 0) /* (B17) I2C1_SCL */ AM62X_IOPAD(0x01ec, PIN_INPUT_PULLUP, 0) /* (A17) I2C1_SDA */ >; }; - local_i2c_pins_default: local-i2c-pins-default { + local_i2c_pins_default: local-i2c-default-pins { pinctrl-single,pins = < AM62X_IOPAD(0x01e0, PIN_INPUT_PULLUP, 0) /* (B16) I2C0_SCL */ AM62X_IOPAD(0x01e4, PIN_INPUT_PULLUP, 0) /* (A16) I2C0_SDA */ >; }; - i2c2_1v8_pins_default: i2c2-pins-default { + i2c2_1v8_pins_default: i2c2-default-pins { pinctrl-single,pins = < AM62X_IOPAD(0x00b0, PIN_INPUT_PULLUP, 1) /* (K22) GPMC0_CSn2.I2C2_SCL */ AM62X_IOPAD(0x00b4, PIN_INPUT_PULLUP, 1) /* (K24) GPMC0_CSn3.I2C2_SDA */ >; }; - mdio0_pins_default: mdio0-pins-default { + mdio0_pins_default: mdio0-default-pins { pinctrl-single,pins = < AM62X_IOPAD(0x0160, PIN_OUTPUT, 7) /* (AD24) MDIO0_MDC.GPIO0_86 */ AM62X_IOPAD(0x015c, PIN_INPUT, 7) /* (AB22) MDIO0_MDIO.GPIO0_85 */ >; }; - rgmii1_pins_default: rgmii1-pins-default { + rgmii1_pins_default: rgmii1-default-pins { pinctrl-single,pins = < AM62X_IOPAD(0x014c, PIN_INPUT, 0) /* (AB17) RGMII1_RD0 */ AM62X_IOPAD(0x0150, PIN_INPUT, 0) /* (AC17) RGMII1_RD1 */ @@ -292,7 +292,7 @@ >; }; - emmc_pins_default: emmc-pins-default { + emmc_pins_default: emmc-default-pins { pinctrl-single,pins = < AM62X_IOPAD(0x0220, PIN_INPUT, 0) /* (Y3) MMC0_CMD */ AM62X_IOPAD(0x0218, PIN_INPUT, 0) /* (AB1) MMC0_CLK */ @@ -307,13 +307,13 @@ >; }; - vdd_3v3_sd_pins_default: vdd-3v3-sd-pins-default { + vdd_3v3_sd_pins_default: vdd-3v3-sd-default-pins { pinctrl-single,pins = < AM62X_IOPAD(0x01c4, PIN_INPUT, 7) /* (B14) SPI0_D1_GPIO1_19 */ >; }; - sd_pins_default: sd-pins-default { + sd_pins_default: sd-default-pins { pinctrl-single,pins = < AM62X_IOPAD(0x023c, PIN_INPUT, 0) /* (A21) MMC1_CMD */ AM62X_IOPAD(0x0234, PIN_INPUT, 0) /* (B22) MMC1_CLK */ @@ -325,7 +325,7 @@ >; }; - wifi_pins_default: wifi-pins-default { + wifi_pins_default: wifi-default-pins { pinctrl-single,pins = < AM62X_IOPAD(0x0120, PIN_INPUT, 0) /* (C24) MMC2_CMD */ AM62X_IOPAD(0x0118, PIN_INPUT, 0) /* (D25) MMC2_CLK */ @@ -338,19 +338,19 @@ >; }; - wifi_en_pins_default: wifi-en-pins-default { + wifi_en_pins_default: wifi-en-default-pins { pinctrl-single,pins = < AM62X_IOPAD(0x009c, PIN_OUTPUT, 7) /* (V25) GPMC0_WAIT1.GPIO0_38 */ >; }; - wifi_wlirq_pins_default: wifi-wlirq-pins-default { + wifi_wlirq_pins_default: wifi-wlirq-default-pins { pinctrl-single,pins = < AM62X_IOPAD(0x00a8, PIN_INPUT, 7) /* (M21) GPMC0_CSn0.GPIO0_41 */ >; }; - spe_pins_default: spe-pins-default { + spe_pins_default: spe-default-pins { pinctrl-single,pins = < AM62X_IOPAD(0x0168, PIN_INPUT, 1) /* (AE21) RGMII2_TXC.RMII2_CRS_DV */ AM62X_IOPAD(0x0180, PIN_INPUT, 1) /* (AD23) RGMII2_RXC.RMII2_REF_CLK */ @@ -366,21 +366,21 @@ >; }; - mikrobus_i2c_pins_default: mikrobus-i2c-pins-default { + mikrobus_i2c_pins_default: mikrobus-i2c-default-pins { pinctrl-single,pins = < AM62X_IOPAD(0x01d0, PIN_INPUT_PULLUP, 2) /* (A15) UART0_CTSn.I2C3_SCL */ AM62X_IOPAD(0x01d4, PIN_INPUT_PULLUP, 2) /* (B15) UART0_RTSn.I2C3_SDA */ >; }; - mikrobus_uart_pins_default: mikrobus-uart-pins-default { + mikrobus_uart_pins_default: mikrobus-uart-default-pins { pinctrl-single,pins = < AM62X_IOPAD(0x01d8, PIN_INPUT, 1) /* (C15) MCAN0_TX.UART5_RXD */ AM62X_IOPAD(0x01dc, PIN_OUTPUT, 1) /* (E15) MCAN0_RX.UART5_TXD */ >; }; - mikrobus_spi_pins_default: mikrobus-spi-pins-default { + mikrobus_spi_pins_default: mikrobus-spi-default-pins { pinctrl-single,pins = < AM62X_IOPAD(0x01b0, PIN_INPUT, 1) /* (A20) MCASP0_ACLKR.SPI2_CLK */ AM62X_IOPAD(0x01ac, PIN_INPUT, 1) /* (E19) MCASP0_AFSR.SPI2_CS0 */ @@ -389,7 +389,7 @@ >; }; - mikrobus_gpio_pins_default: mikrobus-gpio-pins-default { + mikrobus_gpio_pins_default: mikrobus-gpio-default-pins { pinctrl-single,pins = < AM62X_IOPAD(0x019c, PIN_INPUT, 7) /* (B18) MCASP0_AXR1.GPIO1_9 */ AM62X_IOPAD(0x01a0, PIN_INPUT, 7) /* (E18) MCASP0_AXR0.GPIO1_10 */ @@ -397,27 +397,27 @@ >; }; - console_pins_default: console-pins-default { + console_pins_default: console-default-pins { pinctrl-single,pins = < AM62X_IOPAD(0x01c8, PIN_INPUT, 0) /* (D14) UART0_RXD */ AM62X_IOPAD(0x01cc, PIN_OUTPUT, 0) /* (E14) UART0_TXD */ >; }; - wifi_debug_uart_pins_default: wifi-debug-uart-pins-default { + wifi_debug_uart_pins_default: wifi-debug-uart-default-pins { pinctrl-single,pins = < AM62X_IOPAD(0x001c, PIN_INPUT, 3) /* (J23) OSPI0_D4.UART6_RXD */ AM62X_IOPAD(0x0020, PIN_OUTPUT, 3) /* (J25) OSPI0_D5.UART6_TXD */ >; }; - usb1_pins_default: usb1-pins-default { + usb1_pins_default: usb1-default-pins { pinctrl-single,pins = < AM62X_IOPAD(0x0258, PIN_INPUT, 0) /* (F18) USB1_DRVVBUS */ >; }; - pmic_irq_pins_default: pmic-irq-pins-default { + pmic_irq_pins_default: pmic-irq-default-pins { pinctrl-single,pins = < AM62X_IOPAD(0x01f4, PIN_INPUT_PULLUP, 0) /* (D16) EXTINTn */ >; @@ -425,7 +425,7 @@ }; &mcu_pmx0 { - i2c_qwiic_pins_default: i2c-qwiic-pins-default { + i2c_qwiic_pins_default: i2c-qwiic-default-pins { pinctrl-single,pins = < AM62X_MCU_IOPAD(0x0044, PIN_INPUT, 0) /* (A8) MCU_I2C0_SCL */ AM62X_MCU_IOPAD(0x0048, PIN_INPUT, 0) /* (D10) MCU_I2C0_SDA */ @@ -438,14 +438,14 @@ >; }; - i2c_csi_pins_default: i2c-csi-pins-default { + i2c_csi_pins_default: i2c-csi-default-pins { pinctrl-single,pins = < AM62X_MCU_IOPAD(0x004c, PIN_INPUT_PULLUP, 0) /* (B9) WKUP_I2C0_SCL */ AM62X_MCU_IOPAD(0x0050, PIN_INPUT_PULLUP, 0) /* (A9) WKUP_I2C0_SDA */ >; }; - wifi_32k_clk: mcu-clk-out-pins-default { + wifi_32k_clk: mcu-clk-out-default-pins { pinctrl-single,pins = < AM62X_MCU_IOPAD(0x0084, PIN_OUTPUT, 0) /* (A12) WKUP_CLKOUT0 */ >; diff --git a/arch/arm64/boot/dts/ti/k3-am625-phyboard-lyra-rdk.dts b/arch/arm64/boot/dts/ti/k3-am625-phyboard-lyra-rdk.dts index 3a10b21fec1b..a438baf542c2 100644 --- a/arch/arm64/boot/dts/ti/k3-am625-phyboard-lyra-rdk.dts +++ b/arch/arm64/boot/dts/ti/k3-am625-phyboard-lyra-rdk.dts @@ -81,33 +81,33 @@ }; &main_pmx0 { - gpio_keys_pins_default: gpio-keys-pins-default { + gpio_keys_pins_default: gpio-keys-default-pins { pinctrl-single,pins = < AM62X_IOPAD(0x1d4, PIN_INPUT, 7) /* (B15) UART0_RTSn.GPIO1_23 */ >; }; - gpio_exp_int_pins_default: gpio-exp-int-pins-default { + gpio_exp_int_pins_default: gpio-exp-int-default-pins { pinctrl-single,pins = < AM62X_IOPAD(0x244, PIN_INPUT, 7) /* (C17) MMC1_SDWP.GPIO1_49 */ >; }; - main_i2c1_pins_default: main-i2c1-pins-default { + main_i2c1_pins_default: main-i2c1-default-pins { pinctrl-single,pins = < AM62X_IOPAD(0x1e8, PIN_INPUT_PULLUP, 0) /* (B17) I2C1_SCL */ AM62X_IOPAD(0x1ec, PIN_INPUT_PULLUP, 0) /* (A17) I2C1_SDA */ >; }; - main_mcan0_pins_default: main-mcan0-pins-default { + main_mcan0_pins_default: main-mcan0-default-pins { pinctrl-single,pins = < AM62X_IOPAD(0x1dc, PIN_INPUT, 0) /* (E15) MCAN0_RX */ AM62X_IOPAD(0x1d8, PIN_OUTPUT, 0) /* (C15) MCAN0_TX */ >; }; - main_mmc1_pins_default: main-mmc1-pins-default { + main_mmc1_pins_default: main-mmc1-default-pins { pinctrl-single,pins = < AM62X_IOPAD(0x23c, PIN_INPUT_PULLUP, 0) /* (A21) MMC1_CMD */ AM62X_IOPAD(0x234, PIN_INPUT_PULLDOWN, 0) /* (B22) MMC1_CLK */ @@ -119,7 +119,7 @@ >; }; - main_rgmii2_pins_default: main-rgmii2-pins-default { + main_rgmii2_pins_default: main-rgmii2-default-pins { pinctrl-single,pins = < AM62X_IOPAD(0x184, PIN_INPUT, 0) /* (AE23) RGMII2_RD0 */ AM62X_IOPAD(0x188, PIN_INPUT, 0) /* (AB20) RGMII2_RD1 */ @@ -136,14 +136,14 @@ >; }; - main_uart0_pins_default: main-uart0-pins-default { + main_uart0_pins_default: main-uart0-default-pins { pinctrl-single,pins = < AM62X_IOPAD(0x1c8, PIN_INPUT, 0) /* (D14) UART0_RXD */ AM62X_IOPAD(0x1cc, PIN_OUTPUT, 0) /* (E14) UART0_TXD */ >; }; - main_uart1_pins_default: main-uart1-pins-default { + main_uart1_pins_default: main-uart1-default-pins { pinctrl-single,pins = < AM62X_IOPAD(0x194, PIN_INPUT, 2) /* (B19) MCASP0_AXR3.UART1_CTSn */ AM62X_IOPAD(0x198, PIN_OUTPUT, 2) /* (A19) MCASP0_AXR2.UART1_RTSn */ @@ -152,13 +152,13 @@ >; }; - main_usb1_pins_default: main-usb1-pins-default { + main_usb1_pins_default: main-usb1-default-pins { pinctrl-single,pins = < AM62X_IOPAD(0x258, PIN_OUTPUT, 0) /* (F18) USB1_DRVVBUS */ >; }; - user_leds_pins_default: user-leds-pins-default { + user_leds_pins_default: user-leds-default-pins { pinctrl-single,pins = < AM62X_IOPAD(0x084, PIN_OUTPUT, 7) /* (L23) GPMC0_ADVn_ALE.GPIO0_32 */ >; diff --git a/arch/arm64/boot/dts/ti/k3-am625-sk.dts b/arch/arm64/boot/dts/ti/k3-am625-sk.dts index c0a69093c324..3f9ef4053aa6 100644 --- a/arch/arm64/boot/dts/ti/k3-am625-sk.dts +++ b/arch/arm64/boot/dts/ti/k3-am625-sk.dts @@ -101,7 +101,7 @@ }; &main_pmx0 { - main_rgmii2_pins_default: main-rgmii2-pins-default { + main_rgmii2_pins_default: main-rgmii2-default-pins { pinctrl-single,pins = < AM62X_IOPAD(0x184, PIN_INPUT, 0) /* (AE23) RGMII2_RD0 */ AM62X_IOPAD(0x188, PIN_INPUT, 0) /* (AB20) RGMII2_RD1 */ @@ -118,7 +118,7 @@ >; }; - ospi0_pins_default: ospi0-pins-default { + ospi0_pins_default: ospi0-default-pins { pinctrl-single,pins = < AM62X_IOPAD(0x000, PIN_OUTPUT, 0) /* (H24) OSPI0_CLK */ AM62X_IOPAD(0x02c, PIN_OUTPUT, 0) /* (F23) OSPI0_CSn0 */ @@ -134,13 +134,13 @@ >; }; - vdd_sd_dv_pins_default: vdd-sd-dv-pins-default { + vdd_sd_dv_pins_default: vdd-sd-dv-default-pins { pinctrl-single,pins = < AM62X_IOPAD(0x07c, PIN_OUTPUT, 7) /* (P25) GPMC0_CLK.GPIO0_31 */ >; }; - main_gpio1_ioexp_intr_pins_default: main-gpio1-ioexp-intr-pins-default { + main_gpio1_ioexp_intr_pins_default: main-gpio1-ioexp-intr-default-pins { pinctrl-single,pins = < AM62X_IOPAD(0x01d4, PIN_INPUT, 7) /* (B15) UART0_RTSn.GPIO1_23 */ >; diff --git a/arch/arm64/boot/dts/ti/k3-am62a7-sk.dts b/arch/arm64/boot/dts/ti/k3-am62a7-sk.dts index 65caa5611d6d..ecc0e13331c4 100644 --- a/arch/arm64/boot/dts/ti/k3-am62a7-sk.dts +++ b/arch/arm64/boot/dts/ti/k3-am62a7-sk.dts @@ -117,7 +117,7 @@ }; &mcu_pmx0 { - wkup_uart0_pins_default: wkup-uart0-pins-default { + wkup_uart0_pins_default: wkup-uart0-default-pins { pinctrl-single,pins = < AM62AX_MCU_IOPAD(0x0024, PIN_INPUT, 0) /* (C9) WKUP_UART0_RXD */ AM62AX_MCU_IOPAD(0x0028, PIN_OUTPUT, 0) /* (E9) WKUP_UART0_TXD */ @@ -135,14 +135,14 @@ }; &main_pmx0 { - main_uart0_pins_default: main-uart0-pins-default { + main_uart0_pins_default: main-uart0-default-pins { pinctrl-single,pins = < AM62AX_IOPAD(0x1c8, PIN_INPUT, 0) /* (E14) UART0_RXD */ AM62AX_IOPAD(0x1cc, PIN_OUTPUT, 0) /* (D15) UART0_TXD */ >; }; - main_uart1_pins_default: main-uart1-pins-default { + main_uart1_pins_default: main-uart1-default-pins { pinctrl-single,pins = < AM62AX_IOPAD(0x01e8, PIN_INPUT, 1) /* (C17) I2C1_SCL.UART1_RXD */ AM62AX_IOPAD(0x01ec, PIN_OUTPUT, 1) /* (E17) I2C1_SDA.UART1_TXD */ @@ -151,28 +151,28 @@ >; }; - main_i2c0_pins_default: main-i2c0-pins-default { + main_i2c0_pins_default: main-i2c0-default-pins { pinctrl-single,pins = < AM62AX_IOPAD(0x1e0, PIN_INPUT_PULLUP, 0) /* (B16) I2C0_SCL */ AM62AX_IOPAD(0x1e4, PIN_INPUT_PULLUP, 0) /* (A16) I2C0_SDA */ >; }; - main_i2c1_pins_default: main-i2c1-pins-default { + main_i2c1_pins_default: main-i2c1-default-pins { pinctrl-single,pins = < AM62AX_IOPAD(0x1e8, PIN_INPUT_PULLUP, 0) /* (B17) I2C1_SCL */ AM62AX_IOPAD(0x1ec, PIN_INPUT_PULLUP, 0) /* (A17) I2C1_SDA */ >; }; - main_i2c2_pins_default: main-i2c2-pins-default { + main_i2c2_pins_default: main-i2c2-default-pins { pinctrl-single,pins = < AM62AX_IOPAD(0x0b0, PIN_INPUT_PULLUP, 1) /* (K22) GPMC0_CSn2.I2C2_SCL */ AM62AX_IOPAD(0x0b4, PIN_INPUT_PULLUP, 1) /* (K24) GPMC0_CSn3.I2C2_SDA */ >; }; - main_mmc1_pins_default: main-mmc1-pins-default { + main_mmc1_pins_default: main-mmc1-default-pins { pinctrl-single,pins = < AM62AX_IOPAD(0x23c, PIN_INPUT, 0) /* (A21) MMC1_CMD */ AM62AX_IOPAD(0x234, PIN_INPUT, 0) /* (B22) MMC1_CLK */ @@ -184,26 +184,26 @@ >; }; - usr_led_pins_default: usr-led-pins-default { + usr_led_pins_default: usr-led-default-pins { pinctrl-single,pins = < AM62AX_IOPAD(0x244, PIN_OUTPUT, 7) /* (D18) MMC1_SDWP.GPIO1_49 */ >; }; - main_usb1_pins_default: main-usb1-pins-default { + main_usb1_pins_default: main-usb1-default-pins { pinctrl-single,pins = < AM62AX_IOPAD(0x0258, PIN_OUTPUT, 0) /* (F18) USB1_DRVVBUS */ >; }; - main_mdio1_pins_default: main-mdio1-pins-default { + main_mdio1_pins_default: main-mdio1-default-pins { pinctrl-single,pins = < AM62AX_IOPAD(0x160, PIN_OUTPUT, 0) /* (V12) MDIO0_MDC */ AM62AX_IOPAD(0x15c, PIN_INPUT, 0) /* (V13) MDIO0_MDIO */ >; }; - main_rgmii1_pins_default: main-rgmii1-pins-default { + main_rgmii1_pins_default: main-rgmii1-default-pins { pinctrl-single,pins = < AM62AX_IOPAD(0x14c, PIN_INPUT, 0) /* (AB16) RGMII1_RD0 */ AM62AX_IOPAD(0x150, PIN_INPUT, 0) /* (V15) RGMII1_RD1 */ diff --git a/arch/arm64/boot/dts/ti/k3-am62x-sk-common.dtsi b/arch/arm64/boot/dts/ti/k3-am62x-sk-common.dtsi index d39cfc533583..34c8ffc553ec 100644 --- a/arch/arm64/boot/dts/ti/k3-am62x-sk-common.dtsi +++ b/arch/arm64/boot/dts/ti/k3-am62x-sk-common.dtsi @@ -118,14 +118,14 @@ &main_pmx0 { /* First pad number is ALW package and second is AMC package */ - main_uart0_pins_default: main-uart0-pins-default { + main_uart0_pins_default: main-uart0-default-pins { pinctrl-single,pins = < AM62X_IOPAD(0x1c8, PIN_INPUT, 0) /* (D14/A13) UART0_RXD */ AM62X_IOPAD(0x1cc, PIN_OUTPUT, 0) /* (E14/E11) UART0_TXD */ >; }; - main_uart1_pins_default: main-uart1-pins-default { + main_uart1_pins_default: main-uart1-default-pins { pinctrl-single,pins = < AM62X_IOPAD(0x194, PIN_INPUT, 2) /* (B19/B18) MCASP0_AXR3.UART1_CTSn */ AM62X_IOPAD(0x198, PIN_OUTPUT, 2) /* (A19/B17) MCASP0_AXR2.UART1_RTSn */ @@ -134,28 +134,28 @@ >; }; - main_i2c0_pins_default: main-i2c0-pins-default { + main_i2c0_pins_default: main-i2c0-default-pins { pinctrl-single,pins = < AM62X_IOPAD(0x1e0, PIN_INPUT_PULLUP, 0) /* (B16/E12) I2C0_SCL */ AM62X_IOPAD(0x1e4, PIN_INPUT_PULLUP, 0) /* (A16/D14) I2C0_SDA */ >; }; - main_i2c1_pins_default: main-i2c1-pins-default { + main_i2c1_pins_default: main-i2c1-default-pins { pinctrl-single,pins = < AM62X_IOPAD(0x1e8, PIN_INPUT_PULLUP, 0) /* (B17/A17) I2C1_SCL */ AM62X_IOPAD(0x1ec, PIN_INPUT_PULLUP, 0) /* (A17/A16) I2C1_SDA */ >; }; - main_i2c2_pins_default: main-i2c2-pins-default { + main_i2c2_pins_default: main-i2c2-default-pins { pinctrl-single,pins = < AM62X_IOPAD(0x0b0, PIN_INPUT_PULLUP, 1) /* (K22/H18) GPMC0_CSn2.I2C2_SCL */ AM62X_IOPAD(0x0b4, PIN_INPUT_PULLUP, 1) /* (K24/H19) GPMC0_CSn3.I2C2_SDA */ >; }; - main_mmc0_pins_default: main-mmc0-pins-default { + main_mmc0_pins_default: main-mmc0-default-pins { pinctrl-single,pins = < AM62X_IOPAD(0x220, PIN_INPUT, 0) /* (Y3/V3) MMC0_CMD */ AM62X_IOPAD(0x218, PIN_INPUT, 0) /* (AB1/Y1) MMC0_CLK */ @@ -170,7 +170,7 @@ >; }; - main_mmc1_pins_default: main-mmc1-pins-default { + main_mmc1_pins_default: main-mmc1-default-pins { pinctrl-single,pins = < AM62X_IOPAD(0x23c, PIN_INPUT, 0) /* (A21/C18) MMC1_CMD */ AM62X_IOPAD(0x234, PIN_INPUT, 0) /* (B22/A20) MMC1_CLK */ @@ -182,20 +182,20 @@ >; }; - usr_led_pins_default: usr-led-pins-default { + usr_led_pins_default: usr-led-default-pins { pinctrl-single,pins = < AM62X_IOPAD(0x244, PIN_OUTPUT, 7) /* (C17/B15) MMC1_SDWP.GPIO1_49 */ >; }; - main_mdio1_pins_default: main-mdio1-pins-default { + main_mdio1_pins_default: main-mdio1-default-pins { pinctrl-single,pins = < AM62X_IOPAD(0x160, PIN_OUTPUT, 0) /* (AD24/V17) MDIO0_MDC */ AM62X_IOPAD(0x15c, PIN_INPUT, 0) /* (AB22/U16) MDIO0_MDIO */ >; }; - main_rgmii1_pins_default: main-rgmii1-pins-default { + main_rgmii1_pins_default: main-rgmii1-default-pins { pinctrl-single,pins = < AM62X_IOPAD(0x14c, PIN_INPUT, 0) /* (AB17/W15) RGMII1_RD0 */ AM62X_IOPAD(0x150, PIN_INPUT, 0) /* (AC17/Y16) RGMII1_RD1 */ @@ -212,13 +212,13 @@ >; }; - main_usb1_pins_default: main-usb1-pins-default { + main_usb1_pins_default: main-usb1-default-pins { pinctrl-single,pins = < AM62X_IOPAD(0x0258, PIN_OUTPUT, 0) /* (F18/E16) USB1_DRVVBUS */ >; }; - main_mcasp1_pins_default: main-mcasp1-pins-default { + main_mcasp1_pins_default: main-mcasp1-default-pins { pinctrl-single,pins = < AM62X_IOPAD(0x090, PIN_INPUT, 2) /* (M24/K17) GPMC0_BE0N_CLE.MCASP1_ACLKX */ AM62X_IOPAD(0x098, PIN_INPUT, 2) /* (U23/P21) GPMC0_WAIT0.MCASP1_AFSX */ @@ -229,7 +229,7 @@ }; &mcu_pmx0 { - wkup_uart0_pins_default: wkup-uart0-pins-default { + wkup_uart0_pins_default: wkup-uart0-default-pins { pinctrl-single,pins = < AM62X_MCU_IOPAD(0x02c, PIN_INPUT, 0) /* (C6/A7) WKUP_UART0_CTSn */ AM62X_MCU_IOPAD(0x030, PIN_OUTPUT, 0) /* (A4/B4) WKUP_UART0_RTSn */ diff --git a/arch/arm64/boot/dts/ti/k3-am64-phycore-som.dtsi b/arch/arm64/boot/dts/ti/k3-am64-phycore-som.dtsi index 7c2e26ef726c..5606d775153d 100644 --- a/arch/arm64/boot/dts/ti/k3-am64-phycore-som.dtsi +++ b/arch/arm64/boot/dts/ti/k3-am64-phycore-som.dtsi @@ -66,7 +66,7 @@ }; &main_pmx0 { - cpsw_mdio_pins_default: cpsw-mdio-pins-default { + cpsw_mdio_pins_default: cpsw-mdio-default-pins { pinctrl-single,pins = < AM64X_IOPAD(0x01f8, PIN_INPUT, 4) /* (P5) PRG0_PRU1_GPO18.MDIO0_MDIO */ AM64X_IOPAD(0x01fc, PIN_OUTPUT, 4) /* (R2) PRG0_PRU1_GPO19.MDIO0_MDC */ @@ -74,7 +74,7 @@ >; }; - cpsw_rgmii1_pins_default: cpsw-rgmii1-pins-default { + cpsw_rgmii1_pins_default: cpsw-rgmii1-default-pins { pinctrl-single,pins = < AM64X_IOPAD(0x0184, PIN_INPUT, 4) /* (W6) PRG0_PRU0_GPO9.RGMII1_RX_CTL */ AM64X_IOPAD(0x0188, PIN_INPUT, 4) /* (AA5) PRG0_PRU0_GPO10.RGMII1_RXC */ @@ -92,26 +92,26 @@ >; }; - eeprom_wp_pins_default: eeprom-wp-pins-default { + eeprom_wp_pins_default: eeprom-wp-default-pins { pinctrl-single,pins = < AM64X_IOPAD(0x0208, PIN_OUTPUT, 7) /* (D12) SPI0_CS0.GPIO1_42 */ >; }; - leds_pins_default: leds-pins-default { + leds_pins_default: leds-default-pins { pinctrl-single,pins = < AM64X_IOPAD(0x0030, PIN_OUTPUT, 7) /* (L18) OSPI0_CSn1.GPIO0_12 */ >; }; - main_i2c0_pins_default: main-i2c0-pins-default { + main_i2c0_pins_default: main-i2c0-default-pins { pinctrl-single,pins = < AM64X_IOPAD(0x0260, PIN_INPUT, 0) /* (A18) I2C0_SCL */ AM64X_IOPAD(0x0264, PIN_INPUT, 0) /* (B18) I2C0_SDA */ >; }; - ospi0_pins_default: ospi0-pins-default { + ospi0_pins_default: ospi0-default-pins { pinctrl-single,pins = < AM64X_IOPAD(0x0000, PIN_OUTPUT, 0) /* (N20) OSPI0_CLK */ AM64X_IOPAD(0x0008, PIN_INPUT, 0) /* (N19) OSPI0_DQS */ diff --git a/arch/arm64/boot/dts/ti/k3-am642-evm.dts b/arch/arm64/boot/dts/ti/k3-am642-evm.dts index e897feacd122..15c282c93467 100644 --- a/arch/arm64/boot/dts/ti/k3-am642-evm.dts +++ b/arch/arm64/boot/dts/ti/k3-am642-evm.dts @@ -226,7 +226,7 @@ }; &main_pmx0 { - main_mmc1_pins_default: main-mmc1-pins-default { + main_mmc1_pins_default: main-mmc1-default-pins { pinctrl-single,pins = < AM64X_IOPAD(0x0294, PIN_INPUT_PULLUP, 0) /* (J19) MMC1_CMD */ AM64X_IOPAD(0x028c, PIN_INPUT_PULLDOWN, 0) /* (L20) MMC1_CLK */ @@ -240,7 +240,7 @@ >; }; - main_uart1_pins_default: main-uart1-pins-default { + main_uart1_pins_default: main-uart1-default-pins { pinctrl-single,pins = < AM64X_IOPAD(0x0248, PIN_INPUT, 0) /* (D16) UART1_CTSn */ AM64X_IOPAD(0x024c, PIN_OUTPUT, 0) /* (E16) UART1_RTSn */ @@ -249,7 +249,7 @@ >; }; - main_uart0_pins_default: main-uart0-pins-default { + main_uart0_pins_default: main-uart0-default-pins { pinctrl-single,pins = < AM64X_IOPAD(0x0238, PIN_INPUT, 0) /* (B16) UART0_CTSn */ AM64X_IOPAD(0x023c, PIN_OUTPUT, 0) /* (A16) UART0_RTSn */ @@ -258,7 +258,7 @@ >; }; - main_spi0_pins_default: main-spi0-pins-default { + main_spi0_pins_default: main-spi0-default-pins { pinctrl-single,pins = < AM64X_IOPAD(0x0210, PIN_INPUT, 0) /* (D13) SPI0_CLK */ AM64X_IOPAD(0x0208, PIN_OUTPUT, 0) /* (D12) SPI0_CS0 */ @@ -267,28 +267,28 @@ >; }; - main_i2c0_pins_default: main-i2c0-pins-default { + main_i2c0_pins_default: main-i2c0-default-pins { pinctrl-single,pins = < AM64X_IOPAD(0x0260, PIN_INPUT_PULLUP, 0) /* (A18) I2C0_SCL */ AM64X_IOPAD(0x0264, PIN_INPUT_PULLUP, 0) /* (B18) I2C0_SDA */ >; }; - main_i2c1_pins_default: main-i2c1-pins-default { + main_i2c1_pins_default: main-i2c1-default-pins { pinctrl-single,pins = < AM64X_IOPAD(0x0268, PIN_INPUT_PULLUP, 0) /* (C18) I2C1_SCL */ AM64X_IOPAD(0x026c, PIN_INPUT_PULLUP, 0) /* (B19) I2C1_SDA */ >; }; - mdio1_pins_default: mdio1-pins-default { + mdio1_pins_default: mdio1-default-pins { pinctrl-single,pins = < AM64X_IOPAD(0x01fc, PIN_OUTPUT, 4) /* (R2) PRG0_PRU1_GPO19.MDIO0_MDC */ AM64X_IOPAD(0x01f8, PIN_INPUT, 4) /* (P5) PRG0_PRU1_GPO18.MDIO0_MDIO */ >; }; - rgmii1_pins_default: rgmii1-pins-default { + rgmii1_pins_default: rgmii1-default-pins { pinctrl-single,pins = < AM64X_IOPAD(0x01cc, PIN_INPUT, 4) /* (W5) PRG0_PRU1_GPO7.RGMII1_RD0 */ AM64X_IOPAD(0x01d4, PIN_INPUT, 4) /* (Y5) PRG0_PRU1_GPO9.RGMII1_RD1 */ @@ -305,7 +305,7 @@ >; }; - rgmii2_pins_default: rgmii2-pins-default { + rgmii2_pins_default: rgmii2-default-pins { pinctrl-single,pins = < AM64X_IOPAD(0x0108, PIN_INPUT, 4) /* (W11) PRG1_PRU1_GPO0.RGMII2_RD0 */ AM64X_IOPAD(0x010c, PIN_INPUT, 4) /* (V11) PRG1_PRU1_GPO1.RGMII2_RD1 */ @@ -322,13 +322,13 @@ >; }; - main_usb0_pins_default: main-usb0-pins-default { + main_usb0_pins_default: main-usb0-default-pins { pinctrl-single,pins = < AM64X_IOPAD(0x02a8, PIN_OUTPUT, 0) /* (E19) USB0_DRVVBUS */ >; }; - ospi0_pins_default: ospi0-pins-default { + ospi0_pins_default: ospi0-default-pins { pinctrl-single,pins = < AM64X_IOPAD(0x0000, PIN_OUTPUT, 0) /* (N20) OSPI0_CLK */ AM64X_IOPAD(0x002c, PIN_OUTPUT, 0) /* (L19) OSPI0_CSn0 */ @@ -344,27 +344,27 @@ >; }; - main_ecap0_pins_default: main-ecap0-pins-default { + main_ecap0_pins_default: main-ecap0-default-pins { pinctrl-single,pins = < AM64X_IOPAD(0x0270, PIN_INPUT, 0) /* (D18) ECAP0_IN_APWM_OUT */ >; }; - main_mcan0_pins_default: main-mcan0-pins-default { + main_mcan0_pins_default: main-mcan0-default-pins { pinctrl-single,pins = < AM64X_IOPAD(0x0254, PIN_INPUT, 0) /* (B17) MCAN0_RX */ AM64X_IOPAD(0x0250, PIN_OUTPUT, 0) /* (A17) MCAN0_TX */ >; }; - main_mcan1_pins_default: main-mcan1-pins-default { + main_mcan1_pins_default: main-mcan1-default-pins { pinctrl-single,pins = < AM64X_IOPAD(0x025c, PIN_INPUT, 0) /* (D17) MCAN1_RX */ AM64X_IOPAD(0x0258, PIN_OUTPUT, 0) /* (C17) MCAN1_TX */ >; }; - ddr_vtt_pins_default: ddr-vtt-pins-default { + ddr_vtt_pins_default: ddr-vtt-default-pins { pinctrl-single,pins = < AM64X_IOPAD(0x0030, PIN_OUTPUT_PULLUP, 7) /* (L18) OSPI0_CSN1.GPIO0_12 */ >; diff --git a/arch/arm64/boot/dts/ti/k3-am642-phyboard-electra-rdk.dts b/arch/arm64/boot/dts/ti/k3-am642-phyboard-electra-rdk.dts index 59c091bc30ab..9c418abd29d8 100644 --- a/arch/arm64/boot/dts/ti/k3-am642-phyboard-electra-rdk.dts +++ b/arch/arm64/boot/dts/ti/k3-am642-phyboard-electra-rdk.dts @@ -105,47 +105,47 @@ }; &main_pmx0 { - can_tc1_pins_default: can-tc1-pins-default { + can_tc1_pins_default: can-tc1-default-pins { pinctrl-single,pins = < AM64X_IOPAD(0x0084, PIN_OUTPUT, 7) /* (P16) GPMC0_ADVn_ALE.GPIO0_32 */ >; }; - can_tc2_pins_default: can-tc2-pins-default { + can_tc2_pins_default: can-tc2-default-pins { pinctrl-single,pins = < AM64X_IOPAD(0x0090, PIN_OUTPUT, 7) /* (P17) GPMC0_BE0n_CLE.GPIO0_35 */ >; }; - gpio_keys_pins_default: gpio-keys-pins-default { + gpio_keys_pins_default: gpio-keys-default-pins { pinctrl-single,pins = < AM64X_IOPAD(0x0044, PIN_INPUT, 7) /* (T18) GPMC0_AD2.GPIO0_17 */ AM64X_IOPAD(0x0054, PIN_INPUT, 7) /* (V20) GPMC0_AD6.GPIO0_21 */ >; }; - main_i2c1_pins_default: main-i2c1-pins-default { + main_i2c1_pins_default: main-i2c1-default-pins { pinctrl-single,pins = < AM64X_IOPAD(0x0268, PIN_INPUT, 0) /* (C18) I2C1_SCL */ AM64X_IOPAD(0x026c, PIN_INPUT, 0) /* (B19) I2C1_SDA */ >; }; - main_mcan0_pins_default: main-mcan0-pins-default { + main_mcan0_pins_default: main-mcan0-default-pins { pinctrl-single,pins = < AM64X_IOPAD(0x0250, PIN_OUTPUT, 0) /* (A17) MCAN0_TX */ AM64X_IOPAD(0x0254, PIN_INPUT, 0) /* (B17) MCAN0_RX */ >; }; - main_mcan1_pins_default: main-mcan1-pins-default { + main_mcan1_pins_default: main-mcan1-default-pins { pinctrl-single,pins = < AM64X_IOPAD(0x0258, PIN_OUTPUT, 0) /* (C17) MCAN1_TX */ AM64X_IOPAD(0x025c, PIN_INPUT, 0) /* (D17) MCAN1_RX */ >; }; - main_mmc1_pins_default: main-mmc1-pins-default { + main_mmc1_pins_default: main-mmc1-default-pins { pinctrl-single,pins = < AM64X_IOPAD(0x027c, PIN_INPUT_PULLUP, 0) /* (K18) MMC1_DAT3 */ AM64X_IOPAD(0x0280, PIN_INPUT_PULLUP, 0) /* (K19) MMC1_DAT2 */ @@ -158,14 +158,14 @@ >; }; - main_uart0_pins_default: main-uart0-pins-default { + main_uart0_pins_default: main-uart0-default-pins { pinctrl-single,pins = < AM64X_IOPAD(0x0230, PIN_INPUT, 0) /* (D15) UART0_RXD */ AM64X_IOPAD(0x0234, PIN_OUTPUT, 0) /* (C16) UART0_TXD */ >; }; - main_uart1_pins_default: main-uart1-pins-default { + main_uart1_pins_default: main-uart1-default-pins { pinctrl-single,pins = < AM64X_IOPAD(0x0248, PIN_INPUT, 0) /* (D16) UART1_CTSn */ AM64X_IOPAD(0x024C, PIN_OUTPUT, 0) /* (E16) UART1_RTSn */ @@ -174,25 +174,25 @@ >; }; - main_usb0_pins_default: main-usb0-pins-default { + main_usb0_pins_default: main-usb0-default-pins { pinctrl-single,pins = < AM64X_IOPAD(0x02a8, PIN_OUTPUT, 0) /* (E19) USB0_DRVVBUS */ >; }; - pcie_usb_sel_pins_default: pcie-usb-sel-pins-default { + pcie_usb_sel_pins_default: pcie-usb-sel-default-pins { pinctrl-single,pins = < AM64X_IOPAD(0x017c, PIN_OUTPUT, 7) /* (T1) PRG0_PRU0_GPO7.GPIO1_7 */ >; }; - pcie0_pins_default: pcie0-pins-default { + pcie0_pins_default: pcie0-default-pins { pinctrl-single,pins = < AM64X_IOPAD(0x0098, PIN_OUTPUT, 7) /* (W19) GPMC0_WAIT0.GPIO0_37 */ >; }; - user_leds_pins_default: user-leds-pins-default { + user_leds_pins_default: user-leds-default-pins { pinctrl-single,pins = < AM64X_IOPAD(0x003c, PIN_OUTPUT, 7) /* (T20) GPMC0_AD0.GPIO0_15 */ AM64X_IOPAD(0x0040, PIN_OUTPUT, 7) /* (U21) GPMC0_AD1.GPIO0_16 */ diff --git a/arch/arm64/boot/dts/ti/k3-am642-sk.dts b/arch/arm64/boot/dts/ti/k3-am642-sk.dts index 78ae490a0c76..cbce43dbe3f9 100644 --- a/arch/arm64/boot/dts/ti/k3-am642-sk.dts +++ b/arch/arm64/boot/dts/ti/k3-am642-sk.dts @@ -232,7 +232,7 @@ }; &main_pmx0 { - main_mmc1_pins_default: main-mmc1-pins-default { + main_mmc1_pins_default: main-mmc1-default-pins { pinctrl-single,pins = < AM64X_IOPAD(0x029c, PIN_INPUT_PULLUP, 0) /* (C20) MMC1_SDWP */ AM64X_IOPAD(0x0298, PIN_INPUT_PULLUP, 0) /* (D19) MMC1_SDCD */ @@ -246,7 +246,7 @@ >; }; - main_uart0_pins_default: main-uart0-pins-default { + main_uart0_pins_default: main-uart0-default-pins { pinctrl-single,pins = < AM64X_IOPAD(0x0238, PIN_INPUT, 0) /* (B16) UART0_CTSn */ AM64X_IOPAD(0x023c, PIN_OUTPUT, 0) /* (A16) UART0_RTSn */ @@ -255,7 +255,7 @@ >; }; - main_uart1_pins_default: main-uart1-pins-default { + main_uart1_pins_default: main-uart1-default-pins { pinctrl-single,pins = < AM64X_IOPAD(0x0248, PIN_INPUT, 0) /* (D16) UART1_CTSn */ AM64X_IOPAD(0x024c, PIN_OUTPUT, 0) /* (E16) UART1_RTSn */ @@ -264,34 +264,34 @@ >; }; - main_usb0_pins_default: main-usb0-pins-default { + main_usb0_pins_default: main-usb0-default-pins { pinctrl-single,pins = < AM64X_IOPAD(0x02a8, PIN_OUTPUT, 0) /* (E19) USB0_DRVVBUS */ >; }; - main_i2c0_pins_default: main-i2c0-pins-default { + main_i2c0_pins_default: main-i2c0-default-pins { pinctrl-single,pins = < AM64X_IOPAD(0x0260, PIN_INPUT_PULLUP, 0) /* (A18) I2C0_SCL */ AM64X_IOPAD(0x0264, PIN_INPUT_PULLUP, 0) /* (B18) I2C0_SDA */ >; }; - main_i2c1_pins_default: main-i2c1-pins-default { + main_i2c1_pins_default: main-i2c1-default-pins { pinctrl-single,pins = < AM64X_IOPAD(0x0268, PIN_INPUT_PULLUP, 0) /* (C18) I2C1_SCL */ AM64X_IOPAD(0x026c, PIN_INPUT_PULLUP, 0) /* (B19) I2C1_SDA */ >; }; - mdio1_pins_default: mdio1-pins-default { + mdio1_pins_default: mdio1-default-pins { pinctrl-single,pins = < AM64X_IOPAD(0x01fc, PIN_OUTPUT, 4) /* (R2) PRG0_PRU1_GPO19.MDIO0_MDC */ AM64X_IOPAD(0x01f8, PIN_INPUT, 4) /* (P5) PRG0_PRU1_GPO18.MDIO0_MDIO */ >; }; - rgmii1_pins_default: rgmii1-pins-default { + rgmii1_pins_default: rgmii1-default-pins { pinctrl-single,pins = < AM64X_IOPAD(0x011c, PIN_INPUT, 4) /* (AA13) PRG1_PRU1_GPO5.RGMII1_RD0 */ AM64X_IOPAD(0x0128, PIN_INPUT, 4) /* (U12) PRG1_PRU1_GPO8.RGMII1_RD1 */ @@ -308,7 +308,7 @@ >; }; - rgmii2_pins_default: rgmii2-pins-default { + rgmii2_pins_default: rgmii2-default-pins { pinctrl-single,pins = < AM64X_IOPAD(0x0108, PIN_INPUT, 4) /* (W11) PRG1_PRU1_GPO0.RGMII2_RD0 */ AM64X_IOPAD(0x010c, PIN_INPUT, 4) /* (V11) PRG1_PRU1_GPO1.RGMII2_RD1 */ @@ -325,7 +325,7 @@ >; }; - ospi0_pins_default: ospi0-pins-default { + ospi0_pins_default: ospi0-default-pins { pinctrl-single,pins = < AM64X_IOPAD(0x0000, PIN_OUTPUT, 0) /* (N20) OSPI0_CLK */ AM64X_IOPAD(0x002c, PIN_OUTPUT, 0) /* (L19) OSPI0_CSn0 */ @@ -341,24 +341,24 @@ >; }; - main_ecap0_pins_default: main-ecap0-pins-default { + main_ecap0_pins_default: main-ecap0-default-pins { pinctrl-single,pins = < AM64X_IOPAD(0x0270, PIN_INPUT, 0) /* (D18) ECAP0_IN_APWM_OUT */ >; }; - main_wlan_en_pins_default: main-wlan-en-pins-default { + main_wlan_en_pins_default: main-wlan-en-default-pins { pinctrl-single,pins = < AM64X_IOPAD(0x00c4, PIN_OUTPUT_PULLUP, 7) /* (V8) GPIO0_48 */ >; }; - main_com8_ls_en_pins_default: main-com8-ls-en-pins-default { + main_com8_ls_en_pins_default: main-com8-ls-en-default-pins { pinctrl-single,pins = < AM64X_IOPAD(0x00fc, PIN_OUTPUT, 7) /* (U7) PRG1_PRU0_GPO17.GPIO0_62 */ >; }; - main_wlan_pins_default: main-wlan-pins-default { + main_wlan_pins_default: main-wlan-default-pins { pinctrl-single,pins = < AM64X_IOPAD(0x00bc, PIN_INPUT, 7) /* (U8) GPIO0_46 */ >; diff --git a/arch/arm64/boot/dts/ti/k3-am65-iot2050-common.dtsi b/arch/arm64/boot/dts/ti/k3-am65-iot2050-common.dtsi index bbbb5c169ccc..e26bd988e522 100644 --- a/arch/arm64/boot/dts/ti/k3-am65-iot2050-common.dtsi +++ b/arch/arm64/boot/dts/ti/k3-am65-iot2050-common.dtsi @@ -104,7 +104,7 @@ }; &wkup_pmx0 { - wkup_i2c0_pins_default: wkup-i2c0-pins-default { + wkup_i2c0_pins_default: wkup-i2c0-default-pins { pinctrl-single,pins = < /* (AC7) WKUP_I2C0_SCL */ AM65X_WKUP_IOPAD(0x00e0, PIN_INPUT, 0) @@ -113,7 +113,7 @@ >; }; - mcu_i2c0_pins_default: mcu-i2c0-pins-default { + mcu_i2c0_pins_default: mcu-i2c0-default-pins { pinctrl-single,pins = < /* (AD8) MCU_I2C0_SCL */ AM65X_WKUP_IOPAD(0x00e8, PIN_INPUT, 0) @@ -122,21 +122,21 @@ >; }; - arduino_i2c_aio_switch_pins_default: arduino-i2c-aio-switch-pins-default { + arduino_i2c_aio_switch_pins_default: arduino-i2c-aio-switch-default-pins { pinctrl-single,pins = < /* (R2) WKUP_GPIO0_21 */ AM65X_WKUP_IOPAD(0x0024, PIN_OUTPUT, 7) >; }; - push_button_pins_default: push-button-pins-default { + push_button_pins_default: push-button-default-pins { pinctrl-single,pins = < /* (T1) MCU_OSPI1_CLK.WKUP_GPIO0_25 */ AM65X_WKUP_IOPAD(0x0034, PIN_INPUT, 7) >; }; - arduino_uart_pins_default: arduino-uart-pins-default { + arduino_uart_pins_default: arduino-uart-default-pins { pinctrl-single,pins = < /* (P4) MCU_UART0_RXD */ AM65X_WKUP_IOPAD(0x0044, PIN_INPUT, 4) @@ -145,7 +145,7 @@ >; }; - arduino_io_d2_to_d3_pins_default: arduino-io-d2-to-d3-pins-default { + arduino_io_d2_to_d3_pins_default: arduino-io-d2-to-d3-default-pins { pinctrl-single,pins = < /* (P1) WKUP_GPIO0_31 */ AM65X_WKUP_IOPAD(0x004C, PIN_OUTPUT, 7) @@ -154,7 +154,7 @@ >; }; - arduino_io_oe_pins_default: arduino-io-oe-pins-default { + arduino_io_oe_pins_default: arduino-io-oe-default-pins { pinctrl-single,pins = < /* (N4) WKUP_GPIO0_34 */ AM65X_WKUP_IOPAD(0x0058, PIN_OUTPUT, 7) @@ -169,7 +169,7 @@ >; }; - mcu_fss0_ospi0_pins_default: mcu-fss0-ospi0-pins-default { + mcu_fss0_ospi0_pins_default: mcu-fss0-ospi0-default-pins { pinctrl-single,pins = < /* (V1) MCU_OSPI0_CLK */ AM65X_WKUP_IOPAD(0x0000, PIN_OUTPUT, 0) @@ -184,7 +184,7 @@ >; }; - db9_com_mode_pins_default: db9-com-mode-pins-default { + db9_com_mode_pins_default: db9-com-mode-default-pins { pinctrl-single,pins = < /* (AD3) WKUP_GPIO0_5, used as uart0 mode 0 */ AM65X_WKUP_IOPAD(0x00c4, PIN_OUTPUT, 7) @@ -197,7 +197,7 @@ >; }; - leds_pins_default: leds-pins-default { + leds_pins_default: leds-default-pins { pinctrl-single,pins = < /* (T2) WKUP_GPIO0_17, used as user led1 red */ AM65X_WKUP_IOPAD(0x0014, PIN_OUTPUT, 7) @@ -210,7 +210,7 @@ >; }; - mcu_spi0_pins_default: mcu-spi0-pins-default { + mcu_spi0_pins_default: mcu-spi0-default-pins { pinctrl-single,pins = < /* (Y1) MCU_SPI0_CLK */ AM65X_WKUP_IOPAD(0x0090, PIN_INPUT, 0) @@ -223,7 +223,7 @@ >; }; - minipcie_pins_default: minipcie-pins-default { + minipcie_pins_default: minipcie-default-pins { pinctrl-single,pins = < /* (P2) MCU_OSPI1_DQS.WKUP_GPIO0_27 */ AM65X_WKUP_IOPAD(0x003C, PIN_OUTPUT, 7) @@ -232,7 +232,7 @@ }; &main_pmx0 { - main_uart1_pins_default: main-uart1-pins-default { + main_uart1_pins_default: main-uart1-default-pins { pinctrl-single,pins = < AM65X_IOPAD(0x0174, PIN_INPUT, 6) /* (AE23) UART1_RXD */ AM65X_IOPAD(0x014c, PIN_OUTPUT, 6) /* (AD23) UART1_TXD */ @@ -241,14 +241,14 @@ >; }; - main_i2c3_pins_default: main-i2c3-pins-default { + main_i2c3_pins_default: main-i2c3-default-pins { pinctrl-single,pins = < AM65X_IOPAD(0x01c0, PIN_INPUT, 2) /* (AF13) I2C3_SCL */ AM65X_IOPAD(0x01d4, PIN_INPUT, 2) /* (AG12) I2C3_SDA */ >; }; - main_mmc1_pins_default: main-mmc1-pins-default { + main_mmc1_pins_default: main-mmc1-default-pins { pinctrl-single,pins = < AM65X_IOPAD(0x02d4, PIN_INPUT_PULLDOWN, 0) /* (C27) MMC1_CLK */ AM65X_IOPAD(0x02d8, PIN_INPUT_PULLUP, 0) /* (C28) MMC1_CMD */ @@ -261,19 +261,19 @@ >; }; - usb0_pins_default: usb0-pins-default { + usb0_pins_default: usb0-default-pins { pinctrl-single,pins = < AM65X_IOPAD(0x02bc, PIN_OUTPUT, 0) /* (AD9) USB0_DRVVBUS */ >; }; - usb1_pins_default: usb1-pins-default { + usb1_pins_default: usb1-default-pins { pinctrl-single,pins = < AM65X_IOPAD(0x02c0, PIN_OUTPUT, 0) /* (AC8) USB1_DRVVBUS */ >; }; - arduino_io_d4_to_d9_pins_default: arduino-io-d4-to-d9-pins-default { + arduino_io_d4_to_d9_pins_default: arduino-io-d4-to-d9-default-pins { pinctrl-single,pins = < AM65X_IOPAD(0x0084, PIN_OUTPUT, 7) /* (AG18) GPIO0_33 */ AM65X_IOPAD(0x008C, PIN_OUTPUT, 7) /* (AF17) GPIO0_35 */ @@ -284,7 +284,7 @@ >; }; - dss_vout1_pins_default: dss-vout1-pins-default { + dss_vout1_pins_default: dss-vout1-default-pins { pinctrl-single,pins = < AM65X_IOPAD(0x0000, PIN_OUTPUT, 1) /* VOUT1_DATA0 */ AM65X_IOPAD(0x0004, PIN_OUTPUT, 1) /* VOUT1_DATA1 */ @@ -317,13 +317,13 @@ >; }; - dp_pins_default: dp-pins-default { + dp_pins_default: dp-default-pins { pinctrl-single,pins = < AM65X_IOPAD(0x0078, PIN_OUTPUT, 7) /* (AF18) DP rst_n */ >; }; - main_i2c2_pins_default: main-i2c2-pins-default { + main_i2c2_pins_default: main-i2c2-default-pins { pinctrl-single,pins = < AM65X_IOPAD(0x0074, PIN_INPUT, 5) /* (T27) I2C2_SCL */ AM65X_IOPAD(0x0070, PIN_INPUT, 5) /* (R25) I2C2_SDA */ @@ -332,21 +332,21 @@ }; &main_pmx1 { - main_i2c0_pins_default: main-i2c0-pins-default { + main_i2c0_pins_default: main-i2c0-default-pins { pinctrl-single,pins = < AM65X_IOPAD(0x0000, PIN_INPUT, 0) /* (D20) I2C0_SCL */ AM65X_IOPAD(0x0004, PIN_INPUT, 0) /* (C21) I2C0_SDA */ >; }; - main_i2c1_pins_default: main-i2c1-pins-default { + main_i2c1_pins_default: main-i2c1-default-pins { pinctrl-single,pins = < AM65X_IOPAD(0x0008, PIN_INPUT, 0) /* (B21) I2C1_SCL */ AM65X_IOPAD(0x000c, PIN_INPUT, 0) /* (E21) I2C1_SDA */ >; }; - ecap0_pins_default: ecap0-pins-default { + ecap0_pins_default: ecap0-default-pins { pinctrl-single,pins = < AM65X_IOPAD(0x0010, PIN_INPUT, 0) /* (D21) ECAP0_IN_APWM_OUT */ >; diff --git a/arch/arm64/boot/dts/ti/k3-am6528-iot2050-basic-common.dtsi b/arch/arm64/boot/dts/ti/k3-am6528-iot2050-basic-common.dtsi index cd43fd11a5c2..5ab434c02ab6 100644 --- a/arch/arm64/boot/dts/ti/k3-am6528-iot2050-basic-common.dtsi +++ b/arch/arm64/boot/dts/ti/k3-am6528-iot2050-basic-common.dtsi @@ -35,7 +35,7 @@ }; &main_pmx0 { - main_uart0_pins_default: main-uart0-pins-default { + main_uart0_pins_default: main-uart0-default-pins { pinctrl-single,pins = < AM65X_IOPAD(0x01e4, PIN_INPUT, 0) /* (AF11) UART0_RXD */ AM65X_IOPAD(0x01e8, PIN_OUTPUT, 0) /* (AE11) UART0_TXD */ diff --git a/arch/arm64/boot/dts/ti/k3-am654-base-board.dts b/arch/arm64/boot/dts/ti/k3-am654-base-board.dts index c8c80cd756d9..973a89b04a22 100644 --- a/arch/arm64/boot/dts/ti/k3-am654-base-board.dts +++ b/arch/arm64/boot/dts/ti/k3-am654-base-board.dts @@ -147,7 +147,7 @@ }; &wkup_pmx0 { - wkup_uart0_pins_default: wkup-uart0-pins-default { + wkup_uart0_pins_default: wkup-uart0-default-pins { pinctrl-single,pins = < AM65X_WKUP_IOPAD(0x00a0, PIN_INPUT, 0) /* (AB1) WKUP_UART0_RXD */ AM65X_WKUP_IOPAD(0x00a4, PIN_OUTPUT, 0) /* (AB5) WKUP_UART0_TXD */ @@ -156,27 +156,27 @@ >; }; - ddr_vtt_pins_default: ddr-vtt-pins-default { + ddr_vtt_pins_default: ddr-vtt-default-pins { pinctrl-single,pins = < AM65X_WKUP_IOPAD(0x0040, PIN_OUTPUT_PULLUP, 7) /* WKUP_GPIO0_28 */ >; }; - wkup_i2c0_pins_default: wkup-i2c0-pins-default { + wkup_i2c0_pins_default: wkup-i2c0-default-pins { pinctrl-single,pins = < AM65X_WKUP_IOPAD(0x00e0, PIN_INPUT, 0) /* (AC7) WKUP_I2C0_SCL */ AM65X_WKUP_IOPAD(0x00e4, PIN_INPUT, 0) /* (AD6) WKUP_I2C0_SDA */ >; }; - push_button_pins_default: push-button-pins-default { + push_button_pins_default: push-button-default-pins { pinctrl-single,pins = < AM65X_WKUP_IOPAD(0x0030, PIN_INPUT, 7) /* (R5) WKUP_GPIO0_24 */ AM65X_WKUP_IOPAD(0x003c, PIN_INPUT, 7) /* (P2) WKUP_GPIO0_27 */ >; }; - mcu_fss0_ospi0_pins_default: mcu-fss0-ospi0-pins-default { + mcu_fss0_ospi0_pins_default: mcu-fss0-ospi0-default-pins { pinctrl-single,pins = < AM65X_WKUP_IOPAD(0x0000, PIN_OUTPUT, 0) /* (V1) MCU_OSPI0_CLK */ AM65X_WKUP_IOPAD(0x0008, PIN_INPUT, 0) /* (U2) MCU_OSPI0_DQS */ @@ -198,7 +198,7 @@ >; }; - mcu_uart0_pins_default: mcu-uart0-pins-default { + mcu_uart0_pins_default: mcu-uart0-default-pins { pinctrl-single,pins = < AM65X_WKUP_IOPAD(0x0044, PIN_INPUT, 4) /* (P4) MCU_OSPI1_D1.MCU_UART0_RXD */ AM65X_WKUP_IOPAD(0x0048, PIN_OUTPUT, 4) /* (P5) MCU_OSPI1_D2.MCU_UART0_TXD */ @@ -207,7 +207,7 @@ >; }; - mcu_cpsw_pins_default: mcu-cpsw-pins-default { + mcu_cpsw_pins_default: mcu-cpsw-default-pins { pinctrl-single,pins = < AM65X_WKUP_IOPAD(0x0058, PIN_OUTPUT, 0) /* (N4) MCU_RGMII1_TX_CTL */ AM65X_WKUP_IOPAD(0x005c, PIN_INPUT, 0) /* (N5) MCU_RGMII1_RX_CTL */ @@ -224,14 +224,14 @@ >; }; - mcu_mdio_pins_default: mcu-mdio1-pins-default { + mcu_mdio_pins_default: mcu-mdio1-default-pins { pinctrl-single,pins = < AM65X_WKUP_IOPAD(0x008c, PIN_OUTPUT, 0) /* (L1) MCU_MDIO0_MDC */ AM65X_WKUP_IOPAD(0x0088, PIN_INPUT, 0) /* (L4) MCU_MDIO0_MDIO */ >; }; - mcu_i2c0_pins_default: mcu-i2c0-pins-default { + mcu_i2c0_pins_default: mcu-i2c0-default-pins { pinctrl-single,pins = < AM65X_WKUP_IOPAD(0x00e8, PIN_INPUT, 0) /* (AD8) MCU_I2C0_SCL */ AM65X_WKUP_IOPAD(0x00ec, PIN_INPUT, 0) /* (AD7) MCU_I2C0_SDA */ @@ -240,7 +240,7 @@ }; &main_pmx0 { - main_uart0_pins_default: main-uart0-pins-default { + main_uart0_pins_default: main-uart0-default-pins { pinctrl-single,pins = < AM65X_IOPAD(0x01e4, PIN_INPUT, 0) /* (AF11) UART0_RXD */ AM65X_IOPAD(0x01e8, PIN_OUTPUT, 0) /* (AE11) UART0_TXD */ @@ -249,14 +249,14 @@ >; }; - main_i2c2_pins_default: main-i2c2-pins-default { + main_i2c2_pins_default: main-i2c2-default-pins { pinctrl-single,pins = < AM65X_IOPAD(0x0074, PIN_INPUT, 5) /* (T27) GPMC0_CSn3.I2C2_SCL */ AM65X_IOPAD(0x0070, PIN_INPUT, 5) /* (R25) GPMC0_CSn2.I2C2_SDA */ >; }; - main_spi0_pins_default: main-spi0-pins-default { + main_spi0_pins_default: main-spi0-default-pins { pinctrl-single,pins = < AM65X_IOPAD(0x01c4, PIN_INPUT, 0) /* (AH13) SPI0_CLK */ AM65X_IOPAD(0x01c8, PIN_INPUT, 0) /* (AE13) SPI0_D0 */ @@ -265,7 +265,7 @@ >; }; - main_mmc0_pins_default: main-mmc0-pins-default { + main_mmc0_pins_default: main-mmc0-default-pins { pinctrl-single,pins = < AM65X_IOPAD(0x01a8, PIN_INPUT_PULLDOWN, 0) /* (B25) MMC0_CLK */ AM65X_IOPAD(0x01ac, PIN_INPUT_PULLUP, 0) /* (B27) MMC0_CMD */ @@ -282,7 +282,7 @@ >; }; - main_mmc1_pins_default: main-mmc1-pins-default { + main_mmc1_pins_default: main-mmc1-default-pins { pinctrl-single,pins = < AM65X_IOPAD(0x02d4, PIN_INPUT_PULLDOWN, 0) /* (C27) MMC1_CLK */ AM65X_IOPAD(0x02d8, PIN_INPUT_PULLUP, 0) /* (C28) MMC1_CMD */ @@ -295,7 +295,7 @@ >; }; - usb1_pins_default: usb1-pins-default { + usb1_pins_default: usb1-default-pins { pinctrl-single,pins = < AM65X_IOPAD(0x02c0, PIN_OUTPUT, 0) /* (AC8) USB1_DRVVBUS */ >; @@ -303,21 +303,21 @@ }; &main_pmx1 { - main_i2c0_pins_default: main-i2c0-pins-default { + main_i2c0_pins_default: main-i2c0-default-pins { pinctrl-single,pins = < AM65X_IOPAD(0x0000, PIN_INPUT, 0) /* (D20) I2C0_SCL */ AM65X_IOPAD(0x0004, PIN_INPUT, 0) /* (C21) I2C0_SDA */ >; }; - main_i2c1_pins_default: main-i2c1-pins-default { + main_i2c1_pins_default: main-i2c1-default-pins { pinctrl-single,pins = < AM65X_IOPAD(0x0008, PIN_INPUT, 0) /* (B21) I2C1_SCL */ AM65X_IOPAD(0x000c, PIN_INPUT, 0) /* (E21) I2C1_SDA */ >; }; - ecap0_pins_default: ecap0-pins-default { + ecap0_pins_default: ecap0-default-pins { pinctrl-single,pins = < AM65X_IOPAD(0x0010, PIN_INPUT, 0) /* (D21) ECAP0_IN_APWM_OUT */ >; diff --git a/arch/arm64/boot/dts/ti/k3-am6548-iot2050-advanced-common.dtsi b/arch/arm64/boot/dts/ti/k3-am6548-iot2050-advanced-common.dtsi index 0f67e1ec0fb8..be55494b1f3f 100644 --- a/arch/arm64/boot/dts/ti/k3-am6548-iot2050-advanced-common.dtsi +++ b/arch/arm64/boot/dts/ti/k3-am6548-iot2050-advanced-common.dtsi @@ -22,7 +22,7 @@ }; &main_pmx0 { - main_mmc0_pins_default: main-mmc0-pins-default { + main_mmc0_pins_default: main-mmc0-default-pins { pinctrl-single,pins = < AM65X_IOPAD(0x01a8, PIN_INPUT_PULLDOWN, 0) /* (B25) MMC0_CLK */ AM65X_IOPAD(0x01ac, PIN_INPUT_PULLUP, 0) /* (B27) MMC0_CMD */ diff --git a/arch/arm64/boot/dts/ti/k3-am6548-iot2050-advanced-m2.dts b/arch/arm64/boot/dts/ti/k3-am6548-iot2050-advanced-m2.dts index 9209b5a7baa4..cbe44634914f 100644 --- a/arch/arm64/boot/dts/ti/k3-am6548-iot2050-advanced-m2.dts +++ b/arch/arm64/boot/dts/ti/k3-am6548-iot2050-advanced-m2.dts @@ -27,7 +27,7 @@ }; &main_pmx0 { - main_m2_enable_pins_default: main-m2-enable-pins-default { + main_m2_enable_pins_default: main-m2-enable-default-pins { pinctrl-single,pins = < AM65X_IOPAD(0x01c4, PIN_INPUT_PULLUP, 7) /* (AH13) GPIO1_17 */ >; @@ -39,7 +39,7 @@ >; }; - main_pmx0_m2_config_pins_default: main-pmx0-m2-config-pins-default { + main_pmx0_m2_config_pins_default: main-pmx0-m2-config-default-pins { pinctrl-single,pins = < AM65X_IOPAD(0x01c8, PIN_INPUT_PULLUP, 7) /* (AE13) GPIO1_18 */ AM65X_IOPAD(0x01cc, PIN_INPUT_PULLUP, 7) /* (AD13) GPIO1_19 */ @@ -56,7 +56,7 @@ }; &main_pmx1 { - main_pmx1_m2_config_pins_default: main-pmx1-m2-config-pins-default { + main_pmx1_m2_config_pins_default: main-pmx1-m2-config-default-pins { pinctrl-single,pins = < AM65X_IOPAD(0x0018, PIN_INPUT_PULLUP, 7) /* (B22) GPIO1_88 */ AM65X_IOPAD(0x001c, PIN_INPUT_PULLUP, 7) /* (C23) GPIO1_89 */ diff --git a/arch/arm64/boot/dts/ti/k3-am68-sk-base-board.dts b/arch/arm64/boot/dts/ti/k3-am68-sk-base-board.dts index 979898bc5b02..d5889ba3fa46 100644 --- a/arch/arm64/boot/dts/ti/k3-am68-sk-base-board.dts +++ b/arch/arm64/boot/dts/ti/k3-am68-sk-base-board.dts @@ -124,21 +124,21 @@ }; &main_pmx0 { - main_uart8_pins_default: main-uart8-pins-default { + main_uart8_pins_default: main-uart8-default-pins { pinctrl-single,pins = < J721S2_IOPAD(0x0d0, PIN_INPUT, 11) /* (AF26) SPI0_CS1.UART8_RXD */ J721S2_IOPAD(0x0d4, PIN_OUTPUT, 11) /* (AH27) SPI0_CLK.UART8_TXD */ >; }; - main_i2c0_pins_default: main-i2c0-pins-default { + main_i2c0_pins_default: main-i2c0-default-pins { pinctrl-single,pins = < J721S2_IOPAD(0x0e0, PIN_INPUT, 0) /* (AH25) I2C0_SCL */ J721S2_IOPAD(0x0e4, PIN_INPUT, 0) /* (AE24) I2C0_SDA */ >; }; - main_mmc1_pins_default: main-mmc1-pins-default { + main_mmc1_pins_default: main-mmc1-default-pins { pinctrl-single,pins = < J721S2_IOPAD(0x104, PIN_INPUT, 0) /* (P23) MMC1_CLK */ J721S2_IOPAD(0x108, PIN_INPUT, 0) /* (N24) MMC1_CMD */ @@ -150,40 +150,40 @@ >; }; - vdd_sd_dv_pins_default: vdd-sd-dv-pins-default { + vdd_sd_dv_pins_default: vdd-sd-dv-default-pins { pinctrl-single,pins = < J721S2_IOPAD(0x0c4, PIN_INPUT, 7) /* (AB26) ECAP0_IN_APWM_OUT.GPIO0_49 */ >; }; - main_usbss0_pins_default: main-usbss0-pins-default { + main_usbss0_pins_default: main-usbss0-default-pins { pinctrl-single,pins = < J721S2_IOPAD(0x0ec, PIN_OUTPUT, 6) /* (AG25) TIMER_IO1.USB0_DRVVBUS */ >; }; - main_mcan6_pins_default: main-mcan6-pins-default { + main_mcan6_pins_default: main-mcan6-default-pins { pinctrl-single,pins = < J721S2_IOPAD(0x098, PIN_INPUT, 0) /* (V25) MCASP0_AXR10.MCAN6_RX */ J721S2_IOPAD(0x094, PIN_INPUT, 0) /* (AA25) MCASP0_AXR9.MCAN6_TX */ >; }; - main_mcan7_pins_default: main-mcan7-pins-default { + main_mcan7_pins_default: main-mcan7-default-pins { pinctrl-single,pins = < J721S2_IOPAD(0x0a0, PIN_INPUT, 0) /* (AB25) MCASP0_AXR12.MCAN7_RX */ J721S2_IOPAD(0x09c, PIN_INPUT, 0) /* (T24) MCASP0_AXR11.MCAN7_TX */ >; }; - main_i2c4_pins_default: main-i2c4-pins-default { + main_i2c4_pins_default: main-i2c4-default-pins { pinctrl-single,pins = < J721S2_IOPAD(0x010, PIN_INPUT_PULLUP, 8) /* (AF28) MCAN13_RX.I2C4_SDA */ J721S2_IOPAD(0x014, PIN_INPUT_PULLUP, 8) /* (AD25) MCAN14_TX.I2C4_SCL */ >; }; - rpi_header_gpio0_pins_default: rpi-header-gpio0-pins-default { + rpi_header_gpio0_pins_default: rpi-header-gpio0-default-pins { pinctrl-single,pins = < J721S2_IOPAD(0x0a8, PIN_INPUT, 7) /* (U24) MCASP0_AXR14.GPIO0_42 */ J721S2_IOPAD(0x090, PIN_INPUT, 7) /* (W24) MCASP0_AXR8.GPIO0_36 */ @@ -204,7 +204,7 @@ }; &wkup_pmx2 { - wkup_uart0_pins_default: wkup-uart0-pins-default { + wkup_uart0_pins_default: wkup-uart0-default-pins { pinctrl-single,pins = < J721S2_WKUP_IOPAD(0x070, PIN_INPUT, 0) /* (E25) WKUP_GPIO0_6.WKUP_UART0_CTSn */ J721S2_WKUP_IOPAD(0x074, PIN_OUTPUT, 0) /* (F28) WKUP_GPIO0_7.WKUP_UART0_RTSn */ @@ -213,7 +213,7 @@ >; }; - mcu_cpsw_pins_default: mcu-cpsw-pins-default { + mcu_cpsw_pins_default: mcu-cpsw-default-pins { pinctrl-single,pins = < J721S2_WKUP_IOPAD(0x02C, PIN_INPUT, 0) /* (B22) MCU_RGMII1_RD0 */ J721S2_WKUP_IOPAD(0x028, PIN_INPUT, 0) /* (B21) MCU_RGMII1_RD1 */ @@ -230,42 +230,42 @@ >; }; - mcu_mdio_pins_default: mcu-mdio-pins-default { + mcu_mdio_pins_default: mcu-mdio-default-pins { pinctrl-single,pins = < J721S2_WKUP_IOPAD(0x034, PIN_OUTPUT, 0) /* (A21) MCU_MDIO0_MDC */ J721S2_WKUP_IOPAD(0x030, PIN_INPUT, 0) /* (A22) MCU_MDIO0_MDIO */ >; }; - mcu_mcan0_pins_default: mcu-mcan0-pins-default { + mcu_mcan0_pins_default: mcu-mcan0-default-pins { pinctrl-single,pins = < J721S2_WKUP_IOPAD(0x054, PIN_INPUT, 0) /* (E28) MCU_MCAN0_RX */ J721S2_WKUP_IOPAD(0x050, PIN_OUTPUT, 0) /* (E27) MCU_MCAN0_TX */ >; }; - mcu_mcan1_pins_default: mcu-mcan1-pins-default { + mcu_mcan1_pins_default: mcu-mcan1-default-pins { pinctrl-single,pins = < J721S2_WKUP_IOPAD(0x06C, PIN_INPUT, 0) /* (F26) WKUP_GPIO0_5.MCU_MCAN1_RX */ J721S2_WKUP_IOPAD(0x068, PIN_OUTPUT, 0) /* (C23) WKUP_GPIO0_4.MCU_MCAN1_TX*/ >; }; - mcu_i2c0_pins_default: mcu-i2c0-pins-default { + mcu_i2c0_pins_default: mcu-i2c0-default-pins { pinctrl-single,pins = < J721S2_WKUP_IOPAD(0x0a0, PIN_INPUT, 0) /* (G24) MCU_I2C0_SCL */ J721S2_WKUP_IOPAD(0x0a4, PIN_INPUT, 0) /* (J25) MCU_I2C0_SDA */ >; }; - mcu_i2c1_pins_default: mcu-i2c1-pins-default { + mcu_i2c1_pins_default: mcu-i2c1-default-pins { pinctrl-single,pins = < J721S2_WKUP_IOPAD(0x078, PIN_INPUT, 0) /* (F24) WKUP_GPIO0_8.MCU_I2C1_SCL */ J721S2_WKUP_IOPAD(0x07c, PIN_INPUT, 0) /* (H26) WKUP_GPIO0_9.MCU_I2C1_SDA */ >; }; - mcu_uart0_pins_default: mcu-uart0-pins-default { + mcu_uart0_pins_default: mcu-uart0-default-pins { pinctrl-single,pins = < J721S2_WKUP_IOPAD(0x08c, PIN_INPUT, 0) /* (C24) WKUP_GPIO0_13.MCU_UART0_RXD */ J721S2_WKUP_IOPAD(0x088, PIN_OUTPUT, 0) /* (C25) WKUP_GPIO0_12.MCU_UART0_TXD */ diff --git a/arch/arm64/boot/dts/ti/k3-am68-sk-som.dtsi b/arch/arm64/boot/dts/ti/k3-am68-sk-som.dtsi index e2c80fff7478..6c9139f73201 100644 --- a/arch/arm64/boot/dts/ti/k3-am68-sk-som.dtsi +++ b/arch/arm64/boot/dts/ti/k3-am68-sk-som.dtsi @@ -29,7 +29,7 @@ }; &wkup_pmx2 { - wkup_i2c0_pins_default: wkup-i2c0-pins-default { + wkup_i2c0_pins_default: wkup-i2c0-default-pins { pinctrl-single,pins = < J721S2_WKUP_IOPAD(0x098, PIN_INPUT, 0) /* (H24) WKUP_I2C0_SCL */ J721S2_WKUP_IOPAD(0x09c, PIN_INPUT, 0) /* (H27) WKUP_I2C0_SDA */ diff --git a/arch/arm64/boot/dts/ti/k3-am69-sk.dts b/arch/arm64/boot/dts/ti/k3-am69-sk.dts index 6e12a45a2287..d282c2c633c1 100644 --- a/arch/arm64/boot/dts/ti/k3-am69-sk.dts +++ b/arch/arm64/boot/dts/ti/k3-am69-sk.dts @@ -110,21 +110,21 @@ }; &main_pmx0 { - main_uart8_pins_default: main-uart8-pins-default { + main_uart8_pins_default: main-uart8-default-pins { pinctrl-single,pins = < J784S4_IOPAD(0x0d0, PIN_INPUT, 11) /* (AP38) SPI0_CS1.UART8_RXD */ J784S4_IOPAD(0x0d4, PIN_OUTPUT, 11) /* (AN38) SPI0_CLK.UART8_TXD */ >; }; - main_i2c0_pins_default: main-i2c0-pins-default { + main_i2c0_pins_default: main-i2c0-default-pins { pinctrl-single,pins = < J784S4_IOPAD(0x0e0, PIN_INPUT_PULLUP, 0) /* (AN36) I2C0_SCL */ J784S4_IOPAD(0x0e4, PIN_INPUT_PULLUP, 0) /* (AP37) I2C0_SDA */ >; }; - main_mmc1_pins_default: main-mmc1-pins-default { + main_mmc1_pins_default: main-mmc1-default-pins { pinctrl-single,pins = < J784S4_IOPAD(0x104, PIN_INPUT, 0) /* (AB38) MMC1_CLK */ J784S4_IOPAD(0x108, PIN_INPUT, 0) /* (AB36) MMC1_CMD */ @@ -137,13 +137,13 @@ >; }; - vdd_sd_dv_pins_default: vdd-sd-dv-pins-default { + vdd_sd_dv_pins_default: vdd-sd-dv-default-pins { pinctrl-single,pins = < J784S4_IOPAD(0x0C4, PIN_INPUT, 7) /* (AD36) ECAP0_IN_APWM_OUT.GPIO0_49 */ >; }; - rpi_header_gpio0_pins_default: rpi-header-gpio0-pins-default { + rpi_header_gpio0_pins_default: rpi-header-gpio0-default-pins { pinctrl-single,pins = < J784S4_IOPAD(0x0BC, PIN_INPUT, 7) /* (AD33) MCASP1_AFSX.GPIO0_47 */ J784S4_IOPAD(0x06C, PIN_INPUT, 7) /* (AJ37) MCASP4_AFSX.GPIO0_27 */ @@ -164,7 +164,7 @@ }; &wkup_pmx2 { - wkup_uart0_pins_default: wkup-uart0-pins-default { + wkup_uart0_pins_default: wkup-uart0-default-pins { pinctrl-single,pins = < J721S2_WKUP_IOPAD(0x070, PIN_INPUT, 0) /* (L37) WKUP_GPIO0_6.WKUP_UART0_CTSn */ J721S2_WKUP_IOPAD(0x074, PIN_INPUT, 0) /* (L36) WKUP_GPIO0_7.WKUP_UART0_RTSn */ @@ -173,28 +173,28 @@ >; }; - wkup_i2c0_pins_default: wkup-i2c0-pins-default { + wkup_i2c0_pins_default: wkup-i2c0-default-pins { pinctrl-single,pins = < J721S2_WKUP_IOPAD(0x98, PIN_INPUT, 0) /* (N33) WKUP_I2C0_SCL */ J721S2_WKUP_IOPAD(0x9c, PIN_INPUT, 0) /* (N35) WKUP_I2C0_SDA */ >; }; - mcu_uart0_pins_default: mcu-uart0-pins-default { + mcu_uart0_pins_default: mcu-uart0-default-pins { pinctrl-single,pins = < J784S4_WKUP_IOPAD(0x08c, PIN_INPUT, 0) /* (K38) WKUP_GPIO0_13.MCU_UART0_RXD */ J784S4_WKUP_IOPAD(0x088, PIN_OUTPUT, 0) /* (J37) WKUP_GPIO0_12.MCU_UART0_TXD */ >; }; - mcu_i2c0_pins_default: mcu-i2c0-pins-default { + mcu_i2c0_pins_default: mcu-i2c0-default-pins { pinctrl-single,pins = < J784S4_WKUP_IOPAD(0x0a0, PIN_INPUT_PULLUP, 0) /* (M35) MCU_I2C0_SCL */ J784S4_WKUP_IOPAD(0x0a4, PIN_INPUT_PULLUP, 0) /* (G34) MCU_I2C0_SDA */ >; }; - mcu_cpsw_pins_default: mcu-cpsw-pins-default { + mcu_cpsw_pins_default: mcu-cpsw-default-pins { pinctrl-single,pins = < J784S4_WKUP_IOPAD(0x02c, PIN_INPUT, 0) /* (A35) MCU_RGMII1_RD0 */ J784S4_WKUP_IOPAD(0x028, PIN_INPUT, 0) /* (B36) MCU_RGMII1_RD1 */ @@ -211,14 +211,14 @@ >; }; - mcu_mdio_pins_default: mcu-mdio-pins-default { + mcu_mdio_pins_default: mcu-mdio-default-pins { pinctrl-single,pins = < J784S4_WKUP_IOPAD(0x034, PIN_OUTPUT, 0) /* (A36) MCU_MDIO0_MDC */ J784S4_WKUP_IOPAD(0x030, PIN_INPUT, 0) /* (B35) MCU_MDIO0_MDIO */ >; }; - mcu_rpi_hdr1_gpio0_pins_default: mcu-rpi-hdr1-gpio0-pins-default { + mcu_rpi_hdr1_gpio0_pins_default: mcu-rpi-hdr1-gpio0-default-pins { pinctrl-single,pins = < J784S4_WKUP_IOPAD(0x118, PIN_INPUT, 7) /* (N34) WKUP_GPIO0_66 */ J784S4_WKUP_IOPAD(0x05c, PIN_INPUT, 7) /* (J34) WKUP_GPIO0_1 */ @@ -234,7 +234,7 @@ }; &wkup_pmx3 { - mcu_rpi_hdr2_gpio0_pins_default: mcu-rpi-hdr2-gpio0-pins-default { + mcu_rpi_hdr2_gpio0_pins_default: mcu-rpi-hdr2-gpio0-default-pins { pinctrl-single,pins = < J784S4_WKUP_IOPAD(0x0, PIN_INPUT, 7) /* (M33) WKUP_GPIO0_49 */ >; diff --git a/arch/arm64/boot/dts/ti/k3-j7200-common-proc-board.dts b/arch/arm64/boot/dts/ti/k3-j7200-common-proc-board.dts index b5159a30108c..3cf288128c3f 100644 --- a/arch/arm64/boot/dts/ti/k3-j7200-common-proc-board.dts +++ b/arch/arm64/boot/dts/ti/k3-j7200-common-proc-board.dts @@ -90,7 +90,7 @@ }; &wkup_pmx0 { - mcu_uart0_pins_default: mcu-uart0-pins-default { + mcu_uart0_pins_default: mcu-uart0-default-pins { pinctrl-single,pins = < J721E_WKUP_IOPAD(0xf4, PIN_INPUT, 0) /* (D20) MCU_UART0_RXD */ J721E_WKUP_IOPAD(0xf0, PIN_OUTPUT, 0) /* (D19) MCU_UART0_TXD */ @@ -99,7 +99,7 @@ >; }; - wkup_uart0_pins_default: wkup-uart0-pins-default { + wkup_uart0_pins_default: wkup-uart0-default-pins { pinctrl-single,pins = < J721E_WKUP_IOPAD(0xb0, PIN_INPUT, 0) /* (B14) WKUP_UART0_RXD */ J721E_WKUP_IOPAD(0xb4, PIN_OUTPUT, 0) /* (A14) WKUP_UART0_TXD */ @@ -108,7 +108,7 @@ }; &wkup_pmx2 { - mcu_cpsw_pins_default: mcu-cpsw-pins-default { + mcu_cpsw_pins_default: mcu-cpsw-default-pins { pinctrl-single,pins = < J721E_WKUP_IOPAD(0x0000, PIN_OUTPUT, 0) /* MCU_RGMII1_TX_CTL */ J721E_WKUP_IOPAD(0x0004, PIN_INPUT, 0) /* MCU_RGMII1_RX_CTL */ @@ -125,13 +125,13 @@ >; }; - wkup_gpio_pins_default: wkup-gpio-pins-default { + wkup_gpio_pins_default: wkup-gpio-default-pins { pinctrl-single,pins = < J721E_WKUP_IOPAD(0x70, PIN_INPUT, 7) /* (C14) WKUP_GPIO0_6 */ >; }; - mcu_mdio_pins_default: mcu-mdio1-pins-default { + mcu_mdio_pins_default: mcu-mdio1-default-pins { pinctrl-single,pins = < J721E_WKUP_IOPAD(0x0034, PIN_OUTPUT, 0) /* (L1) MCU_MDIO0_MDC */ J721E_WKUP_IOPAD(0x0030, PIN_INPUT, 0) /* (L4) MCU_MDIO0_MDIO */ @@ -140,7 +140,7 @@ }; &main_pmx0 { - main_uart0_pins_default: main-uart0-pins-default { + main_uart0_pins_default: main-uart0-default-pins { pinctrl-single,pins = < J721E_IOPAD(0xb0, PIN_INPUT, 0) /* (T16) UART0_RXD */ J721E_IOPAD(0xb4, PIN_OUTPUT, 0) /* (T17) UART0_TXD */ @@ -149,28 +149,28 @@ >; }; - main_uart1_pins_default: main-uart1-pins-default { + main_uart1_pins_default: main-uart1-default-pins { pinctrl-single,pins = < J721E_IOPAD(0xb8, PIN_INPUT, 0) /* (T18) UART1_RXD */ J721E_IOPAD(0xbc, PIN_INPUT, 0) /* (T20) UART1_TXD */ >; }; - main_uart3_pins_default: main-uart3-pins-default { + main_uart3_pins_default: main-uart3-default-pins { pinctrl-single,pins = < J721E_IOPAD(0x60, PIN_INPUT, 11) /* (T15) MCAN8_TX.UART3_CTSn */ J721E_IOPAD(0x30, PIN_INPUT, 11) /* (Y18) MCAN2_TX.UART3_RXD */ >; }; - main_i2c1_pins_default: main-i2c1-pins-default { + main_i2c1_pins_default: main-i2c1-default-pins { pinctrl-single,pins = < J721E_IOPAD(0xdc, PIN_INPUT_PULLUP, 3) /* (U3) ECAP0_IN_APWM_OUT.I2C1_SCL */ J721E_IOPAD(0xe0, PIN_INPUT_PULLUP, 3) /* (T3) EXT_REFCLK1.I2C1_SDA */ >; }; - main_mmc1_pins_default: main-mmc1-pins-default { + main_mmc1_pins_default: main-mmc1-default-pins { pinctrl-single,pins = < J721E_IOPAD(0x104, PIN_INPUT, 0) /* (M20) MMC1_CMD */ J721E_IOPAD(0x100, PIN_INPUT, 0) /* (P21) MMC1_CLK */ @@ -183,7 +183,7 @@ >; }; - vdd_sd_dv_pins_default: vdd-sd-dv-pins-default { + vdd_sd_dv_pins_default: vdd-sd-dv-default-pins { pinctrl-single,pins = < J721E_IOPAD(0xd0, PIN_OUTPUT, 7) /* (T5) SPI0_D1.GPIO0_55 */ >; @@ -191,7 +191,7 @@ }; &main_pmx1 { - main_usbss0_pins_default: main-usbss0-pins-default { + main_usbss0_pins_default: main-usbss0-default-pins { pinctrl-single,pins = < J721E_IOPAD(0x04, PIN_OUTPUT, 0) /* (T4) USB0_DRVVBUS */ >; diff --git a/arch/arm64/boot/dts/ti/k3-j7200-evm-quad-port-eth-exp.dtso b/arch/arm64/boot/dts/ti/k3-j7200-evm-quad-port-eth-exp.dtso index 31b932eebc0a..34a0747cbe69 100644 --- a/arch/arm64/boot/dts/ti/k3-j7200-evm-quad-port-eth-exp.dtso +++ b/arch/arm64/boot/dts/ti/k3-j7200-evm-quad-port-eth-exp.dtso @@ -92,7 +92,7 @@ }; &main_pmx0 { - mdio0_pins_default: mdio0-pins-default { + mdio0_pins_default: mdio0-default-pins { pinctrl-single,pins = < J721E_IOPAD(0x00a8, PIN_OUTPUT, 5) /* (W19) UART8_TXD.MDIO0_MDC */ J721E_IOPAD(0x00a4, PIN_INPUT, 5) /* (W14) UART8_RXD.MDIO0_MDIO */ diff --git a/arch/arm64/boot/dts/ti/k3-j7200-som-p0.dtsi b/arch/arm64/boot/dts/ti/k3-j7200-som-p0.dtsi index e763d571b916..b37f4f88ece4 100644 --- a/arch/arm64/boot/dts/ti/k3-j7200-som-p0.dtsi +++ b/arch/arm64/boot/dts/ti/k3-j7200-som-p0.dtsi @@ -83,7 +83,7 @@ }; &wkup_pmx0 { - mcu_fss0_hpb0_pins_default: mcu-fss0-hpb0-pins-default { + mcu_fss0_hpb0_pins_default: mcu-fss0-hpb0-default-pins { pinctrl-single,pins = < J721E_WKUP_IOPAD(0x0, PIN_OUTPUT, 1) /* (B6) MCU_OSPI0_CLK.MCU_HYPERBUS0_CK */ J721E_WKUP_IOPAD(0x4, PIN_OUTPUT, 1) /* (C8) MCU_OSPI0_LBCLKO.MCU_HYPERBUS0_CKn */ @@ -101,7 +101,7 @@ >; }; - mcu_fss0_ospi0_pins_default: mcu-fss0-ospi0-pins-default { + mcu_fss0_ospi0_pins_default: mcu-fss0-ospi0-default-pins { pinctrl-single,pins = < J721E_WKUP_IOPAD(0x0000, PIN_OUTPUT, 0) /* MCU_OSPI0_CLK */ J721E_WKUP_IOPAD(0x002c, PIN_OUTPUT, 0) /* MCU_OSPI0_CSn0 */ @@ -119,7 +119,7 @@ }; &wkup_pmx2 { - wkup_i2c0_pins_default: wkup-i2c0-pins-default { + wkup_i2c0_pins_default: wkup-i2c0-default-pins { pinctrl-single,pins = < J721E_WKUP_IOPAD(0x98, PIN_INPUT_PULLUP, 0) /* (F20) WKUP_I2C0_SCL */ J721E_WKUP_IOPAD(0x9c, PIN_INPUT_PULLUP, 0) /* (H21) WKUP_I2C0_SDA */ @@ -128,7 +128,7 @@ }; &main_pmx0 { - main_i2c0_pins_default: main-i2c0-pins-default { + main_i2c0_pins_default: main-i2c0-default-pins { pinctrl-single,pins = < J721E_IOPAD(0xd4, PIN_INPUT_PULLUP, 0) /* (V3) I2C0_SCL */ J721E_IOPAD(0xd8, PIN_INPUT_PULLUP, 0) /* (W2) I2C0_SDA */ diff --git a/arch/arm64/boot/dts/ti/k3-j721e-beagleboneai64.dts b/arch/arm64/boot/dts/ti/k3-j721e-beagleboneai64.dts index 27347a07d330..66aac145e753 100644 --- a/arch/arm64/boot/dts/ti/k3-j721e-beagleboneai64.dts +++ b/arch/arm64/boot/dts/ti/k3-j721e-beagleboneai64.dts @@ -305,7 +305,7 @@ }; &main_pmx0 { - led_pins_default: led-pins-default { + led_pins_default: led-default-pins { pinctrl-single,pins = < J721E_IOPAD(0x184, PIN_INPUT, 7) /* (T23) RGMII5_RD0.GPIO0_96 */ J721E_IOPAD(0x180, PIN_INPUT, 7) /* (R23) RGMII5_RD1.GPIO0_95 */ @@ -315,7 +315,7 @@ >; }; - main_mmc1_pins_default: main-mmc1-pins-default { + main_mmc1_pins_default: main-mmc1-default-pins { pinctrl-single,pins = < J721E_IOPAD(0x254, PIN_INPUT, 0) /* (R29) MMC1_CMD */ J721E_IOPAD(0x250, PIN_INPUT, 0) /* (P25) MMC1_CLK */ @@ -328,64 +328,64 @@ >; }; - main_uart0_pins_default: main-uart0-pins-default { + main_uart0_pins_default: main-uart0-default-pins { pinctrl-single,pins = < J721E_IOPAD(0x1e8, PIN_INPUT, 0) /* (AB2) UART0_RXD */ J721E_IOPAD(0x1ec, PIN_OUTPUT, 0) /* (AB3) UART0_TXD */ >; }; - sd_pwr_en_pins_default: sd-pwr-en-pins-default { + sd_pwr_en_pins_default: sd-pwr-en-default-pins { pinctrl-single,pins = < J721E_IOPAD(0x14c, PIN_INPUT, 7) /* (AA29) PRG0_PRU1_GPO19.GPIO0_82 */ >; }; - vdd_sd_dv_alt_pins_default: vdd-sd-dv-alt-pins-default { + vdd_sd_dv_alt_pins_default: vdd-sd-dv-alt-default-pins { pinctrl-single,pins = < J721E_IOPAD(0x1d8, PIN_INPUT, 7) /* (W4) SPI1_CS1.GPIO0_117 */ >; }; - main_usbss0_pins_default: main-usbss0-pins-default { + main_usbss0_pins_default: main-usbss0-default-pins { pinctrl-single,pins = < J721E_IOPAD(0x210, PIN_INPUT, 7) /* (W3) MCAN1_RX.GPIO1_3 - USBC_DIR */ >; }; - main_usbss1_pins_default: main-usbss1-pins-default { + main_usbss1_pins_default: main-usbss1-default-pins { pinctrl-single,pins = < J721E_IOPAD(0x290, INPUT_DISABLE, 1) /* (U6) USB0_DRVVBUS.USB1_DRVVBUS */ >; }; - dp0_3v3_en_pins_default:dp0-3v3-en-pins-default { + dp0_3v3_en_pins_default:dp0-3v3-en-default-pins { pinctrl-single,pins = < J721E_IOPAD(0xc8, PIN_INPUT, 7) /* (AE26) PRG0_PRU0_GPO6.GPIO0_49 */ >; }; - dp0_pins_default: dp0-pins-default { + dp0_pins_default: dp0-default-pins { pinctrl-single,pins = < J721E_IOPAD(0x1c4, PIN_INPUT, 5) /* (Y4) SPI0_CS1.DP0_HPD */ >; }; - main_i2c0_pins_default: main-i2c0-pins-default { + main_i2c0_pins_default: main-i2c0-default-pins { pinctrl-single,pins = < J721E_IOPAD(0x220, PIN_INPUT_PULLUP, 0) /* (AC5) I2C0_SCL */ J721E_IOPAD(0x224, PIN_INPUT_PULLUP, 0) /* (AA5) I2C0_SDA */ >; }; - main_i2c1_pins_default: main-i2c1-pins-default { + main_i2c1_pins_default: main-i2c1-default-pins { pinctrl-single,pins = < J721E_IOPAD(0x228, PIN_INPUT_PULLUP, 0) /* (Y6) I2C1_SCL */ J721E_IOPAD(0x22c, PIN_INPUT_PULLUP, 0) /* (AA6) I2C1_SDA */ >; }; - main_i2c2_pins_default: main-i2c2-pins-default { + main_i2c2_pins_default: main-i2c2-default-pins { pinctrl-single,pins = < J721E_IOPAD(0x208, PIN_INPUT_PULLUP, 4) /* (W5) MCAN0_RX.I2C2_SCL */ J721E_IOPAD(0x20c, PIN_INPUT_PULLUP, 4) /* (W6) MCAN0_TX.I2C2_SDA */ @@ -394,14 +394,14 @@ >; }; - main_i2c3_pins_default: main-i2c3-pins-default { + main_i2c3_pins_default: main-i2c3-default-pins { pinctrl-single,pins = < J721E_IOPAD(0x270, PIN_INPUT_PULLUP, 4) /* (T26) MMC2_CLK.I2C3_SCL */ J721E_IOPAD(0x274, PIN_INPUT_PULLUP, 4) /* (T25) MMC2_CMD.I2C3_SDA */ >; }; - main_i2c4_pins_default: main-i2c4-pins-default { + main_i2c4_pins_default: main-i2c4-default-pins { pinctrl-single,pins = < J721E_IOPAD(0x1e0, PIN_INPUT_PULLUP, 2) /* (Y5) SPI1_D0.I2C4_SCL */ J721E_IOPAD(0x1dc, PIN_INPUT_PULLUP, 2) /* (Y1) SPI1_CLK.I2C4_SDA */ @@ -410,14 +410,14 @@ >; }; - main_i2c5_pins_default: main-i2c5-pins-default { + main_i2c5_pins_default: main-i2c5-default-pins { pinctrl-single,pins = < J721E_IOPAD(0x150, PIN_INPUT_PULLUP, 2) /* (Y26) PRG0_MDIO0_MDIO.I2C5_SCL */ J721E_IOPAD(0x154, PIN_INPUT_PULLUP, 2) /* (AA27) PRG0_MDIO0_MDC.I2C5_SDA */ >; }; - main_i2c6_pins_default: main-i2c6-pins-default { + main_i2c6_pins_default: main-i2c6-default-pins { pinctrl-single,pins = < J721E_IOPAD(0x1d0, PIN_INPUT_PULLUP, 2) /* (AA3) SPI0_D1.I2C6_SCL */ J721E_IOPAD(0x1e4, PIN_INPUT_PULLUP, 2) /* (Y2) SPI1_D1.I2C6_SDA */ @@ -426,21 +426,21 @@ >; }; - csi0_gpio_pins_default: csi0-gpio-pins-default { + csi0_gpio_pins_default: csi0-gpio-default-pins { pinctrl-single,pins = < J721E_IOPAD(0x19c, PIN_INPUT_PULLDOWN, 7) /* (W27) RGMII6_TD0.GPIO0_102 */ J721E_IOPAD(0x1a0, PIN_INPUT_PULLDOWN, 7) /* (W29) RGMII6_TXC.GPIO0_103 */ >; }; - csi1_gpio_pins_default: csi1-gpio-pins-default { + csi1_gpio_pins_default: csi1-gpio-default-pins { pinctrl-single,pins = < J721E_IOPAD(0x198, PIN_INPUT_PULLDOWN, 7) /* (V25) RGMII6_TD1.GPIO0_101 */ J721E_IOPAD(0x1b0, PIN_INPUT_PULLDOWN, 7) /* (W24) RGMII6_RD1.GPIO0_107 */ >; }; - pcie1_rst_pins_default: pcie1-rst-pins-default { + pcie1_rst_pins_default: pcie1-rst-default-pins { pinctrl-single,pins = < J721E_IOPAD(0x5c, PIN_INPUT, 7) /* (AG23) PRG1_PRU1_GPO1.GPIO0_22 */ >; @@ -448,13 +448,13 @@ }; &wkup_pmx0 { - eeprom_wp_pins_default: eeprom-wp-pins-default { + eeprom_wp_pins_default: eeprom-wp-default-pins { pinctrl-single,pins = < J721E_WKUP_IOPAD(0xc4, PIN_OUTPUT_PULLUP, 7) /* (G24) WKUP_GPIO0_5 */ >; }; - mcu_adc0_pins_default: mcu-adc0-pins-default { + mcu_adc0_pins_default: mcu-adc0-default-pins { pinctrl-single,pins = < J721E_WKUP_IOPAD(0x130, PIN_INPUT, 0) /* (K25) MCU_ADC0_AIN0 */ J721E_WKUP_IOPAD(0x134, PIN_INPUT, 0) /* (K26) MCU_ADC0_AIN1 */ @@ -466,13 +466,13 @@ >; }; - mcu_adc1_pins_default: mcu-adc1-pins-default { + mcu_adc1_pins_default: mcu-adc1-default-pins { pinctrl-single,pins = < J721E_WKUP_IOPAD(0x150, PIN_INPUT, 0) /* (N23) MCU_ADC1_AIN0 */ >; }; - mikro_bus_pins_default: mikro-bus-pins-default { + mikro_bus_pins_default: mikro-bus-default-pins { pinctrl-single,pins = < J721E_WKUP_IOPAD(0x108, PIN_INPUT, 7) /* SDAPULLEN (E26) PMIC_POWER_EN0.WKUP_GPIO0_66 */ J721E_WKUP_IOPAD(0xd4, PIN_INPUT, 7) /* SDA (G26) WKUP_GPIO0_9.MCU_I2C1_SDA */ @@ -495,7 +495,7 @@ >; }; - mcu_cpsw_pins_default: mcu-cpsw-pins-default { + mcu_cpsw_pins_default: mcu-cpsw-default-pins { pinctrl-single,pins = < J721E_WKUP_IOPAD(0x84, PIN_INPUT, 0) /* (B24) MCU_RGMII1_RD0 */ J721E_WKUP_IOPAD(0x80, PIN_INPUT, 0) /* (A24) MCU_RGMII1_RD1 */ @@ -512,34 +512,34 @@ >; }; - mcu_mdio_pins_default: mcu-mdio1-pins-default { + mcu_mdio_pins_default: mcu-mdio1-default-pins { pinctrl-single,pins = < J721E_WKUP_IOPAD(0x8c, PIN_OUTPUT, 0) /* (F23) MCU_MDIO0_MDC */ J721E_WKUP_IOPAD(0x88, PIN_INPUT, 0) /* (E23) MCU_MDIO0_MDIO */ >; }; - sw_pwr_pins_default: sw-pwr-pins-default { + sw_pwr_pins_default: sw-pwr-default-pins { pinctrl-single,pins = < J721E_WKUP_IOPAD(0xc0, PIN_INPUT, 7) /* (G25) WKUP_GPIO0_4 */ >; }; - wkup_i2c0_pins_default: wkup-i2c0-pins-default { + wkup_i2c0_pins_default: wkup-i2c0-default-pins { pinctrl-single,pins = < J721E_WKUP_IOPAD(0xf8, PIN_INPUT_PULLUP, 0) /* (J25) WKUP_I2C0_SCL */ J721E_WKUP_IOPAD(0xfc, PIN_INPUT_PULLUP, 0) /* (H24) WKUP_I2C0_SDA */ >; }; - wkup_uart0_pins_default: wkup-uart0-pins-default { + wkup_uart0_pins_default: wkup-uart0-default-pins { pinctrl-single,pins = < J721E_WKUP_IOPAD(0xa0, PIN_INPUT, 0) /* (J29) WKUP_UART0_RXD */ J721E_WKUP_IOPAD(0xa4, PIN_OUTPUT, 0) /* (J28) WKUP_UART0_TXD */ >; }; - mcu_usbss1_pins_default: mcu-usbss1-pins-default { + mcu_usbss1_pins_default: mcu-usbss1-default-pins { pinctrl-single,pins = < J721E_WKUP_IOPAD(0x3c, PIN_OUTPUT_PULLUP, 5) /* (A23) MCU_OSPI1_LBCLKO.WKUP_GPIO0_30 */ >; diff --git a/arch/arm64/boot/dts/ti/k3-j721e-common-proc-board.dts b/arch/arm64/boot/dts/ti/k3-j721e-common-proc-board.dts index 5fc002e5a18c..c1cbbae76182 100644 --- a/arch/arm64/boot/dts/ti/k3-j721e-common-proc-board.dts +++ b/arch/arm64/boot/dts/ti/k3-j721e-common-proc-board.dts @@ -186,7 +186,7 @@ }; &main_pmx0 { - main_uart0_pins_default: main-uart0-pins-default { + main_uart0_pins_default: main-uart0-default-pins { pinctrl-single,pins = < J721E_IOPAD(0x1d4, PIN_INPUT, 1) /* (Y3) SPI1_CS0.UART0_CTSn */ J721E_IOPAD(0x1c0, PIN_OUTPUT, 1) /* (AA2) SPI0_CS0.UART0_RTSn */ @@ -195,34 +195,34 @@ >; }; - main_uart1_pins_default: main-uart1-pins-default { + main_uart1_pins_default: main-uart1-default-pins { pinctrl-single,pins = < J721E_IOPAD(0x1f8, PIN_INPUT, 0) /* (AA4) UART1_RXD */ J721E_IOPAD(0x1fc, PIN_OUTPUT, 0) /* (AB4) UART1_TXD */ >; }; - main_uart2_pins_default: main-uart2-pins-default { + main_uart2_pins_default: main-uart2-default-pins { pinctrl-single,pins = < J721E_IOPAD(0x1dc, PIN_INPUT, 3) /* (Y1) SPI1_CLK.UART2_RXD */ J721E_IOPAD(0x1e0, PIN_OUTPUT, 3) /* (Y5) SPI1_D0.UART2_TXD */ >; }; - main_uart4_pins_default: main-uart4-pins-default { + main_uart4_pins_default: main-uart4-default-pins { pinctrl-single,pins = < J721E_IOPAD(0x190, PIN_INPUT, 1) /* (W23) RGMII6_TD3.UART4_RXD */ J721E_IOPAD(0x194, PIN_OUTPUT, 1) /* (W28) RGMII6_TD2.UART4_TXD */ >; }; - sw10_button_pins_default: sw10-button-pins-default { + sw10_button_pins_default: sw10-button-default-pins { pinctrl-single,pins = < J721E_IOPAD(0x0, PIN_INPUT, 7) /* (AC18) EXTINTn.GPIO0_0 */ >; }; - main_mmc1_pins_default: main-mmc1-pins-default { + main_mmc1_pins_default: main-mmc1-default-pins { pinctrl-single,pins = < J721E_IOPAD(0x254, PIN_INPUT, 0) /* (R29) MMC1_CMD */ J721E_IOPAD(0x250, PIN_INPUT, 0) /* (P25) MMC1_CLK */ @@ -236,66 +236,66 @@ >; }; - vdd_sd_dv_alt_pins_default: vdd-sd-dv-alt-pins-default { + vdd_sd_dv_alt_pins_default: vdd-sd-dv-alt-default-pins { pinctrl-single,pins = < J721E_IOPAD(0x1d8, PIN_INPUT, 7) /* (W4) SPI1_CS1.GPIO0_117 */ >; }; - main_usbss0_pins_default: main-usbss0-pins-default { + main_usbss0_pins_default: main-usbss0-default-pins { pinctrl-single,pins = < J721E_IOPAD(0x290, PIN_OUTPUT, 0) /* (U6) USB0_DRVVBUS */ J721E_IOPAD(0x210, PIN_INPUT, 7) /* (W3) MCAN1_RX.GPIO1_3 */ >; }; - main_usbss1_pins_default: main-usbss1-pins-default { + main_usbss1_pins_default: main-usbss1-default-pins { pinctrl-single,pins = < J721E_IOPAD(0x214, PIN_OUTPUT, 4) /* (V4) MCAN1_TX.USB1_DRVVBUS */ >; }; - dp0_pins_default: dp0-pins-default { + dp0_pins_default: dp0-default-pins { pinctrl-single,pins = < J721E_IOPAD(0x1c4, PIN_INPUT, 5) /* SPI0_CS1.DP0_HPD */ >; }; - main_i2c1_exp4_pins_default: main-i2c1-exp4-pins-default { + main_i2c1_exp4_pins_default: main-i2c1-exp4-default-pins { pinctrl-single,pins = < J721E_IOPAD(0x230, PIN_INPUT, 7) /* (U2) ECAP0_IN_APWM_OUT.GPIO1_11 */ >; }; - main_i2c0_pins_default: main-i2c0-pins-default { + main_i2c0_pins_default: main-i2c0-default-pins { pinctrl-single,pins = < J721E_IOPAD(0x220, PIN_INPUT_PULLUP, 0) /* (AC5) I2C0_SCL */ J721E_IOPAD(0x224, PIN_INPUT_PULLUP, 0) /* (AA5) I2C0_SDA */ >; }; - main_i2c1_pins_default: main-i2c1-pins-default { + main_i2c1_pins_default: main-i2c1-default-pins { pinctrl-single,pins = < J721E_IOPAD(0x228, PIN_INPUT_PULLUP, 0) /* (Y6) I2C1_SCL */ J721E_IOPAD(0x22c, PIN_INPUT_PULLUP, 0) /* (AA6) I2C1_SDA */ >; }; - main_i2c3_pins_default: main-i2c3-pins-default { + main_i2c3_pins_default: main-i2c3-default-pins { pinctrl-single,pins = < J721E_IOPAD(0x270, PIN_INPUT_PULLUP, 4) /* (T26) MMC2_CLK.I2C3_SCL */ J721E_IOPAD(0x274, PIN_INPUT_PULLUP, 4) /* (T25) MMC2_CMD.I2C3_SDA */ >; }; - main_i2c6_pins_default: main-i2c6-pins-default { + main_i2c6_pins_default: main-i2c6-default-pins { pinctrl-single,pins = < J721E_IOPAD(0x1d0, PIN_INPUT_PULLUP, 2) /* (AA3) SPI0_D1.I2C6_SCL */ J721E_IOPAD(0x1e4, PIN_INPUT_PULLUP, 2) /* (Y2) SPI1_D1.I2C6_SDA */ >; }; - mcasp10_pins_default: mcasp10-pins-default { + mcasp10_pins_default: mcasp10-default-pins { pinctrl-single,pins = < J721E_IOPAD(0x158, PIN_OUTPUT_PULLDOWN, 12) /* (U23) RGMII5_TX_CTL.MCASP10_ACLKX */ J721E_IOPAD(0x15c, PIN_OUTPUT_PULLDOWN, 12) /* (U26) RGMII5_RX_CTL.MCASP10_AFSX */ @@ -309,27 +309,27 @@ >; }; - audi_ext_refclk2_pins_default: audi-ext-refclk2-pins-default { + audi_ext_refclk2_pins_default: audi-ext-refclk2-default-pins { pinctrl-single,pins = < J721E_IOPAD(0x1a4, PIN_OUTPUT, 3) /* (W26) RGMII6_RXC.AUDIO_EXT_REFCLK2 */ >; }; - main_mcan0_pins_default: main-mcan0-pins-default { + main_mcan0_pins_default: main-mcan0-default-pins { pinctrl-single,pins = < J721E_IOPAD(0x208, PIN_INPUT, 0) /* (W5) MCAN0_RX */ J721E_IOPAD(0x20c, PIN_OUTPUT, 0) /* (W6) MCAN0_TX */ >; }; - main_mcan2_pins_default: main-mcan2-pins-default { + main_mcan2_pins_default: main-mcan2-default-pins { pinctrl-single,pins = < J721E_IOPAD(0x01f0, PIN_INPUT, 3) /* (AC2) MCAN2_RX.GPIO0_123 */ J721E_IOPAD(0x01f4, PIN_OUTPUT, 3) /* (AB1) MCAN2_TX.GPIO0_124 */ >; }; - main_mcan2_gpio_pins_default: main-mcan2-gpio-pins-default { + main_mcan2_gpio_pins_default: main-mcan2-gpio-default-pins { pinctrl-single,pins = < J721E_IOPAD(0x200, PIN_INPUT, 7) /* (AC4) UART1_CTSn.GPIO0_127 */ >; @@ -337,14 +337,14 @@ }; &wkup_pmx0 { - wkup_uart0_pins_default: wkup-uart0-pins-default { + wkup_uart0_pins_default: wkup-uart0-default-pins { pinctrl-single,pins = < J721E_WKUP_IOPAD(0xa0, PIN_INPUT, 0) /* (J29) WKUP_UART0_RXD */ J721E_WKUP_IOPAD(0xa4, PIN_OUTPUT, 0) /* (J28) WKUP_UART0_TXD */ >; }; - mcu_uart0_pins_default: mcu-uart0-pins-default { + mcu_uart0_pins_default: mcu-uart0-default-pins { pinctrl-single,pins = < J721E_WKUP_IOPAD(0xe8, PIN_INPUT, 0) /* (H29) WKUP_GPIO0_14.MCU_UART0_CTSn */ J721E_WKUP_IOPAD(0xec, PIN_OUTPUT, 0) /* (J27) WKUP_GPIO0_15.MCU_UART0_RTSn */ @@ -353,13 +353,13 @@ >; }; - sw11_button_pins_default: sw11-button-pins-default { + sw11_button_pins_default: sw11-button-default-pins { pinctrl-single,pins = < J721E_WKUP_IOPAD(0xcc, PIN_INPUT, 7) /* (G28) WKUP_GPIO0_7 */ >; }; - mcu_fss0_ospi1_pins_default: mcu-fss0-ospi1-pins-default { + mcu_fss0_ospi1_pins_default: mcu-fss0-ospi1-default-pins { pinctrl-single,pins = < J721E_WKUP_IOPAD(0x34, PIN_OUTPUT, 0) /* (F22) MCU_OSPI1_CLK */ J721E_WKUP_IOPAD(0x50, PIN_OUTPUT, 0) /* (C22) MCU_OSPI1_CSn0 */ @@ -372,7 +372,7 @@ >; }; - mcu_cpsw_pins_default: mcu-cpsw-pins-default { + mcu_cpsw_pins_default: mcu-cpsw-default-pins { pinctrl-single,pins = < J721E_WKUP_IOPAD(0x0058, PIN_OUTPUT, 0) /* MCU_RGMII1_TX_CTL */ J721E_WKUP_IOPAD(0x005c, PIN_INPUT, 0) /* MCU_RGMII1_RX_CTL */ @@ -389,41 +389,41 @@ >; }; - mcu_mdio_pins_default: mcu-mdio1-pins-default { + mcu_mdio_pins_default: mcu-mdio1-default-pins { pinctrl-single,pins = < J721E_WKUP_IOPAD(0x008c, PIN_OUTPUT, 0) /* MCU_MDIO0_MDC */ J721E_WKUP_IOPAD(0x0088, PIN_INPUT, 0) /* MCU_MDIO0_MDIO */ >; }; - mcu_mcan0_pins_default: mcu-mcan0-pins-default { + mcu_mcan0_pins_default: mcu-mcan0-default-pins { pinctrl-single,pins = < J721E_WKUP_IOPAD(0xac, PIN_INPUT, 0) /* (C29) MCU_MCAN0_RX */ J721E_WKUP_IOPAD(0xa8, PIN_OUTPUT, 0) /* (D29) MCU_MCAN0_TX */ >; }; - mcu_mcan0_gpio_pins_default: mcu-mcan0-gpio-pins-default { + mcu_mcan0_gpio_pins_default: mcu-mcan0-gpio-default-pins { pinctrl-single,pins = < J721E_WKUP_IOPAD(0xb0, PIN_INPUT, 7) /* (F26) WKUP_GPIO0_0 */ J721E_WKUP_IOPAD(0x98, PIN_INPUT, 7) /* (E28) MCU_SPI0_D1.WKUP_GPIO0_54 */ >; }; - mcu_mcan1_pins_default: mcu-mcan1-pins-default { + mcu_mcan1_pins_default: mcu-mcan1-default-pins { pinctrl-single,pins = < J721E_WKUP_IOPAD(0xc4, PIN_INPUT, 0) /* (G24) WKUP_GPIO0_5.MCU_MCAN1_RX */ J721E_WKUP_IOPAD(0xc0, PIN_OUTPUT, 0) /* (G25) WKUP_GPIO0_4.MCU_MCAN1_TX */ >; }; - mcu_mcan1_gpio_pins_default: mcu-mcan1-gpio-pins-default { + mcu_mcan1_gpio_pins_default: mcu-mcan1-gpio-default-pins { pinctrl-single,pins = < J721E_WKUP_IOPAD(0xb8, PIN_INPUT, 7) /* (F28) WKUP_GPIO0_2 */ >; }; - wkup_gpio_pins_default: wkup-gpio-pins-default { + wkup_gpio_pins_default: wkup-gpio-default-pins { pinctrl-single,pins = < J721E_WKUP_IOPAD(0xd0, PIN_INPUT, 7) /* (C14) WKUP_GPIO0_8 */ >; diff --git a/arch/arm64/boot/dts/ti/k3-j721e-evm-quad-port-eth-exp.dtso b/arch/arm64/boot/dts/ti/k3-j721e-evm-quad-port-eth-exp.dtso index 6ff7b6ad33ed..6f0adf591b98 100644 --- a/arch/arm64/boot/dts/ti/k3-j721e-evm-quad-port-eth-exp.dtso +++ b/arch/arm64/boot/dts/ti/k3-j721e-evm-quad-port-eth-exp.dtso @@ -94,7 +94,7 @@ }; &main_pmx0 { - mdio0_pins_default: mdio0-pins-default { + mdio0_pins_default: mdio0-default-pins { pinctrl-single,pins = < J721E_IOPAD(0x1bc, PIN_OUTPUT, 0) /* (V24) MDIO0_MDC */ J721E_IOPAD(0x1b8, PIN_INPUT, 0) /* (V26) MDIO0_MDIO */ diff --git a/arch/arm64/boot/dts/ti/k3-j721e-sk.dts b/arch/arm64/boot/dts/ti/k3-j721e-sk.dts index ce6eb93fca9e..0ee4f38ec8f0 100644 --- a/arch/arm64/boot/dts/ti/k3-j721e-sk.dts +++ b/arch/arm64/boot/dts/ti/k3-j721e-sk.dts @@ -289,7 +289,7 @@ }; &main_pmx0 { - main_mmc1_pins_default: main-mmc1-pins-default { + main_mmc1_pins_default: main-mmc1-default-pins { pinctrl-single,pins = < J721E_IOPAD(0x254, PIN_INPUT, 0) /* (R29) MMC1_CMD */ J721E_IOPAD(0x250, PIN_INPUT, 0) /* (P25) MMC1_CLK */ @@ -302,7 +302,7 @@ >; }; - main_uart0_pins_default: main-uart0-pins-default { + main_uart0_pins_default: main-uart0-default-pins { pinctrl-single,pins = < J721E_IOPAD(0x1f0, PIN_INPUT, 0) /* (AC2) UART0_CTSn */ J721E_IOPAD(0x1f4, PIN_OUTPUT, 0) /* (AB1) UART0_RTSn */ @@ -311,60 +311,60 @@ >; }; - main_uart1_pins_default: main-uart1-pins-default { + main_uart1_pins_default: main-uart1-default-pins { pinctrl-single,pins = < J721E_IOPAD(0x1f8, PIN_INPUT, 0) /* (AA4) UART1_RXD */ J721E_IOPAD(0x1fc, PIN_OUTPUT, 0) /* (AB4) UART1_TXD */ >; }; - main_i2c0_pins_default: main-i2c0-pins-default { + main_i2c0_pins_default: main-i2c0-default-pins { pinctrl-single,pins = < J721E_IOPAD(0x220, PIN_INPUT_PULLUP, 0) /* (AC5) I2C0_SCL */ J721E_IOPAD(0x224, PIN_INPUT_PULLUP, 0) /* (AA5) I2C0_SDA */ >; }; - main_i2c1_pins_default: main-i2c1-pins-default { + main_i2c1_pins_default: main-i2c1-default-pins { pinctrl-single,pins = < J721E_IOPAD(0x228, PIN_INPUT_PULLUP, 0) /* (Y6) I2C1_SCL */ J721E_IOPAD(0x22c, PIN_INPUT_PULLUP, 0) /* (AA6) I2C1_SDA */ >; }; - main_i2c3_pins_default: main-i2c3-pins-default { + main_i2c3_pins_default: main-i2c3-default-pins { pinctrl-single,pins = < J721E_IOPAD(0x270, PIN_INPUT_PULLUP, 4) /* (T26) MMC2_CLK.I2C3_SCL */ J721E_IOPAD(0x274, PIN_INPUT_PULLUP, 4) /* (T25) MMC2_CMD.I2C3_SDA */ >; }; - main_usbss0_pins_default: main-usbss0-pins-default { + main_usbss0_pins_default: main-usbss0-default-pins { pinctrl-single,pins = < J721E_IOPAD(0x290, PIN_OUTPUT, 0) /* (U6) USB0_DRVVBUS */ J721E_IOPAD(0x210, PIN_INPUT, 7) /* (W3) MCAN1_RX.GPIO1_3 */ >; }; - main_usbss1_pins_default: main-usbss1-pins-default { + main_usbss1_pins_default: main-usbss1-default-pins { pinctrl-single,pins = < J721E_IOPAD(0x214, PIN_OUTPUT, 4) /* (V4) MCAN1_TX.USB1_DRVVBUS */ >; }; - dp0_pins_default: dp0-pins-default { + dp0_pins_default: dp0-default-pins { pinctrl-single,pins = < J721E_IOPAD(0x1c4, PIN_INPUT, 5) /* SPI0_CS1.DP0_HPD */ >; }; - dp_pwr_en_pins_default: dp-pwr-en-pins-default { + dp_pwr_en_pins_default: dp-pwr-en-default-pins { pinctrl-single,pins = < J721E_IOPAD(0x1c0, PIN_INPUT, 7) /* (AA2) SPI0_CS0.GPIO0_111 */ >; }; - dss_vout0_pins_default: dss-vout0-pins-default { + dss_vout0_pins_default: dss-vout0-default-pins { pinctrl-single,pins = < J721E_IOPAD(0x58, PIN_OUTPUT, 10) /* (AE22) PRG1_PRU1_GPO0.VOUT0_DATA0 */ J721E_IOPAD(0x5c, PIN_OUTPUT, 10) /* (AG23) PRG1_PRU1_GPO1.VOUT0_DATA1 */ @@ -397,33 +397,33 @@ >; }; - hdmi_hpd_pins_default: hdmi-hpd-pins-default { + hdmi_hpd_pins_default: hdmi-hpd-default-pins { pinctrl-single,pins = < J721E_IOPAD(0x204, PIN_INPUT, 7) /* (AD5) UART1_RTSn.GPIO1_0 */ >; }; - hdmi_pdn_pins_default: hdmi-pdn-pins-default { + hdmi_pdn_pins_default: hdmi-pdn-default-pins { pinctrl-single,pins = < J721E_IOPAD(0x200, PIN_INPUT, 7) /* (AC4) UART1_CTSn.GPIO0_127 */ >; }; /* Reset for M.2 E Key slot on PCIe0 */ - ekey_reset_pins_default: ekey-reset-pns-pins-default { + ekey_reset_pins_default: ekey-reset-pns-default-pins { pinctrl-single,pins = < J721E_IOPAD(0x124, PIN_INPUT, 7) /* (Y24) PRG0_PRU1_GPO9.GPIO0_72 */ >; }; - main_i2c5_pins_default: main-i2c5-pins-default { + main_i2c5_pins_default: main-i2c5-default-pins { pinctrl-single,pins = < J721E_IOPAD(0x150, PIN_INPUT_PULLUP, 2) /* (Y26) PRG0_MDIO0_MDIO.I2C5_SCL */ J721E_IOPAD(0x154, PIN_INPUT_PULLUP, 2) /* (AA27) PRG0_MDIO0_MDC.I2C5_SDA */ >; }; - rpi_header_gpio0_pins_default: rpi-header-gpio0-pins-default { + rpi_header_gpio0_pins_default: rpi-header-gpio0-default-pins { pinctrl-single,pins = < J721E_IOPAD(0x01C, PIN_INPUT, 7) /* (AD22) PRG1_PRU0_GPO6.GPIO0_7 */ J721E_IOPAD(0x120, PIN_INPUT, 7) /* (AA28) PRG0_PRU1_GPO8.GPIO0_71 */ @@ -451,7 +451,7 @@ >; }; - rpi_header_gpio1_pins_default: rpi-header-gpio1-pins-default { + rpi_header_gpio1_pins_default: rpi-header-gpio1-default-pins { pinctrl-single,pins = < J721E_IOPAD(0x234, PIN_INPUT, 7) /* (U3) EXT_REFCLK1.GPIO1_12 */ >; @@ -459,7 +459,7 @@ }; &wkup_pmx0 { - mcu_cpsw_pins_default: mcu-cpsw-pins-default { + mcu_cpsw_pins_default: mcu-cpsw-default-pins { pinctrl-single,pins = < J721E_WKUP_IOPAD(0x84, PIN_INPUT, 0) /* (B24) MCU_RGMII1_RD0 */ J721E_WKUP_IOPAD(0x80, PIN_INPUT, 0) /* (A24) MCU_RGMII1_RD1 */ @@ -476,14 +476,14 @@ >; }; - mcu_mdio_pins_default: mcu-mdio1-pins-default { + mcu_mdio_pins_default: mcu-mdio1-default-pins { pinctrl-single,pins = < J721E_WKUP_IOPAD(0x8c, PIN_OUTPUT, 0) /* (F23) MCU_MDIO0_MDC */ J721E_WKUP_IOPAD(0x88, PIN_INPUT, 0) /* (E23) MCU_MDIO0_MDIO */ >; }; - mcu_fss0_ospi0_pins_default: mcu-fss0-ospi0-pins-default { + mcu_fss0_ospi0_pins_default: mcu-fss0-ospi0-default-pins { pinctrl-single,pins = < J721E_WKUP_IOPAD(0x0, PIN_OUTPUT, 0) /* (E20) MCU_OSPI0_CLK */ J721E_WKUP_IOPAD(0x2c, PIN_OUTPUT, 0) /* (F19) MCU_OSPI0_CSn0 */ @@ -499,26 +499,26 @@ >; }; - vdd_mmc1_en_pins_default: vdd-mmc1-en-pins-default { + vdd_mmc1_en_pins_default: vdd-mmc1-en-default-pins { pinctrl-single,pins = < J721E_WKUP_IOPAD(0xd0, PIN_OUTPUT, 7) /* (G27) WKUP_GPIO0_8 */ >; }; - vdd_sd_dv_alt_pins_default: vdd-sd-dv-alt-pins-default { + vdd_sd_dv_alt_pins_default: vdd-sd-dv-alt-default-pins { pinctrl-single,pins = < J721E_WKUP_IOPAD(0xd4, PIN_OUTPUT, 7) /* (G26) WKUP_GPIO0_9 */ >; }; - wkup_uart0_pins_default: wkup-uart0-pins-default { + wkup_uart0_pins_default: wkup-uart0-default-pins { pinctrl-single,pins = < J721E_WKUP_IOPAD(0xa0, PIN_INPUT, 0) /* (J29) WKUP_UART0_RXD */ J721E_WKUP_IOPAD(0xa4, PIN_OUTPUT, 0) /* (J28) WKUP_UART0_TXD */ >; }; - mcu_uart0_pins_default: mcu-uart0-pins-default { + mcu_uart0_pins_default: mcu-uart0-default-pins { pinctrl-single,pins = < J721E_WKUP_IOPAD(0xf0, PIN_INPUT, 2) /* (D26) MCU_I3C0_SCL.MCU_UART0_CTSn */ J721E_WKUP_IOPAD(0xf4, PIN_OUTPUT, 2)/* (D25) MCU_I3C0_SDA.MCU_UART0_RTSn */ @@ -527,7 +527,7 @@ >; }; - wkup_i2c0_pins_default: wkup-i2c0-pins-default { + wkup_i2c0_pins_default: wkup-i2c0-default-pins { pinctrl-single,pins = < J721E_WKUP_IOPAD(0xf8, PIN_INPUT_PULLUP, 0) /* (J25) WKUP_I2C0_SCL */ J721E_WKUP_IOPAD(0xfc, PIN_INPUT_PULLUP, 0) /* (H24) WKUP_I2C0_SDA */ @@ -535,7 +535,7 @@ }; /* Reset for M.2 M Key slot on PCIe1 */ - mkey_reset_pins_default: mkey-reset-pns-pins-default { + mkey_reset_pins_default: mkey-reset-pns-default-pins { pinctrl-single,pins = < J721E_WKUP_IOPAD(0xdc, PIN_INPUT, 7) /* (H27) WKUP_GPIO0_11 */ >; diff --git a/arch/arm64/boot/dts/ti/k3-j721e-som-p0.dtsi b/arch/arm64/boot/dts/ti/k3-j721e-som-p0.dtsi index 8431f5f57cd2..38ae13cc3aa3 100644 --- a/arch/arm64/boot/dts/ti/k3-j721e-som-p0.dtsi +++ b/arch/arm64/boot/dts/ti/k3-j721e-som-p0.dtsi @@ -145,14 +145,14 @@ }; &wkup_pmx0 { - wkup_i2c0_pins_default: wkup-i2c0-pins-default { + wkup_i2c0_pins_default: wkup-i2c0-default-pins { pinctrl-single,pins = < J721E_WKUP_IOPAD(0xf8, PIN_INPUT_PULLUP, 0) /* (J25) WKUP_I2C0_SCL */ J721E_WKUP_IOPAD(0xfc, PIN_INPUT_PULLUP, 0) /* (H24) WKUP_I2C0_SDA */ >; }; - mcu_fss0_ospi0_pins_default: mcu-fss0-ospi0-pins-default { + mcu_fss0_ospi0_pins_default: mcu-fss0-ospi0-default-pins { pinctrl-single,pins = < J721E_WKUP_IOPAD(0x0000, PIN_OUTPUT, 0) /* MCU_OSPI0_CLK */ J721E_WKUP_IOPAD(0x0008, PIN_INPUT, 0) /* MCU_OSPI0_DQS */ @@ -168,7 +168,7 @@ >; }; - mcu_fss0_hpb0_pins_default: mcu-fss0-hpb0-pins-default { + mcu_fss0_hpb0_pins_default: mcu-fss0-hpb0-default-pins { pinctrl-single,pins = < J721E_WKUP_IOPAD(0x0, PIN_OUTPUT, 1) /* MCU_HYPERBUS0_CK */ J721E_WKUP_IOPAD(0x4, PIN_OUTPUT, 1) /* MCU_HYPERBUS0_CKn */ diff --git a/arch/arm64/boot/dts/ti/k3-j721s2-common-proc-board.dts b/arch/arm64/boot/dts/ti/k3-j721s2-common-proc-board.dts index e7136ddb9178..04d4739d7245 100644 --- a/arch/arm64/boot/dts/ti/k3-j721s2-common-proc-board.dts +++ b/arch/arm64/boot/dts/ti/k3-j721s2-common-proc-board.dts @@ -112,7 +112,7 @@ }; &main_pmx0 { - main_uart8_pins_default: main-uart8-pins-default { + main_uart8_pins_default: main-uart8-default-pins { pinctrl-single,pins = < J721S2_IOPAD(0x040, PIN_INPUT, 14) /* (AC28) MCASP0_AXR0.UART8_CTSn */ J721S2_IOPAD(0x044, PIN_OUTPUT, 14) /* (Y26) MCASP0_AXR1.UART8_RTSn */ @@ -121,14 +121,14 @@ >; }; - main_i2c3_pins_default: main-i2c3-pins-default { + main_i2c3_pins_default: main-i2c3-default-pins { pinctrl-single,pins = < J721S2_IOPAD(0x064, PIN_INPUT_PULLUP, 13) /* (W28) MCAN0_TX.I2C3_SCL */ J721S2_IOPAD(0x060, PIN_INPUT_PULLUP, 13) /* (AC27) MCASP2_AXR1.I2C3_SDA */ >; }; - main_mmc1_pins_default: main-mmc1-pins-default { + main_mmc1_pins_default: main-mmc1-default-pins { pinctrl-single,pins = < J721S2_IOPAD(0x104, PIN_INPUT, 0) /* (P23) MMC1_CLK */ J721S2_IOPAD(0x108, PIN_INPUT, 0) /* (N24) MMC1_CMD */ @@ -141,13 +141,13 @@ >; }; - vdd_sd_dv_pins_default: vdd-sd-dv-pins-default { + vdd_sd_dv_pins_default: vdd-sd-dv-default-pins { pinctrl-single,pins = < J721S2_IOPAD(0x020, PIN_INPUT, 7) /* (AA23) MCAN15_RX.GPIO0_8 */ >; }; - main_usbss0_pins_default: main-usbss0-pins-default { + main_usbss0_pins_default: main-usbss0-default-pins { pinctrl-single,pins = < J721S2_IOPAD(0x0ec, PIN_OUTPUT, 6) /* (AG25) TIMER_IO1.USB0_DRVVBUS */ >; @@ -155,7 +155,7 @@ }; &wkup_pmx2 { - wkup_uart0_pins_default: wkup-uart0-pins-default { + wkup_uart0_pins_default: wkup-uart0-default-pins { pinctrl-single,pins = < J721S2_WKUP_IOPAD(0x070, PIN_INPUT, 0) /* (E25) WKUP_GPIO0_6.WKUP_UART0_CTSn */ J721S2_WKUP_IOPAD(0x074, PIN_OUTPUT, 0) /* (F28) WKUP_GPIO0_7.WKUP_UART0_RTSn */ @@ -164,7 +164,7 @@ >; }; - mcu_uart0_pins_default: mcu-uart0-pins-default { + mcu_uart0_pins_default: mcu-uart0-default-pins { pinctrl-single,pins = < J721S2_WKUP_IOPAD(0x090, PIN_INPUT, 0) /* (B24) WKUP_GPIO0_14.MCU_UART0_CTSn */ J721S2_WKUP_IOPAD(0x094, PIN_OUTPUT, 0) /* (D25) WKUP_GPIO0_15.MCU_UART0_RTSn */ @@ -173,7 +173,7 @@ >; }; - mcu_cpsw_pins_default: mcu-cpsw-pins-default { + mcu_cpsw_pins_default: mcu-cpsw-default-pins { pinctrl-single,pins = < J721S2_WKUP_IOPAD(0x02c, PIN_INPUT, 0) /* (B22) MCU_RGMII1_RD0 */ J721S2_WKUP_IOPAD(0x028, PIN_INPUT, 0) /* (B21) MCU_RGMII1_RD1 */ @@ -190,41 +190,41 @@ >; }; - mcu_mdio_pins_default: mcu-mdio-pins-default { + mcu_mdio_pins_default: mcu-mdio-default-pins { pinctrl-single,pins = < J721S2_WKUP_IOPAD(0x034, PIN_OUTPUT, 0) /* (A21) MCU_MDIO0_MDC */ J721S2_WKUP_IOPAD(0x030, PIN_INPUT, 0) /* (A22) MCU_MDIO0_MDIO */ >; }; - mcu_mcan0_pins_default: mcu-mcan0-pins-default { + mcu_mcan0_pins_default: mcu-mcan0-default-pins { pinctrl-single,pins = < J721S2_WKUP_IOPAD(0x054, PIN_INPUT, 0) /* (E28) MCU_MCAN0_RX */ J721S2_WKUP_IOPAD(0x050, PIN_OUTPUT, 0) /* (E27) MCU_MCAN0_TX */ >; }; - mcu_mcan1_pins_default: mcu-mcan1-pins-default { + mcu_mcan1_pins_default: mcu-mcan1-default-pins { pinctrl-single,pins = < J721S2_WKUP_IOPAD(0x06c, PIN_INPUT, 0) /* (F26) WKUP_GPIO0_5.MCU_MCAN1_RX */ J721S2_WKUP_IOPAD(0x068, PIN_OUTPUT, 0) /*(C23) WKUP_GPIO0_4.MCU_MCAN1_TX */ >; }; - mcu_mcan0_gpio_pins_default: mcu-mcan0-gpio-pins-default { + mcu_mcan0_gpio_pins_default: mcu-mcan0-gpio-default-pins { pinctrl-single,pins = < J721S2_WKUP_IOPAD(0x058, PIN_INPUT, 7) /* (D26) WKUP_GPIO0_0 */ J721S2_WKUP_IOPAD(0x040, PIN_INPUT, 7) /* (B25) MCU_SPI0_D1.WKUP_GPIO0_69 */ >; }; - mcu_mcan1_gpio_pins_default: mcu-mcan1-gpio-pins-default { + mcu_mcan1_gpio_pins_default: mcu-mcan1-gpio-default-pins { pinctrl-single,pins = < J721S2_WKUP_IOPAD(0x060, PIN_INPUT, 7) /* (C28) WKUP_GPIO0_2 */ >; }; - mcu_adc0_pins_default: mcu-adc0-pins-default { + mcu_adc0_pins_default: mcu-adc0-default-pins { pinctrl-single,pins = < J721S2_WKUP_IOPAD(0x0cc, PIN_INPUT, 0) /* (L25) MCU_ADC0_AIN0 */ J721S2_WKUP_IOPAD(0x0d0, PIN_INPUT, 0) /* (K25) MCU_ADC0_AIN1 */ @@ -237,7 +237,7 @@ >; }; - mcu_adc1_pins_default: mcu-adc1-pins-default { + mcu_adc1_pins_default: mcu-adc1-default-pins { pinctrl-single,pins = < J721S2_WKUP_IOPAD(0x0ec, PIN_INPUT, 0) /* (P25) MCU_ADC1_AIN0 */ J721S2_WKUP_IOPAD(0x0f0, PIN_INPUT, 0) /* (R25) MCU_ADC1_AIN1 */ @@ -250,7 +250,7 @@ >; }; - mcu_fss0_ospi1_pins_default: mcu-fss0-ospi1-pins-default { + mcu_fss0_ospi1_pins_default: mcu-fss0-ospi1-default-pins { pinctrl-single,pins = < J721S2_WKUP_IOPAD(0x040, PIN_OUTPUT, 0) /* (A19) MCU_OSPI1_CLK */ J721S2_WKUP_IOPAD(0x05c, PIN_OUTPUT, 0) /* (D20) MCU_OSPI1_CSn0 */ diff --git a/arch/arm64/boot/dts/ti/k3-j721s2-som-p0.dtsi b/arch/arm64/boot/dts/ti/k3-j721s2-som-p0.dtsi index c1a6c36cde1d..d57dd43da0ef 100644 --- a/arch/arm64/boot/dts/ti/k3-j721s2-som-p0.dtsi +++ b/arch/arm64/boot/dts/ti/k3-j721s2-som-p0.dtsi @@ -40,7 +40,7 @@ }; &wkup_pmx0 { - mcu_fss0_ospi0_pins_default: mcu-fss0-ospi0-pins-default { + mcu_fss0_ospi0_pins_default: mcu-fss0-ospi0-default-pins { pinctrl-single,pins = < J721S2_WKUP_IOPAD(0x000, PIN_OUTPUT, 0) /* (D19) MCU_OSPI0_CLK */ J721S2_WKUP_IOPAD(0x02c, PIN_OUTPUT, 0) /* (F15) MCU_OSPI0_CSn0 */ @@ -62,7 +62,7 @@ }; &wkup_pmx2 { - wkup_i2c0_pins_default: wkup-i2c0-pins-default { + wkup_i2c0_pins_default: wkup-i2c0-default-pins { pinctrl-single,pins = < J721S2_WKUP_IOPAD(0x98, PIN_INPUT, 0) /* (H24) WKUP_I2C0_SCL */ J721S2_WKUP_IOPAD(0x9c, PIN_INPUT, 0) /* (H27) WKUP_I2C0_SDA */ @@ -71,14 +71,14 @@ }; &main_pmx0 { - main_i2c0_pins_default: main-i2c0-pins-default { + main_i2c0_pins_default: main-i2c0-default-pins { pinctrl-single,pins = < J721S2_IOPAD(0x0e0, PIN_INPUT_PULLUP, 0) /* (AH25) I2C0_SCL */ J721S2_IOPAD(0x0e4, PIN_INPUT_PULLUP, 0) /* (AE24) I2C0_SDA */ >; }; - main_mcan16_pins_default: main-mcan16-pins-default { + main_mcan16_pins_default: main-mcan16-default-pins { pinctrl-single,pins = < J721S2_IOPAD(0x028, PIN_INPUT, 0) /* (AB24) MCAN16_RX */ J721S2_IOPAD(0x024, PIN_OUTPUT, 0) /* (Y28) MCAN16_TX */ diff --git a/arch/arm64/boot/dts/ti/k3-j784s4-evm.dts b/arch/arm64/boot/dts/ti/k3-j784s4-evm.dts index 09f052c94844..430b8a2c5df5 100644 --- a/arch/arm64/boot/dts/ti/k3-j784s4-evm.dts +++ b/arch/arm64/boot/dts/ti/k3-j784s4-evm.dts @@ -252,7 +252,7 @@ }; &main_pmx0 { - main_uart8_pins_default: main-uart8-pins-default { + main_uart8_pins_default: main-uart8-default-pins { pinctrl-single,pins = < J784S4_IOPAD(0x040, PIN_INPUT, 14) /* (AF37) MCASP0_AXR0.UART8_CTSn */ J784S4_IOPAD(0x044, PIN_OUTPUT, 14) /* (AG37) MCASP0_AXR1.UART8_RTSn */ @@ -261,14 +261,14 @@ >; }; - main_i2c0_pins_default: main-i2c0-pins-default { + main_i2c0_pins_default: main-i2c0-default-pins { pinctrl-single,pins = < J784S4_IOPAD(0x0e0, PIN_INPUT_PULLUP, 0) /* (AN36) I2C0_SCL */ J784S4_IOPAD(0x0e4, PIN_INPUT_PULLUP, 0) /* (AP37) I2C0_SDA */ >; }; - main_mmc1_pins_default: main-mmc1-pins-default { + main_mmc1_pins_default: main-mmc1-default-pins { pinctrl-single,pins = < J784S4_IOPAD(0x104, PIN_INPUT, 0) /* (AB38) MMC1_CLK */ J784S4_IOPAD(0x108, PIN_INPUT, 0) /* (AB36) MMC1_CMD */ @@ -281,7 +281,7 @@ >; }; - vdd_sd_dv_pins_default: vdd-sd-dv-pins-default { + vdd_sd_dv_pins_default: vdd-sd-dv-default-pins { pinctrl-single,pins = < J784S4_IOPAD(0x020, PIN_INPUT, 7) /* (AJ35) MCAN15_RX.GPIO0_8 */ >; @@ -289,7 +289,7 @@ }; &wkup_pmx2 { - wkup_uart0_pins_default: wkup-uart0-pins-default { + wkup_uart0_pins_default: wkup-uart0-default-pins { pinctrl-single,pins = < J721S2_WKUP_IOPAD(0x070, PIN_INPUT, 0) /* (L37) WKUP_GPIO0_6.WKUP_UART0_CTSn */ J721S2_WKUP_IOPAD(0x074, PIN_INPUT, 0) /* (L36) WKUP_GPIO0_7.WKUP_UART0_RTSn */ @@ -298,14 +298,14 @@ >; }; - wkup_i2c0_pins_default: wkup-i2c0-pins-default { + wkup_i2c0_pins_default: wkup-i2c0-default-pins { pinctrl-single,pins = < J721S2_WKUP_IOPAD(0x98, PIN_INPUT, 0) /* (N33) WKUP_I2C0_SCL */ J721S2_WKUP_IOPAD(0x9c, PIN_INPUT, 0) /* (N35) WKUP_I2C0_SDA */ >; }; - mcu_uart0_pins_default: mcu-uart0-pins-default { + mcu_uart0_pins_default: mcu-uart0-default-pins { pinctrl-single,pins = < J784S4_WKUP_IOPAD(0x090, PIN_INPUT, 0) /* (H37) WKUP_GPIO0_14.MCU_UART0_CTSn */ J784S4_WKUP_IOPAD(0x094, PIN_OUTPUT, 0) /* (K37) WKUP_GPIO0_15.MCU_UART0_RTSn */ @@ -314,7 +314,7 @@ >; }; - mcu_cpsw_pins_default: mcu-cpsw-pins-default { + mcu_cpsw_pins_default: mcu-cpsw-default-pins { pinctrl-single,pins = < J784S4_WKUP_IOPAD(0x02c, PIN_INPUT, 0) /* (A35) MCU_RGMII1_RD0 */ J784S4_WKUP_IOPAD(0x028, PIN_INPUT, 0) /* (B36) MCU_RGMII1_RD1 */ @@ -331,14 +331,14 @@ >; }; - mcu_mdio_pins_default: mcu-mdio-pins-default { + mcu_mdio_pins_default: mcu-mdio-default-pins { pinctrl-single,pins = < J784S4_WKUP_IOPAD(0x034, PIN_OUTPUT, 0) /* (A36) MCU_MDIO0_MDC */ J784S4_WKUP_IOPAD(0x030, PIN_INPUT, 0) /* (B35) MCU_MDIO0_MDIO */ >; }; - mcu_adc0_pins_default: mcu-adc0-pins-default { + mcu_adc0_pins_default: mcu-adc0-default-pins { pinctrl-single,pins = < J784S4_WKUP_IOPAD(0x134, PIN_INPUT, 0) /* (P36) MCU_ADC0_AIN0 */ J784S4_WKUP_IOPAD(0x138, PIN_INPUT, 0) /* (V36) MCU_ADC0_AIN1 */ @@ -351,7 +351,7 @@ >; }; - mcu_adc1_pins_default: mcu-adc1-pins-default { + mcu_adc1_pins_default: mcu-adc1-default-pins { pinctrl-single,pins = < J784S4_WKUP_IOPAD(0x154, PIN_INPUT, 0) /* (Y38) MCU_ADC1_AIN0 */ J784S4_WKUP_IOPAD(0x158, PIN_INPUT, 0) /* (Y34) MCU_ADC1_AIN1 */ @@ -366,7 +366,7 @@ }; &wkup_pmx0 { - mcu_fss0_ospi0_pins_default: mcu-fss0-ospi0-pins-default { + mcu_fss0_ospi0_pins_default: mcu-fss0-ospi0-default-pins { pinctrl-single,pins = < J784S4_WKUP_IOPAD(0x000, PIN_OUTPUT, 0) /* (E32) MCU_OSPI0_CLK */ J784S4_WKUP_IOPAD(0x02c, PIN_OUTPUT, 0) /* (A32) MCU_OSPI0_CSn0 */ @@ -384,7 +384,7 @@ >; }; - mcu_fss0_ospi1_pins_default: mcu-fss0-ospi1-pins-default { + mcu_fss0_ospi1_pins_default: mcu-fss0-ospi1-default-pins { pinctrl-single,pins = < J784S4_WKUP_IOPAD(0x040, PIN_OUTPUT, 0) /* (F32) MCU_OSPI1_CLK */ J784S4_WKUP_IOPAD(0x05c, PIN_OUTPUT, 0) /* (G32) MCU_OSPI1_CSn0 */ -- cgit