[
    {
        "BriefDescription": "This event is deprecated. Refer to new event BUS_LOCK.SELF_LOCKS",
        "Counter": "0,1,2,3",
        "Deprecated": "1",
        "EdgeDetect": "1",
        "EventCode": "0x63",
        "EventName": "BUS_LOCK.ALL",
        "SampleAfterValue": "200003"
    },
    {
        "BriefDescription": "Counts the number of unhalted cycles a core is blocked due to an accepted lock issued by other cores.",
        "Counter": "0,1,2,3",
        "EventCode": "0x63",
        "EventName": "BUS_LOCK.BLOCK_CYCLES",
        "PublicDescription": "Counts the number of unhalted cycles a core is blocked due to an accepted lock issued by other cores. Counts on a per core basis.",
        "SampleAfterValue": "200003",
        "UMask": "0x2"
    },
    {
        "BriefDescription": "This event is deprecated. Refer to new event BUS_LOCK.BLOCK_CYCLES",
        "Counter": "0,1,2,3",
        "Deprecated": "1",
        "EventCode": "0x63",
        "EventName": "BUS_LOCK.CYCLES_OTHER_BLOCK",
        "SampleAfterValue": "200003",
        "UMask": "0x2"
    },
    {
        "BriefDescription": "This event is deprecated. Refer to new event BUS_LOCK.LOCK_CYCLES",
        "Counter": "0,1,2,3",
        "Deprecated": "1",
        "EventCode": "0x63",
        "EventName": "BUS_LOCK.CYCLES_SELF_BLOCK",
        "SampleAfterValue": "200003",
        "UMask": "0x1"
    },
    {
        "BriefDescription": "Counts the number of unhalted cycles a core is blocked due to an accepted lock it issued.",
        "Counter": "0,1,2,3",
        "EventCode": "0x63",
        "EventName": "BUS_LOCK.LOCK_CYCLES",
        "PublicDescription": "Counts the number of unhalted cycles a core is blocked due to an accepted lock it issued. Counts on a per core basis.",
        "SampleAfterValue": "200003",
        "UMask": "0x1"
    },
    {
        "BriefDescription": "Counts the number of bus locks a core issued its self (e.g. lock to UC or Split Lock) and does not include cache locks.",
        "Counter": "0,1,2,3",
        "EdgeDetect": "1",
        "EventCode": "0x63",
        "EventName": "BUS_LOCK.SELF_LOCKS",
        "PublicDescription": "Counts the number of bus locks a core issued its self (e.g. lock to UC or Split Lock) and does not include cache locks. Counts on a per core basis.",
        "SampleAfterValue": "200003"
    },
    {
        "BriefDescription": "This event is deprecated. Refer to new event MEM_BOUND_STALLS.LOAD_DRAM_HIT",
        "Counter": "0,1,2,3",
        "Deprecated": "1",
        "EventCode": "0x34",
        "EventName": "C0_STALLS.LOAD_DRAM_HIT",
        "SampleAfterValue": "200003",
        "UMask": "0x4"
    },
    {
        "BriefDescription": "This event is deprecated. Refer to new event MEM_BOUND_STALLS.LOAD_L2_HIT",
        "Counter": "0,1,2,3",
        "Deprecated": "1",
        "EventCode": "0x34",
        "EventName": "C0_STALLS.LOAD_L2_HIT",
        "SampleAfterValue": "200003",
        "UMask": "0x1"
    },
    {
        "BriefDescription": "This event is deprecated. Refer to new event MEM_BOUND_STALLS.LOAD_LLC_HIT",
        "Counter": "0,1,2,3",
        "Deprecated": "1",
        "EventCode": "0x34",
        "EventName": "C0_STALLS.LOAD_LLC_HIT",
        "SampleAfterValue": "200003",
        "UMask": "0x2"
    },
    {
        "BriefDescription": "Counts the number of core cycles during which interrupts are masked (disabled).",
        "Counter": "0,1,2,3",
        "EventCode": "0xcb",
        "EventName": "HW_INTERRUPTS.MASKED",
        "PublicDescription": "Counts the number of core cycles during which interrupts are masked (disabled). Increments by 1 each core cycle that EFLAGS.IF is 0, regardless of whether interrupts are pending or not.",
        "SampleAfterValue": "200003",
        "UMask": "0x2"
    },
    {
        "BriefDescription": "Counts the number of core cycles during which there are pending interrupts while interrupts are masked (disabled).",
        "Counter": "0,1,2,3",
        "EventCode": "0xcb",
        "EventName": "HW_INTERRUPTS.PENDING_AND_MASKED",
        "PublicDescription": "Counts the number of core cycles during which there are pending interrupts while interrupts are masked (disabled). Increments by 1 each core cycle that both EFLAGS.IF is 0 and an INTR is pending (which means the APIC is telling the ROB to cause an INTR). This event does not increment if EFLAGS.IF is 0 but all interrupt in the APICs Interrupt Request Register (IRR) are inhibited by the PPR (thus either by ISRV or TPR)  because in these cases the interrupts would be held up in the APIC and would not be pended to the ROB. This event does count when an interrupt is only inhibited by MOV/POP SS state machines or the STI state machine. These extra inhibits only last for a single instructions and would not be important.",
        "SampleAfterValue": "200003",
        "UMask": "0x4"
    },
    {
        "BriefDescription": "Counts the number of hardware interrupts received by the processor.",
        "Counter": "0,1,2,3",
        "EventCode": "0xcb",
        "EventName": "HW_INTERRUPTS.RECEIVED",
        "SampleAfterValue": "203",
        "UMask": "0x1"
    },
    {
        "BriefDescription": "Counts all code reads that have any type of response.",
        "Counter": "0,1,2,3",
        "EventCode": "0XB7",
        "EventName": "OCR.ALL_CODE_RD.ANY_RESPONSE",
        "MSRIndex": "0x1a6,0x1a7",
        "MSRValue": "0x10044",
        "PublicDescription": "Counts all code reads that have any type of response. Available PDIST counters: 0",
        "SampleAfterValue": "100003",
        "UMask": "0x1"
    },
    {
        "BriefDescription": "Counts all code reads that have an outstanding request. Returns the number of cycles until the response is received (i.e. XQ to XQ latency).",
        "Counter": "0,1,2,3",
        "EventCode": "0XB7",
        "EventName": "OCR.ALL_CODE_RD.OUTSTANDING",
        "MSRIndex": "0x1a6",
        "MSRValue": "0x8000000000000044",
        "PublicDescription": "Counts all code reads that have an outstanding request. Returns the number of cycles until the response is received (i.e. XQ to XQ latency). Available PDIST counters: 0",
        "SampleAfterValue": "100003",
        "UMask": "0x1"
    },
    {
        "BriefDescription": "Counts streaming stores which modify a full 64 byte cacheline that have any type of response.",
        "Counter": "0,1,2,3",
        "EventCode": "0XB7",
        "EventName": "OCR.FULL_STREAMING_WR.ANY_RESPONSE",
        "MSRIndex": "0x1a6,0x1a7",
        "MSRValue": "0x800000010000",
        "PublicDescription": "Counts streaming stores which modify a full 64 byte cacheline that have any type of response. Available PDIST counters: 0",
        "SampleAfterValue": "100003",
        "UMask": "0x1"
    },
    {
        "BriefDescription": "Counts miscellaneous requests, such as I/O accesses, that have any type of response.",
        "Counter": "0,1,2,3",
        "EventCode": "0XB7",
        "EventName": "OCR.OTHER.ANY_RESPONSE",
        "MSRIndex": "0x1a6,0x1a7",
        "MSRValue": "0x18000",
        "PublicDescription": "Counts miscellaneous requests, such as I/O accesses, that have any type of response. Available PDIST counters: 0",
        "SampleAfterValue": "100003",
        "UMask": "0x1"
    },
    {
        "BriefDescription": "Counts streaming stores which modify only part of a 64 byte cacheline that have any type of response.",
        "Counter": "0,1,2,3",
        "EventCode": "0XB7",
        "EventName": "OCR.PARTIAL_STREAMING_WR.ANY_RESPONSE",
        "MSRIndex": "0x1a6,0x1a7",
        "MSRValue": "0x400000010000",
        "PublicDescription": "Counts streaming stores which modify only part of a 64 byte cacheline that have any type of response. Available PDIST counters: 0",
        "SampleAfterValue": "100003",
        "UMask": "0x1"
    },
    {
        "BriefDescription": "Counts all hardware and software prefetches that have any type of response.",
        "Counter": "0,1,2,3",
        "EventCode": "0XB7",
        "EventName": "OCR.PREFETCHES.ANY_RESPONSE",
        "MSRIndex": "0x1a6,0x1a7",
        "MSRValue": "0x10470",
        "PublicDescription": "Counts all hardware and software prefetches that have any type of response. Available PDIST counters: 0",
        "SampleAfterValue": "100003",
        "UMask": "0x1"
    },
    {
        "BriefDescription": "Counts streaming stores that have any type of response.",
        "Counter": "0,1,2,3",
        "EventCode": "0XB7",
        "EventName": "OCR.STREAMING_WR.ANY_RESPONSE",
        "MSRIndex": "0x1a6,0x1a7",
        "MSRValue": "0x10800",
        "PublicDescription": "Counts streaming stores that have any type of response. Available PDIST counters: 0",
        "SampleAfterValue": "100003",
        "UMask": "0x1"
    },
    {
        "BriefDescription": "Counts uncached memory reads that have any type of response.",
        "Counter": "0,1,2,3",
        "EventCode": "0XB7",
        "EventName": "OCR.UC_RD.ANY_RESPONSE",
        "MSRIndex": "0x1a6,0x1a7",
        "MSRValue": "0x100000010000",
        "PublicDescription": "Counts uncached memory reads that have any type of response. Available PDIST counters: 0",
        "SampleAfterValue": "100003",
        "UMask": "0x1"
    },
    {
        "BriefDescription": "Counts uncached memory reads that have an outstanding request. Returns the number of cycles until the response is received (i.e. XQ to XQ latency).",
        "Counter": "0,1,2,3",
        "EventCode": "0XB7",
        "EventName": "OCR.UC_RD.OUTSTANDING",
        "MSRIndex": "0x1a6",
        "MSRValue": "0x8000100000000000",
        "PublicDescription": "Counts uncached memory reads that have an outstanding request. Returns the number of cycles until the response is received (i.e. XQ to XQ latency). Available PDIST counters: 0",
        "SampleAfterValue": "100003",
        "UMask": "0x1"
    },
    {
        "BriefDescription": "Counts uncached memory writes that have any type of response.",
        "Counter": "0,1,2,3",
        "EventCode": "0XB7",
        "EventName": "OCR.UC_WR.ANY_RESPONSE",
        "MSRIndex": "0x1a6,0x1a7",
        "MSRValue": "0x200000010000",
        "PublicDescription": "Counts uncached memory writes that have any type of response. Available PDIST counters: 0",
        "SampleAfterValue": "100003",
        "UMask": "0x1"
    }
]