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| author | Pierre-Yves MORDRET <pierre-yves.mordret@st.com> | 2018-04-20 11:14:00 +0200 |
|---|---|---|
| committer | Alexandre Torgue <alexandre.torgue@st.com> | 2018-05-04 09:45:39 +0200 |
| commit | ea1c404e8e2feb54ab3d13624477d013c1c9408c (patch) | |
| tree | 4ed911ecc9199704a08657728547d3a0b8a5a2c9 | |
| parent | da6cddc7e8a40e6e8617deaae905c3e7bfcfdf94 (diff) | |
ARM: dts: stm32: Add DMAv2 support on STM32MP157C
Activate DMAv2 for STM32MP157C
Signed-off-by: Pierre-Yves MORDRET <pierre-yves.mordret@st.com>
Signed-off-by: Alexandre Torgue <alexandre.torgue@st.com>
| -rw-r--r-- | arch/arm/boot/dts/stm32mp157c.dtsi | 32 |
1 files changed, 32 insertions, 0 deletions
diff --git a/arch/arm/boot/dts/stm32mp157c.dtsi b/arch/arm/boot/dts/stm32mp157c.dtsi index 9c1a6c48d318..af8bdeeed44e 100644 --- a/arch/arm/boot/dts/stm32mp157c.dtsi +++ b/arch/arm/boot/dts/stm32mp157c.dtsi @@ -495,6 +495,38 @@ }; }; + dma1: dma@48000000 { + compatible = "st,stm32-dma"; + reg = <0x48000000 0x400>; + interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 47 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&rcc DMA1>; + #dma-cells = <4>; + st,mem2mem; + }; + + dma2: dma@48001000 { + compatible = "st,stm32-dma"; + reg = <0x48001000 0x400>; + interrupts = <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&rcc DMA2>; + #dma-cells = <4>; + st,mem2mem; + }; + rcc: rcc@50000000 { compatible = "st,stm32mp1-rcc", "syscon"; reg = <0x50000000 0x1000>; |