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authorRussell King (Oracle) <rmk+kernel@armlinux.org.uk>2022-06-21 10:58:17 +0100
committerRussell King (Oracle) <rmk+kernel@armlinux.org.uk>2022-06-21 10:58:17 +0100
commit81ef1a85eee6a9ab9a140db4feeee3a1775d50d9 (patch)
treeda094122412ff516a72b6ec03909bded29f6a46e
parent793c5fb61059ce1132fdfa7b25ac58813e5f403b (diff)
parent017a20b3b1b344b949473fc09edbe626aa325dd4 (diff)
Merge branches 'net-queue' and 'pci-mobiveil' into cex7
-rw-r--r--drivers/pci/controller/mobiveil/pcie-layerscape-gen4.c79
-rw-r--r--drivers/pci/controller/mobiveil/pcie-mobiveil-host.c18
-rw-r--r--drivers/pci/controller/mobiveil/pcie-mobiveil.h7
3 files changed, 102 insertions, 2 deletions
diff --git a/drivers/pci/controller/mobiveil/pcie-layerscape-gen4.c b/drivers/pci/controller/mobiveil/pcie-layerscape-gen4.c
index d7b7350f02dd..7348a4cd0901 100644
--- a/drivers/pci/controller/mobiveil/pcie-layerscape-gen4.c
+++ b/drivers/pci/controller/mobiveil/pcie-layerscape-gen4.c
@@ -22,8 +22,13 @@
#include "pcie-mobiveil.h"
+#define REV_1_0 (0x10)
+
/* LUT and PF control registers */
#define PCIE_LUT_OFF 0x80000
+#define PCIE_LUT_GCR 0x28
+#define PCIE_LUT_GCR_RRE 0
+
#define PCIE_PF_OFF 0xc0000
#define PCIE_PF_INT_STAT 0x18
#define PF_INT_STAT_PABRST BIT(31)
@@ -40,8 +45,20 @@ struct ls_g4_pcie {
struct mobiveil_pcie pci;
struct delayed_work dwork;
int irq;
+ u8 rev;
};
+static inline u32 ls_g4_pcie_lut_readl(struct ls_g4_pcie *pcie, u32 off)
+{
+ return ioread32(pcie->pci.csr_axi_slave_base + PCIE_LUT_OFF + off);
+}
+
+static inline void ls_g4_pcie_lut_writel(struct ls_g4_pcie *pcie,
+ u32 off, u32 val)
+{
+ iowrite32(val, pcie->pci.csr_axi_slave_base + PCIE_LUT_OFF + off);
+}
+
static inline u32 ls_g4_pcie_pf_readl(struct ls_g4_pcie *pcie, u32 off)
{
return ioread32(pcie->pci.csr_axi_slave_base + PCIE_PF_OFF + off);
@@ -53,6 +70,41 @@ static inline void ls_g4_pcie_pf_writel(struct ls_g4_pcie *pcie,
iowrite32(val, pcie->pci.csr_axi_slave_base + PCIE_PF_OFF + off);
}
+static bool ls_g4_pcie_is_bridge(struct ls_g4_pcie *pcie)
+{
+ struct mobiveil_pcie *mv_pci = &pcie->pci;
+ u32 header_type;
+
+ header_type = mobiveil_csr_readb(mv_pci, PCI_HEADER_TYPE);
+ header_type &= 0x7f;
+
+ return header_type == PCI_HEADER_TYPE_BRIDGE;
+}
+
+static void workaround_A011451(struct ls_g4_pcie *pcie)
+{
+ struct mobiveil_pcie *mv_pci = &pcie->pci;
+ u32 val;
+
+ /* Set ACK latency timeout */
+ val = mobiveil_csr_readl(mv_pci, GPEX_ACK_REPLAY_TO);
+ val &= ~(ACK_LAT_TO_VAL_MASK << ACK_LAT_TO_VAL_SHIFT);
+ val |= (4 << ACK_LAT_TO_VAL_SHIFT);
+ mobiveil_csr_writel(mv_pci, val, GPEX_ACK_REPLAY_TO);
+}
+
+static int ls_g4_pcie_host_init(struct mobiveil_pcie *pci)
+{
+ struct ls_g4_pcie *pcie = to_ls_g4_pcie(pci);
+
+ pcie->rev = mobiveil_csr_readb(pci, PCI_REVISION_ID);
+
+ if (pcie->rev == REV_1_0)
+ workaround_A011451(pcie);
+
+ return 0;
+}
+
static int ls_g4_pcie_link_up(struct mobiveil_pcie *pci)
{
struct ls_g4_pcie *pcie = to_ls_g4_pcie(pci);
@@ -184,18 +236,40 @@ static void ls_g4_pcie_reset(struct work_struct *work)
ctrl &= ~PCI_BRIDGE_CTL_BUS_RESET;
mobiveil_csr_writew(mv_pci, ctrl, PCI_BRIDGE_CONTROL);
- if (!ls_g4_pcie_reinit_hw(pcie))
+ if (ls_g4_pcie_reinit_hw(pcie))
return;
ls_g4_pcie_enable_interrupt(pcie);
}
+static int ls_g4_pcie_read_other_conf(struct pci_bus *bus, unsigned int devfn,
+ int where, int size, u32 *val)
+{
+ struct mobiveil_pcie *pci = bus->sysdata;
+ struct ls_g4_pcie *pcie = to_ls_g4_pcie(pci);
+ int ret;
+
+ if (pcie->rev == REV_1_0)
+ ls_g4_pcie_lut_writel(pcie, PCIE_LUT_GCR,
+ 0 << PCIE_LUT_GCR_RRE);
+
+ ret = pci_generic_config_read(bus, devfn, where, size, val);
+
+ if (pcie->rev == REV_1_0)
+ ls_g4_pcie_lut_writel(pcie, PCIE_LUT_GCR,
+ 1 << PCIE_LUT_GCR_RRE);
+
+ return ret;
+}
+
static struct mobiveil_rp_ops ls_g4_pcie_rp_ops = {
.interrupt_init = ls_g4_pcie_interrupt_init,
+ .read_other_conf = ls_g4_pcie_read_other_conf,
};
static const struct mobiveil_pab_ops ls_g4_pcie_pab_ops = {
.link_up = ls_g4_pcie_link_up,
+ .host_init = ls_g4_pcie_host_init,
};
static int __init ls_g4_pcie_probe(struct platform_device *pdev)
@@ -234,6 +308,9 @@ static int __init ls_g4_pcie_probe(struct platform_device *pdev)
return ret;
}
+ if (!ls_g4_pcie_is_bridge(pcie))
+ return -ENODEV;
+
ls_g4_pcie_enable_interrupt(pcie);
return 0;
diff --git a/drivers/pci/controller/mobiveil/pcie-mobiveil-host.c b/drivers/pci/controller/mobiveil/pcie-mobiveil-host.c
index 31a7bdebe540..defdb9a460f6 100644
--- a/drivers/pci/controller/mobiveil/pcie-mobiveil-host.c
+++ b/drivers/pci/controller/mobiveil/pcie-mobiveil-host.c
@@ -76,9 +76,21 @@ static void __iomem *mobiveil_pcie_map_bus(struct pci_bus *bus,
return rp->config_axi_slave_base + where;
}
+static int mobiveil_pcie_config_read(struct pci_bus *bus, unsigned int devfn,
+ int where, int size, u32 *val)
+{
+ struct mobiveil_pcie *pcie = bus->sysdata;
+ struct mobiveil_root_port *rp = &pcie->rp;
+
+ if (bus->number > to_pci_host_bridge(bus->bridge)->busnr &&
+ rp->ops->read_other_conf)
+ return rp->ops->read_other_conf(bus, devfn, where, size, val);
+
+ return pci_generic_config_read(bus, devfn, where, size, val);
+}
static struct pci_ops mobiveil_pcie_ops = {
.map_bus = mobiveil_pcie_map_bus,
- .read = pci_generic_config_read,
+ .read = mobiveil_pcie_config_read,
.write = pci_generic_config_write,
};
@@ -298,6 +310,10 @@ int mobiveil_host_init(struct mobiveil_pcie *pcie, bool reinit)
value |= PCI_CLASS_BRIDGE_PCI_NORMAL << 8;
mobiveil_csr_writel(pcie, value, PAB_INTP_AXI_PIO_CLASS);
+ /* Platform specific host init */
+ if (pcie->ops->host_init)
+ return pcie->ops->host_init(pcie);
+
return 0;
}
diff --git a/drivers/pci/controller/mobiveil/pcie-mobiveil.h b/drivers/pci/controller/mobiveil/pcie-mobiveil.h
index 6082b8afbc31..e03cc8e1399a 100644
--- a/drivers/pci/controller/mobiveil/pcie-mobiveil.h
+++ b/drivers/pci/controller/mobiveil/pcie-mobiveil.h
@@ -86,6 +86,10 @@
#define PAB_AXI_AMAP_PEX_WIN_H(win) PAB_REG_ADDR(0x0bac, win)
#define PAB_INTP_AXI_PIO_CLASS 0x474
+#define GPEX_ACK_REPLAY_TO 0x438
+#define ACK_LAT_TO_VAL_MASK 0x1fff
+#define ACK_LAT_TO_VAL_SHIFT 0
+
#define PAB_PEX_AMAP_CTRL(win) PAB_REG_ADDR(0x4ba0, win)
#define AMAP_CTRL_EN_SHIFT 0
#define AMAP_CTRL_TYPE_SHIFT 1
@@ -146,6 +150,8 @@ struct mobiveil_pcie;
struct mobiveil_rp_ops {
int (*interrupt_init)(struct mobiveil_pcie *pcie);
+ int (*read_other_conf)(struct pci_bus *bus, unsigned int devfn,
+ int where, int size, u32 *val);
};
struct mobiveil_root_port {
@@ -161,6 +167,7 @@ struct mobiveil_root_port {
struct mobiveil_pab_ops {
int (*link_up)(struct mobiveil_pcie *pcie);
+ int (*host_init)(struct mobiveil_pcie *pcie);
};
struct mobiveil_pcie {