diff options
author | Laurent Pinchart <laurent.pinchart@ideasonboard.com> | 2023-04-18 18:31:04 +0300 |
---|---|---|
committer | Shawn Guo <shawnguo@kernel.org> | 2023-05-14 11:12:23 +0800 |
commit | 9da15c4c850dd53309e07d5611f33655f8f8c05d (patch) | |
tree | d6350fca80ad7f9c40b9dbc4d8303d32ac488aa7 | |
parent | dae1b3fd06e8416fdfbc7440a62d5cd845c633a7 (diff) |
arm64: dts: imx8mp: Add ISI DT node
Add a DT node for the i.MX8MP ISI instance, and model to connection to
two CSI-2 receivers (CSIS).
Signed-off-by: Laurent Pinchart <laurent.pinchart@ideasonboard.com>
Reviewed-by: Paul Elder <paul.elder@ideasonboard.com>
Signed-off-by: Shawn Guo <shawnguo@kernel.org>
-rw-r--r-- | arch/arm64/boot/dts/freescale/imx8mp.dtsi | 42 |
1 files changed, 42 insertions, 0 deletions
diff --git a/arch/arm64/boot/dts/freescale/imx8mp.dtsi b/arch/arm64/boot/dts/freescale/imx8mp.dtsi index 5a0424aba28c..8d26bd3ceb25 100644 --- a/arch/arm64/boot/dts/freescale/imx8mp.dtsi +++ b/arch/arm64/boot/dts/freescale/imx8mp.dtsi @@ -1342,6 +1342,40 @@ }; }; + isi_0: isi@32e00000 { + compatible = "fsl,imx8mp-isi"; + reg = <0x32e00000 0x4000>; + interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&clk IMX8MP_CLK_MEDIA_AXI_ROOT>, + <&clk IMX8MP_CLK_MEDIA_APB_ROOT>; + clock-names = "axi", "apb"; + fsl,blk-ctrl = <&media_blk_ctrl>; + power-domains = <&media_blk_ctrl IMX8MP_MEDIABLK_PD_ISI>; + status = "disabled"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + + isi_in_0: endpoint { + remote-endpoint = <&mipi_csi_0_out>; + }; + }; + + port@1 { + reg = <1>; + + isi_in_1: endpoint { + remote-endpoint = <&mipi_csi_1_out>; + }; + }; + }; + }; + mipi_csi_0: csi@32e40000 { compatible = "fsl,imx8mp-mipi-csi2", "fsl,imx8mm-mipi-csi2"; reg = <0x32e40000 0x10000>; @@ -1368,6 +1402,10 @@ port@1 { reg = <1>; + + mipi_csi_0_out: endpoint { + remote-endpoint = <&isi_in_0>; + }; }; }; }; @@ -1398,6 +1436,10 @@ port@1 { reg = <1>; + + mipi_csi_1_out: endpoint { + remote-endpoint = <&isi_in_1>; + }; }; }; }; |