diff options
| author | Russell King <rmk+kernel@armlinux.org.uk> | 2020-03-10 13:40:12 +0000 |
|---|---|---|
| committer | Russell King <rmk+kernel@armlinux.org.uk> | 2020-10-12 22:41:20 +0100 |
| commit | cb1a58ad0e47e361c11302b930d27915f919881c (patch) | |
| tree | 213fade213e2aac50366ea43d3ff1f01789e27b5 | |
| parent | 27900f6c502bf248ecb713ed8f52922098df398d (diff) | |
dpaa2-mac: add 10GBASE-R PCS support
Add support for the 10GBASE-R PCS internal PHY, which we only use to
check the link status, since it offers a single fixed speed at fixed
full duplex only.
Signed-off-by: Russell King <rmk+kernel@armlinux.org.uk>
| -rw-r--r-- | drivers/net/ethernet/freescale/dpaa2/dpaa2-mac.c | 22 |
1 files changed, 22 insertions, 0 deletions
diff --git a/drivers/net/ethernet/freescale/dpaa2/dpaa2-mac.c b/drivers/net/ethernet/freescale/dpaa2/dpaa2-mac.c index 49af3f1af32b..9ca7b51d61f6 100644 --- a/drivers/net/ethernet/freescale/dpaa2/dpaa2-mac.c +++ b/drivers/net/ethernet/freescale/dpaa2/dpaa2-mac.c @@ -44,6 +44,10 @@ static void lynx_pcs_get_state(struct phylink_pcs *pcs, phylink_mii_c22_pcs_get_state(lynx->mdio, state); break; + case PHY_INTERFACE_MODE_10GBASER: + phylink_mii_c45_pcs_get_state(lynx->mdio, state); + break; + default: break; } @@ -157,6 +161,10 @@ static int phy_mode(enum dpmac_eth_if eth_if, phy_interface_t *if_mode) *if_mode = PHY_INTERFACE_MODE_SGMII; break; + case DPMAC_ETH_IF_XFI: + *if_mode = PHY_INTERFACE_MODE_10GBASER; + break; + default: return -EINVAL; } @@ -213,6 +221,9 @@ static bool dpaa2_mac_phy_mode_mismatch(struct dpaa2_mac *mac, case PHY_INTERFACE_MODE_1000BASEX: return interface != mac->if_mode && !mac->pcs; + case PHY_INTERFACE_MODE_10GBASER: + return interface != mac->if_mode && !mac->pcs; + case PHY_INTERFACE_MODE_RGMII: case PHY_INTERFACE_MODE_RGMII_ID: case PHY_INTERFACE_MODE_RGMII_RXID: @@ -242,6 +253,17 @@ static void dpaa2_mac_validate(struct phylink_config *config, switch (state->interface) { case PHY_INTERFACE_MODE_NA: + case PHY_INTERFACE_MODE_10GBASER: + phylink_set(mask, 10000baseT_Full); + phylink_set(mask, 10000baseKR_Full); + phylink_set(mask, 10000baseCR_Full); + phylink_set(mask, 10000baseSR_Full); + phylink_set(mask, 10000baseLR_Full); + phylink_set(mask, 10000baseLRM_Full); + phylink_set(mask, 10000baseER_Full); + if (state->interface != PHY_INTERFACE_MODE_NA) + break; + /* fallthrough */ case PHY_INTERFACE_MODE_1000BASEX: case PHY_INTERFACE_MODE_SGMII: case PHY_INTERFACE_MODE_RGMII: |