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authorHou Zhiqiang <Zhiqiang.Hou@nxp.com>2019-09-25 10:21:28 +0100
committerRussell King (Oracle) <rmk+kernel@armlinux.org.uk>2022-04-02 10:42:27 +0100
commitf15f6cfed67170b9c3999ee4784531a145e45ee3 (patch)
tree5d5e9999c2426654780345c269608b8de0d0c2b4
parent6056bc876a7bc9f336bacfd917732674442ca2b9 (diff)
PCI: mobiveil: ls_pcie_g4: add Workaround for A-011577
PCIe configuration access to non-existent function triggered SERROR interrupt exception. Workaround: Disable error reporting on AXI bus during the Vendor ID read transactions in enumeration. This ERRATA is only for LX2160A Rev1.0, and it will be fixed in Rev2.0. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Russell King <rmk+kernel@armlinux.org.uk>
-rw-r--r--drivers/pci/controller/mobiveil/pcie-layerscape-gen4.c37
-rw-r--r--drivers/pci/controller/mobiveil/pcie-mobiveil-host.c18
-rw-r--r--drivers/pci/controller/mobiveil/pcie-mobiveil.h3
3 files changed, 57 insertions, 1 deletions
diff --git a/drivers/pci/controller/mobiveil/pcie-layerscape-gen4.c b/drivers/pci/controller/mobiveil/pcie-layerscape-gen4.c
index f35464653f34..43dede26cc7c 100644
--- a/drivers/pci/controller/mobiveil/pcie-layerscape-gen4.c
+++ b/drivers/pci/controller/mobiveil/pcie-layerscape-gen4.c
@@ -22,8 +22,13 @@
#include "pcie-mobiveil.h"
+#define REV_1_0 (0x10)
+
/* LUT and PF control registers */
#define PCIE_LUT_OFF 0x80000
+#define PCIE_LUT_GCR 0x28
+#define PCIE_LUT_GCR_RRE 0
+
#define PCIE_PF_OFF 0xc0000
#define PCIE_PF_INT_STAT 0x18
#define PF_INT_STAT_PABRST BIT(31)
@@ -40,6 +45,7 @@ struct ls_g4_pcie {
struct mobiveil_pcie pci;
struct delayed_work dwork;
int irq;
+ u8 rev;
};
static inline u32 ls_g4_pcie_lut_readl(struct ls_g4_pcie *pcie, u32 off)
@@ -75,6 +81,15 @@ static bool ls_g4_pcie_is_bridge(struct ls_g4_pcie *pcie)
return header_type == PCI_HEADER_TYPE_BRIDGE;
}
+static int ls_g4_pcie_host_init(struct mobiveil_pcie *pci)
+{
+ struct ls_g4_pcie *pcie = to_ls_g4_pcie(pci);
+
+ pcie->rev = mobiveil_csr_readb(pci, PCI_REVISION_ID);
+
+ return 0;
+}
+
static int ls_g4_pcie_link_up(struct mobiveil_pcie *pci)
{
struct ls_g4_pcie *pcie = to_ls_g4_pcie(pci);
@@ -212,12 +227,34 @@ static void ls_g4_pcie_reset(struct work_struct *work)
ls_g4_pcie_enable_interrupt(pcie);
}
+static int ls_g4_pcie_read_other_conf(struct pci_bus *bus, unsigned int devfn,
+ int where, int size, u32 *val)
+{
+ struct mobiveil_pcie *pci = bus->sysdata;
+ struct ls_g4_pcie *pcie = to_ls_g4_pcie(pci);
+ int ret;
+
+ if (pcie->rev == REV_1_0 && where == PCI_VENDOR_ID)
+ ls_g4_pcie_lut_writel(pcie, PCIE_LUT_GCR,
+ 0 << PCIE_LUT_GCR_RRE);
+
+ ret = pci_generic_config_read(bus, devfn, where, size, val);
+
+ if (pcie->rev == REV_1_0 && where == PCI_VENDOR_ID)
+ ls_g4_pcie_lut_writel(pcie, PCIE_LUT_GCR,
+ 1 << PCIE_LUT_GCR_RRE);
+
+ return ret;
+}
+
static struct mobiveil_rp_ops ls_g4_pcie_rp_ops = {
.interrupt_init = ls_g4_pcie_interrupt_init,
+ .read_other_conf = ls_g4_pcie_read_other_conf,
};
static const struct mobiveil_pab_ops ls_g4_pcie_pab_ops = {
.link_up = ls_g4_pcie_link_up,
+ .host_init = ls_g4_pcie_host_init,
};
static int __init ls_g4_pcie_probe(struct platform_device *pdev)
diff --git a/drivers/pci/controller/mobiveil/pcie-mobiveil-host.c b/drivers/pci/controller/mobiveil/pcie-mobiveil-host.c
index f3547aa60140..bd6da925e546 100644
--- a/drivers/pci/controller/mobiveil/pcie-mobiveil-host.c
+++ b/drivers/pci/controller/mobiveil/pcie-mobiveil-host.c
@@ -76,9 +76,21 @@ static void __iomem *mobiveil_pcie_map_bus(struct pci_bus *bus,
return rp->config_axi_slave_base + where;
}
+static int mobiveil_pcie_config_read(struct pci_bus *bus, unsigned int devfn,
+ int where, int size, u32 *val)
+{
+ struct mobiveil_pcie *pcie = bus->sysdata;
+ struct mobiveil_root_port *rp = &pcie->rp;
+
+ if (bus->number > to_pci_host_bridge(bus->bridge)->busnr &&
+ rp->ops->read_other_conf)
+ return rp->ops->read_other_conf(bus, devfn, where, size, val);
+
+ return pci_generic_config_read(bus, devfn, where, size, val);
+}
static struct pci_ops mobiveil_pcie_ops = {
.map_bus = mobiveil_pcie_map_bus,
- .read = pci_generic_config_read,
+ .read = mobiveil_pcie_config_read,
.write = pci_generic_config_write,
};
@@ -298,6 +310,10 @@ int mobiveil_host_init(struct mobiveil_pcie *pcie, bool reinit)
value |= (PCI_CLASS_BRIDGE_PCI << 16);
mobiveil_csr_writel(pcie, value, PAB_INTP_AXI_PIO_CLASS);
+ /* Platform specific host init */
+ if (pcie->ops->host_init)
+ return pcie->ops->host_init(pcie);
+
return 0;
}
diff --git a/drivers/pci/controller/mobiveil/pcie-mobiveil.h b/drivers/pci/controller/mobiveil/pcie-mobiveil.h
index 6082b8afbc31..ec5f1104a9e4 100644
--- a/drivers/pci/controller/mobiveil/pcie-mobiveil.h
+++ b/drivers/pci/controller/mobiveil/pcie-mobiveil.h
@@ -146,6 +146,8 @@ struct mobiveil_pcie;
struct mobiveil_rp_ops {
int (*interrupt_init)(struct mobiveil_pcie *pcie);
+ int (*read_other_conf)(struct pci_bus *bus, unsigned int devfn,
+ int where, int size, u32 *val);
};
struct mobiveil_root_port {
@@ -161,6 +163,7 @@ struct mobiveil_root_port {
struct mobiveil_pab_ops {
int (*link_up)(struct mobiveil_pcie *pcie);
+ int (*host_init)(struct mobiveil_pcie *pcie);
};
struct mobiveil_pcie {