diff options
| author | Dmitry Baryshkov <dmitry.baryshkov@linaro.org> | 2025-01-17 08:09:09 +0100 |
|---|---|---|
| committer | Russell King (Oracle) <rmk+kernel@armlinux.org.uk> | 2025-01-22 20:55:01 +0000 |
| commit | f520fab580c9179bacc432f3a3bf1eada73fdfcc (patch) | |
| tree | 291121a3117af02ca4dc82d6b38e43f40891173e | |
| parent | a9ff94477836cb43d94efbd9a851213944800177 (diff) | |
Fix C&P error left unnoticed during the reviews. The FORMAT field spans
over bits 29-31, not 24-27 of the CTR register.
Closes: https://lore.kernel.org/linux-arm-msm/01515ea0-c6f0-479f-9da5-764d9ee79ed6@samsung.com/
Fixes: a9ff94477836 ("ARM: 9433/2: implement cacheinfo support")
Reported-by: Marek Szyprowski <m.szyprowski@samsung.com>
Reviewed-by: Linus Walleij <linus.walleij@linaro.org>
Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
Signed-off-by: Russell King (Oracle) <rmk+kernel@armlinux.org.uk>
| -rw-r--r-- | arch/arm/kernel/cacheinfo.c | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/arch/arm/kernel/cacheinfo.c b/arch/arm/kernel/cacheinfo.c index a8eabcaa18d8..e1469b641780 100644 --- a/arch/arm/kernel/cacheinfo.c +++ b/arch/arm/kernel/cacheinfo.c @@ -23,7 +23,7 @@ #define MAX_CACHE_LEVEL 7 /* Max 7 level supported */ -#define CTR_FORMAT_MASK GENMASK(27, 24) +#define CTR_FORMAT_MASK GENMASK(31, 29) #define CTR_FORMAT_ARMV6 0 #define CTR_FORMAT_ARMV7 4 #define CTR_CWG_MASK GENMASK(27, 24) |