diff options
| author | Vladimir Oltean <vladimir.oltean@nxp.com> | 2020-01-06 03:34:10 +0200 |
|---|---|---|
| committer | Russell King <rmk+kernel@armlinux.org.uk> | 2020-01-29 23:16:29 +0000 |
| commit | 1c011988a1d4b713eb4359502236a607430332c5 (patch) | |
| tree | fefdc5f67aff58575ac6002b653955e9eb2223b2 | |
| parent | 29478504fe6df21aa1ea4dd02e11c2a6d4ba0c65 (diff) | |
net: phylink: make QSGMII a valid PHY mode for in-band AN
QSGMII is a SerDes protocol clocked at 5 Gbaud (4 times higher than
SGMII which is clocked at 1.25 Gbaud), with the same 8b/10b encoding and
some extra symbols for synchronization. Logically it offers 4 SGMII
interfaces multiplexed onto the same physical lanes. Each MAC PCS has
its own in-band AN process with the system side of the QSGMII PHY, which
is identical to the regular SGMII AN process.
So allow QSGMII as a valid in-band AN mode, since it is no different
from software perspective from regular SGMII.
Signed-off-by: Vladimir Oltean <vladimir.oltean@nxp.com>
Signed-off-by: David S. Miller <davem@davemloft.net>
| -rw-r--r-- | drivers/net/phy/phylink.c | 1 |
1 files changed, 1 insertions, 0 deletions
diff --git a/drivers/net/phy/phylink.c b/drivers/net/phy/phylink.c index 89da28f30c10..734df5d8054a 100644 --- a/drivers/net/phy/phylink.c +++ b/drivers/net/phy/phylink.c @@ -281,6 +281,7 @@ static int phylink_parse_mode(struct phylink *pl, struct fwnode_handle *fwnode) switch (pl->link_config.interface) { case PHY_INTERFACE_MODE_SGMII: + case PHY_INTERFACE_MODE_QSGMII: phylink_set(pl->supported, 10baseT_Half); phylink_set(pl->supported, 10baseT_Full); phylink_set(pl->supported, 100baseT_Half); |