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authorMarek BehĂșn <kabel@kernel.org>2020-10-20 19:09:12 +0200
committerRussell King <rmk+kernel@armlinux.org.uk>2021-02-15 13:22:02 +0000
commit28ef56cfa3ce93c75ce57a336d83896037df2784 (patch)
tree4c26adbb43aee50061da04fa63741cf19ce21cae
parent59c428e36d2326b535a4b3fc86eb354c596fb50d (diff)
net: dsa: mv88e6xxx: implement .phylink_get_interfaces operation
Implement the .phylink_get_interfaces method for mv88e6xxx driver. We are currently only interested in SGMII, 1000base-x and 2500base-x modes (for the SFP code). USXGMII and 10gbase-r can be added later for Amethyst. XAUI and RXAUI are irrelevant for SFP (but maybe not for QSFP?). Signed-off-by: Marek BehĂșn <kabel@kernel.org> Signed-off-by: Russell King <rmk+kernel@armlinux.org.uk>
-rw-r--r--drivers/net/dsa/mv88e6xxx/chip.c57
-rw-r--r--drivers/net/dsa/mv88e6xxx/chip.h2
2 files changed, 59 insertions, 0 deletions
diff --git a/drivers/net/dsa/mv88e6xxx/chip.c b/drivers/net/dsa/mv88e6xxx/chip.c
index 54aa942eedaa..c8074443110f 100644
--- a/drivers/net/dsa/mv88e6xxx/chip.c
+++ b/drivers/net/dsa/mv88e6xxx/chip.c
@@ -660,6 +660,50 @@ static void mv88e6xxx_validate(struct dsa_switch *ds, int port,
phylink_helper_basex_speed(state);
}
+static void mv88e6352_phylink_get_interfaces(struct mv88e6xxx_chip *chip,
+ int port,
+ unsigned long *supported)
+{
+ if (mv88e6xxx_serdes_get_lane(chip, port)) {
+ /* FIXME: does code for 6352 family support changing between
+ * SGMII and 1000base-x?
+ */
+ __set_bit(PHY_INTERFACE_MODE_SGMII, supported);
+ __set_bit(PHY_INTERFACE_MODE_1000BASEX, supported);
+ }
+}
+
+static void mv88e6341_phylink_get_interfaces(struct mv88e6xxx_chip *chip,
+ int port,
+ unsigned long *supported)
+{
+ if (port == 5) {
+ __set_bit(PHY_INTERFACE_MODE_SGMII, supported);
+ __set_bit(PHY_INTERFACE_MODE_1000BASEX, supported);
+ __set_bit(PHY_INTERFACE_MODE_2500BASEX, supported);
+ }
+}
+
+static void mv88e6390_phylink_get_interfaces(struct mv88e6xxx_chip *chip,
+ int port,
+ unsigned long *supported)
+{
+ if (port == 9 || port == 10) {
+ __set_bit(PHY_INTERFACE_MODE_SGMII, supported);
+ __set_bit(PHY_INTERFACE_MODE_1000BASEX, supported);
+ __set_bit(PHY_INTERFACE_MODE_2500BASEX, supported);
+ }
+}
+
+static void mv88e6xxx_get_interfaces(struct dsa_switch *ds, int port,
+ unsigned long *supported)
+{
+ struct mv88e6xxx_chip *chip = ds->priv;
+
+ if (chip->info->ops->phylink_get_interfaces)
+ chip->info->ops->phylink_get_interfaces(chip, port, supported);
+}
+
static void mv88e6xxx_mac_config(struct dsa_switch *ds, int port,
unsigned int mode,
const struct phylink_link_state *state)
@@ -3457,6 +3501,7 @@ static const struct mv88e6xxx_ops mv88e6141_ops = {
.serdes_irq_enable = mv88e6390_serdes_irq_enable,
.serdes_irq_status = mv88e6390_serdes_irq_status,
.gpio_ops = &mv88e6352_gpio_ops,
+ .phylink_get_interfaces = mv88e6341_phylink_get_interfaces,
.phylink_validate = mv88e6341_phylink_validate,
};
@@ -3629,6 +3674,7 @@ static const struct mv88e6xxx_ops mv88e6172_ops = {
.serdes_get_regs_len = mv88e6352_serdes_get_regs_len,
.serdes_get_regs = mv88e6352_serdes_get_regs,
.gpio_ops = &mv88e6352_gpio_ops,
+ .phylink_get_interfaces = mv88e6352_phylink_get_interfaces,
.phylink_validate = mv88e6352_phylink_validate,
};
@@ -3727,6 +3773,7 @@ static const struct mv88e6xxx_ops mv88e6176_ops = {
.serdes_get_regs_len = mv88e6352_serdes_get_regs_len,
.serdes_get_regs = mv88e6352_serdes_get_regs,
.gpio_ops = &mv88e6352_gpio_ops,
+ .phylink_get_interfaces = mv88e6352_phylink_get_interfaces,
.phylink_validate = mv88e6352_phylink_validate,
};
@@ -3826,6 +3873,7 @@ static const struct mv88e6xxx_ops mv88e6190_ops = {
.serdes_get_regs_len = mv88e6390_serdes_get_regs_len,
.serdes_get_regs = mv88e6390_serdes_get_regs,
.gpio_ops = &mv88e6352_gpio_ops,
+ .phylink_get_interfaces = mv88e6390_phylink_get_interfaces,
.phylink_validate = mv88e6390_phylink_validate,
};
@@ -3886,6 +3934,7 @@ static const struct mv88e6xxx_ops mv88e6190x_ops = {
.serdes_get_regs_len = mv88e6390_serdes_get_regs_len,
.serdes_get_regs = mv88e6390_serdes_get_regs,
.gpio_ops = &mv88e6352_gpio_ops,
+ .phylink_get_interfaces = mv88e6390_phylink_get_interfaces,
.phylink_validate = mv88e6390x_phylink_validate,
};
@@ -3945,6 +3994,7 @@ static const struct mv88e6xxx_ops mv88e6191_ops = {
.serdes_get_regs = mv88e6390_serdes_get_regs,
.avb_ops = &mv88e6390_avb_ops,
.ptp_ops = &mv88e6352_ptp_ops,
+ .phylink_get_interfaces = mv88e6390_phylink_get_interfaces,
.phylink_validate = mv88e6390_phylink_validate,
};
@@ -4004,6 +4054,7 @@ static const struct mv88e6xxx_ops mv88e6240_ops = {
.gpio_ops = &mv88e6352_gpio_ops,
.avb_ops = &mv88e6352_avb_ops,
.ptp_ops = &mv88e6352_ptp_ops,
+ .phylink_get_interfaces = mv88e6352_phylink_get_interfaces,
.phylink_validate = mv88e6352_phylink_validate,
};
@@ -4104,6 +4155,7 @@ static const struct mv88e6xxx_ops mv88e6290_ops = {
.gpio_ops = &mv88e6352_gpio_ops,
.avb_ops = &mv88e6390_avb_ops,
.ptp_ops = &mv88e6352_ptp_ops,
+ .phylink_get_interfaces = mv88e6390_phylink_get_interfaces,
.phylink_validate = mv88e6390_phylink_validate,
};
@@ -4244,6 +4296,7 @@ static const struct mv88e6xxx_ops mv88e6341_ops = {
.gpio_ops = &mv88e6352_gpio_ops,
.avb_ops = &mv88e6390_avb_ops,
.ptp_ops = &mv88e6352_ptp_ops,
+ .phylink_get_interfaces = mv88e6341_phylink_get_interfaces,
.phylink_validate = mv88e6341_phylink_validate,
};
@@ -4390,6 +4443,7 @@ static const struct mv88e6xxx_ops mv88e6352_ops = {
.serdes_get_stats = mv88e6352_serdes_get_stats,
.serdes_get_regs_len = mv88e6352_serdes_get_regs_len,
.serdes_get_regs = mv88e6352_serdes_get_regs,
+ .phylink_get_interfaces = mv88e6352_phylink_get_interfaces,
.phylink_validate = mv88e6352_phylink_validate,
};
@@ -4454,6 +4508,7 @@ static const struct mv88e6xxx_ops mv88e6390_ops = {
.serdes_get_stats = mv88e6390_serdes_get_stats,
.serdes_get_regs_len = mv88e6390_serdes_get_regs_len,
.serdes_get_regs = mv88e6390_serdes_get_regs,
+ .phylink_get_interfaces = mv88e6390_phylink_get_interfaces,
.phylink_validate = mv88e6390_phylink_validate,
};
@@ -4517,6 +4572,7 @@ static const struct mv88e6xxx_ops mv88e6390x_ops = {
.gpio_ops = &mv88e6352_gpio_ops,
.avb_ops = &mv88e6390_avb_ops,
.ptp_ops = &mv88e6352_ptp_ops,
+ .phylink_get_interfaces = mv88e6390_phylink_get_interfaces,
.phylink_validate = mv88e6390x_phylink_validate,
};
@@ -5383,6 +5439,7 @@ static const struct dsa_switch_ops mv88e6xxx_switch_ops = {
.get_tag_protocol = mv88e6xxx_get_tag_protocol,
.setup = mv88e6xxx_setup,
.teardown = mv88e6xxx_teardown,
+ .phylink_get_interfaces = mv88e6xxx_get_interfaces,
.phylink_validate = mv88e6xxx_validate,
.phylink_mac_link_state = mv88e6xxx_serdes_pcs_get_state,
.phylink_mac_config = mv88e6xxx_mac_config,
diff --git a/drivers/net/dsa/mv88e6xxx/chip.h b/drivers/net/dsa/mv88e6xxx/chip.h
index 3543055bcb51..6f513778ed26 100644
--- a/drivers/net/dsa/mv88e6xxx/chip.h
+++ b/drivers/net/dsa/mv88e6xxx/chip.h
@@ -571,6 +571,8 @@ struct mv88e6xxx_ops {
const struct mv88e6xxx_ptp_ops *ptp_ops;
/* Phylink */
+ void (*phylink_get_interfaces)(struct mv88e6xxx_chip *chip, int port,
+ unsigned long *supported);
void (*phylink_validate)(struct mv88e6xxx_chip *chip, int port,
unsigned long *mask,
struct phylink_link_state *state);