diff options
author | Russell King <rmk+kernel@armlinux.org.uk> | 2020-03-03 12:15:38 +0000 |
---|---|---|
committer | Russell King <rmk+kernel@armlinux.org.uk> | 2020-04-16 23:03:52 +0100 |
commit | 48bd6083efcd1277fa414d6a7eb1759fe420e733 (patch) | |
tree | 6ecfc9b43eb820fb9e9374a06291a283f5b4ac42 | |
parent | 73416fc29dc7df860f2396e44298742ac0ca589d (diff) |
net: mvpp2: fill in phy interface mode bitmap
Fill in the phy interface mode bitmap for the Marvell mvpp2 driver, so
phylink can know which interfaces are supported by the MAC.
Signed-off-by: Russell King <rmk+kernel@armlinux.org.uk>
-rw-r--r-- | drivers/net/ethernet/marvell/mvpp2/mvpp2_main.c | 23 |
1 files changed, 23 insertions, 0 deletions
diff --git a/drivers/net/ethernet/marvell/mvpp2/mvpp2_main.c b/drivers/net/ethernet/marvell/mvpp2/mvpp2_main.c index 9e8d8d319bff..e74d89a2754d 100644 --- a/drivers/net/ethernet/marvell/mvpp2/mvpp2_main.c +++ b/drivers/net/ethernet/marvell/mvpp2/mvpp2_main.c @@ -5452,6 +5452,29 @@ static int mvpp2_port_probe(struct platform_device *pdev, port->phylink_config.dev = &dev->dev; port->phylink_config.type = PHYLINK_NETDEV; + if (mvpp2_port_supports_xlg(port)) { + __set_bit(PHY_INTERFACE_MODE_10GBASER, + port->phylink_config.supported_interfaces); + __set_bit(PHY_INTERFACE_MODE_XAUI, + port->phylink_config.supported_interfaces); + } + if (mvpp2_port_supports_rgmii(port)) { + __set_bit(PHY_INTERFACE_MODE_RGMII, + port->phylink_config.supported_interfaces); + __set_bit(PHY_INTERFACE_MODE_RGMII_ID, + port->phylink_config.supported_interfaces); + __set_bit(PHY_INTERFACE_MODE_RGMII_TXID, + port->phylink_config.supported_interfaces); + __set_bit(PHY_INTERFACE_MODE_RGMII_RXID, + port->phylink_config.supported_interfaces); + } + __set_bit(PHY_INTERFACE_MODE_SGMII, + port->phylink_config.supported_interfaces); + __set_bit(PHY_INTERFACE_MODE_1000BASEX, + port->phylink_config.supported_interfaces); + __set_bit(PHY_INTERFACE_MODE_2500BASEX, + port->phylink_config.supported_interfaces); + phylink = phylink_create(&port->phylink_config, port_fwnode, phy_mode, &mvpp2_phylink_ops); if (IS_ERR(phylink)) { |