net: mvneta: split out GMAC

Split out the code handling the GMAC from the rest of the driver.  This
block appears to be shared amongst several revisions of the IP.

Signed-off-by: Russell King <rmk+kernel@armlinux.org.uk>

5 files changed, 450 insertions, 326 deletions

diff --git a/drivers/net/ethernet/marvell/Kconfig b/drivers/net/ethernet/marvell/Kconfig
index 884d64114bff..26c6b93fa009 100644
--- a/drivers/net/ethernet/marvell/Kconfig
+++ b/drivers/net/ethernet/marvell/Kconfig
@@ -60,6 +60,7 @@ config MVNETA_BM_ENABLE
 config MVNETA
 	tristate "Marvell Armada 370/38x/XP/37xx network interface support"
 	depends on ARCH_MVEBU || COMPILE_TEST
+	select MVGMAC
 	select MVMDIO
 	select PHYLINK
 	select PAGE_POOL
@@ -73,6 +74,9 @@ config MVNETA
 	  driver, which should be used for the older Marvell SoCs
 	  (Dove, Orion, Discovery, Kirkwood).
 
+config MVGMAC
+	tristate
+
 config MVNETA_BM
 	tristate
 	depends on !64BIT
diff --git a/drivers/net/ethernet/marvell/Makefile b/drivers/net/ethernet/marvell/Makefile
index ceba4aa4f026..d400984f83b7 100644
--- a/drivers/net/ethernet/marvell/Makefile
+++ b/drivers/net/ethernet/marvell/Makefile
@@ -7,6 +7,7 @@ obj-$(CONFIG_MVMDIO) += mvmdio.o
 obj-$(CONFIG_MV643XX_ETH) += mv643xx_eth.o
 obj-$(CONFIG_MVNETA_BM) += mvneta_bm.o
 obj-$(CONFIG_MVNETA) += mvneta.o
+obj-$(CONFIG_MVGMAC) += mvgmac.o
 obj-$(CONFIG_MVPP2) += mvpp2/
 obj-$(CONFIG_PXA168_ETH) += pxa168_eth.o
 obj-$(CONFIG_SKGE) += skge.o
diff --git a/drivers/net/ethernet/marvell/mvgmac.c b/drivers/net/ethernet/marvell/mvgmac.c
new file mode 100644
index 000000000000..0c1354a1e397
--- /dev/null
+++ b/drivers/net/ethernet/marvell/mvgmac.c
@@ -0,0 +1,369 @@
+/*
+ * GMAC driver for Marvell network interfaces on Armada SoCs.
+ *
+ * Copyright (C) 2012 Marvell
+ *
+ * Rami Rosen <rosenr@marvell.com>
+ * Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
+ *
+ * Split from mvneta and mvpp2 by Russell King.
+ *
+ * This file is licensed under the terms of the GNU General Public
+ * License version 2. This program is licensed "as is" without any
+ * warranty of any kind, whether express or implied.
+ */
+#include <linux/bitfield.h>
+#include <linux/export.h>
+#include <linux/io.h>
+#include <linux/phylink.h>
+
+#include "mvgmac.h"
+
+enum {
+	GMAC_CTRL0_REG		= 0x00,
+	GMAC_CTRL0_PORT_ENABLE		= BIT(0),
+	GMAC_CTRL0_PORT_1000BASE_X	= BIT(1),
+	GMAC_CTRL0_MAX_RX_SIZE_SHIFT	= 2,
+	GMAC_CTRL0_MAX_RX_SIZE_MASK	= 0x1fff << GMAC_CTRL0_MAX_RX_SIZE_SHIFT,
+	GMAC_CTRL0_MIB_CNTR_ENABLE	= BIT(15),
+
+	GMAC_CTRL2_REG		= 0x08,
+	GMAC_CTRL2_INBAND_AN_SGMII	= BIT(0),
+	GMAC_CTRL2_PCS_ENABLE		= BIT(3),
+	GMAC_CTRL2_PORT_RGMII		= BIT(4),
+	GMAC_CTRL2_PORT_RESET		= BIT(6),
+
+	GMAC_ANEG_REG		= 0x0c,
+	GMAC_ANEG_FORCE_LINK_DOWN	= BIT(0),
+	GMAC_ANEG_FORCE_LINK_PASS	= BIT(1),
+	GMAC_ANEG_INBAND_AN_ENABLE	= BIT(2),
+	GMAC_ANEG_AN_BYPASS_ENABLE	= BIT(3),
+	GMAC_ANEG_INBAND_RESTART_AN	= BIT(4),
+	GMAC_ANEG_MII_SPEED		= BIT(5),
+	GMAC_ANEG_GMII_SPEED		= BIT(6),
+	GMAC_ANEG_AN_SPEED_ENABLE	= BIT(7),
+	GMAC_ANEG_CONFIG_FLOW_CTRL	= BIT(8),
+	GMAC_ANEG_ADVERT_SYM_FLOW_CTRL	= BIT(9),
+	GMAC_ANEG_AN_FLOW_CTRL_ENABLE	= BIT(11),
+	GMAC_ANEG_FULL_DUPLEX		= BIT(12),
+	GMAC_ANEG_AN_DUPLEX_ENABLE	= BIT(13),
+
+	GMAC_STATUS_REG		= 0x10,
+	MVGMAC_LINK_UP			= BIT(0),
+	MVGMAC_SPEED_1000		= BIT(1),
+	MVGMAC_SPEED_100		= BIT(2),
+	MVGMAC_FULL_DUPLEX		= BIT(3),
+	MVGMAC_RX_FLOW_CTRL_ENABLE	= BIT(4),
+	MVGMAC_TX_FLOW_CTRL_ENABLE	= BIT(5),
+	MVGMAC_RX_FLOW_CTRL_ACTIVE	= BIT(6),
+	MVGMAC_TX_FLOW_CTRL_ACTIVE	= BIT(7),
+	MVGMAC_AN_COMPLETE		= BIT(11),
+	MVGMAC_SYNC_OK			= BIT(14),
+
+	GMAC_CTRL4_REG		= 0x90,
+	GMAC_CTRL4_SHORT_PREAMBLE_ENABLE = BIT(1),
+
+	GMAC_LPI_CTRL0_REG	= 0xc0,
+	GMAC_LPI_CTRL0_TS		= 0xff << 8,
+	GMAC_LPI_CTRL1_REG	= 0xc4,
+	GMAC_LPI_CTRL1_REQ_EN		= BIT(0),
+	GMAC_LPI_CTRL1_TW		= 0xfff << 4,
+	GMAC_LPI_CTRL2_REG	= 0xc8,
+	GMAC_LPI_STATUS_REG	= 0xcc,
+	GMAC_LPI_CNTR_REG	= 0xd0,
+};
+
+#define insert(var, mask, val) ({					\
+	u32 __mask = mask;						\
+	((var) & ~(__mask)) | (((val) << __ffs(__mask)) & (__mask));	\
+})
+
+static void mvgmac_modify(void __iomem *reg, u32 mask, u32 val)
+{
+	u32 v;
+
+	val &= mask;
+	v = readl_relaxed(reg) & ~mask;
+	writel_relaxed(v | val, reg);
+}
+
+#define mvgmac_set(reg, val) mvgmac_modify(reg, val, val)
+#define mvgmac_clear(reg, val) mvgmac_modify(reg, val, 0)
+
+/* Change maximum receive size of the port. */
+void mvgmac_set_max_rx_size(struct mvgmac *gmac, size_t max_rx_size)
+{
+	int size = (max_rx_size - MARVELL_HEADER_SIZE) / 2;
+
+	mvgmac_modify(gmac->base + GMAC_CTRL0_REG,
+		      GMAC_CTRL0_MAX_RX_SIZE_MASK,
+		      FIELD_PREP(GMAC_CTRL0_MAX_RX_SIZE_MASK, size));
+}
+EXPORT_SYMBOL_GPL(mvgmac_set_max_rx_size);
+
+/* Enable the port by setting the port enable bit of the MAC control register */
+void mvgmac_port_enable(struct mvgmac *gmac)
+{
+	mvgmac_set(gmac->base + GMAC_CTRL0_REG,
+		   GMAC_CTRL0_PORT_ENABLE | GMAC_CTRL0_MIB_CNTR_ENABLE);
+}
+EXPORT_SYMBOL_GPL(mvgmac_port_enable);
+
+/* Disable the port */
+void mvgmac_port_disable(struct mvgmac *gmac)
+{
+	mvgmac_clear(gmac->base + GMAC_CTRL0_REG, GMAC_CTRL0_PORT_ENABLE);
+}
+EXPORT_SYMBOL_GPL(mvgmac_port_disable);
+
+void mvgmac_link_unforce(struct mvgmac *gmac)
+{
+	mvgmac_clear(gmac->base + GMAC_ANEG_REG,
+		     GMAC_ANEG_FORCE_LINK_PASS | GMAC_ANEG_FORCE_LINK_DOWN);
+}
+EXPORT_SYMBOL_GPL(mvgmac_link_unforce);
+
+void mvgmac_link_force_down(struct mvgmac *gmac)
+{
+	mvgmac_modify(gmac->base + GMAC_ANEG_REG,
+		      GMAC_ANEG_FORCE_LINK_PASS | GMAC_ANEG_FORCE_LINK_DOWN,
+		      GMAC_ANEG_FORCE_LINK_DOWN);
+}
+EXPORT_SYMBOL_GPL(mvgmac_link_force_down);
+
+void mvgmac_link_down(struct mvgmac *gmac, int mode)
+{
+	if (!phylink_autoneg_inband(mode))
+		mvgmac_link_force_down(gmac);
+}
+EXPORT_SYMBOL_GPL(mvgmac_link_down);
+
+void mvgmac_link_up(struct mvgmac *gmac, int mode, int speed, int duplex,
+		    bool tx_pause, bool rx_pause)
+{
+	u32 an_mask, an_val;
+
+	an_mask = GMAC_ANEG_CONFIG_FLOW_CTRL;
+	an_val = FIELD_PREP(GMAC_ANEG_CONFIG_FLOW_CTRL, tx_pause || rx_pause);
+
+	if (!phylink_autoneg_inband(mode)) {
+		an_mask |= GMAC_ANEG_FORCE_LINK_DOWN |
+			   GMAC_ANEG_FORCE_LINK_PASS |
+			   GMAC_ANEG_MII_SPEED |
+			   GMAC_ANEG_GMII_SPEED |
+			   GMAC_ANEG_FULL_DUPLEX;
+		an_val |= GMAC_ANEG_FORCE_LINK_PASS;
+
+		if (speed == SPEED_1000 || speed == SPEED_2500)
+			an_val |= GMAC_ANEG_GMII_SPEED;
+		else if (speed == SPEED_100)
+			an_val |= GMAC_ANEG_MII_SPEED;
+
+		if (duplex == DUPLEX_FULL)
+			an_val |= GMAC_ANEG_FULL_DUPLEX;
+	}
+
+	mvgmac_modify(gmac->base + GMAC_ANEG_REG, an_mask, an_val);
+}
+EXPORT_SYMBOL_GPL(mvgmac_link_up);
+
+void mvgmac_link_change(struct mvgmac *gmac)
+{
+	u32 gmac_stat = readl_relaxed(gmac->base + GMAC_STATUS_REG);
+
+	phylink_pcs_change(&gmac->pcs, !!(gmac_stat & MVGMAC_LINK_UP));
+}
+EXPORT_SYMBOL_GPL(mvgmac_link_change);
+
+void mvgmac_pcs_get_state(struct phylink_pcs *pcs,
+			  struct phylink_link_state *state)
+{
+	struct mvgmac *gmac = pcs_to_mvgmac(pcs);
+	u32 gmac_stat = readl_relaxed(gmac->base + GMAC_STATUS_REG);
+
+	if (gmac_stat & MVGMAC_SPEED_1000)
+		state->speed =
+			state->interface == PHY_INTERFACE_MODE_2500BASEX ?
+			SPEED_2500 : SPEED_1000;
+	else if (gmac_stat & MVGMAC_SPEED_100)
+		state->speed = SPEED_100;
+	else
+		state->speed = SPEED_10;
+
+	state->an_complete = !!(gmac_stat & MVGMAC_AN_COMPLETE);
+	state->link = !!(gmac_stat & MVGMAC_LINK_UP);
+	state->duplex = !!(gmac_stat & MVGMAC_FULL_DUPLEX);
+
+	if (gmac_stat & MVGMAC_RX_FLOW_CTRL_ENABLE)
+		state->pause |= MLO_PAUSE_RX;
+	if (gmac_stat & MVGMAC_TX_FLOW_CTRL_ENABLE)
+		state->pause |= MLO_PAUSE_TX;
+}
+EXPORT_SYMBOL_GPL(mvgmac_pcs_get_state);
+
+void mvgmac_pcs_an_restart(struct phylink_pcs *pcs)
+{
+	struct mvgmac *gmac = pcs_to_mvgmac(pcs);
+	u32 gmac_an = readl_relaxed(gmac->base + GMAC_ANEG_REG);
+
+	writel_relaxed(gmac_an | GMAC_ANEG_INBAND_RESTART_AN,
+		       gmac->base + GMAC_ANEG_REG);
+	writel_relaxed(gmac_an & ~GMAC_ANEG_INBAND_RESTART_AN,
+		       gmac->base + GMAC_ANEG_REG);
+}
+EXPORT_SYMBOL_GPL(mvgmac_pcs_an_restart);
+
+int mvgmac_pcs_config(struct phylink_pcs *pcs, unsigned int neg_mode,
+		      phy_interface_t interface,
+		      const unsigned long *advertising,
+		      bool permit_pause_to_mac)
+{
+	struct mvgmac *gmac = pcs_to_mvgmac(pcs);
+	u32 mask, val, an, old_an, changed;
+
+	mask = GMAC_ANEG_INBAND_AN_ENABLE |
+	       GMAC_ANEG_INBAND_RESTART_AN |
+	       GMAC_ANEG_AN_SPEED_ENABLE |
+	       GMAC_ANEG_AN_FLOW_CTRL_ENABLE |
+	       GMAC_ANEG_AN_DUPLEX_ENABLE;
+
+	if (neg_mode == PHYLINK_PCS_NEG_INBAND_ENABLED) {
+		mask |= GMAC_ANEG_MII_SPEED |
+			GMAC_ANEG_GMII_SPEED |
+			GMAC_ANEG_FULL_DUPLEX;
+		val = GMAC_ANEG_INBAND_AN_ENABLE;
+
+		if (interface == PHY_INTERFACE_MODE_SGMII) {
+			/* SGMII mode receives the speed and duplex from PHY */
+			val |= GMAC_ANEG_AN_SPEED_ENABLE |
+			       GMAC_ANEG_AN_DUPLEX_ENABLE;
+		} else {
+			/* 802.3z mode has fixed speed and duplex */
+			val |= GMAC_ANEG_GMII_SPEED |
+			       GMAC_ANEG_FULL_DUPLEX;
+
+			/* The FLOW_CTRL_ENABLE bit selects either the hardware
+			 * automatically or the GMAC_ANEG_FLOW_CTRL manually
+			 * controls the GMAC pause mode.
+			 */
+			if (permit_pause_to_mac)
+				val |= GMAC_ANEG_AN_FLOW_CTRL_ENABLE;
+
+			/* Update the advertisement bits */
+			mask |= GMAC_ANEG_ADVERT_SYM_FLOW_CTRL;
+			if (phylink_test(advertising, Pause))
+				val |= GMAC_ANEG_ADVERT_SYM_FLOW_CTRL;
+		}
+	} else {
+		/* Phy or fixed speed - disable in-band AN modes */
+		val = 0;
+	}
+
+	old_an = an = readl_relaxed(gmac->base + GMAC_ANEG_REG);
+	an = (an & ~mask) | val;
+	changed = old_an ^ an;
+	if (changed)
+		writel_relaxed(an, gmac->base + GMAC_ANEG_REG);
+
+	/* We are only interested in the advertisement bits changing */
+	return !!(changed & GMAC_ANEG_ADVERT_SYM_FLOW_CTRL);
+}
+EXPORT_SYMBOL_GPL(mvgmac_pcs_config);
+
+void mvgmac_config_mac(struct mvgmac *gmac, unsigned int mode,
+		       const struct phylink_link_state *state)
+{
+	u32 new_ctrl0, gmac_ctrl0 = readl_relaxed(gmac->base + GMAC_CTRL0_REG);
+	u32 new_ctrl2, gmac_ctrl2 = readl_relaxed(gmac->base + GMAC_CTRL2_REG);
+	u32 new_ctrl4, gmac_ctrl4 = readl_relaxed(gmac->base + GMAC_CTRL4_REG);
+
+	new_ctrl0 = gmac_ctrl0 & ~GMAC_CTRL0_PORT_1000BASE_X;
+	new_ctrl2 = gmac_ctrl2 & ~(GMAC_CTRL2_INBAND_AN_SGMII |
+				   GMAC_CTRL2_PORT_RESET);
+	new_ctrl4 = gmac_ctrl4 & ~GMAC_CTRL4_SHORT_PREAMBLE_ENABLE;
+
+	/* Even though it might look weird, when we're configured in
+	 * SGMII or QSGMII mode, the RGMII bit needs to be set.
+	 */
+	new_ctrl2 |= GMAC_CTRL2_PORT_RGMII;
+
+	if (state->interface == PHY_INTERFACE_MODE_QSGMII ||
+	    state->interface == PHY_INTERFACE_MODE_SGMII ||
+	    phy_interface_mode_is_8023z(state->interface))
+		new_ctrl2 |= GMAC_CTRL2_PCS_ENABLE;
+
+	if (!phylink_autoneg_inband(mode)) {
+		/* Phy or fixed speed - nothing to do, leave the
+		 * configured speed, duplex and flow control as-is.
+		 */
+	} else if (state->interface == PHY_INTERFACE_MODE_SGMII) {
+		/* SGMII mode receives the state from the PHY */
+		new_ctrl2 |= GMAC_CTRL2_INBAND_AN_SGMII;
+	} else {
+		/* 802.3z negotiation - 1000BaseX */
+		new_ctrl0 |= GMAC_CTRL0_PORT_1000BASE_X;
+	}
+
+	/* When at 2.5G, the link partner can send frames with shortened
+	 * preambles.
+	 */
+	if (state->interface == PHY_INTERFACE_MODE_2500BASEX)
+		new_ctrl4 |= GMAC_CTRL4_SHORT_PREAMBLE_ENABLE;
+
+	if (new_ctrl0 != gmac_ctrl0)
+		writel_relaxed(new_ctrl0, gmac->base + GMAC_CTRL0_REG);
+	if (new_ctrl2 != gmac_ctrl2)
+		writel_relaxed(new_ctrl2, gmac->base + GMAC_CTRL2_REG);
+	if (new_ctrl4 != gmac_ctrl4)
+		writel_relaxed(new_ctrl4, gmac->base + GMAC_CTRL4_REG);
+
+	if (gmac_ctrl2 & GMAC_CTRL2_PORT_RESET) {
+		while ((readl_relaxed(gmac->base + GMAC_CTRL2_REG) &
+			GMAC_CTRL2_PORT_RESET) != 0)
+			continue;
+	}
+}
+EXPORT_SYMBOL_GPL(mvgmac_config_mac);
+
+void mvgmac_set_lpi_timers(struct mvgmac *gmac, unsigned int timer)
+{
+	u32 ts, tw, status;
+
+	status = readl_relaxed(gmac->base + GMAC_STATUS_REG);
+	if (status & MVGMAC_SPEED_1000) {
+		/* At 1G speeds, the timer resolution are 1us, and
+		 * 802.3 says tw is 16.5us. Round up to 17us.
+		 */
+		tw = 17;
+		ts = timer;
+	} else {
+		/* At 100M speeds, the timer resolutions are 10us, and
+		 * 802.3 says tw is 30us.
+		 */
+		tw = 3;
+		ts = DIV_ROUND_UP(timer, 10);
+	}
+
+	if (ts > 255)
+		ts = 255;
+
+	mvgmac_modify(gmac->base + GMAC_LPI_CTRL0_REG,
+		      GMAC_LPI_CTRL0_TS,
+		      FIELD_PREP(GMAC_LPI_CTRL0_TS, ts));
+
+	mvgmac_modify(gmac->base + GMAC_LPI_CTRL1_REG,
+		      GMAC_LPI_CTRL1_TW,
+		      FIELD_PREP(GMAC_LPI_CTRL1_TW, tw));
+}
+EXPORT_SYMBOL_GPL(mvgmac_set_lpi_timers);
+
+void mvgmac_set_eee(struct mvgmac *gmac, bool enable)
+{
+	mvgmac_modify(gmac->base + GMAC_LPI_CTRL1_REG,
+		      GMAC_LPI_CTRL1_REQ_EN,
+		      FIELD_PREP(GMAC_LPI_CTRL1_REQ_EN, enable));
+}
+EXPORT_SYMBOL_GPL(mvgmac_set_eee);
+
+MODULE_DESCRIPTION("Marvell GMAC driver");
+MODULE_LICENSE("GPL");
diff --git a/drivers/net/ethernet/marvell/mvgmac.h b/drivers/net/ethernet/marvell/mvgmac.h
new file mode 100644
index 000000000000..34081b4fe54b
--- /dev/null
+++ b/drivers/net/ethernet/marvell/mvgmac.h
@@ -0,0 +1,47 @@
+#ifndef MVGMAC_H
+#define MVGMAC_H
+
+#include <linux/phylink.h>
+
+/* The two bytes Marvell header. Either contains a special value used by
+ * Marvell switches when a specific hardware mode is enabled (not supported
+ * by this driver) or is filled automatically by zeroes on the RX side.
+ * Those two bytes being at the front of the Ethernet header, they allow
+ * to have the IP header aligned on a 4 bytes boundary automatically: the
+ * hardware skips those two bytes on its own.
+ */
+#define MARVELL_HEADER_SIZE 2
+
+struct mvgmac {
+	void __iomem *base;
+	struct phylink_pcs pcs;
+};
+
+static inline struct mvgmac *pcs_to_mvgmac(struct phylink_pcs *pcs)
+{
+	return container_of(pcs, struct mvgmac, pcs);
+}
+
+void mvgmac_set_max_rx_size(struct mvgmac *gmac, size_t max_rx_size);
+void mvgmac_port_enable(struct mvgmac *gmac);
+void mvgmac_port_disable(struct mvgmac *gmac);
+void mvgmac_link_unforce(struct mvgmac *gmac);
+void mvgmac_link_force_down(struct mvgmac *gmac);
+void mvgmac_link_down(struct mvgmac *gmac, int mode);
+void mvgmac_link_up(struct mvgmac *gmac, int mode, int speed, int duplex,
+		    bool tx_pause, bool rx_pause);
+void mvgmac_link_change(struct mvgmac *gmac);
+void mvgmac_pcs_get_state(struct phylink_pcs *pcs,
+			  struct phylink_link_state *state);
+void mvgmac_pcs_an_restart(struct phylink_pcs *pcs);
+int mvgmac_pcs_config(struct phylink_pcs *pcs, unsigned int neg_mode,
+		      phy_interface_t interface,
+		      const unsigned long *advertising,
+		      bool permit_pause_to_mac);
+void mvgmac_config_mac(struct mvgmac *gmac, unsigned int mode,
+		       const struct phylink_link_state *state);
+
+void mvgmac_set_lpi_timers(struct mvgmac *gmac, unsigned int timer);
+void mvgmac_set_eee(struct mvgmac *gmac, bool enable);
+
+#endif
diff --git a/drivers/net/ethernet/marvell/mvneta.c b/drivers/net/ethernet/marvell/mvneta.c
index 00402c252325..e6562b011a3d 100644
--- a/drivers/net/ethernet/marvell/mvneta.c
+++ b/drivers/net/ethernet/marvell/mvneta.c
@@ -34,6 +34,7 @@
 #include <linux/skbuff.h>
 #include <net/hwbm.h>
 #include "mvneta_bm.h"
+#include "mvgmac.h"
 #include <net/ip.h>
 #include <net/ipv6.h>
 #include <net/tso.h>
@@ -196,43 +197,7 @@
 #define      MVNETA_RXQ_ENABLE_MASK              0x000000ff
 #define MVETH_TXQ_TOKEN_COUNT_REG(q)             (0x2700 + ((q) << 4))
 #define MVETH_TXQ_TOKEN_CFG_REG(q)               (0x2704 + ((q) << 4))
-#define MVNETA_GMAC_CTRL_0                       0x2c00
-#define      MVNETA_GMAC_MAX_RX_SIZE_SHIFT       2
-#define      MVNETA_GMAC_MAX_RX_SIZE_MASK        0x7ffc
-#define      MVNETA_GMAC0_PORT_1000BASE_X        BIT(1)
-#define      MVNETA_GMAC0_PORT_ENABLE            BIT(0)
-#define MVNETA_GMAC_CTRL_2                       0x2c08
-#define      MVNETA_GMAC2_INBAND_AN_ENABLE       BIT(0)
-#define      MVNETA_GMAC2_PCS_ENABLE             BIT(3)
-#define      MVNETA_GMAC2_PORT_RGMII             BIT(4)
-#define      MVNETA_GMAC2_PORT_RESET             BIT(6)
-#define MVNETA_GMAC_STATUS                       0x2c10
-#define      MVNETA_GMAC_LINK_UP                 BIT(0)
-#define      MVNETA_GMAC_SPEED_1000              BIT(1)
-#define      MVNETA_GMAC_SPEED_100               BIT(2)
-#define      MVNETA_GMAC_FULL_DUPLEX             BIT(3)
-#define      MVNETA_GMAC_RX_FLOW_CTRL_ENABLE     BIT(4)
-#define      MVNETA_GMAC_TX_FLOW_CTRL_ENABLE     BIT(5)
-#define      MVNETA_GMAC_RX_FLOW_CTRL_ACTIVE     BIT(6)
-#define      MVNETA_GMAC_TX_FLOW_CTRL_ACTIVE     BIT(7)
-#define      MVNETA_GMAC_AN_COMPLETE             BIT(11)
-#define      MVNETA_GMAC_SYNC_OK                 BIT(14)
-#define MVNETA_GMAC_AUTONEG_CONFIG               0x2c0c
-#define      MVNETA_GMAC_FORCE_LINK_DOWN         BIT(0)
-#define      MVNETA_GMAC_FORCE_LINK_PASS         BIT(1)
-#define      MVNETA_GMAC_INBAND_AN_ENABLE        BIT(2)
-#define      MVNETA_GMAC_AN_BYPASS_ENABLE        BIT(3)
-#define      MVNETA_GMAC_INBAND_RESTART_AN       BIT(4)
-#define      MVNETA_GMAC_CONFIG_MII_SPEED        BIT(5)
-#define      MVNETA_GMAC_CONFIG_GMII_SPEED       BIT(6)
-#define      MVNETA_GMAC_AN_SPEED_EN             BIT(7)
-#define      MVNETA_GMAC_CONFIG_FLOW_CTRL        BIT(8)
-#define      MVNETA_GMAC_ADVERT_SYM_FLOW_CTRL    BIT(9)
-#define      MVNETA_GMAC_AN_FLOW_CTRL_EN         BIT(11)
-#define      MVNETA_GMAC_CONFIG_FULL_DUPLEX      BIT(12)
-#define      MVNETA_GMAC_AN_DUPLEX_EN            BIT(13)
-#define MVNETA_GMAC_CTRL_4                       0x2c90
-#define      MVNETA_GMAC4_SHORT_PREAMBLE_ENABLE  BIT(1)
+#define MVNETA_GMAC_BASE                         0x2c00
 #define MVNETA_MIB_COUNTERS_BASE                 0x3000
 #define      MVNETA_MIB_LATE_COLLISION           0x7c
 #define MVNETA_DA_FILT_SPEC_MCAST                0x3400
@@ -283,14 +248,6 @@
 					 (MVNETA_TXQ_BUCKET_REFILL_BASE_PERIOD_NS * \
 					  MVNETA_TXQ_BUCKET_REFILL_PERIOD))
 
-#define MVNETA_LPI_CTRL_0                        0x2cc0
-#define      MVNETA_LPI_CTRL_0_TS                (0xff << 8)
-#define MVNETA_LPI_CTRL_1                        0x2cc4
-#define      MVNETA_LPI_REQUEST_ENABLE           BIT(0)
-#define      MVNETA_LPI_CTRL_1_TW                (0xfff << 4)
-#define MVNETA_LPI_CTRL_2                        0x2cc8
-#define MVNETA_LPI_STATUS                        0x2ccc
-
 #define MVNETA_CAUSE_TXQ_SENT_DESC_ALL_MASK	 0xff
 
 /* Descriptor ring Macros */
@@ -312,7 +269,7 @@
  * boundary automatically: the hardware skips those two bytes on its
  * own.
  */
-#define MVNETA_MH_SIZE			2
+#define MVNETA_MH_SIZE			MARVELL_HEADER_SIZE
 
 #define MVNETA_VLAN_TAG_LEN             4
 
@@ -535,9 +492,9 @@ struct mvneta_port {
 	unsigned int tx_csum_limit;
 	struct phylink *phylink;
 	struct phylink_config phylink_config;
-	struct phylink_pcs phylink_pcs;
 	struct phy *comphy;
 
+	struct mvgmac gmac;
 	struct mvneta_bm *bm_priv;
 	struct mvneta_bm_pool *pool_long;
 	struct mvneta_bm_pool *pool_short;
@@ -926,19 +883,6 @@ mvneta_rxq_next_desc_get(struct mvneta_rx_queue *rxq)
 	return rxq->descs + rx_desc;
 }
 
-/* Change maximum receive size of the port. */
-static void mvneta_max_rx_size_set(struct mvneta_port *pp, int max_rx_size)
-{
-	u32 val;
-
-	val =  mvreg_read(pp, MVNETA_GMAC_CTRL_0);
-	val &= ~MVNETA_GMAC_MAX_RX_SIZE_MASK;
-	val |= ((max_rx_size - MVNETA_MH_SIZE) / 2) <<
-		MVNETA_GMAC_MAX_RX_SIZE_SHIFT;
-	mvreg_write(pp, MVNETA_GMAC_CTRL_0, val);
-}
-
-
 /* Set rx queue offset */
 static void mvneta_rxq_offset_set(struct mvneta_port *pp,
 				  struct mvneta_rx_queue *rxq,
@@ -1343,26 +1287,10 @@ static void mvneta_port_down(struct mvneta_port *pp)
 	udelay(200);
 }
 
-/* Enable the port by setting the port enable bit of the MAC control register */
-static void mvneta_port_enable(struct mvneta_port *pp)
-{
-	u32 val;
-
-	/* Enable port */
-	val = mvreg_read(pp, MVNETA_GMAC_CTRL_0);
-	val |= MVNETA_GMAC0_PORT_ENABLE;
-	mvreg_write(pp, MVNETA_GMAC_CTRL_0, val);
-}
-
 /* Disable the port and wait for about 200 usec before retuning */
 static void mvneta_port_disable(struct mvneta_port *pp)
 {
-	u32 val;
-
-	/* Reset the Enable bit in the Serial Control Register */
-	val = mvreg_read(pp, MVNETA_GMAC_CTRL_0);
-	val &= ~MVNETA_GMAC0_PORT_ENABLE;
-	mvreg_write(pp, MVNETA_GMAC_CTRL_0, val);
+	mvgmac_port_disable(&pp->gmac);
 
 	udelay(200);
 }
@@ -3253,14 +3181,6 @@ static irqreturn_t mvneta_percpu_isr(int irq, void *dev_id)
 	return IRQ_HANDLED;
 }
 
-static void mvneta_link_change(struct mvneta_port *pp)
-{
-	u32 gmac_stat = mvreg_read(pp, MVNETA_GMAC_STATUS);
-
-	phylink_pcs_change(&pp->phylink_pcs,
-			   !!(gmac_stat & MVNETA_GMAC_LINK_UP));
-}
-
 /* NAPI handler
  * Bits 0 - 7 of the causeRxTx register indicate that are transmitted
  * packets on the corresponding TXQ (Bit 0 is for TX queue 1).
@@ -3290,7 +3210,7 @@ static int mvneta_poll(struct napi_struct *napi, int budget)
 
 		if (cause_misc & (MVNETA_CAUSE_PHY_STATUS_CHANGE |
 				  MVNETA_CAUSE_LINK_CHANGE))
-			mvneta_link_change(pp);
+			mvgmac_link_change(&pp->gmac);
 	}
 
 	/* Release Tx descriptors */
@@ -3747,11 +3667,11 @@ static void mvneta_start_dev(struct mvneta_port *pp)
 
 	WARN_ON(mvneta_config_interface(pp, pp->phy_interface));
 
-	mvneta_max_rx_size_set(pp, pp->pkt_size);
+	mvgmac_set_max_rx_size(&pp->gmac, pp->pkt_size);
 	mvneta_txq_max_tx_size_set(pp, pp->pkt_size);
 
 	/* start the Rx/Tx activity */
-	mvneta_port_enable(pp);
+	mvgmac_port_enable(&pp->gmac);
 
 	if (!pp->neta_armada3700) {
 		/* Enable polling on the port */
@@ -3953,11 +3873,6 @@ static int mvneta_set_mac_addr(struct net_device *dev, void *addr)
 	return 0;
 }
 
-static struct mvneta_port *mvneta_pcs_to_port(struct phylink_pcs *pcs)
-{
-	return container_of(pcs, struct mvneta_port, phylink_pcs);
-}
-
 static unsigned int mvneta_pcs_query_inband(struct phylink_pcs *pcs,
 					    phy_interface_t interface)
 {
@@ -3981,105 +3896,23 @@ static unsigned int mvneta_pcs_query_inband(struct phylink_pcs *pcs,
 	return LINK_INBAND_VALID;
 }
 
-static void mvneta_pcs_get_state(struct phylink_pcs *pcs,
-				 struct phylink_link_state *state)
-{
-	struct mvneta_port *pp = mvneta_pcs_to_port(pcs);
-	u32 gmac_stat;
-
-	gmac_stat = mvreg_read(pp, MVNETA_GMAC_STATUS);
-
-	if (gmac_stat & MVNETA_GMAC_SPEED_1000)
-		state->speed =
-			state->interface == PHY_INTERFACE_MODE_2500BASEX ?
-			SPEED_2500 : SPEED_1000;
-	else if (gmac_stat & MVNETA_GMAC_SPEED_100)
-		state->speed = SPEED_100;
-	else
-		state->speed = SPEED_10;
-
-	state->an_complete = !!(gmac_stat & MVNETA_GMAC_AN_COMPLETE);
-	state->link = !!(gmac_stat & MVNETA_GMAC_LINK_UP);
-	state->duplex = !!(gmac_stat & MVNETA_GMAC_FULL_DUPLEX);
-
-	if (gmac_stat & MVNETA_GMAC_RX_FLOW_CTRL_ENABLE)
-		state->pause |= MLO_PAUSE_RX;
-	if (gmac_stat & MVNETA_GMAC_TX_FLOW_CTRL_ENABLE)
-		state->pause |= MLO_PAUSE_TX;
-}
-
 static int mvneta_pcs_config(struct phylink_pcs *pcs, unsigned int neg_mode,
 			     phy_interface_t interface,
 			     const unsigned long *advertising,
 			     bool permit_pause_to_mac)
 {
-	struct mvneta_port *pp = mvneta_pcs_to_port(pcs);
-	u32 mask, val, an, old_an, changed;
-
-	mask = MVNETA_GMAC_INBAND_AN_ENABLE |
-	       MVNETA_GMAC_INBAND_RESTART_AN |
-	       MVNETA_GMAC_AN_SPEED_EN |
-	       MVNETA_GMAC_AN_FLOW_CTRL_EN |
-	       MVNETA_GMAC_AN_DUPLEX_EN;
-
-	if (neg_mode == PHYLINK_PCS_NEG_INBAND_ENABLED) {
-		mask |= MVNETA_GMAC_CONFIG_MII_SPEED |
-			MVNETA_GMAC_CONFIG_GMII_SPEED |
-			MVNETA_GMAC_CONFIG_FULL_DUPLEX;
-		val = MVNETA_GMAC_INBAND_AN_ENABLE;
-
-		if (interface == PHY_INTERFACE_MODE_SGMII) {
-			/* SGMII mode receives the speed and duplex from PHY */
-			val |= MVNETA_GMAC_AN_SPEED_EN |
-			       MVNETA_GMAC_AN_DUPLEX_EN;
-		} else {
-			/* 802.3z mode has fixed speed and duplex */
-			val |= MVNETA_GMAC_CONFIG_GMII_SPEED |
-			       MVNETA_GMAC_CONFIG_FULL_DUPLEX;
+	/* We should never see Asym_Pause set */
+	WARN_ON(phylink_test(advertising, Asym_Pause));
 
-			/* The FLOW_CTRL_EN bit selects either the hardware
-			 * automatically or the CONFIG_FLOW_CTRL manually
-			 * controls the GMAC pause mode.
-			 */
-			if (permit_pause_to_mac)
-				val |= MVNETA_GMAC_AN_FLOW_CTRL_EN;
-
-			/* Update the advertisement bits */
-			mask |= MVNETA_GMAC_ADVERT_SYM_FLOW_CTRL;
-			if (phylink_test(advertising, Pause))
-				val |= MVNETA_GMAC_ADVERT_SYM_FLOW_CTRL;
-		}
-	} else {
-		/* Phy or fixed speed - disable in-band AN modes */
-		val = 0;
-	}
-
-	old_an = an = mvreg_read(pp, MVNETA_GMAC_AUTONEG_CONFIG);
-	an = (an & ~mask) | val;
-	changed = old_an ^ an;
-	if (changed)
-		mvreg_write(pp, MVNETA_GMAC_AUTONEG_CONFIG, an);
-
-	/* We are only interested in the advertisement bits changing */
-	return !!(changed & MVNETA_GMAC_ADVERT_SYM_FLOW_CTRL);
-}
-
-static void mvneta_pcs_an_restart(struct phylink_pcs *pcs)
-{
-	struct mvneta_port *pp = mvneta_pcs_to_port(pcs);
-	u32 gmac_an = mvreg_read(pp, MVNETA_GMAC_AUTONEG_CONFIG);
-
-	mvreg_write(pp, MVNETA_GMAC_AUTONEG_CONFIG,
-		    gmac_an | MVNETA_GMAC_INBAND_RESTART_AN);
-	mvreg_write(pp, MVNETA_GMAC_AUTONEG_CONFIG,
-		    gmac_an & ~MVNETA_GMAC_INBAND_RESTART_AN);
+	return mvgmac_pcs_config(pcs, neg_mode, interface, advertising,
+				 permit_pause_to_mac);
 }
 
 static const struct phylink_pcs_ops mvneta_phylink_pcs_ops = {
 	.pcs_query_inband = mvneta_pcs_query_inband,
-	.pcs_get_state = mvneta_pcs_get_state,
+	.pcs_get_state = mvgmac_pcs_get_state,
 	.pcs_config = mvneta_pcs_config,
-	.pcs_an_restart = mvneta_pcs_an_restart,
+	.pcs_an_restart = mvgmac_pcs_an_restart,
 };
 
 static struct phylink_pcs *mvneta_mac_select_pcs(struct phylink_config *config,
@@ -4088,7 +3921,7 @@ static struct phylink_pcs *mvneta_mac_select_pcs(struct phylink_config *config,
 	struct net_device *ndev = to_net_dev(config->dev);
 	struct mvneta_port *pp = netdev_priv(ndev);
 
-	return &pp->phylink_pcs;
+	return &pp->gmac.pcs;
 }
 
 static int mvneta_mac_prepare(struct phylink_config *config, unsigned int mode,
@@ -4096,7 +3929,6 @@ static int mvneta_mac_prepare(struct phylink_config *config, unsigned int mode,
 {
 	struct net_device *ndev = to_net_dev(config->dev);
 	struct mvneta_port *pp = netdev_priv(ndev);
-	u32 val;
 
 	if (pp->phy_interface != interface ||
 	    phylink_autoneg_inband(mode)) {
@@ -4105,10 +3937,7 @@ static int mvneta_mac_prepare(struct phylink_config *config, unsigned int mode,
 		 * can only change the port mode and in-band enable when the
 		 * link is down.
 		 */
-		val = mvreg_read(pp, MVNETA_GMAC_AUTONEG_CONFIG);
-		val &= ~MVNETA_GMAC_FORCE_LINK_PASS;
-		val |= MVNETA_GMAC_FORCE_LINK_DOWN;
-		mvreg_write(pp, MVNETA_GMAC_AUTONEG_CONFIG, val);
+		mvgmac_link_force_down(&pp->gmac);
 	}
 
 	if (pp->phy_interface != interface)
@@ -4130,55 +3959,8 @@ static void mvneta_mac_config(struct phylink_config *config, unsigned int mode,
 {
 	struct net_device *ndev = to_net_dev(config->dev);
 	struct mvneta_port *pp = netdev_priv(ndev);
-	u32 new_ctrl0, gmac_ctrl0 = mvreg_read(pp, MVNETA_GMAC_CTRL_0);
-	u32 new_ctrl2, gmac_ctrl2 = mvreg_read(pp, MVNETA_GMAC_CTRL_2);
-	u32 new_ctrl4, gmac_ctrl4 = mvreg_read(pp, MVNETA_GMAC_CTRL_4);
-
-	new_ctrl0 = gmac_ctrl0 & ~MVNETA_GMAC0_PORT_1000BASE_X;
-	new_ctrl2 = gmac_ctrl2 & ~(MVNETA_GMAC2_INBAND_AN_ENABLE |
-				   MVNETA_GMAC2_PORT_RESET);
-	new_ctrl4 = gmac_ctrl4 & ~(MVNETA_GMAC4_SHORT_PREAMBLE_ENABLE);
-
-	/* Even though it might look weird, when we're configured in
-	 * SGMII or QSGMII mode, the RGMII bit needs to be set.
-	 */
-	new_ctrl2 |= MVNETA_GMAC2_PORT_RGMII;
-
-	if (state->interface == PHY_INTERFACE_MODE_QSGMII ||
-	    state->interface == PHY_INTERFACE_MODE_SGMII ||
-	    phy_interface_mode_is_8023z(state->interface))
-		new_ctrl2 |= MVNETA_GMAC2_PCS_ENABLE;
-
-	if (!phylink_autoneg_inband(mode)) {
-		/* Phy or fixed speed - nothing to do, leave the
-		 * configured speed, duplex and flow control as-is.
-		 */
-	} else if (state->interface == PHY_INTERFACE_MODE_SGMII) {
-		/* SGMII mode receives the state from the PHY */
-		new_ctrl2 |= MVNETA_GMAC2_INBAND_AN_ENABLE;
-	} else {
-		/* 802.3z negotiation - only 1000base-X */
-		new_ctrl0 |= MVNETA_GMAC0_PORT_1000BASE_X;
-	}
 
-	/* When at 2.5G, the link partner can send frames with shortened
-	 * preambles.
-	 */
-	if (state->interface == PHY_INTERFACE_MODE_2500BASEX)
-		new_ctrl4 |= MVNETA_GMAC4_SHORT_PREAMBLE_ENABLE;
-
-	if (new_ctrl0 != gmac_ctrl0)
-		mvreg_write(pp, MVNETA_GMAC_CTRL_0, new_ctrl0);
-	if (new_ctrl2 != gmac_ctrl2)
-		mvreg_write(pp, MVNETA_GMAC_CTRL_2, new_ctrl2);
-	if (new_ctrl4 != gmac_ctrl4)
-		mvreg_write(pp, MVNETA_GMAC_CTRL_4, new_ctrl4);
-
-	if (gmac_ctrl2 & MVNETA_GMAC2_PORT_RESET) {
-		while ((mvreg_read(pp, MVNETA_GMAC_CTRL_2) &
-			MVNETA_GMAC2_PORT_RESET) != 0)
-			continue;
-	}
+	mvgmac_config_mac(&pp->gmac, mode, state);
 }
 
 static int mvneta_mac_finish(struct phylink_config *config, unsigned int mode,
@@ -4186,7 +3968,7 @@ static int mvneta_mac_finish(struct phylink_config *config, unsigned int mode,
 {
 	struct net_device *ndev = to_net_dev(config->dev);
 	struct mvneta_port *pp = netdev_priv(ndev);
-	u32 val, clk;
+	u32 clk;
 
 	/* Disable 1ms clock if not in in-band mode */
 	if (!phylink_autoneg_inband(mode)) {
@@ -4202,11 +3984,8 @@ static int mvneta_mac_finish(struct phylink_config *config, unsigned int mode,
 	/* Allow the link to come up if in in-band mode, otherwise the
 	 * link is forced via mac_link_down()/mac_link_up()
 	 */
-	if (phylink_autoneg_inband(mode)) {
-		val = mvreg_read(pp, MVNETA_GMAC_AUTONEG_CONFIG);
-		val &= ~MVNETA_GMAC_FORCE_LINK_DOWN;
-		mvreg_write(pp, MVNETA_GMAC_AUTONEG_CONFIG, val);
-	}
+	if (phylink_autoneg_inband(mode))
+		mvgmac_link_unforce(&pp->gmac);
 
 	return 0;
 }
@@ -4216,16 +3995,9 @@ static void mvneta_mac_link_down(struct phylink_config *config,
 {
 	struct net_device *ndev = to_net_dev(config->dev);
 	struct mvneta_port *pp = netdev_priv(ndev);
-	u32 val;
 
 	mvneta_port_down(pp);
-
-	if (!phylink_autoneg_inband(mode)) {
-		val = mvreg_read(pp, MVNETA_GMAC_AUTONEG_CONFIG);
-		val &= ~MVNETA_GMAC_FORCE_LINK_PASS;
-		val |= MVNETA_GMAC_FORCE_LINK_DOWN;
-		mvreg_write(pp, MVNETA_GMAC_AUTONEG_CONFIG, val);
-	}
+	mvgmac_link_down(&pp->gmac, mode);
 }
 
 static void mvneta_mac_link_up(struct phylink_config *config,
@@ -4236,95 +4008,25 @@ static void mvneta_mac_link_up(struct phylink_config *config,
 {
 	struct net_device *ndev = to_net_dev(config->dev);
 	struct mvneta_port *pp = netdev_priv(ndev);
-	u32 val;
-
-	if (!phylink_autoneg_inband(mode)) {
-		val = mvreg_read(pp, MVNETA_GMAC_AUTONEG_CONFIG);
-		val &= ~(MVNETA_GMAC_FORCE_LINK_DOWN |
-			 MVNETA_GMAC_CONFIG_MII_SPEED |
-			 MVNETA_GMAC_CONFIG_GMII_SPEED |
-			 MVNETA_GMAC_CONFIG_FLOW_CTRL |
-			 MVNETA_GMAC_CONFIG_FULL_DUPLEX);
-		val |= MVNETA_GMAC_FORCE_LINK_PASS;
-
-		if (speed == SPEED_1000 || speed == SPEED_2500)
-			val |= MVNETA_GMAC_CONFIG_GMII_SPEED;
-		else if (speed == SPEED_100)
-			val |= MVNETA_GMAC_CONFIG_MII_SPEED;
-
-		if (duplex == DUPLEX_FULL)
-			val |= MVNETA_GMAC_CONFIG_FULL_DUPLEX;
-
-		if (tx_pause || rx_pause)
-			val |= MVNETA_GMAC_CONFIG_FLOW_CTRL;
-
-		mvreg_write(pp, MVNETA_GMAC_AUTONEG_CONFIG, val);
-	} else {
-		/* When inband doesn't cover flow control or flow control is
-		 * disabled, we need to manually configure it. This bit will
-		 * only have effect if MVNETA_GMAC_AN_FLOW_CTRL_EN is unset.
-		 */
-		val = mvreg_read(pp, MVNETA_GMAC_AUTONEG_CONFIG);
-		val &= ~MVNETA_GMAC_CONFIG_FLOW_CTRL;
-
-		if (tx_pause || rx_pause)
-			val |= MVNETA_GMAC_CONFIG_FLOW_CTRL;
-
-		mvreg_write(pp, MVNETA_GMAC_AUTONEG_CONFIG, val);
-	}
 
+	mvgmac_link_up(&pp->gmac, mode, speed, duplex, tx_pause, rx_pause);
 	mvneta_port_up(pp);
 }
 
 static void mvneta_mac_disable_tx_lpi(struct phylink_config *config)
 {
 	struct mvneta_port *pp = netdev_priv(to_net_dev(config->dev));
-	u32 lpi1;
 
-	lpi1 = mvreg_read(pp, MVNETA_LPI_CTRL_1);
-	lpi1 &= ~MVNETA_LPI_REQUEST_ENABLE;
-	mvreg_write(pp, MVNETA_LPI_CTRL_1, lpi1);
+	mvgmac_set_eee(&pp->gmac, false);
 }
 
 static void mvneta_mac_enable_tx_lpi(struct phylink_config *config, u32 timer)
 {
 	struct mvneta_port *pp = netdev_priv(to_net_dev(config->dev));
-	u32 ts, tw, lpi0, lpi1, status;
-
-	status = mvreg_read(pp, MVNETA_GMAC_STATUS);
-
-	if (status & MVNETA_GMAC_SPEED_1000) {
-		/* At 1G speeds, the timer resolution are 1us, and
-		 * 802.3 says tw is 16.5us. Round up to 17us.
-		 */
-		tw = 17;
-		ts = timer;
-	} else {
-		/* At 100M speeds, the timer resolutions are 10us, and
-		 * 802.3 says tw is 30us.
-		 */
-		tw = 3;
-		ts = DIV_ROUND_UP(timer, 10);
-	}
-
-	if (ts > 255)
-		ts = 255;
-
-	/* Ensure LPI generation is disabled */
-	lpi1 = mvreg_read(pp, MVNETA_LPI_CTRL_1);
-	mvreg_write(pp, MVNETA_LPI_CTRL_1, lpi1 & ~MVNETA_LPI_REQUEST_ENABLE);
-
-	/* Configure ts */
-	lpi0 = mvreg_read(pp, MVNETA_LPI_CTRL_0) & ~MVNETA_LPI_CTRL_0_TS;
-	lpi0 |= FIELD_PREP(MVNETA_LPI_CTRL_0_TS, ts);
-	mvreg_write(pp, MVNETA_LPI_CTRL_0, lpi0);
-
-	/* Configure tw */
-	lpi1 &= ~MVNETA_LPI_CTRL_1_TW;
-	lpi1 |= FIELD_PREP(MVNETA_LPI_CTRL_1_TW, tw);
 
-	/* Enable LPI generation */
-	mvreg_write(pp, MVNETA_LPI_CTRL_1, lpi1 | MVNETA_LPI_REQUEST_ENABLE);
+	mvgmac_set_eee(&pp->gmac, false);
+	mvgmac_set_lpi_timers(&pp->gmac, timer);
+	mvgmac_set_eee(&pp->gmac, true);
 }
 
 static const struct phylink_mac_ops mvneta_phylink_ops = {
@@ -5544,8 +5246,9 @@ static int mvneta_probe(struct platform_device *pdev)
 	if (!IS_ERR(pp->clk_bus))
 		clk_prepare_enable(pp->clk_bus);
 
-	pp->phylink_pcs.ops = &mvneta_phylink_pcs_ops;
-	pp->phylink_pcs.neg_mode = true;
+	pp->gmac.base = pp->base + MVNETA_GMAC_BASE;
+	pp->gmac.pcs.ops = &mvneta_phylink_pcs_ops;
+	pp->gmac.pcs.neg_mode = true;
 
 	pp->phylink_config.dev = &dev->dev;
 	pp->phylink_config.type = PHYLINK_NETDEV;