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authorRichard Zhu <r65037@freescale.com>2013-07-16 11:28:46 +0800
committerShawn Guo <shawn.guo@linaro.org>2013-08-22 23:29:25 +0800
commit0fb1f804269e549b556b475c8655bc862c220622 (patch)
tree32ecacf8cc60836f533173bfecd13adc0ef0245d
parent98a3e804de9158f6e3d568f45c02552af47a0367 (diff)
ARM: dtsi: enable ahci sata on imx6q platforms
Only imx6q has the ahci sata controller, enable it on imx6q platforms. Signed-off-by: Richard Zhu <r65037@freescale.com> Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
-rw-r--r--arch/arm/boot/dts/imx6q-sabreauto.dts4
-rw-r--r--arch/arm/boot/dts/imx6q-sabrelite.dts4
-rw-r--r--arch/arm/boot/dts/imx6q-sabresd.dts4
-rw-r--r--arch/arm/boot/dts/imx6q.dtsi9
4 files changed, 21 insertions, 0 deletions
diff --git a/arch/arm/boot/dts/imx6q-sabreauto.dts b/arch/arm/boot/dts/imx6q-sabreauto.dts
index 9e634ccb798f..334b9247e78c 100644
--- a/arch/arm/boot/dts/imx6q-sabreauto.dts
+++ b/arch/arm/boot/dts/imx6q-sabreauto.dts
@@ -19,3 +19,7 @@
model = "Freescale i.MX6 Quad SABRE Automotive Board";
compatible = "fsl,imx6q-sabreauto", "fsl,imx6q";
};
+
+&sata {
+ status = "okay";
+};
diff --git a/arch/arm/boot/dts/imx6q-sabrelite.dts b/arch/arm/boot/dts/imx6q-sabrelite.dts
index 38b8aeac5c56..e0f4cd041c70 100644
--- a/arch/arm/boot/dts/imx6q-sabrelite.dts
+++ b/arch/arm/boot/dts/imx6q-sabrelite.dts
@@ -65,6 +65,10 @@
};
};
+&sata {
+ status = "okay";
+};
+
&ecspi1 {
fsl,spi-num-chipselects = <1>;
cs-gpios = <&gpio3 19 0>;
diff --git a/arch/arm/boot/dts/imx6q-sabresd.dts b/arch/arm/boot/dts/imx6q-sabresd.dts
index 5e62c2427b07..9cbdfe7a0931 100644
--- a/arch/arm/boot/dts/imx6q-sabresd.dts
+++ b/arch/arm/boot/dts/imx6q-sabresd.dts
@@ -19,3 +19,7 @@
model = "Freescale i.MX6 Quad SABRE Smart Device Board";
compatible = "fsl,imx6q-sabresd", "fsl,imx6q";
};
+
+&sata {
+ status = "okay";
+};
diff --git a/arch/arm/boot/dts/imx6q.dtsi b/arch/arm/boot/dts/imx6q.dtsi
index f492c620c9f2..76a84e80a1ab 100644
--- a/arch/arm/boot/dts/imx6q.dtsi
+++ b/arch/arm/boot/dts/imx6q.dtsi
@@ -116,6 +116,15 @@
};
};
+ sata: sata@02200000 {
+ compatible = "fsl,imx6q-ahci";
+ reg = <0x02200000 0x4000>;
+ interrupts = <0 39 0x04>;
+ clocks = <&clks 154>, <&clks 187>, <&clks 105>;
+ clock-names = "sata", "sata_ref", "ahb";
+ status = "disabled";
+ };
+
ipu2: ipu@02800000 {
#crtc-cells = <1>;
compatible = "fsl,imx6q-ipu";