diff options
| author | Hui Wang <jason77.wang@gmail.com> | 2012-06-20 14:41:50 +0800 |
|---|---|---|
| committer | Shawn Guo <shawn.guo@linaro.org> | 2012-07-12 14:59:11 +0800 |
| commit | 8ad7a3058791d92de98cfb57eb799d37e9d30413 (patch) | |
| tree | 1101029b2d12d85aaa99e7e24a2892191dab485e | |
| parent | 74bd88f78f5ac7f30e0ff75e41b0daeec8d4d3bc (diff) | |
ARM: dts: imx6q-sabrelite: add ecspi1 pinctrl support
Imx6q sabrelite board uses ecspi1 to connect a spi flash sst25vf016b,
we need to add pinctrl information for it in the dts, otherwise the
ecspi1 driver can't work and the connected flash is wrongly
detected as a mr25h256 flash like this:
m25p80 spi32766.0: found mr25h256, expected sst25vf016b
m25p80 spi32766.0: mr25h256 (32 Kbytes)
Cc: Richard Zhao <richard.zhao@freescale.com>
Signed-off-by: Hui Wang <jason77.wang@gmail.com>
Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
| -rw-r--r-- | arch/arm/boot/dts/imx6q-sabrelite.dts | 3 | ||||
| -rw-r--r-- | arch/arm/boot/dts/imx6q.dtsi | 8 |
2 files changed, 11 insertions, 0 deletions
diff --git a/arch/arm/boot/dts/imx6q-sabrelite.dts b/arch/arm/boot/dts/imx6q-sabrelite.dts index 46fdfd1d5cd1..d42e851ceb97 100644 --- a/arch/arm/boot/dts/imx6q-sabrelite.dts +++ b/arch/arm/boot/dts/imx6q-sabrelite.dts @@ -27,6 +27,8 @@ ecspi@02008000 { /* eCSPI1 */ fsl,spi-num-chipselects = <1>; cs-gpios = <&gpio3 19 0>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_ecspi1_1>; status = "okay"; flash: m25p80@0 { @@ -50,6 +52,7 @@ pinctrl_gpio_hog: gpiohog { fsl,pins = < 144 0x80000000 /* MX6Q_PAD_EIM_D22__GPIO_3_22 */ + 121 0x80000000 /* MX6Q_PAD_EIM_D19__GPIO_3_19 */ >; }; }; diff --git a/arch/arm/boot/dts/imx6q.dtsi b/arch/arm/boot/dts/imx6q.dtsi index 693f31f206dd..c25d49584814 100644 --- a/arch/arm/boot/dts/imx6q.dtsi +++ b/arch/arm/boot/dts/imx6q.dtsi @@ -581,6 +581,14 @@ 1517 0x17059>; /* MX6Q_PAD_SD4_DAT7__USDHC4_DAT7 */ }; }; + + ecspi1 { + pinctrl_ecspi1_1: ecspi1grp-1 { + fsl,pins = <101 0x100b1 /* MX6Q_PAD_EIM_D17__ECSPI1_MISO */ + 109 0x100b1 /* MX6Q_PAD_EIM_D18__ECSPI1_MOSI */ + 94 0x100b1>; /* MX6Q_PAD_EIM_D16__ECSPI1_SCLK */ + }; + }; }; dcic@020e4000 { /* DCIC1 */ |