diff options
| author | Russell King <rmk+kernel@arm.linux.org.uk> | 2015-10-01 20:27:19 +0100 |
|---|---|---|
| committer | Russell King <rmk+kernel@armlinux.org.uk> | 2017-05-05 18:42:38 +0100 |
| commit | c32cd1c82725b2acf73669d88a5e6045d0eb267b (patch) | |
| tree | 068798190a8aa8bd6f8e21d79343680888de97bb | |
| parent | 4e26a01585b224ab7f3f2f6a23eecd563bb28f77 (diff) | |
phylink: add ethtool nway_reset support
Add ethtool nway_reset support to phylink, to allow userspace to
request a re-negotiation of the link.
Reviewed-by: Florian Fainelli <f.fainelli@gmail.com>
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
| -rw-r--r-- | drivers/net/phy/phylink.c | 14 | ||||
| -rw-r--r-- | include/linux/phylink.h | 1 |
2 files changed, 15 insertions, 0 deletions
diff --git a/drivers/net/phy/phylink.c b/drivers/net/phy/phylink.c index e474209a03f7..fae39e919459 100644 --- a/drivers/net/phy/phylink.c +++ b/drivers/net/phy/phylink.c @@ -790,6 +790,20 @@ int phylink_ethtool_ksettings_set(struct phylink *pl, } EXPORT_SYMBOL_GPL(phylink_ethtool_ksettings_set); +int phylink_ethtool_nway_reset(struct phylink *pl) +{ + int ret = 0; + + mutex_lock(&pl->config_mutex); + if (pl->phydev) + ret = phy_restart_aneg(pl->phydev); + phylink_mac_an_restart(pl); + mutex_unlock(&pl->config_mutex); + + return ret; +} +EXPORT_SYMBOL_GPL(phylink_ethtool_nway_reset); + /* This emulates MII registers for a fixed-mode phy operating as per the * passed in state. "aneg" defines if we report negotiation is possible. * diff --git a/include/linux/phylink.h b/include/linux/phylink.h index 62786d27a5fc..1fa3ad72f01a 100644 --- a/include/linux/phylink.h +++ b/include/linux/phylink.h @@ -123,6 +123,7 @@ int phylink_ethtool_ksettings_get(struct phylink *, struct ethtool_link_ksettings *); int phylink_ethtool_ksettings_set(struct phylink *, const struct ethtool_link_ksettings *); +int phylink_ethtool_nway_reset(struct phylink *); int phylink_mii_ioctl(struct phylink *, struct ifreq *, int); int phylink_set_link(struct phylink *pl, unsigned int mode, u8 port, |