diff options
| author | Paul Burton <paul.burton@mips.com> | 2019-10-01 21:53:29 +0000 |
|---|---|---|
| committer | Paul Burton <paul.burton@mips.com> | 2019-10-07 09:42:42 -0700 |
| commit | 27aab27259aec1f200cf1f84f02b8192d27abe64 (patch) | |
| tree | f81012697b69d1faf6007bfdf4ccb562f00fdd95 | |
| parent | 59361e9975fd567a642f4ee32fd0ea662ffa7040 (diff) | |
MIPS: bitops: ins start position is always an immediate
The start position for an ins instruction is always encoded as an
immediate, so allowing registers to be used by the inline asm makes no
sense. It should never happen anyway since a bit index should always be
small enough to be treated as an immediate, but remove the nonsensical
"r" for sanity.
Signed-off-by: Paul Burton <paul.burton@mips.com>
Cc: linux-mips@vger.kernel.org
Cc: Huacai Chen <chenhc@lemote.com>
Cc: Jiaxun Yang <jiaxun.yang@flygoat.com>
Cc: linux-kernel@vger.kernel.org
| -rw-r--r-- | arch/mips/include/asm/bitops.h | 6 |
1 files changed, 3 insertions, 3 deletions
diff --git a/arch/mips/include/asm/bitops.h b/arch/mips/include/asm/bitops.h index 0f5329e32e87..03532ae9f528 100644 --- a/arch/mips/include/asm/bitops.h +++ b/arch/mips/include/asm/bitops.h @@ -85,7 +85,7 @@ static inline void set_bit(unsigned long nr, volatile unsigned long *addr) " " __INS "%0, %3, %2, 1 \n" " " __SC "%0, %1 \n" : "=&r" (temp), "+" GCC_OFF_SMALL_ASM() (*m) - : "ir" (bit), "r" (~0) + : "i" (bit), "r" (~0) : __LLSC_CLOBBER); } while (unlikely(!temp)); return; @@ -150,7 +150,7 @@ static inline void clear_bit(unsigned long nr, volatile unsigned long *addr) " " __INS "%0, $0, %2, 1 \n" " " __SC "%0, %1 \n" : "=&r" (temp), "+" GCC_OFF_SMALL_ASM() (*m) - : "ir" (bit) + : "i" (bit) : __LLSC_CLOBBER); } while (unlikely(!temp)); return; @@ -383,7 +383,7 @@ static inline int test_and_clear_bit(unsigned long nr, " " __INS "%0, $0, %3, 1 \n" " " __SC "%0, %1 \n" : "=&r" (temp), "+" GCC_OFF_SMALL_ASM() (*m), "=&r" (res) - : "ir" (bit) + : "i" (bit) : __LLSC_CLOBBER); } while (unlikely(!temp)); } else { |