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authorAndrey Smirnov <andrew.smirnov@gmail.com>2016-08-03 20:33:34 +0100
committerRussell King <rmk+kernel@armlinux.org.uk>2016-08-12 16:47:04 +0100
commit55604b7ab1b5b8f560721e69b1ac059bd8d2078e (patch)
tree18028ea6bd367aff08d068f63c24fe5fb8524a69
parentfc1473103cfa0b785dd3ff8de2430fec42cfc8ad (diff)
ARM: 8593/1: cache-l2x0.c: Do not clear bit 23 in prefetch control register
As per L2C-310 TRM[1]: "... You can control this feature using bits 30,27 and 23 of the Prefetch Control Register. Bit 23 and 27 are only used if you set bit 30 HIGH..." which means there is no need to clear bit 23 if bit 30 is being cleared. [1] http://infocenter.arm.com/help/index.jsp?topic=/com.arm.doc.ddi0246e/CJAJACBJ.html Acked-by: Arnd Bergmann <arnd@arndb.de> Signed-off-by: Andrey Smirnov <andrew.smirnov@gmail.com> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
-rw-r--r--arch/arm/mm/cache-l2x0.c7
1 files changed, 2 insertions, 5 deletions
diff --git a/arch/arm/mm/cache-l2x0.c b/arch/arm/mm/cache-l2x0.c
index 7e624872bd6f..ca5595fa072a 100644
--- a/arch/arm/mm/cache-l2x0.c
+++ b/arch/arm/mm/cache-l2x0.c
@@ -709,11 +709,8 @@ static void __init l2c310_fixup(void __iomem *base, u32 cache_id,
if (revision >= L310_CACHE_ID_RTL_R3P0 &&
revision < L310_CACHE_ID_RTL_R3P2) {
u32 val = l2x0_saved_regs.prefetch_ctrl;
- /* I don't think bit23 is required here... but iMX6 does so */
- if (val & (L310_PREFETCH_CTRL_DBL_LINEFILL |
- L310_PREFETCH_CTRL_DBL_LINEFILL_INCR)) {
- val &= ~(L310_PREFETCH_CTRL_DBL_LINEFILL |
- L310_PREFETCH_CTRL_DBL_LINEFILL_INCR);
+ if (val & L310_PREFETCH_CTRL_DBL_LINEFILL) {
+ val &= ~L310_PREFETCH_CTRL_DBL_LINEFILL;
l2x0_saved_regs.prefetch_ctrl = val;
errata[n++] = "752271";
}