diff options
| author | Ville Syrjälä <ville.syrjala@linux.intel.com> | 2016-05-11 22:44:48 +0300 |
|---|---|---|
| committer | Ville Syrjälä <ville.syrjala@linux.intel.com> | 2016-05-13 21:31:18 +0300 |
| commit | 4b6cd64eb94cca95e8a9ad0d3888f627e4070cff (patch) | |
| tree | c96bfc7f975029c9c040f79d75fc0a5ec8e200c2 | |
| parent | 430e05de7607911c9e5b872fc94b8416c153325e (diff) | |
drm/i915: Kill off dead code from skl_dpll0_enable()
We calculate the CDCLK_CTL value from scratch so no need to attempt
some form of RMW first.
Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Link: http://patchwork.freedesktop.org/patch/msgid/1462995892-32416-10-git-send-email-ville.syrjala@linux.intel.com
Reviewed-by: Jani Nikula <jani.nikula@intel.com>
| -rw-r--r-- | drivers/gpu/drm/i915/intel_display.c | 5 |
1 files changed, 0 insertions, 5 deletions
diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c index a6bdabc7cbea..76934a5a7c49 100644 --- a/drivers/gpu/drm/i915/intel_display.c +++ b/drivers/gpu/drm/i915/intel_display.c @@ -5562,17 +5562,12 @@ skl_dpll0_enable(struct drm_i915_private *dev_priv, unsigned int required_vco) u32 val; /* select the minimum CDCLK before enabling DPLL 0 */ - val = I915_READ(CDCLK_CTL); - val &= ~CDCLK_FREQ_SEL_MASK | ~CDCLK_FREQ_DECIMAL_MASK; - val |= CDCLK_FREQ_337_308; - if (required_vco == 8640) min_freq = 308570; else min_freq = 337500; val = CDCLK_FREQ_337_308 | skl_cdclk_decimal(min_freq); - I915_WRITE(CDCLK_CTL, val); POSTING_READ(CDCLK_CTL); |