diff options
| author | Tom St Denis <tom.stdenis@amd.com> | 2020-06-16 08:47:04 -0400 |
|---|---|---|
| committer | Alex Deucher <alexander.deucher@amd.com> | 2020-07-01 01:59:22 -0400 |
| commit | 614c56111cc73f0a828634dcb2eecd2035c2104b (patch) | |
| tree | d37b561ad04770bf62b6c4c575fb3a1af6b8ecac | |
| parent | 9fb10671011143d15b6b40d6d5fa9c52c57e9d63 (diff) | |
drm/amd/amdgpu: Fix offset for SQ_DEBUG_STS_GLOBAL on gfx10 (v2)
Despite having different IP offsets the computed address of the register(s)
are the same between gfx7..gfx10. This patch fixes the offset relative
to the GC block on gfx10.
(v2): SQ_DEBUG_STS_GLOBAL2 is 0x10 higher ...
Signed-off-by: Tom St Denis <tom.stdenis@amd.com>
Acked-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
| -rw-r--r-- | drivers/gpu/drm/amd/include/asic_reg/gc/gc_10_1_0_offset.h | 4 | ||||
| -rw-r--r-- | drivers/gpu/drm/amd/include/asic_reg/gc/gc_10_3_0_offset.h | 4 |
2 files changed, 4 insertions, 4 deletions
diff --git a/drivers/gpu/drm/amd/include/asic_reg/gc/gc_10_1_0_offset.h b/drivers/gpu/drm/amd/include/asic_reg/gc/gc_10_1_0_offset.h index baac40fa70e7..18d34bbceebe 100644 --- a/drivers/gpu/drm/amd/include/asic_reg/gc/gc_10_1_0_offset.h +++ b/drivers/gpu/drm/amd/include/asic_reg/gc/gc_10_1_0_offset.h @@ -21,9 +21,9 @@ #ifndef _gc_10_1_0_OFFSET_HEADER #define _gc_10_1_0_OFFSET_HEADER -#define mmSQ_DEBUG_STS_GLOBAL 0x0309 +#define mmSQ_DEBUG_STS_GLOBAL 0x10A9 #define mmSQ_DEBUG_STS_GLOBAL_BASE_IDX 0 -#define mmSQ_DEBUG_STS_GLOBAL2 0x0310 +#define mmSQ_DEBUG_STS_GLOBAL2 0x10B0 #define mmSQ_DEBUG_STS_GLOBAL2_BASE_IDX 0 // addressBlock: gc_sdma0_sdma0dec diff --git a/drivers/gpu/drm/amd/include/asic_reg/gc/gc_10_3_0_offset.h b/drivers/gpu/drm/amd/include/asic_reg/gc/gc_10_3_0_offset.h index 0bde3b4e9567..05d1b0a5f6d2 100644 --- a/drivers/gpu/drm/amd/include/asic_reg/gc/gc_10_3_0_offset.h +++ b/drivers/gpu/drm/amd/include/asic_reg/gc/gc_10_3_0_offset.h @@ -22,9 +22,9 @@ #ifndef _gc_10_3_0_OFFSET_HEADER #define _gc_10_3_0_OFFSET_HEADER -#define mmSQ_DEBUG_STS_GLOBAL 0x0309 +#define mmSQ_DEBUG_STS_GLOBAL 0x10A9 #define mmSQ_DEBUG_STS_GLOBAL_BASE_IDX 0 -#define mmSQ_DEBUG_STS_GLOBAL2 0x0310 +#define mmSQ_DEBUG_STS_GLOBAL2 0x10B0 #define mmSQ_DEBUG_STS_GLOBAL2_BASE_IDX 0 // addressBlock: gc_sdma0_sdma0dec |