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authorRussell King <rmk+kernel@armlinux.org.uk>2016-12-11 16:05:38 +0000
committerRussell King <rmk+kernel@armlinux.org.uk>2019-11-10 23:04:45 +0000
commitb410ae89916f8166cdd15e04650e1023d34f2938 (patch)
tree287372d0e2b0bc015b9d10a6ce5daa98a72026f8
parent8b60b4c8c597b936e9e75381c7c8966856f3e514 (diff)
arm64: dts: marvell: mcbin: update 10G PHYs definitions
Add the pinctrl settings and interrupts for the 10G PHYs. Signed-off-by: Russell King <rmk+kernel@armlinux.org.uk>
-rw-r--r--arch/arm64/boot/dts/marvell/armada-8040-mcbin.dts38
1 files changed, 38 insertions, 0 deletions
diff --git a/arch/arm64/boot/dts/marvell/armada-8040-mcbin.dts b/arch/arm64/boot/dts/marvell/armada-8040-mcbin.dts
index 7d98bc3d15e8..8cedb9a223bb 100644
--- a/arch/arm64/boot/dts/marvell/armada-8040-mcbin.dts
+++ b/arch/arm64/boot/dts/marvell/armada-8040-mcbin.dts
@@ -14,19 +14,46 @@
"marvell,armada-ap806-quad", "marvell,armada-ap806";
};
+&cp0_pinctrl {
+ cp0_xg_mdio_pins: xg-mdio-pins {
+ marvell,pins = "mpp42", "mpp43";
+ marvell,function = "xg";
+ };
+ cp0_phy1_pins: phy1-pins { /* phy interrupt */
+ marvell,pins = "mpp49";
+ marvell,function = "gpio";
+ };
+ cp0_phy0_pins: phy0-pins { /* phy interrupt */
+ marvell,pins = "mpp50";
+ marvell,function = "gpio";
+ };
+};
+
&cp0_xmdio {
+ pinctrl-names = "default";
+ pinctrl-0 = <&cp0_xg_mdio_pins>;
status = "okay";
phy0: ethernet-phy@0 {
compatible = "ethernet-phy-ieee802.3-c45";
+ pinctrl-names = "default";
+ pinctrl-0 = <&cp0_phy0_pins &cp1_phy0_pins>;
+ /* should use in-band negotiation */
reg = <0>;
sfp = <&sfp_eth0>;
+ interrupt-parent = <&cp0_gpio2>;
+ interrupts = <18 IRQ_TYPE_LEVEL_LOW>;
};
phy8: ethernet-phy@8 {
compatible = "ethernet-phy-ieee802.3-c45";
+ pinctrl-names = "default";
+ pinctrl-0 = <&cp0_phy1_pins &cp1_phy1_pins>;
+ /* should use in-band negotiation */
reg = <8>;
sfp = <&sfp_eth1>;
+ interrupt-parent = <&cp0_gpio2>;
+ interrupts = <17 IRQ_TYPE_LEVEL_LOW>;
};
};
@@ -44,6 +71,17 @@
phy-mode = "10gbase-kr";
};
+&cp1_pinctrl {
+ cp1_phy1_pins: phy1-pins { /* phy reset */
+ marvell,pins = "mpp9";
+ marvell,function = "gpio";
+ };
+ cp1_phy0_pins: phy0-pins { /* phy reset */
+ marvell,pins = "mpp31";
+ marvell,function = "gpio";
+ };
+};
+
/*==================*/
#ifdef MCBIN_USE_MVPP2_DRIVER