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author | Peng Fan <peng.fan@nxp.com> | 2021-11-12 14:26:02 +0800 |
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committer | Shawn Guo <shawnguo@kernel.org> | 2021-11-23 17:25:52 +0800 |
commit | cb551b5e3bab54265f374a394e239f5e492a5742 (patch) | |
tree | 000a966a2126f780ccf551c966ab36dab522ebb1 /COPYING | |
parent | c190510714df168b9d6387bc29844acbe9a39521 (diff) |
arm64: dts: imx8m: add cache info
i.MX8M Family use A53 Cores and has 32KB ICache with 32KB DCache.
- Icache is 2-way set associative
- Dcache is 4-way set associative
- L2cache is 16-way set associative
- Line size are 64bytes
Except i.MX8MQ has 1MB L2 Cache, others has 512KB L2 Cache.
So add the cache info in device tree and let use could see that
from /sys/devices/system/cpu/cpu[x]/cache/
Signed-off-by: Peng Fan <peng.fan@nxp.com>
Signed-off-by: Shawn Guo <shawnguo@kernel.org>
Diffstat (limited to 'COPYING')
0 files changed, 0 insertions, 0 deletions